Semiconductor package and method for forming the same and method for forming dummy die

Abstract

Embodiments of the present invention provide a dummy grain with improved thermal conductivity and warpage control. The dummy grain includes an adjustment layer formed on a semiconductor substrate. The adjustment layer has a thermal conductivity in the range of about 30 W / mK to about 100 W / mK. The adjustment layer may include silicon nitride or silicon carbide.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor packages, methods of forming the same, and methods of forming dummy dies. Prior Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacture of semiconductor devices generally involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using a lithography process to form circuit components and elements on the semiconductor substrate. Typically, dozens or hundreds of integrated circuits are fabricated on a single semiconductor wafer, and the individual dies on the wafer are singulated by sawing along scribe lines. For example, the individual dies are typically packaged separately in a multi-chip module or other type of package.

[0003] Three-dimensional integrated circuits (3DICs) are a relatively new development in the field of semiconductor packaging, where multiple semiconductor dies are stacked on top of each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. For example, 3DICs can provide improved integration density and other advantages such as faster speed and higher bandwidth due to reduced interconnect lengths between the stacked dies. Summary of the Invention

[0004] In some embodiments, a semiconductor package is provided that includes a first die having a first bonding film; a second die stacked over the first die and bonded to the first die through the first bonding film; and a dummy die stacked over the first die and bonded to the first die through the first bonding film, wherein the dummy die includes: a substrate; an adjustment layer formed over the substrate, wherein the adjustment layer has a thermal conductivity in a range between about 30 W / mK and about 100 W / mK; and a second bonding film formed over the adjustment layer, wherein the second bonding film is bonded to the first bonding film.

[0005] In some embodiments, a method of forming a semiconductor package is provided. The method includes bonding a first die to a second die, where the first die includes a first bonding film and the second die is bonded to the first bonding film; and bonding a dummy die to the first die, where the dummy die includes: a substrate; an adjustment layer formed over the substrate, where the adjustment layer has a thermal conductivity in the range of between about 30 W / mK and about 100 W / mK; and a second bonding film formed over the adjustment layer, and the first bonding film is bonded to the second bonding film.

[0006] In some other embodiments, a method of forming a dummy die is provided. The method includes depositing an adjustment layer on a front side of a semiconductor substrate; depositing a bonding film on the adjustment layer; forming a cutting pattern over the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the cutting pattern to form cutting grooves; depositing a protective layer in the cutting grooves and on the bonding film; attaching a carrier wafer to the protective layer; and grinding the semiconductor substrate from a back side to expose the protective layer in the cutting grooves. Brief Description of the Drawings

[0007] Embodiments of the present invention can be better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to the standard convention in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of the various components may be arbitrarily enlarged or reduced for clear illustration. FIG. 1 is a flowchart of forming dummy dies according to an embodiment of the present invention. FIGS. 2, 3, 4, 5, 6, 7, 8, 9A, 9B, 9C, 9D, 9E, and 10 schematically show various processing stages during the manufacture of a dummy die according to an embodiment of the present invention. FIG. 11 shows improved thermal conductivity in a dummy die according to an embodiment of the present invention. FIGS. 12A and 12B schematically show improved warpage control in a dummy die according to an embodiment of the present invention. FIG. 13 is a flowchart of forming an integrated circuit package according to an embodiment of the present invention. FIGS. 14, 15, 16A, 16B, 16C, 17A, 17B, 18, 19, 20, and 21 schematically show various processing stages during the manufacture of an integrated circuit package according to an embodiment of the present invention. FIG. 22 is a flowchart of forming an integrated circuit package according to an embodiment of the present invention. Figures 23A, 23B, 23C, 23D, 24A, 24B, 24C, and 25 schematically show various processing stages during the manufacture of an integrated circuit package in accordance with an embodiment of the present invention. Embodiments

[0008] It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the dimensions of the components are not limited to the scope or values of one embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the components. In addition, in the following description, embodiments in which a first component is formed above or on a second component include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components such that the first and second components do not directly contact. In addition, repeated reference symbols and / or words may be used in different examples of the disclosure. These repeated symbols or words are for the purpose of simplification and clarity and are not intended to limit the relationship between the various embodiments and / or the described external structures.

[0009] For ease of description of the relationship of one element or component in the drawings to another (plural) element or (plural) component, spatial relative terms such as "under", "below", "lower", "above", "upper", and the like may be used. In addition to the orientation shown in the drawings, the spatial relative terms also encompass different orientations of the device during use or operation. The device may also be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the descriptions of the spatial relative terms used may be interpreted accordingly.

[0010] Embodiments will be described with respect to embodiments in a particular context, namely integrated circuit packaging. However, other embodiments may also be applied to other electrical connection components, including but not limited to package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, die-to-wafer assemblies, in-package assembly, substrate-in-process, interposer or the like, or mounting input components, boards, dies or other components, or combinations for connecting packages or mounting any type of integrated circuit or electrical component. The various embodiments described herein allow for packaging functional components (e.g., integrated circuit dies) of different functions and sizes (e.g., heights) within the same integrated circuit package. The various embodiments described herein can be integrated into chip-on-wafer-on-substrate processes and chip-on-chip-on-substrate (CoCoS) processes.

[0011] Embodiments of the present invention relate to a dummy die having an adjustment layer to increase thermal conductivity and warp control. The adjustment layer may include one or more layers of materials having a thermal conductivity in the range between about 30 W / mK and about 100 W / mK. In some embodiments, the adjustment layer may include silicon nitride or silicon carbide. In some embodiments, the dummy die may be bonded to another die through a bonding film including dummy conductors formed therein to further improve thermal conductivity.

[0012] FIG. 1 is a flowchart of a method 100 for forming dummy dies according to an embodiment of the present invention. Specifically, the method 100 is for a system on integrated circuit (SoIC) package to have dummy dies with improved thermal conductivity. The dummy dies can be regarded as device-free dies. The dummy dies generally do not have any electronic components. For example, the dummy dies generally do not have any active components or functional components, such as transistors, capacitors, resistors, diodes, photodiodes, fuse elements, and / or other similar components. The dummy dies may include a semiconductor substrate or a bonding structure. Embodiments of the present invention provide dummy dies with a bonding structure, which have improved thermal conductivity and / or improved warpage adjustment.

[0013] FIGS. 2-8, 9A-9E, and 10 schematically show various processing steps during the manufacture of a dummy substrate 200 according to an embodiment of the present invention. Specifically, FIGS. 2-8, 9A-9E, and 10 show the formation of dummy devices using the method 100.

[0014] In operation 102, an adhesive layer 204 is deposited on a substrate 202, as shown in FIG. 2. FIG. 2 is a schematic partial cross-sectional view of the substrate 202. A plurality of dummy substrates 200 will be formed from the substrate 202.

[0015] The substrate 202 is formed of one or more semiconductor materials. In some embodiments, the substrate 202 is a bulk substrate, including elemental semiconductors (such as silicon or germanium in crystalline, polycrystalline, or amorphous structures), compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations of the foregoing, or other suitable materials. In some embodiments, the substrate 202 may include one or more dopants. The substrate 202 may also be in the form of silicon-on-insulator (SOI). The silicon-on-insulator substrate may include a semiconductor material layer (such as silicon, germanium, and / or the like) formed on an insulating layer (such as a buried oxide and / or the like formed on a silicon substrate). In addition, other substrates including multi-layer substrates, graded substrates, mixed-orientation substrates, combinations of any of the foregoing, and / or the like may be used.

[0016] The adhesive layer 204 is deposited on the front side 202f of the substrate 202. In some embodiments, the adhesive layer 204 can be formed by flowing an oxidation precursor into a processing chamber. In some embodiments, one or more cleaning processes can be performed to remove native oxides and / or contaminants from the substrate 202 before forming the adhesive layer 204.

[0017] The adhesive layer 204 provides adhesion between subsequent layers to be formed on the substrate 202. In some embodiments, when the substrate 202 includes silicon, the adhesive layer 204 includes silicon oxide. In some embodiments, the adhesive layer 204 is formed of undoped silica glass (USG). In some embodiments, the adhesive layer 204 has a thickness in the range of about 100 Å to about 1000 Å. If the thickness of the adhesive layer 204 is less than 100 Å, the adhesion effect of the adhesive layer 204 may not provide sufficient viscosity of the subsequent layer to the substrate 202 to maintain subsequent processes (such as grinding and planarization), for example, cracks may form in the adhesive layer 204. If the thickness of the adhesive layer 204 is greater than 1000 Å, the ductility of the adhesive layer 204 may be reduced, and bending may form in the adhesive layer 204.

[0018] In operation 104, an adjustment layer 206 is deposited above the adhesive layer 204 on the substrate 202, as shown in FIG. 2. In some embodiments, the adjustment layer 206 provides improved thermal conductivity in the subsequently formed dummy substrate 200. In addition, the adjustment layer 206 also provides stress modulation or warp adjustment to the substrate 202.

[0019] The adjustment layer 206 has a thickness T1. In some embodiments, the thickness T1 is in the range of about 3000 Å to about 6000 Å. A thickness T1 less than 3000 Å may not provide sufficient thermal conductivity or stress modulation / warp adjustment. A thickness T1 greater than 6000 Å may generate too much stress and cause the adjustment layer 206 to peel off from the substrate 202.

[0020] In some embodiments, the adjustment layer 206 can be a heat conducting layer having a thermal conductivity in the range of about 30 W / mK to about 100 W / mK. In some embodiments, the adjustment layer 206 can include a suitable dielectric film, such as a semiconductor nitride or a semiconductor carbide. In some embodiments, the adjustment layer 206 can include silicon nitride (Si 3N 4 or SiN), silicon-rich silicon nitride, nitrogen-rich silicon nitride, silicon carbide, or the like.

[0021] In some embodiments, the adjustment layer 206 may be silicon nitride. The adjustment layer 206 may be formed by introducing precursors containing a nitrogen source and a semiconductor source. In some embodiments, the adjustment layer 206 is formed in a low temperature range to improve the thermal conductivity and avoid forming hot spots in the integrated circuit system.

[0022] In operation 106, a bonding film 208 is deposited over the adjustment layer 206, as shown in FIG. 3. FIG. 3 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 106. The bonding film 208 is configured to bond the dummy die to other dies to be formed during subsequent packaging. In particular, the bonding film 208 may be selected from any suitable material to bond the adjustment layer 206 to another die or another bonding film. The bonding film 208 may be formed of any suitable material used for bonding in packaging. In some embodiments, the bonding film 208 is formed of an oxide material. For example, the bonding film 208 is formed of undoped silica glass. In some embodiments, the bonding film 208 has a thickness in the range of about 100 Å to about 1000 Å. The thickness of the bonding film 208 may be selected according to the queue time. Since the bonding film 208 can absorb moisture during the waiting time, it is desirable to have a thinner bonding film 208 so that if the queue time of the dummy substrate 200 is longer during packaging, excessive moisture retention in the integrated circuit packaging can be avoided.

[0023] In operation 108, a photoresist layer 210 is deposited over the bonding film 208, and a cutting pattern is formed in the photoresist layer 210, as shown in FIG. 4. FIG. 4 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 108. The photoresist layer 210 may be deposited over the bonding film 208. A photolithography process is performed to form a cutting pattern having grooves 212 in the photoresist layer 210. The photoresist layer 210 is selectively removed to form the grooves 212. The grooves 212 may form a grid defining a plurality of rectangular regions. As shown in FIG. 4, the bonding film 208 is exposed at the bottom of the grooves 212.

[0024] In operation 110, one or more etching processes are performed to etch through the bonding film 208, the adjustment layer 206, the adhesive layer 204 and into the substrate 202 to form cutting grooves 214, as shown in FIG. 5. FIG. 5 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 110. The patterned photoresist layer 210 is used as a mask for forming the cutting grooves 214. The cutting grooves 214 can be formed in the bonding film 208, the adjustment layer 206, the adhesive layer 204 and into the substrate 202 to form a plurality of dummy regions 216. The cutting grooves 214 are formed in the substrate 202 but do not pass through the substrate 202, so that the dummy regions 216 remain connected through the substrate 202. The cutting grooves 214 are deep enough so that when the substrate 202 is polished from the back side, the dummy regions 216 can be separated from each other. In some embodiments, the cutting grooves 214 have a width W1 in the range of about 6 um to about 10 um.

[0025] In operation 112, a protective layer 218 is deposited to fill the cutting grooves 214 and cover the dummy regions 216, as shown in FIG. 6. FIG. 6 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 112. The protective layer 218 is used to cover and protect the exposed portions of the bonding film 208 and the substrate 202, the adhesive layer 204 and the adjustment layer 206 during subsequent processing. The protective layer 218 can be formed of any material capable of isolating the dummy regions 216 from the processing environment during subsequent processing. The protective layer 218 can also be easily removed from the dummy regions 216. In some embodiments, the protective layer 218 can be formed of a photoresist material. In some embodiments, the protective layer 218 can be deposited over the dummy regions 216 through a spin coating process and a subsequent curing process (such as a low-temperature curing technique). However, any suitable coating, any suitable deposition technique and any suitable curing technique can also be used. Alternatively, the protective layer 218 can be a curable resin, a polyimide coating, a polybenzoxazole (PBO), an epoxy resin film or the like.

[0026] In operation 114, a back grinding tape 220 and a carrier wafer 222 are attached to the protective layer 218, as shown in FIG. 7. FIG. 7 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 114. First, the back grinding tape 220 is attached to the protective layer 218. Then, the carrier wafer 222 is attached to the back grinding tape 220 so that the substrate 202 can be thinned from the back side 202b.

[0027] In operation 116, the substrate 202 is flipped, and a backside grinding process is performed to thin the substrate 202 from the backside 202b, as shown in FIG. 8. FIG. 8 is a partial cross-sectional schematic view of the dummy substrate 200 after operation 116. The backside grinding process reduces the thickness of the substrate 202 to a target thickness according to the design.

[0028] In some embodiments, a backside grinding process is performed to reduce the thickness of the substrate 202 and "cut" the dummy substrate 200 into a plurality of dummy dies 224. As shown in FIG. 8, the backside grinding process removes the portion of the substrate 202 without the scribe grooves 214 and exposes the protective layer 218. In some embodiments, the concentration of the protective layer 218 in the grinding waste can be used as the endpoint of the backside grinding process. After the backside grinding process, the thickness of the substrate 202 is reduced to a thickness T2. In some embodiments, the thickness T2 ranges between about 50 μm and about 100 μm.

[0029] Although the dummy dies 224 are created after operation 116, the plurality of dummy dies 224 are still connected through the protective layer 218. The dummy dies 224 are separated by the scribe grooves 214 that fill the protective layer 218. The bonding film 208 on each dummy die 224 contacts the protective layer 218, and the protective layer 218 is attached to the backside grinding tape 220.

[0030] In operation 118, one or more expansion processes are performed to increase the distance between the dummy dies 224, as shown in FIGS. 9A - 9E. FIG. 9A is a partial cross-sectional schematic view of the dummy dies 224 after operation 118. FIGS. 9B and 9C are schematic top views of the plurality of dummy dies 224 before and after the expansion process. FIGS. 9D and 9E are schematic top views of the plurality of dummy dies 224 before and after the second expansion process.

[0031] After the backside grinding process, the plurality of dummy dies 224 are flipped and attached to the expansion tape 226 on the frame 228. As shown in FIG. 9A, the plurality of dummy dies 224 adhere to the expansion tape 226 on the backside 202b. Then, the carrier wafer 222 and the backside grinding tape 220 are removed. Then, the expansion tape 226 is stretched so that the scribe grooves 214 between the dummy dies 224 become wider.

[0032] In some embodiments, ultraviolet radiation 230 can be applied to the expansion tape 226 such that the expansion tape 226 can be relaxed and stretched to increase the distance between adjacent dummy dies 224. As shown in FIG. 9B, before the expansion process, the distance between adjacent dummy dies 224 is the width W1 of the cutting groove 214. As described above, the width W1 ranges between about 6 um and about 10 um. As shown in FIG. 9C, after stretching the expansion tape 226, the distance between adjacent dummy dies 224 is the width W1'. In some embodiments, the width W1' ranges between about 60 um and about 65 um. The expanded width W1' allows the dummy dies 224 to be individually picked up from the expansion tape 226 for subsequent packaging.

[0033] In some embodiments, one or more expansion processes can be performed to further increase the distance between adjacent dummy dies 224 for ease of handling. As shown in FIG. 9D, the dummy dies 224 can be transferred from the expansion tape 226 on the frame 228 to a second expansion tape 226' on a second frame 228'. In FIG. 9E, the second expansion tape 226' is stretched and the distance between adjacent dummy dies 224 is increased to the width W1''. In some embodiments, the width W1'' ranges between about 450 um and about 550 um. Although two expansion processes are shown in the example, more or fewer expansion processes can be used to achieve the desired distance between the dummy dies 224 such that the dummy dies 224 can be picked up by a die handling tool.

[0034] In operation 120, the dummy dies 224 are cleaned and prepared for subsequent packaging, as shown in FIG. 10. FIG. 10 is a partial cross-sectional schematic view of the dummy dies 224 after operation 120. The dummy dies 224 are cleaned through a suitable process (such as an ashing process when the protective layer 218 includes a photoresist material) to remove the protective layer 218. After cleaning, the bonding film 208 on each dummy die 224 is exposed. The extended distance W1' allows the dummy dies 224 to be individually picked up from the expansion tape 226 for packaging.

[0035] The dummy die 224 according to an embodiment of the present invention includes an adjustment layer (such as the adjustment layer 206) deposited on the substrate 202, and the adjustment layer replaces the oxygen-based bonding film. The adjustment layer 206 is formed of a material with high thermal conductivity, thereby improving heat dissipation in the integrated packaging. The adjustment layer 206 can also be a high-stress layer to improve wafer warpage control, thereby improving bonding quality.

[0036] FIG. 11 includes the thermal conductivity and temperature curves of silicon oxide and silicon nitride. Curve 250 is the thermal conductivity and temperature curve of silicon oxide. Curve 252 is the thermal conductivity and temperature curve of silicon nitride. According to the current art, silicon oxide is used for dummy dies. Silicon oxide promotes the bonding between dummy dies and other dies in an integrated circuit package. According to an embodiment of the present invention, an adjustment layer 206 is used to replace the silicon oxide in the dummy die. The adjustment layer 206 can be formed of silicon nitride. As shown in FIG. 11, the thermal conductivity of silicon nitride is much higher than that of silicon oxide (especially at low temperatures). For example, the thermal conductivity of silicon nitride is about 55 W / mK, while the thermal conductivity of silicon oxide is about 25 W / mK. Therefore, by using the adjustment layer 206 having silicon nitride to replace the silicon oxide layer, the embodiment of the present invention improves the heat dissipation between the dummy die and the device die in the bonding region.

[0037] In some embodiments, the adjustment layer 206 is designed to achieve the desired warpage. For example, a negative warpage in the dummy die may be desired to improve the bonding quality. When the substrate warps towards its back side, it is defined as negative warpage. FIG. 12A is a cross-sectional schematic view of the dummy die 224 to show the negative warpage. In FIG. 12A, the dummy die 224 is positioned with the back side 202b of the substrate 202 facing up and the bonding film 208 facing down. When the dummy die 224 has no warpage, the contour 260 of the dummy die 224 is flat. When the dummy die 224 has negative warpage, the contour of the dummy die 224 is presented by curve 262. In the case of negative warpage, the bonding film 208 first contacts the die to be bonded in the central region, and the contact area expands from the central region to the edge region, thereby improving the bonding quality.

[0038] In the state-of-the-art technology, negative warpage is achieved by depositing a specific thickness of silicon oxide. For example, a silicon oxide layer having a thickness in the range of about 15 kÅ to about 20 kÅ is applied to a semiconductor substrate to achieve negative warpage to improve the bonding quality. The adjustment layer 206 according to an embodiment of the present invention can achieve the same or greater negative warpage at a smaller thickness.

[0039] FIG. 12B schematically shows the warpage corresponding to adjusting the thickness of the adjustment layer 206. Line 264 annotates the negative warpage in a wafer having a silicon oxide film in the range of about 15 kÅ to about 20 kÅ in thickness. Line 266 annotates the warpage value of the adjustment layer 206 according to an embodiment of the present invention. The adjustment layer 206 is formed of silicon nitride. When the adjustment layer 206 has a thickness of 3.5 kÅ, the negative warpage in the dummy die 224 is slightly less than the negative warpage achieved through a silicon oxide film in the range of about 15 kÅ to about 20 kÅ in thickness. When the adjustment layer 206 has a thickness of 4.5 kÅ, the negative warpage in the dummy die 224 is about 50% greater than the negative warpage achieved through a silicon oxide film in the range of about 15 kÅ to about 20 kÅ in thickness. When the adjustment layer 206 has a thickness of 5.5 kÅ, the negative warpage in the dummy die 224 is about twice the negative warpage achieved through a silicon oxide film in the range of about 15 kÅ to about 20 kÅ in thickness.

[0040] As shown in FIG. 12B, the adjustment layer 206 according to an embodiment of the present invention can achieve the same amount or greater negative warpage with a thinner film. The reduced thickness between the dummy die and the die to be bonded further improves heat dissipation.

[0041] FIG. 13 is a flowchart of a method 300 for forming an integrated circuit package according to an embodiment of the present invention. The dummy die according to an embodiment of the present invention can be used in the method 300. FIGS. 14-24 schematically show various processing stages during the manufacture of an integrated circuit package 400 according to an embodiment of the present invention. The integrated circuit package 400 can be manufactured by using the method 300.

[0042] The method 300 can be used to form a three-dimensional integrated circuit (3DIC) package. In a general formation process of forming a three-dimensional integrated circuit, two layers of dies are vertically stacked, and an electrical connection is formed between the two layers of dies. For example, the top die is stacked above the bottom die. The top die and the bottom die can have different sizes. The dummy die can be used to compensate for the size difference between the top die and the bottom die. In the method 300, the larger bottom die is bonded to the smaller top die and one or more dummy dies. It should be understood that the terms "top die" and "bottom die" are used for convenience of description, but do not necessarily refer to the physical position of the die.

[0043] In operation 302, the first die 406 is attached to the carrier wafer 402 for bonding to a second die, as shown in FIG. 14. FIG. 14 is a cross-sectional schematic view of the integrated circuit package 400 after operation 302. The first die 406 may be referred to as the bottom die, and the bottom die is attached to the carrier wafer 402 through an adhesive layer 404.

[0044] The first die 406 can be a logic die, a memory die, a three-dimensional integrated circuit die, a central processing unit (CPU) die, a graphic process unit (GPU) die, a system-on-chip (SOC) die, a micro-electro-mechanical-system (MEMS) die, or the like. The first die 406 can be a single die or a combined die, such as a chiplet having two or more dies. In some embodiments, the first die 406 can be a chiplet including two or more cores, central processing unit processors, graphic processing unit processors, and a bus network connecting the two or more cores. Viewed from a top view, the first die 406 can be quadrilateral, rectangular, or square.

[0045] The carrier wafer 402 can include, for example, glass, silicon oxide, aluminum oxide, and the like. The adhesive layer 404 can be applied to the carrier wafer 402. Alternatively, the carrier wafer 402 can include a carrier tape. The adhesive layer 404 can be used to bond the carrier wafer 402 to other devices, such as the first die 406. In some embodiments, the adhesive layer 404 can be a thermal release film. In some embodiments, the adhesive layer 404 can be an ultraviolet (UV) glue, and when the UV glue is exposed to ultraviolet light, the UV glue loses its viscosity. Any suitable adhesive can be used, and all such adhesives are fully included within the scope of the embodiments of the present invention.

[0046] The first die 406 can include a substrate 412, a device layer 414 formed in and on the substrate 412, and an interconnect structure 416 formed on the device layer 414. The interconnect structure 416 can include multiple layers of dielectric materials, and conductive components 418 are formed in the dielectric materials.

[0047] The substrate 412 may include bulk silicon (doped or undoped) or an active layer of a silicon-on-insulator substrate. Generally, a silicon-on-insulator substrate includes a semiconductor material layer, such as silicon, germanium, silicon germanium, silicon-on-insulator, silicon germanium on insulator (SGOI), or a combination of the foregoing. Other substrates including multi-layer substrates, graded substrates, or hybrid orientation substrates may be used. The substrate 412 has a front side 408 and a back side 410. The device layer 414 is formed on the front side 408 of the substrate 412. In operation 302, the first die 406 is attached to the carrier wafer 402 such that the back side 410 of the substrate 412 faces upward for subsequent bonding.

[0048] The device layer 414 includes various devices, such as transistors, capacitors, resistors, inductors, and the like, which can be used to generate the desired structural and functional requirements for the design of the first die 406.

[0049] The interconnect structure 416 is formed above the device layer 414 above the front side 408 of the substrate 412. The conductive components 418 embedded in the interconnect structure 416 are designed to connect the various devices in the device layer 414 to form a functional circuit. The interconnect structure 416 is formed of alternating layers of dielectric and conductive materials and can be formed through any suitable process, such as deposition, damascene, dual damascene, etc.

[0050] In operation 304, a bonding film 420 is deposited above the first die 406, as shown in FIG. 15. FIG. 15 is a cross-sectional schematic view of the integrated circuit package 400 after operation 304. In some embodiments, a grinding process may be performed to thin the substrate 412 to a desired thickness before depositing the bonding film 420.

[0051] Although FIG. 14 shows only a single first die 406 in a single layer, during the packaging process, a plurality of dies to be processed simultaneously may be placed above the carrier wafer 402. The filler material 419 may be injected into the cavities between adjacent dies. In some embodiments, the filler material 419 may include epoxy resin, resin, molding compound resin, or the like. After the filler material 419 is placed in the cavities between the dies, the filler material 419 may be cured to harden the filler material 419 for optimal protection. Although the exact curing process depends at least in part on the specific material selected for the filler material 419. In some embodiments, the filler material 419 may be cured by heating the filler material 419 to a temperature between about 100°C and about 130°C. A chemical mechanical polishing (CMP) process may be performed to remove the filler material 419 deposited above the first die 406 and to thin the substrate 412 in the first die 406.

[0052] In some embodiments, the bonding film 420 may be formed of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant dielectric material having a dielectric constant value less than about 3.0. The low dielectric constant dielectric material may include a carbon-containing low dielectric constant dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In some embodiments, the bonding film 420 may be formed by suitable manufacturing techniques, such as chemical vapor deposition (CVD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0053] In operation 306, bonding pad components 422 (also referred to as bond pad metals (BPMs)) are formed in the bonding film 420, as shown in FIGS. 16A, 16B, and 16C. FIG. 16A is a cross-sectional schematic view of the integrated circuit package 400 after operation 306. FIG. 16B is a plan view of the integrated circuit package along line B-B in FIG. 16A. FIG. 16C is a plan view of the integrated circuit package along line C-C in FIG. 16A.

[0054] The bonding pad component 422 can be formed of copper or other suitable metals to facilitate subsequent bonding. In some embodiments, the bonding pad component 422 can be formed through any suitable manufacturing technique, such as electroplating or deposition. In some embodiments, the bonding pad component 422 can be formed through an inlay process, such as a single inlay process or a dual inlay process. The bonding pad component 422 is configured to bond with the bonding pad component on the second die. The bonding pad components 422 are arranged in an area corresponding to the second die and in a pattern that matches the bonding pad components in the second die. FIG. 16B schematically shows the distribution of the bonding pad components 422 in the bonding film 420. The number of bonding pad components 422 can be less than or more than that shown in FIG. 16B. The bonding pad components 422 can be designed according to requirements and / or design layouts. In some embodiments, the top surface of the bonding pad component 422 and the top surface of the bonding film 420 are substantially coplanar to provide a suitable surface for subsequent bonding. Planarity can be achieved through, for example, a planarization step (such as a chemical mechanical polishing (CMP) step or a mechanical polishing step). After planarization, the first die 406 has a substantially flat bonding surface 406b, and the bonding surface 406b includes the area of the bonding film 420 and the area of the bonding pad components 422.

[0055] In some embodiments, a portion of the bonding pad component 422 is connected to through semiconductor vias (TSVs) 424. The semiconductor vias 424 are buried in the substrate. In some embodiments, the semiconductor vias 424 can be formed of copper or other suitable metals that are easy to form dielectric-dielectric (D-D) and metal-metal (M-M) bonds. In some embodiments, the semiconductor vias 424 can be formed simultaneously with the bonding pad component 422 through an inlay process. In other embodiments, the semiconductor vias 424 can be prefabricated together with the device layer 414 during the front-end process. The semiconductor vias 424 can be used to provide an electrical connection between the first die 406 and the second die bonded to the first die 406. The first end of the semiconductor via 424 contacts the bonding pad component 422, and the second end of the semiconductor via 424 contacts the conductive component 418 in the interconnect structure 416. The conductive component 418 can be connected to the active components and / or passive components in the device layer 414.

[0056] FIG. 16C schematically shows the distribution of the semiconductor vias 424 in the substrate 412. The number of semiconductor vias 424 can be less than or more than that shown in FIG. 16C. The number and layout of the semiconductor vias 424 are designed according to requirements and / or design layouts.

[0057] In operation 308, the second die 426 and one or more dummy dies 224 are bonded to the first die 406, as shown in FIGS. 17A-17B. FIG. 17A is a cross-sectional schematic view of the integrated circuit package 400 after operation 308. FIG. 17B is a plan view of the integrated circuit package along line B-B in FIG. 17A.

[0058] The second die 426 can be a logic die, a memory die, a three-dimensional integrated circuit die, a central processing unit die, a graphics processing unit die, a system-on-chip die, a microelectromechanical system die, or the like. The second die 426 can be a single die or a combined die, such as a chiplet having two or more dies. In some embodiments, the second die 426 can be a memory die.

[0059] The second die 426 can include a substrate 428, a device layer 430 formed in and on the substrate 428, and an interconnect structure 432 formed on the device layer 430. The interconnect structure 432 can include multiple dielectric materials with conductive components 434 formed therein. The second die 426 can include a dielectric layer 436 formed above the interconnect structure 432. The dielectric layer 436 includes bond pads 438 and bond vias 440 buried therein. A bond film 442 is formed on the dielectric layer 436. Bond pad components 444 are formed in the bond film 442.

[0060] The substrate 428 can include bulk silicon (doped or undoped) or the active layer of a silicon-on-insulator substrate. Generally, a silicon-on-insulator substrate includes a semiconductor material layer, such as silicon, germanium, silicon-germanium, silicon-on-insulator, silicon-germanium-on-insulator (SGOI), or a combination thereof. Other substrates including multi-layer substrates, graded substrates, or hybrid orientation substrates can be used. The device layer 430 is formed on the front side of the substrate 428. In operation 308, the second die 426 is bonded to the first die 406 with the back side of the substrate 428 facing up.

[0061] The device layer 430 includes various devices, such as transistors, capacitors, resistors, inductors, and the like, which can be used to generate the desired structures and functional requirements for the design of the second die 426.

[0062] The interconnect structure 432 is formed above the device layer 430 above the front side of the substrate 428. The conductive components 434 buried in the interconnect structure 432 are designed to connect various devices in the device layer 430 to form a functional circuit. The interconnect structure 432 is formed by alternating layers of dielectric and conductive materials and can be formed through any suitable process, such as deposition, damascene, dual damascene, etc.

[0063] The dielectric layer 436 may include one or more dielectric layers. In some embodiments, the material of the dielectric layer 436 may be silicon oxide, silicon nitride, silicon oxynitride, or a dielectric layer formed of other suitable dielectric materials. In some embodiments, the dielectric layer 436 may be undoped silicon glass, a low dielectric constant material, an ultra-low dielectric constant material, silicon oxide, or the like. The bonding pads 438 and the bonding vias 440 may be formed of aluminum, aluminum copper, or other suitable conductive materials.

[0064] In some embodiments, the bonding film 442 may be formed of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant dielectric material having a dielectric constant value less than about 3.0. The dielectric constant dielectric material may include a carbon-containing low dielectric constant dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. In some embodiments, the bonding film 442 may be formed through suitable manufacturing techniques such as chemical vapor deposition (CVD), high density plasma chemical vapor deposition (HDPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0065] The bonding pad component 444 may be formed of copper or other suitable metals to facilitate subsequent bonding. In some embodiments, the bonding pad component 444 may be formed through any suitable manufacturing technique such as electroplating or deposition. In some embodiments, the bonding pad component 444 may be formed through an inlay process such as a single inlay process or a dual inlay process. The bonding pad component 444 is configured to bond with the bonding pad component 422 on the first die 406. In some embodiments, the bonding pad component 444 is arranged in a layout that is a mirror image of the bonding pad component 422. A portion of the bonding pad component 444 contacts the bonding pad 438 through the bonding via 440 to provide an electrical connection to the components in the device layer 430.

[0066] In some embodiments, the top surface of the bonding pad component 444 and the top surface of the bonding film 442 are substantially coplanar to provide a suitable surface for subsequent bonding. Planarity can be achieved through, for example, a planarization step such as a chemical mechanical polishing (CMP) step or a mechanical polishing step. After planarization, the second die 426 has a substantially flat bonding surface 426b, and the bonding surface 426b includes the area of the bonding film 442 and the area of the bonding pad component 444.

[0067] In some embodiments, the first die 406 and the second die 426 may be bonded in a face-to-face manner, as shown in FIG. 17A. The bonding film 442 of the second die 426 is bonded to the bonding film 420 of the first die 406 through dielectric-to-dielectric bonding, and the bonding pad component 444 of the second die 426 is bonded to the bonding pad component 422 of the first die 406 through metal-to-metal bonding. The bonding process may be referred to as dielectric-to-dielectric and metal-to-metal bonding.

[0068] Before bonding the second die 426 to the first die 406, the second die 426 may be picked up and placed on the bonding surface 406b of the first die 406 such that the bonding surface 406b of the first die 406 directly contacts the bonding surface 426b of the second die 426, and the bonding pad component 422 is aligned and directly contacts the bonding pad component 444. In some embodiments, in order to facilitate dielectric-to-dielectric and metal-to-metal bonding between the first die 406 and the second die 426, surface preparation of the bonding surfaces of the first die 406 and the second die 426 may be performed. For example, the surface preparation may include surface cleaning and activation. In some embodiments, the bonding surface 406b of the first die 406 and the bonding surface 426b of the second die 426 may be cleaned by wet cleaning.

[0069] After bonding, dielectric-to-dielectric and metal-to-metal bonding surfaces are formed between the first die 406 and the second die 426. In some embodiments, the metal-to-metal bonding at the dielectric-to-dielectric and metal-to-metal bonding interface is copper-to-copper bonding. In some embodiments, the dielectric-to-dielectric bonding at the dielectric-to-dielectric and metal-to-metal bonding interface is achieved by generating Si-O-Si bonds. After bonding, the first die 406 is electrically connected to the second die 426 through the bonding between the bonding pad component 444 and the bonding pad component 422. During the dielectric-to-dielectric and metal-to-metal bonding process, a low-temperature heating process is performed in the range of about 100°C to about 280°C to strengthen the dielectric-to-dielectric bonding at the dielectric-to-dielectric and metal-to-metal bonding interface. A high-temperature heating process is performed in the range of about 100°C to about 400°C to promote the metal-to-metal bonding at the dielectric-to-dielectric and metal-to-metal bonding interface.

[0070] As shown in FIG. 17B, the second die 426 is smaller than the first die 406. One or more dummy dies 224 are bonded to the first die 406 such that the bottom layer and the top layer are of substantially the same size. FIG. 17B depicts four dummy dies 224. Depending on the design of the integrated circuit package 400, fewer or more dummy dies 224 may be included.

[0071] According to the shapes, sizes, and relative positions of the first die 406 and the second die 426, the shapes and sizes of each dummy die 224 can be selected. According to the surface area of the larger die or the first die 406 in the integrated circuit package 400, the surface area of each dummy die 224 can be selected. In some embodiments, the ratio of the surface area of each dummy die 224 to the surface area of the first die 406 can range between about 7.5% and about 10%. The shape of the dummy die 224 can be rectangular, square, or other shapes that conform to the layout.

[0072] Before bonding the dummy die 224 to the first die 406, the dummy die 224 can be picked up from a frame (such as the frame 228 in FIG. 10) and placed on the bonding surface 406b of the first die 406 such that the bonding surface 406b of the first die 406 directly contacts the bonding film 208 of the dummy die 224. In some embodiments, in order to facilitate dielectric-to-dielectric and metal-to-metal bonding between the dummy die 224 and the first die 406, surface preparation for the bonding surfaces of the first die 406 and the dummy die 224 can be performed. The surface preparation can include surface cleaning and activation.

[0073] The dummy dies 224 are stacked on and bonded to the first die 406. The dummy dies 224 are arranged side by side with each other and with the second die 426. In some embodiments, the dummy dies 224 are fusion bonded to the first die 406. In other words, the dummy dies 224 are bonded to the first die 406 through dielectric-to-dielectric bonding. In some embodiments, the dummy dies 224 can be bonded through a low-temperature heating process in the range of about 100°C to about 280°C to strengthen the dielectric-to-dielectric bonding. In some embodiments, the dummy dies 224 can be bonded to the first die 406 and the second die 426 can be bonded to the first die 406 in the same dielectric-to-dielectric and metal-to-metal bonding process. Alternatively, bonding the dummy dies 224 to the first die 406 and bonding the second die 426 to the first die 406 can be performed in separate bonding processes.

[0074] In operation 310, a dielectric film 446 is deposited over the integrated circuit package 400 to fill the gap between the dummy die 224 and the second die 426, as shown in FIG. 18. FIG. 18 is a cross-sectional schematic view of the integrated circuit package 400 after operation 310. In some embodiments, the dielectric film 446 may comprise an oxide material such as silicon oxide (SiO), tetraethoxysilane (TEOS), borophosphorous tetraethyl orthosilicate (BPTEOS), or the like. The dielectric film 446 may also be a nitride material. The dielectric film 446 may also be a low dielectric constant dielectric material, a polymer material, other dielectric materials, the like, or a combination of the foregoing. The dielectric film 446 may also be formed by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), plasma vapor deposition (PVD), or similar methods.

[0075] In operation 312, a planarization process is performed, as shown in FIG. 19. FIG. 19 is a cross-sectional schematic view of the integrated circuit package 400 after operation 312. The planarization process removes the excess dielectric film 446 over the dummy die 224 and the second die 426. The planarization process may also be used to thin the dummy die 224 and the second die 426 to produce a planar surface 448 for further processing.

[0076] In operation 314, a second carrier wafer 450 is attached to the integrated circuit package 400 on the surface 448, as shown in FIG. 20. FIG. 20 is a cross-sectional schematic view of the integrated circuit package 400 after operation 314. In some embodiments, a bonding film 452 is formed over the second carrier wafer 450. A bonding film 454 is formed over the planar surface 448 of the integrated circuit package 400. In some embodiments, the bonding films 452 and 454 are formed of an oxide material. For example, the bonding films 452 and 454 may comprise a dielectric material such as silicon oxide, silicon oxynitride, or the like.

[0077] The integrated circuit package 400 is attached to the second carrier wafer 450 through bonding films 452 and 454. After the second carrier wafer 450 is attached to the integrated circuit package 400, the carrier wafer 402 can be removed, and the integrated circuit package 400 can be flipped to form contacts above the front side of the first die 406. In some embodiments, surface preparation (such as surface cleaning and activation) can be performed to expose the topmost layer of the conductive component 418 for subsequent processing.

[0078] In operation 316, a redistribution layer (RDL) structure 456 and external connectors 464 are formed above the first die 406, as shown in FIG. 21. FIG. 21 is a cross-sectional schematic view of the integrated circuit package 400 after operation 316.

[0079] The redistribution layer structure 456 may include one or more conductive layers 462 formed in one or more passivation layers 458. In some embodiments, the redistribution layer structure 456 may include a protective layer 460 disposed above the passivation layer 458. The passivation layer 458 may be formed of a nitrogen-based material. The protective layer 460 may be formed of silicon oxide, silicon nitride, or a combination thereof. The conductive layer 462 may include metals such as aluminum, copper, tungsten, titanium, and combinations thereof. The conductive layer 462 can be deposited by chemical vapor deposition and the unwanted portions can be etched away, leaving the redistribution layer structure 456. Alternatively, other materials and processes (such as known damascene processes) can be used to form the redistribution layer structure 456.

[0080] The external connectors 464 can be contact bumps, such as microbumps or controlled collapse chip connection (C4) bumps. The external connectors 464 can include materials such as tin or other suitable materials such as silver or copper. In some embodiments, the external connectors 464 are tin solder bumps formed by any suitable method such as evaporation, electroplating, printing, solder transfer, or ball placement. After a tin layer has been formed on the structure, reflow soldering is performed to shape the material into the desired bump shape. A protective layer 466 can be formed between the redistribution layer structure 456 and the external connectors 464. In some embodiments, the protective layer 466 can be formed of polyimide or the like.

[0081] As shown in FIG. 21, the substrate 202 in the dummy die 224 and the substrate 412 in the first die 406 are bonded through the bonding film 420, the bonding film 208, the adjustment layer 206, and the adhesive layer 204. During operation, the heat generated in the device layer 414 can be dissipated from the substrate 412 to the substrate 202 through the bonding layers (i.e., the bonding film 420, the bonding film 208, the adjustment layer 206, and the adhesive layer 204). Since the adjustment layer 206 has improved thermal conductivity, heat dissipation is improved. In addition, since the adjustment layer 206 is used to cause warping of the dummy die 224, the effective bonding length between the dummy die 224 and the first die 406 is also improved, so as to improve the bonding quality. The improved bonding quality further improves the heat transfer between the dummy die 224 and the first die 406.

[0082] FIG. 22 is a flowchart of a method 500 for forming an integrated circuit package according to an embodiment of the present invention. FIGS. 23A-23D, 24A-24C, and 25 schematically show various processing stages during the manufacture of the integrated circuit package 600 using 500.

[0083] The method 500 is similar to the method 300, except that the method 500 includes operations 506 and 508 in place of operations 306 and 308 of the method 300. In operation 506, a dummy conductor is formed in the first die. In operation 508, the dummy die is bonded to the first die in the region having the dummy conductor. The method 500 starts with operations 302 and 304. The corresponding stages can be as shown in FIGS. 14 and 15.

[0084] In operation 506, a dummy conductor 602 other than the bonding pad component 422 is formed in the bonding film 420, as shown in FIGS. 23A and 23B. FIG. 23A is a schematic cross-sectional view of the integrated circuit package 600 after operation 506. FIG. 23B is a plan view of the integrated circuit package 600. FIGS. 23C and 23D are partial cross-sectional schematic views of the dummy conductor according to an embodiment of the present invention.

[0085] The dummy conductor 602 is a conductive component formed in the bonding film 420, such as a via or a wire. The dummy conductor 602 is configured to further improve the thermal conductivity between the first die 406 and the dummy die 224.

[0086] Similar to the bonding pad component 422, the dummy conductor 602 is a conductive component, wire, and / or via hole formed in the bonding film 420. As described above, at least a portion of the bonding pad component 422 is connected to the semiconductor vias 424 formed in the substrate 412 of the first die 406. The bonding pad component 422 is also intended to be connected to a conductor in the die to be bonded, such as the bonding pad component 444 in the second die 426. Unlike the bonding pad component 422, the dummy conductor 602 is electrically floating in the bonding film 420. That is, the dummy conductor 602 is not connected to any conductor in the first die 406. The dummy conductor 602 is also not connected to any conductive component in the die to be bonded (such as the dummy die 224).

[0087] The dummy conductor 602 can be formed of copper or other suitable metals. In some embodiments, the dummy conductor 602 can be formed by suitable manufacturing techniques, such as electroplating or deposition. The dummy conductor 602 can be formed by forming trenches and vias in the bonding film 420 and filling the trenches and vias in the bonding film 420. In some embodiments, the dummy conductor 602 can be formed by an inlay process, such as a single inlay process or a dual inlay process. In some embodiments, the dummy conductor 602 can be formed simultaneously with the bonding pad component 422.

[0088] After operation 506, the top surfaces of the dummy conductor 602 and the bonding pad component 422 and the top surface of the bonding film 420 are substantially coplanar to provide a suitable surface for subsequent bonding. Planarity can be achieved, for example, through a planarization step (such as a chemical mechanical polishing (CMP) step or a mechanical polishing step). After planarization, the first die 406 has a substantially flat bonding surface 606b, and the bonding surface 606b includes regions of the bonding film 420, regions of the bonding pad component 422, and regions of the dummy conductor 602.

[0089] In some embodiments, the dummy conductor 602 can have a height H in the bonding film 420. In some embodiments, the height H of the dummy conductor 602 can range between about 1 kÅ and about 20 kÅ. In some embodiments, the height H of the dummy conductor 602 can be substantially the same as the height of the bonding pad component 422.

[0090] In some embodiments, the height H of the dummy conductor 602 may be buried in the bonding film 420, as shown in FIG. 23A. In other embodiments, the dummy conductor 602 may have the same thickness as the bonding film 420, such that the dummy conductor 602 contacts the back side of the substrate 412, as shown in FIG. 23C. In other embodiments, the height H of the dummy conductor 602 may be greater than the thickness of the bonding film 420, such that the dummy conductor 602 extends into the substrate 412, as shown in FIG. 23D.

[0091] FIG. 23B schematically shows the distribution of the dummy conductors 602 in the bonding film 420. As shown in FIG. 23B, the arrangement of the dummy conductors 602 in the region of the bonding film 420 is configured to receive subsequently bonded dummy dies. FIG. 23B is a schematic depiction of the dummy conductors 602. The number, shape, and arrangement of the dummy conductors 602 can be arranged in any suitable manner. In some embodiments, the total surface area of the dummy conductors 602 may be selected first. The shape and layout of the dummy conductors 602 can be determined to achieve the total surface area.

[0092] In some embodiments, the total surface area of the dummy conductors 602 may be determined by the surface area of the dummy dies to be bonded. For example, the ratio of the total surface area of the dummy conductors 602 that are bonded to the dummy dies to the surface area of the dummy dies may range between about 0.03 and about 0.3.

[0093] In other embodiments, the surface area of the first die 406 (i.e., the die on which the dummy conductors 602 are formed) may affect the total surface area of the dummy conductors 602. For example, the ratio of the total surface area of the dummy conductors 602 to the surface area of the first die 406 may range between about 0.001 and about 0.01.

[0094] In other embodiments, the surface area of the second die 426 (i.e., the non-dummy die that is bonded to the first die 406) may affect the total surface area of the dummy conductors 602. For example, the ratio of the total surface area of the dummy conductors 602 to the surface area of the second die 426 may range between about 0.003 and about 0.03.

[0095] The dummy conductor 602 can be of any suitable shape and arrangement to achieve the total surface area. For example, the dummy conductor 602 can be a via hole with a size D in the range of about 0.01 mm to about 0.1 mm. In other embodiments, the dummy conductor 602 can be a wire with a width in the range of about 0.01 mm to about 0.1 mm and a length in the range of about 1 mm to about 10 mm. In some embodiments, the dummy conductors 602 can have the same size. In other embodiments, the dummy conductors 602 can have a mixed shape.

[0096] In some embodiments, the dummy conductors 602 can be distributed in one or more dummy regions 604. Each dummy region 604 can have a shape similar to that of the dummy die 224 to be bonded thereto. The dummy region 604 can be slightly smaller than the surface area of the dummy die 224 such that no conductor band is formed around the edge of the dummy die 224 after the bonding described in operation 508.

[0097] In operation 508, the second die 426 and one or more dummy dies 224 are bonded to the first die 406 as shown in FIGS. 24A - 24C. FIG. 24A is a cross-sectional schematic view of the integrated circuit package 600 after operation 508. FIG. 24B is a plan view of the integrated circuit package 600. FIG. 24C is a partial plan view showing the dummy conductors 602 relative to the dummy dies 224 after the bonding.

[0098] The first die 406 and the second die 426 can be bonded through a dielectric-to-dielectric and metal-to-metal bonding process as described in operation 308 above. The dummy dies 224 are bonded to the first die 406 via the dummy conductors 602 in the bonding surface. The dummy dies 224 are positioned side by side and side by side with the second die 426 above the region of the dummy conductors 602. In some embodiments, the dummy dies 224 are fusion bonded to the first die 406. In some embodiments, the dummy dies 224 can be bonded through a low-temperature heating process in the range of about 100°C to about 280°C to strengthen the dielectric-to-dielectric bonding.

[0099] In some embodiments, the dummy dies 224 are aligned and positioned above the corresponding dummy regions 604 such that no conductor band 606 is formed in the edge region of each dummy die 224 as shown in FIG. 24C. The conductor band 606 reduces the non-bonded length near the edge region of the dummy die 224, thereby improving the bonding quality. In some embodiments, the conductor band 606 can have a width BW in the range of about 1 mm to about 2 mm.

[0100] In some embodiments, the dummy die 224 may be bonded to the first die 406 and the second die 426 may be bonded to the first die 406 in the same dielectric-to-dielectric and metal-to-metal bonding processes. Alternatively, bonding the dummy die 224 to the first die 406 and bonding the second die 426 to the first die 406 may be performed in separate bonding processes.

[0101] After operation 508, operations 310, 312, 314, and 316 of the above method 300 may be performed. FIG. 25 is a cross-sectional schematic view of the integrated circuit package 600 after operation 316.

[0102] As shown in FIG. 25, the substrate 202 in the dummy die 224 and the substrate 412 in the first die 406 are bonded through a film stack, which includes a bonding film 420 having a dummy conductor 602, a bonding film 208, an adjustment layer 206, and an adhesive layer 204. During operation, heat generated in the device layer 414 may dissipate from the substrate 412 to the substrate 202 through the film stack. In addition to the material in the adjustment layer 206, the thermal conductivity of the film stack is further improved by the presence of the dummy conductor 602 in the bonding film 420.

[0103] Embodiments of the present invention provide a dummy die with an improved bonding structure. Specifically, the dummy die according to embodiments of the present invention increases the thermal conductivity through the dummy die and improves the warpage adjustment with a thinner film. Embodiments of the present invention further include a dummy conductor to bond with the dummy die, which further increases the thermal conductivity. The increased thermal conductivity improves the heat dissipation in the integrated circuit package according to embodiments of the present invention.

[0104] It should be understood that not all advantages need to be discussed herein, and for all embodiments or examples, no specific advantage is required, and different embodiments or examples may provide different advantages.

[0105] Some embodiments of the present invention relate to a semiconductor package, which includes: a first die having a first bonding film; a second die stacked above the first die and bonded to the first die through the first bonding film; and a dummy die stacked above the first die and bonded to the first die through the first bonding film, wherein the dummy die includes: a substrate; an adjustment layer formed above the substrate, wherein the adjustment layer has a thermal conductivity in the range of about 30 W / mK to about 100 W / mK; and a second bonding film formed above the adjustment layer, wherein the second bonding film is bonded to the first bonding film.

[0106] In some other embodiments, the adjustment layer comprises silicon nitride or silicon carbide.

[0107] In some other embodiments, the adjustment layer has a thickness in the range of from about 3 kÅ to about 6 kÅ.

[0108] In some other embodiments, the second bonding film has a thickness in the range of from about 100 Å to about 1000 Å.

[0109] In some other embodiments, the second bonding film comprises silicon oxide.

[0110] In some other embodiments, the semiconductor package further comprises: an adhesive layer disposed between the substrate and the adjustment layer.

[0111] In some other embodiments, the adhesive layer comprises silicon oxide.

[0112] In some other embodiments, the semiconductor package further comprises: one or more dummy conductors formed in the first bonding film, wherein the one or more dummy conductors contact the second bonding film.

[0113] In some other embodiments, the first bonding film includes a zone surrounding the one or more dummy conductors, the zone contacting an edge region of the dummy die, and the one or more dummy conductors are disposed in the zone.

[0114] Some embodiments of the present invention relate to a method that includes: bonding a first die to a second die, wherein the first die includes a first bonding film and the second die is bonded to the first bonding film; and bonding a dummy die to the first die, wherein the dummy die includes: a substrate; an adjustment layer formed over the substrate, wherein the adjustment layer has a thermal conductivity in the range of from about 30 W / mK to about 100 W / mK; and a second bonding film formed over the adjustment layer, and the first bonding film is bonded to the second bonding film.

[0115] In some other embodiments, the adjustment layer comprises silicon nitride or silicon carbide.

[0116] In some other embodiments, the above method further includes forming one or more dummy conductors in the first bonding film, wherein the step of bonding the dummy die to the first die includes placing the dummy die above the one or more dummy conductors.

[0117] In some other embodiments, the steps of bonding the first die to the second die and bonding the dummy die to the first die are performed simultaneously.

[0118] In some other embodiments, the above method further includes: depositing a dielectric material between the second die and the dummy die; and forming an external connector above the first die, wherein the external connector and the first bonding film are disposed above two sides of the first die.

[0119] Some embodiments of the present invention relate to a method for forming a dummy die, the method including: depositing an adjustment layer on a front side of a semiconductor substrate; depositing a bonding film on the adjustment layer; forming a cutting pattern above the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the cutting pattern to form cutting grooves; depositing a protective layer in the cutting grooves and on the bonding film; attaching a carrier wafer to the protective layer; and grinding the semiconductor substrate from a back side to expose the protective layer in the cutting grooves.

[0120] In some other embodiments, the above method further includes: depositing an adhesive layer on a front side of the semiconductor substrate, and the adjustment layer is deposited on the adhesive layer.

[0121] In some other embodiments, the adhesive layer includes silicon oxide.

[0122] In some other embodiments, the adjustment layer includes silicon nitride or silicon carbide.

[0123] In some other embodiments, the above method further includes: after grinding the semiconductor substrate, attaching an expansion tape to a back side of the semiconductor substrate; and stretching the expansion tape to widen the cutting grooves.

[0124] In some other embodiments, the above method further includes: removing the protective layer to expose the bonding film.

[0125] The foregoing text outlines the features of many embodiments, enabling those with ordinary knowledge in the technical field to better understand the embodiments of the present invention from various aspects. Those with ordinary knowledge in the technical field should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention.

[0126] 100, 300, 500: Method 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 302, 304, 306, 308, 310, 312, 314, 316, 506, 508: Operation 200: dummy substrate 202, 412, 428: substrate 202f, 408: front side 202b, 410: back side 204: adhesive layer 206: adjustment layer 208, 420, 442, 452, 454: bonding film 210: photoresist layer 212: groove 214: scribe groove 216, 604: dummy area 218, 460, 466: protective layer 220: back grinding tape 222, 402: carrier wafer 224: dummy die 226: expansion tape 228: frame 226’: second expansion tape 228’: second frame 230: ultraviolet radiation 250, 252, 262: curve 260: contour 264, 266: line 400, 600: integrated circuit package 406: first die 406b, 426b, 606b: bonding surface 414,430: Device layer 416,432: Interconnection structure 418,434: Conductive component 419: Filling material 422,444: Bonding pad component 424: Semiconductor via 426: Second die 436: Dielectric layer 438: Bonding pad 440: Bonding via hole 446: Dielectric film 448: Surface 450: Second carrier wafer 456: Redistribution layer structure 458: Passivation layer 462: Conductive layer 464: External connector 602:Dummy conductor 606: Conductorless tape D: Dimension H: Height T1,T2: Thickness W1,W1’,W1’’,BW: Width

Claims

1. A semiconductor package comprising: a first die having a first bonding film; a second die stacked on the first die and bonded to the first die through the first bonding film; and a dummy die stacked on the first die and bonded to the first die through the first bonding film, wherein the dummy die comprises: a substrate; an adjustment layer formed on the substrate, wherein the adjustment layer has a thermal conductivity in the range of about 30 W / mK to about 100 W / mK, wherein the adjustment layer comprises silicon nitride, and the thickness of the adjustment layer is in the range of about 3000 Å to about 6000 Å; and a second bonding film formed on the adjustment layer, wherein the second bonding film is bonded to the first bonding film, wherein the thickness of the second bonding film is less than the thickness of the adjustment layer.

2. The semiconductor package of claim 1, wherein the second bonding film comprises silicon oxide.

3. The semiconductor package of claim 2 further includes: an adhesive layer disposed between the substrate and the adjustment layer.

4. The semiconductor package of claim 3, wherein the adhesive layer comprises silicon oxide.

5. The semiconductor package of any one of claims 1 to 4 further includes: one or more dummy conductors formed in the first bonding film, wherein the one or more dummy conductors contact the second bonding film.

6. The semiconductor package of claim 5, wherein the first bonding film includes a band surrounding the one or more dummy conductors, the band contacting an edge region of the dummy die, and the one or more dummy conductors being disposed in the band.

7. A method of forming a semiconductor package, comprising: bonding a first die to a second die, wherein the first die includes a first bonding film and the second die is bonded to the first bonding film; and bonding a dummy die to the first die, wherein the dummy die includes: a substrate; an adjustment layer formed over the substrate, wherein the adjustment layer has a thermal conductivity in the range of about 30 W / mK to about 100 W / mK, wherein the adjustment layer includes silicon nitride and the thickness of the adjustment layer is in the range of about 3000 Å to about 6000 Å; and a second bonding film formed over the adjustment layer, wherein the first bonding film is bonded to the second bonding film, wherein the thickness of the second bonding film is less than the thickness of the adjustment layer.

8. The method of forming a semiconductor package as claimed in claim 7 further includes forming one or more dummy conductors in the first bonding film, wherein the step of bonding the dummy die to the first die includes placing the dummy die over the one or more dummy conductors.

9. A method for forming a semiconductor package as claimed in claim 7 or 8, wherein the steps of bonding the first die to the second die and bonding the dummy die to the first die are performed simultaneously.

10. The method of forming a semiconductor package as claimed in claim 7 or 8 further includes: depositing a dielectric material between the second die and the dummy die; and forming an external connector above the first die, wherein the external connector and the first bonding film are disposed above both sides of the first die.

11. A method for forming a dummy die, comprising: depositing an adjustment layer on a front side of a semiconductor substrate, wherein the adjustment layer comprises silicon nitride and the thickness of the adjustment layer is in the range of about 3000 Å to about 6000 Å; depositing a bonding film on the adjustment layer, wherein the thickness of the bonding film is less than the thickness of the adjustment layer; forming a dicing pattern over the bonding film; etching through the bonding film, the adjustment layer, and into the semiconductor substrate using the dicing pattern to form a dicing trench; depositing a protective layer in the dicing trench and on the bonding film; attaching a carrier wafer to the protective layer; and grinding the semiconductor substrate from a back side to expose the protective layer in the dicing trench.

12. The method for forming a dummy die as claimed in claim 11 further includes: depositing an adhesive layer on the front side of the semiconductor substrate, and depositing the adjustment layer on the adhesive layer.

13. The method for forming a dummy die as claimed in claim 11 or 12 further includes: attaching an expansion tape to the back side of the semiconductor substrate after grinding the semiconductor substrate; and stretching the expansion tape to widen the dicing groove.

14. The method for forming a dummy grain as claimed in claim 13 further includes: removing the protective layer to expose the bonding film.

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