Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes: a first redistribution substrate; a first semiconductor wafer located on the first redistribution substrate; a second redistribution substrate located on the first semiconductor wafer; an inter-substrate through electrode located on one side of the first semiconductor wafer on the first redistribution substrate and connecting the first redistribution substrate to the second redistribution substrate; a second semiconductor wafer located on the first semiconductor wafer; and a heat dissipation structure located on the second semiconductor wafer.

Description

Semiconductor Package and Method of Manufacturing the Same Embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. [Cross-reference to Related Applications] This application is based on and claims priority to Korean Patent Application No. 10-2023-0039025, filed on Mar. 24, 2023, and Korean Patent Application No. 10-2023-0054200, filed on Apr. 25, 2023, with the Korean Intellectual Property Office, the entire disclosures of each of the Korean patent applications being incorporated herein by reference in their entirety. Due to the rapid development of the electronics industry and the demands of users, electronic devices have become more compact and lightweight. As electronic devices are miniaturized and their weight is reduced, semiconductor packages used in the electronic devices are also miniaturized and lightweight, and thus, the semiconductor packages can have high reliability, high performance, and large capacity. Embodiments can be achieved by providing a semiconductor package including: a first redistribution layer substrate; a first semiconductor chip disposed on the first redistribution layer substrate; a second redistribution layer substrate disposed on the first semiconductor chip; an inter-substrate through-electrode disposed on the first redistribution layer substrate at one side of the first semiconductor chip and connecting the first redistribution layer substrate to the second redistribution layer substrate; a second semiconductor chip disposed on the first semiconductor chip; and a heat dissipation structure disposed on the second semiconductor chip. Embodiments can be achieved by providing a semiconductor package including: a first redistribution layer substrate; a stacked chip structure disposed on the first redistribution layer substrate; a second redistribution layer substrate disposed on the stacked chip structure; an inter-substrate through-electrode disposed on the first redistribution layer substrate on one side of the stacked chip structure and connecting the first redistribution layer substrate to the second redistribution layer substrate; and a heat dissipation structure disposed on the second redistribution layer substrate at a portion corresponding to the stacked chip structure, wherein the stacked chip structure includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and an interposer chip disposed on the first semiconductor chip and at one side of the second semiconductor chip. An embodiment can be achieved by providing a semiconductor package, the semiconductor package including: a first redistribution substrate; a first semiconductor chip located on the first redistribution substrate; a second redistribution substrate located on the first semiconductor chip; an inter-substrate through electrode located on one side of the first semiconductor chip on the first redistribution substrate and connecting the first redistribution substrate to the second redistribution substrate; a second semiconductor chip located on the first semiconductor chip; and a memory device located on the second redistribution substrate, wherein the memory device and the second semiconductor chip are configured to exchange the memory signal without the memory signal passing through the first redistribution substrate. An embodiment can be achieved by providing a method of manufacturing a semiconductor package, the method including: preparing a first redistribution substrate; mounting a first semiconductor chip on the first redistribution substrate; forming an inter-substrate through electrode on one side of the first semiconductor chip on the first redistribution substrate; sealing the inter-substrate through electrode and the first semiconductor chip with a sealant; forming a second redistribution substrate on the first semiconductor chip, the inter-substrate through electrode, and the sealant; and mounting a second semiconductor chip on the first semiconductor chip or the second redistribution substrate. An embodiment can be achieved by providing a method of manufacturing a semiconductor package, the method including: preparing a first redistribution substrate; mounting a stacked chip structure on the first redistribution substrate; forming an inter-substrate through electrode on one side of the stacked chip structure on the first redistribution substrate; sealing the inter-substrate through electrode and the stacked chip structure with a sealant; forming a second redistribution substrate on the stacked chip structure, the inter-substrate through electrode, and the sealant; and stacking a memory device and a heat dissipation structure on the second redistribution substrate, wherein mounting the stacked chip structure includes: mounting a second semiconductor chip on a first semiconductor chip; mounting an interposer chip on one side of the second semiconductor chip on the first semiconductor chip; and mounting the first semiconductor chip on the first redistribution substrate. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements and will not be described redundantly. FIG. 1 is a cross-sectional view of a semiconductor package 1000 according to an embodiment. FIG. 2 is a more detailed cross-sectional view of the first semiconductor chip in the semiconductor package 1000 shown in FIG. 1. Referring to FIGS. 1 and 2, the semiconductor package 1000 according to an embodiment may include a lower package 100, a heat dissipation structure 200, a memory device 300, external connection terminals 400, and passive devices 500. The lower package 100 may include a first redistribution substrate 110, a first semiconductor chip 120, a second redistribution substrate 130, an inter-substrate via electrode 140, a sealant 150, and a second semiconductor chip 160. The first redistribution substrate 110 may be located below the first semiconductor chip 120 and may redistribute the chip pads of the first semiconductor chip 120 to an external area of the first semiconductor chip 120. In an embodiment, the first redistribution substrate 110 may include a first body insulating layer 112 and a first redistribution line 114. The first redistribution line 114 may be formed in multiple layers and may be connected to each other by vias. The first body insulating layer 112 may include an insulating material such as a photo imageable dielectric (PID) resin and may further include an inorganic filler. In an embodiment, according to the multi-layer structure of the first redistribution line 114, the first body insulating layer 112 may have a multi-layer structure. In an embodiment, as shown in FIG. 1, the first body insulating layer 112 may be a single layer structure. In an embodiment, the first body insulating layer 112 may have a multi-layer structure, and different layers of the first body insulating layer 112 may include the same material or different materials from each other. The external connection terminal 400 may be located on the lower surface of the first body insulating layer 112. The external connection terminal 400 may be located on an external connection pad on the lower surface of the first body insulating layer 112. The external connection terminal 400 may be electrically connected to the first semiconductor chip 120 through the first redistribution line 114 of the first redistribution substrate 110 and the bump 125. The external connection terminal 400 may be located on a first lower surface of the first redistribution substrate 110 corresponding to the lower surface of the first semiconductor chip 120 and on a second lower surface of the first redistribution substrate 110 extending outward from the first lower surface in the x direction. In an embodiment, a package structure in which the external connection terminal 400 is disposed in an area wider than the lower surface of the first semiconductor chip 120 may be referred to as a fan-out (FO) package structure. In an embodiment, a package structure in which the external connection terminal 400 is only located on a portion corresponding to the lower surface of the first semiconductor chip 120 may be referred to as a fan-in (FI) package structure. The first semiconductor chip 120 may be mounted on the first redistribution substrate 110 by the bump 125. The bump 125 may include, for example, a pillar and solder. In an embodiment, the bump 125 may include only solder. The first semiconductor wafer 120 may be located on one side (in the x direction) of the first redistribution substrate 110. In an embodiment, as shown in FIG. 1, the first semiconductor wafer 120 may be displaced or offset to the right in the x direction on the first redistribution substrate 110. In an embodiment, the first semiconductor wafer 120 may be offset to the right in the x direction, and the second semiconductor wafer 160 and the heat dissipation structure 200 located on the second semiconductor wafer 160 may also be offset to the right. Such an arrangement structure may be a method to help effectively dissipate the heat generated from the first semiconductor wafer 120 and the second semiconductor wafer 160. The first semiconductor wafer 120 may be an analog chip. In an embodiment, the first semiconductor wafer 120 may be a modem chip that supports the communication of the second semiconductor wafer 160. In an embodiment, the first semiconductor wafer 120 may include various types of integrated devices that support the operation of the second semiconductor wafer 160. The first semiconductor wafer 120 may include a multi-channel input / output (I / O) interface for exchanging memory signals with the memory device 300. In an embodiment, as shown in FIG. 2, the first semiconductor wafer 120 may include a substrate 121, a device layer 123, a back wiring layer 127, and a through electrode 129. The substrate 121 may constitute the body of the first semiconductor wafer 120 and may be based on a silicon substrate. The device layer 123 may be located on the lower portion of the substrate 121. In an embodiment, the device layer 123 may include an integrated circuit layer and a multi-wiring layer connected to the integrated circuit layer, and active devices such as transistors are provided in the integrated circuit layer. In an embodiment, the multi-wiring layer may occupy most of the device layer 123, and the integrated circuit layer may occupy only a part of the device layer 123. In an embodiment, as shown in FIG. 2, most of the device layer 123 may be a multi-wiring layer, and the integrated circuit layer may be located on the upper portion of the central portion of the device layer 123. In an embodiment, as the name implies, the multi-wiring layer may include wires of multiple layers, and the wires of different layers may be connected to each other by vias. Chip pads connected by wires may be located on the lower surface of the device layer 123, and the bumps 125 may be located on the chip pads. The back wiring layer 127 may be located on the substrate 121. The wire can be located in the back wiring layer 127, and the wire can be single-layer or multi-layer. In the case of multi-layer wiring, the wirings of different layers can be connected to each other by vias. The upper pads connected to the wire can be located on the upper surface of the back wiring layer 127. The rewiring lines of the second rewiring substrate 130 can be connected to the upper pads of the back wiring layer 127. The through electrode 129 can pass through the substrate 121 to connect the wires of the back wiring layer 127 and the wires of the device layer 123 to each other. In an embodiment, the through electrode 129 can penetrate the silicon constituting the substrate 121, and the through electrode 129 can be referred to as a through silicon via (TSV). In an embodiment, the through electrode 129 can include a via-first structure formed before the integrated circuit layer forming the device layer 123, a via-middle structure formed after forming the integrated circuit layer and before forming the multi-wiring layer of the device layer 123, and a via-last structure formed after forming the multi-wiring layer. In an embodiment, in FIG. 1, the through electrode 129 can correspond to, for example, the via-middle structure. In the semiconductor package 1000 according to the embodiment, the through electrode 129 can be formed as the via-first structure or the via-last structure. In the first semiconductor wafer 120, the lower surface can be the front surface as the active surface, and the upper surface can be the back surface as the inactive surface. In an embodiment, the lower surface of the device layer 123 can correspond to the front surface of the first semiconductor wafer 120, and the upper surface of the back wiring layer 127 can correspond to the back surface of the first semiconductor wafer 120. The chip pads can be located on the front surface as the active surface, and the first semiconductor wafer 120 can be mounted on the first rewiring substrate 110 in a flip-chip structure by the bumps 125 on the chip pads. The second rewiring substrate 130 can be located on the first semiconductor wafer 120, the inter-substrate through electrode 140, and the sealant 150. The second redistribution substrate 130 may have a structure similar to that of the first redistribution substrate 110 and may have a thickness different from that of the first redistribution substrate 110. In an embodiment, the second redistribution substrate 130 may include a body insulating layer and redistribution lines, and the number of layers of the redistribution lines may be less than the number of layers of the first redistribution lines 114 of the first redistribution substrate 110. In an embodiment, the number of layers of the redistribution lines of the second redistribution substrate 130 may be substantially the same as the number of layers of the first redistribution lines 114 of the first redistribution substrate 110. In an embodiment, the redistribution lines of the second redistribution substrate 130 may be electrically connected to the external connection terminals 400 through the inter-substrate through electrodes 140 and the first redistribution lines 114 of the first redistribution substrate 110. The inter-substrate through electrodes 140 may be located between the first redistribution substrate 110 and the second redistribution substrate 130. In an embodiment, the sealant 150 may be located between the first redistribution substrate 110 and the second redistribution substrate 130, and the inter-substrate through electrodes 140 may have a structure extending through the sealant 150. The inter-substrate through electrodes 140 may electrically connect the first redistribution substrate 110 and the second redistribution substrate 130. In an embodiment, the inter-substrate through electrodes 140 may be connected to the first redistribution lines 114 of the first redistribution substrate 110 and may also be connected to the redistribution lines of the second redistribution substrate 130. The inter-substrate through electrodes 140 may include, for example, Cu. In an embodiment, the inter-substrate through electrodes 140 may be formed by electroplating using a seed metal. The inter-substrate through electrodes 140 may be referred to as Cu pillars or through posts. The seed metal may include, for example, Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). In the semiconductor package 1000 according to an embodiment, the seed metal may be included as part of the inter-substrate through electrodes 140. In an embodiment, the seed metal may include Cu, and the inter-substrate through electrodes 140 may also include Cu. In FIG. 1, the seed metal is not shown separately. The sealant 150 may be located between the first redistribution substrate 110 and the second redistribution substrate 130. As used herein, the term "or" is not necessarily an exclusive term. For example, "A or B" will include A, B, or both A and B. The sealant 150 may cover and seal the side surfaces of the first semiconductor wafer 120. Additionally, the sealant 150 may cover the side surfaces of the inter-substrate vias 140. In an embodiment, as shown in FIG. 1, the sealant 150 may be filled between the first redistribution substrate 110 and the first semiconductor wafer 120 and between the bumps 125 on the lower surface of the first semiconductor wafer 120. In an embodiment, an underfill may be filled between the bumps 125 on the lower surface of the first semiconductor wafer 120, and the sealant 150 may cover the side surfaces of the first semiconductor wafer 120 and the side surfaces of the underfill. The sealant 150 may include an insulating material such as a thermosetting resin (e.g., an epoxy resin), a thermoplastic resin (e.g., polyimide), or a resin containing a reinforcing material (e.g., an inorganic filler). In an embodiment, the sealant 150 may include an Ajinomoto Build-up Film (ABF), FR-4, or a Bismaleimide Triazine (BT) resin. In an embodiment, the sealant 150 may include a molding material such as an epoxy molding compound (EMC) or a photosensitive material such as a photo imageable encapsulant (PIE). The second semiconductor wafer 160 may be mounted on the second redistribution substrate 130. In an embodiment, the second semiconductor wafer 160 may be located on the right side of the second redistribution substrate 130 in the x direction, e.g., corresponding to the position of the first semiconductor wafer 120. In an embodiment, the second semiconductor wafer 160 may be located above the first semiconductor wafer 120, and the signal path between the first semiconductor wafer 120 and the second semiconductor wafer 160 may be minimized. The second semiconductor wafer 160 may be mounted on the second redistribution substrate 130 by, for example, fine bumps. In an embodiment, the second semiconductor wafer 160 may be mounted on the second redistribution substrate 130 by pad-to-pad bonding, hybrid bonding (HB), or bonding using an anisotropic conductive film (ACF). In an embodiment, the pad may include Cu, and pad-to-pad bonding is also referred to as Cu-to-Cu bonding. HB may represent a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF is an anisotropic conductive film formed to conduct electricity in only one direction, and may represent a conductive film formed by mixing fine conductive particles and a bonding resin into a film state. In semiconductor package 1000 according to an embodiment, the second semiconductor chip 160 may be mounted on the second redistribution substrate 130 using HB, the substrate pads of the second redistribution substrate 130 may be coupled to the pads of the second semiconductor chip 160, and the body insulation layer of the second redistribution substrate 130 may be coupled to the insulation layer of the second semiconductor chip 160. The second semiconductor chip 160 may include a plurality of logic elements. Here, the logic element may refer to an element that performs various signal processes by including, for example, logic circuits (such as AND, OR, NOT, flip-flop, etc.). In semiconductor package 1000 according to an embodiment, the second semiconductor chip 160 may be, for example, an application processor (AP) chip. Depending on the function of the second semiconductor chip 160, the second semiconductor chip 160 may also be referred to as a control chip, a processing chip, a central processing unit (CPU) chip, etc. The second semiconductor chip 160 may include a substrate and a device layer, and different from the first semiconductor chip 120, may not include a back-end wiring layer and a through electrode. The device layer may include an integrated circuit layer and a multi-wiring layer. The integrated circuit layer may include a plurality of integrated elements. The multi-wiring layer may be located below the integrated circuit layer and may include multi-layered wires. In the second semiconductor chip 160, the lower surface may be the front surface as the effective surface, and the upper surface may be the back surface as the ineffective surface. In an embodiment, the lower surface of the device layer may correspond to the front surface of the second semiconductor chip 160, and the upper surface of the substrate may correspond to the back surface of the second semiconductor chip 160. The heat dissipation structure 200 may be stacked on the second semiconductor chip 160 by the adhesive layer 210. The heat dissipation structure 200 may include, for example, a heatsink or a heatslug. The bonding layer 210 may include a material with high thermal conductivity. In an embodiment, the bonding layer 210 may comprise a thermal interface material (TIM) or a thermally conductive resin. The TIM may include materials with high thermal conductivity (e.g., low thermal resistance) such as grease, tape, an elastomer filling pad, or a phase change material. The memory device 300 may be mounted on the second redistribution substrate 130 adjacent to the second semiconductor wafer 160. The memory device 300 may be a single chip or may be a package including multiple chips. In an embodiment, the memory device 300 may be a package, and the semiconductor package 1000 according to the embodiment may correspond to a package on package (POP) structure. In an embodiment, the semiconductor package 1000 may have a structure in which the memory device 300 as an upper package is stacked on the lower package 100. The memory device 300 may be mounted on the second redistribution substrate 130 in a flip chip bonding structure or a wire bonding structure. The various structures and bonding structures of the memory device 300 will be described in more detail in the description of FIGS. 4A to 4C. The external connection terminals 400 may be located on the external connection pads on the lower surface of the first redistribution substrate 110 and may be electrically connected to the first redistribution lines 114 through the external connection pads. The external connection terminals 400 may connect the semiconductor package 1000 to a package substrate of an external system or a main board of an electronic device such as a mobile device. The external connection terminals 400 may include conductive materials such as solder, tin (Sn), silver (Ag), copper (Cu), or aluminum (Al). The passive device 500 may be located on the lower surface of the first redistribution substrate 110. In an embodiment, the passive device 500 may be located on or inside the first redistribution substrate 110. In an embodiment, the passive device 500 may be located on the lower surface, upper surface, or inside the second redistribution substrate 130. The passive device 500 may include two-terminal components such as resistors, inductors, or capacitors. In the semiconductor package 1000 according to the embodiment, the passive device 500 may include a multi-layer ceramic capacitor (MLCC) 510 and an Si capacitor 520. In the semiconductor package 1000 according to the embodiment, only the first semiconductor wafer 120 may be located between the first redistribution substrate 110 and the second redistribution substrate 130. In an embodiment, the distance between the first rewiring substrate 110 and the second rewiring substrate 130 can be reduced, thereby reducing the size and pitch of the inter-substrate vias 140. In this way, the thickness and size of the entire semiconductor package 1000 can be reduced. Additionally, in the semiconductor package 1000 according to an embodiment, the heat dissipation structure 200 can be directly stacked on the second semiconductor chip 160, and the upper surface of the first semiconductor chip 120 can directly contact the lower surface of the second rewiring substrate 130. Accordingly, the heat generated from the first semiconductor chip 120 and the second semiconductor chip 160 can be effectively dissipated through the second rewiring substrate 130 and the heat dissipation structure 200. In addition, in the semiconductor package 1000 according to an embodiment, the signal transmission path for exchanging memory signals between the memory device 300 and the second semiconductor chip 160 can be minimized. In an embodiment, the memory signals between the memory device 300 and the second semiconductor chip 160 can be transmitted through the second rewiring substrate 130 and the semiconductor chip 120, and the memory signals do not pass through the inter-substrate vias 140 and the first rewiring substrate 110. In this way, the operating performance of the semiconductor package 1000 according to an embodiment can be significantly improved at the system level. In an embodiment, the operating performance can include, for example, heat reduction, signal integrity (SI) improvement, power ratio (performance / power consumption) improvement, etc. The signal transmission path between the memory device 300 and the second semiconductor chip 160 in the semiconductor package 1000 according to an embodiment will be described in more detail in the description of FIGS. 3A and 3B. FIGS. 3A and 3B are cross-sectional views showing the transmission paths of the memory signals in the semiconductor package Com. according to a comparative example and the transmission paths of the memory signals in the semiconductor package 1000 shown in FIG. 1. Referring to FIGS. 3A and 3B, the semiconductor package Com. according to the comparative example can have a structure in which the second semiconductor chip 2nd-CH is stacked on the first semiconductor chip 1st-CH, and the first semiconductor chip 1st-CH can be mounted on the first rewiring substrate 1st-RDL. The first semiconductor chip 1st-CH and the second semiconductor chip 2nd-CH can be sealed using a sealant Mo, and the second redistribution layer substrate 2nd-RDL can cover the sealant Mo and the second semiconductor chip 2nd-CH. The through-via pillar Cu-P can penetrate the sealant Mo to connect the first redistribution layer substrate 1st-RDL to the second redistribution layer substrate 2nd-RDL. A heat sink HS can be stacked on the second redistribution layer substrate 2nd-RDL corresponding to the position of the second semiconductor chip 2nd-CH, and a memory element Me can be installed adjacent to one side of the heat sink HS on the second redistribution layer substrate 2nd-RDL. In the semiconductor package Com. according to the comparative example having such a structure as described above, as indicated by the arrow, the transmission of the memory signal between the memory element Me and the second semiconductor chip 2nd-CH can be achieved via the second redistribution layer substrate 2nd-RDL, the through-via pillar Cu-P, the first redistribution layer substrate 1st-RDL, and the first semiconductor chip 1st-CH. Here, the memory signal can refer to a signal related to storing information in the memory element Me and reading information from the memory element Me. In FIG. 3A, PD1 and PD2 can represent passive components, SB represents solder balls, Mo represents a sealing material, and Bm represents bumps. In contrast, in the semiconductor package 1000 according to the embodiment, only the first semiconductor chip 120 can be located between the first redistribution layer substrate 110 and the second redistribution layer substrate 130, and the second semiconductor chip 160 can be disposed on the second redistribution layer substrate 130. In addition, in the semiconductor package 1000 according to the embodiment, the transmission of the memory signal between the memory device 300 and the second semiconductor chip 160, as indicated by the arrow, can be implemented via the second wiring substrate 130 and the first semiconductor chip 120, and can be not through the inter-substrate via electrodes 140 and the first wiring substrate 110. In the embodiment, the signal transmission path can be described in more detail by using the structure of the first semiconductor chip 120 shown in FIG. 2, and the memory device 300 and the second semiconductor chip 160 can exchange memory signals via the second wiring substrate 130, the post-wiring layer 127, the via electrode 129, the device layer 123, the via electrode 129, the post-wiring layer 127, and the second wiring substrate 130. Therefore, in the semiconductor package 1000 according to the embodiment, the inter-substrate via electrodes 140 and the first wiring substrate 110 can be not used for the transmission of the memory signal, and the signal transmission path of the memory signal can be minimized. In addition, the inter-substrate via electrodes 140 can be only used for power transmission and ground transmission, and the number of the inter-substrate via electrodes 140 can be significantly reduced. In addition, the distance between the first wiring substrate 110 and the second wiring substrate 130 can be reduced, and the length of the inter-substrate via electrodes 140 can also be reduced. In this way, the size and pitch of the inter-substrate via electrodes 140 can be significantly reduced, and the size and thickness of the entire semiconductor package 1000 can be reduced. In the embodiment, in the semiconductor package 1000 according to the embodiment, power and ground can be externally applied to the memory device 300 via the first wiring substrate 110, the inter-substrate via electrodes 140, and the second wiring substrate 130. FIGS. 4A to 4C are cross-sectional views showing the structure of the memory device 300 in the semiconductor package 1000 shown in FIG. 1 in more detail. Referring to FIG. 4A, the memory device 300 can include a volatile memory device such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), or can include a non-volatile memory device such as a flash memory. In the semiconductor package 1000 according to the embodiment, the memory device 300 can be, for example, a DRAM device. The memory device 300 can be mounted on the second wiring substrate 130 by using a flip-chip bonding structure using bumps 350. The memory device 300 can have a single memory chip structure or can have a package structure including multiple memory chips. Referring to FIG. 4B, the memory device 300a can include a plurality of stacked memory chips 310-1 to 310-4, and can be mounted on the second wiring substrate 130 by using a wire bonding structure using a bonding layer 325 and wires 330w. In an embodiment, as shown in FIG. 4B, four memory chips 310-1 to 310-4 can be stacked. In an embodiment, three or fewer memory chips, or five or more memory chips can be stacked. In an embodiment, the memory chips can be stacked in a zigzag structure or a combination structure of a stair structure and a zigzag structure. Referring to FIG. 4C, the memory device 300b can be a high bandwidth memory (HBM) package. In an embodiment, the memory device 300b can include a base chip 310 and a plurality of core chips 320 located on the base chip 310. In an embodiment, through electrodes 330 can be included in the base chip 310 and the core chips 320. In an embodiment, the uppermost core chip among the core chips 320 may not include a through electrode 330. The base chip 310 can include logic elements. In an embodiment, the base chip 310 can be a logic chip. The base chip 310 can be located below the core chips 320, can integrate the signals of the core chips 320 to transmit the signals to the outside, and can transmit external signals and power to the core chips 320. In an embodiment, the base chip 310 can be referred to as a buffer chip or a control chip. Each of the core chips 320 can be a plurality of memory chips. In an embodiment, each of the core chips 320 can be a DRAM chip. The core chips 320 can be stacked on the base chip 310 or the lower core chips 320 by pad-to-pad bonding, hybrid bonding, bonding using a bonding member, or bonding using ACF. In an embodiment, as shown in FIG. 4C, four core chips 320-1, 320-2, 320-3, and 320-4 can be stacked. In an embodiment, three or fewer core chips, or five or more core chips can be stacked. Bumps 350 can be located on the lower surface of the base chip 310. The bumps 350 can be connected to the through electrodes 330. The bumps 350 can include pillars and solder, or can include only solder. The memory device 300b can be mounted on the second wiring substrate 130 by the bumps 350. The core chips 320 on the base chip 310 can be sealed by an internal sealant 340. In an embodiment, the uppermost core chip 320-4 among the core chips 320 may not be covered by the internal sealant 340. In an embodiment, the upper surface of the uppermost core chip 320-4 can be covered by the internal sealant 340. FIGS. 5 to 7 are cross-sectional views of semiconductor packages according to embodiments. The description given with reference to FIGS. 1 to 4C may be briefly described or may not be repeated here. Referring to FIG. 5, the semiconductor package 1000a according to an embodiment may be different from the semiconductor package 1000 shown in FIG. 1 in terms of the structure of the lower package 100a. The semiconductor package 1000a according to an embodiment may include a lower package 100a, a heat dissipation structure 200, a memory device 300, external connection terminals 400, and passive devices 500. The heat dissipation structure 200, the memory device 300, the external connection terminals 400, and the passive devices 500 may be the same as those described with reference to the semiconductor package 1000 shown in FIG. 1. The lower package 100a may include a first redistribution substrate 110, a first semiconductor chip 120, a second redistribution substrate 130, an inter-substrate via electrode 140a, a sealant 150, and a second semiconductor chip 160. The first redistribution substrate 110, the first semiconductor chip 120, the second redistribution substrate 130, the sealant 150, and the second semiconductor chip 160 may be the same as those described for the lower package 100 of the semiconductor package 1000 shown in FIG. 1. In the semiconductor package 1000 according to an embodiment, the inter-substrate via electrode 140a may include an electrode metal layer 142 and a barrier metal layer 144. In an embodiment, the electrode metal layer 142 may include, for example, Cu, W, Al, etc. In an embodiment, the barrier metal layer 144 may include, for example, Ti / TiN. The inter-substrate via electrode 140a may be formed by laser drilling and deposition processes. In an embodiment, the inter-substrate via electrode 140a may be formed by forming trenches in the sealant 150 through a laser drilling process and filling the trenches with a metal material through a deposition process. In an embodiment, due to the method of forming the inter-substrate via electrode 140a, the size and pitch of the inter-substrate via electrode 140a may be larger than the size and pitch of the inter-substrate via electrode 140 of the semiconductor package 1000 shown in FIG. 1. In an embodiment, the inter-substrate via electrode 140a may have substantially the same size and pitch as the inter-substrate via electrode 140 of the semiconductor package 1000 shown in FIG. 1. Referring to FIG. 6, the semiconductor package 1000b according to an embodiment may be different from the semiconductor package 1000 shown in FIG. 1 in terms of the structure of the lower package 100b. In the semiconductor package 1000b according to an embodiment, the lower package 100b may include a first wiring substrate 110, a first semiconductor chip 120, a second wiring substrate 130a, an inter-substrate through electrode 140, a sealant 150, and a second semiconductor chip 160. The first wiring substrate 110, the inter-substrate through electrode 140, and the sealant 150 may be the same as those described for the lower package 100 of the semiconductor package 1000 shown in FIG. 1. In the semiconductor package 1000b according to an embodiment, the second semiconductor chip 160 may be directly stacked on the first semiconductor chip 120. The first semiconductor chip 120 and the second semiconductor chip 160 may form a stacked chip structure (SC in FIG. 14A). Using the stacked chip structure SC, the first semiconductor chip 120 and the second semiconductor chip 160 may be mounted together on the first wiring substrate 110. In the stacked chip structure, the second semiconductor chip 160 may be stacked on the first semiconductor chip 120 by bonding using fine bumps, bonding using ACF, HB, etc. In the semiconductor package 1000 according to an embodiment, the second wiring substrate 130 may cover the inter-substrate through electrode 140 and the sealant 150, and may cover only a part of the upper surface of the first semiconductor chip 120. In an embodiment, on the upper surface of the first semiconductor chip 120, the second wiring substrate 130 and the second semiconductor chip 160 may be adjacent to each other (e.g., laterally) with a predetermined gap therebetween. The heat dissipation structure 200 may be stacked on the second semiconductor chip 160 and may be bonded to the second semiconductor chip 160 by an adhesive layer 210. In the semiconductor package 1000b according to an embodiment, the transmission of the memory signal between the memory device 300 and the second semiconductor chip 160 may not pass through the inter-substrate through electrode 140 and the first wiring substrate 110. In the semiconductor package 1000b according to an embodiment, the memory device 300 and the second semiconductor chip 160 may exchange memory signals via the second wiring substrate 130, the post-wiring layer 127, the through electrode 129, the device layer 123, the through electrode 129, and the post-wiring layer 127. The second wiring substrate 130 may not be located between the first semiconductor chip 120 and the second semiconductor chip 160, the signal transmission path may be shortened, and the heat dissipation performance of the first semiconductor chip 120 and the second semiconductor chip 160 may be further improved. Referring to FIG. 7, the semiconductor package 1000c according to an embodiment may be substantially the same as the semiconductor package 1000b shown in FIG. 6, except that the lower package 100c may include an inter-substrate through electrode 140a. The inter-substrate through electrode 140a may include an electrode metal layer 142 and a barrier metal layer 144. The inter-substrate through electrode 140a may be the same as that described with reference to the semiconductor package 1000a shown in FIG. 5. FIGS. 8A and 9 are cross-sectional views of semiconductor packages 1000d and 1000e according to embodiments, and FIG. 8B is a cross-sectional view more specifically showing the interposer wafer in the semiconductor package 1000d shown in FIG. 8A. The description given with reference to FIGS. 1 to 7 may be briefly described or may not be repeated here. Referring to FIGS. 8A and 8B, the semiconductor package 1000d according to an embodiment may be significantly different from the semiconductor package 1000 shown in FIG. 1 in terms of the structure of the lower package 100d. The semiconductor package 1000d according to an embodiment may include a lower package 100d, a heat dissipation structure 200, a memory device 300, external connection terminals 400, and passive devices 500. The heat dissipation structure 200, the memory device 300, the external connection terminals 400, and the passive devices 500 may be the same as those described with reference to the semiconductor package 1000 shown in FIG. 1, except that the heat dissipation structure 200 is stacked on the second redistribution substrate 130. The lower package 100d may include a first redistribution substrate 110, a first semiconductor wafer 120, a second redistribution substrate 130, an inter-substrate through electrode 140b, a sealant 150a, a second semiconductor wafer 160, and an interposer wafer 170. In an embodiment, the first semiconductor wafer 120, the second semiconductor wafer 160, and the interposer wafer 170 may form a stacked wafer structure (refer to SC in FIG. 14A), and the stacked wafer structure SC may be located between the first redistribution substrate 110 and the second redistribution substrate 130. The stacked wafer structure SC may be located between the first redistribution substrate 110 and the second redistribution substrate 130, the distance between the first redistribution substrate 110 and the second redistribution substrate 130 may be increased, and thus, the size and pitch of the inter-substrate through electrode 140b may be increased. In an embodiment, the thickness of the sealant 150a may also be increased. As shown in FIG. 8A, the interposer wafer 170 may be stacked on the upper surface of the first semiconductor wafer 120. In an embodiment, the interposer chip 170 may be adjacent to the second semiconductor chip 160 in a state where there is a predetermined interval or distance (e.g., laterally) between the interposer chip 170 and the second semiconductor chip 160. The interposer chip 170 may be, for example, a silicon interposer chip. In an embodiment, as shown in FIG. 8B, the interposer chip 170 may include a silicon substrate 172, through electrodes 174, lower pads 176, and upper pads 178. The through electrodes 174 may directly connect the lower pads 176 and the upper pads 178. In the semiconductor package 1000d according to the present embodiment, the interposer chip 170 may be included, and the transmission of memory signals between the memory device 300 and the second semiconductor chip 160 may not pass through the inter-substrate through electrodes 140b and the first redistribution substrate 110. In the semiconductor package 1000d according to an embodiment, the memory device 300 and the second semiconductor chip 160 may exchange memory signals via the second redistribution substrate 130, the interposer chip 170, the post-wiring layer 127, the through electrode 129, the device layer 123, the through electrode 129, and the post-wiring layer 127. Referring to FIG. 9, the semiconductor package 1000e according to an embodiment may be substantially the same as the semiconductor package 1000d shown in FIG. 8A, except that the lower package 100e may include the inter-substrate through electrode 140c. The inter-substrate through electrode 140c may include an electrode metal layer 142 and a barrier metal layer 144. The inter-substrate through electrode 140c may be the same as the description given for the semiconductor package 1000a shown in FIG. 5. In the semiconductor package 1000e according to an embodiment, the inter-substrate through electrode 140c may have a structure that passes through the thick sealant 150a (which surrounds the side surface of the stacked chip structure (SC shown in FIG. 14A)) rather than the first semiconductor chip 120, and thus, the size and pitch may be increased compared to the inter-substrate through electrode 140a of the semiconductor package 1000a shown in FIG. 5. FIGS. 10A to 10G are schematic cross-sectional views of each stage in the method of manufacturing the semiconductor package 1000 shown in FIG. 1 according to an embodiment. In the description, reference will also be made to FIG. 1, and the description given with reference to FIGS. 1 to 4C may be briefly described only or may not be repeated. Referring to FIG. 10A, in the method of manufacturing the semiconductor package 1000 according to an embodiment, first, the first redistribution substrate 110 may be formed. The first redistribution substrate 110 may include a first body insulating layer 112 and first redistribution lines 114. The first redistribution substrate 110 may be formed on a carrier substrate. The carrier substrate may be a large-sized substrate such as a wafer. In an embodiment, the redistribution substrate formed on the carrier substrate may also be a large-sized redistribution substrate including a plurality of first redistribution substrates 110. In an embodiment, a semiconductor package individualized by a singulation process after subsequent components are formed on the large-sized redistribution substrate may be referred to as a wafer level package (WLP). For ease of explanation, only one first redistribution substrate 110 and components corresponding to the one first redistribution substrate 110 are shown in FIG. 10A and subsequent diagrams. Thereafter, a seed metal may be formed on the first redistribution substrate 110. The seed metal may be used when forming the inter-substrate vias 140 by electroplating later. In a method of manufacturing a semiconductor package according to an embodiment, for example, the seed metal may include Cu. Referring to FIG. 10B, thereafter, a first semiconductor chip 120 may be mounted on the first redistribution substrate 110. The first semiconductor chip 120 may be mounted on the first redistribution substrate 110 in a flip chip bonding structure using bumps 125. In an embodiment, as shown in FIG. 10B, the first semiconductor chip 120 may be offset to one side in the x direction, for example, to the right. Referring to FIG. 10C, after the first semiconductor chip 120 is mounted, the inter-substrate vias 140 may be formed on the first redistribution substrate 110. As described above, the inter-substrate vias 140 may be formed by electroplating. In an embodiment, a photoresist (PR) may be coated on the first redistribution substrate 110, and a PR pattern exposing the seed metal on the upper surface of the first redistribution substrate 110 may be formed by an exposure process. Next, the inter-substrate vias 140 may be formed by electroplating using the seed metal. Thereafter, the PR pattern may be removed, and the seed metal exposed by removing the PR pattern may be removed. Referring to FIG. 10D, after the inter-substrate vias 140 are formed, a sealant 150 covering the side surfaces of the first semiconductor chip 120 and the side surfaces of the inter-substrate vias 140 may be formed. The sealant 150 may first be formed thick enough to cover the upper surface of the first semiconductor wafer 120 and the upper surface of the inter-substrate through electrode 140. Thereafter, an upper portion of the sealant 150 may be removed by a grinding process to expose the upper surface of the first semiconductor wafer 120 and the upper surface of the inter-substrate through electrode 140, and thus, the sealant 150 may cover the side surfaces of the first semiconductor wafer 120 and the inter-substrate through electrode 140. As shown in FIG. 10D, the sealant 150 may be filled between the first semiconductor wafer 120 and the first redistribution substrate 110 and between the respective bumps 125. Referring to FIG. 10E, after the sealant 150 is formed, the second redistribution substrate 130 may be formed. The second redistribution substrate 130 may be formed by substantially the same method as the first redistribution substrate 110. Accordingly, the second redistribution substrate 130 may include a body insulating layer and redistribution lines. The second redistribution substrate 130 may be formed such that substrate pads connected to the redistribution lines are connected to the inter-substrate through electrode 140 and also to upper pads of the post-wiring layer 127 of the first semiconductor wafer 120. Referring to FIG. 10F, after the second redistribution substrate 130 is formed, the second semiconductor wafer 160 may be mounted on the second redistribution substrate 130. The second semiconductor wafer 160 may be mounted on the second redistribution substrate 130 by using, for example, fine bumps. In an embodiment, the second semiconductor wafer 160 may be mounted on the second redistribution substrate 130 by HB or by bonding using ACF. In an embodiment, the second semiconductor wafer 160 may be mounted on the second redistribution substrate 130 corresponding to the position of the first semiconductor wafer 120 to minimize a signal transmission path. In an embodiment, the second semiconductor wafer 160 may be offset to the right in the x direction and mounted on the second redistribution substrate 130. Referring to FIG. 10G, thereafter, the heat dissipation structure 200 may be stacked on the second semiconductor wafer 160 and the heat dissipation structure 200 may be bonded to the second semiconductor wafer 160 by using the bonding layer 210. Next, the memory device 300 may be installed adjacent to the second semiconductor wafer 160 on the second wiring substrate 130, and the lower surface of the first wiring substrate 110 may have external connection terminals 400 and passive devices 500. Thus, the manufacturing of the semiconductor package 1000 shown in FIG. 1 may be completed. As a reference, the setting of the external connection terminals 400 and the passive devices 500 may be performed after separating the first wiring substrate 110 from the carrier substrate. In addition, by individualizing a wafer-level package structure including a plurality of semiconductor packages through singulation, the semiconductor package 1000 shown in FIG. 1 may be substantially completed. The singulation process by singulation may be equally applicable to the method of manufacturing a semiconductor package according to the following other embodiments. FIGS. 11A to 11D are schematic cross-sectional views of each stage in the method of manufacturing the semiconductor package shown in FIG. 5 according to an embodiment. In the description, reference will also be made to FIG. 5, and the description already given with reference to FIGS. 5 and 10A to 10G may be briefly described only or may not be repeated here. Referring to FIG. 11A, in the method of manufacturing the semiconductor package 1000a according to an embodiment, by the processes shown in FIGS. 10A and 10B, the first wiring substrate 110 may be formed and the first semiconductor wafer 120 may be installed on the first wiring substrate 110. In an embodiment, the inter-substrate through electrodes 140a may be formed later by a laser drilling process, and the seed metal may not be formed on the upper surface of the first wiring substrate 110. After installing the first semiconductor wafer 120, a sealant 150 may be formed to cover the side surfaces of the first semiconductor wafer 120. Initially, the sealant 150 may be formed thick enough to cover the upper surface of the first semiconductor wafer 120. Thereafter, the upper portion of the sealant 150 may be removed by a grinding process to expose the upper surface of the first semiconductor wafer 120, and thus the sealant 150 may cover the side surfaces of the first semiconductor wafer 120. In addition, the sealant 150 may be filled between the first semiconductor wafer 120 and the first wiring substrate 110 and between the respective bumps 125. Referring to FIG. 11B, after forming the sealant 150, a plurality of trenches T may be formed in the sealant 150 by a laser drilling process. The upper surface of the first wiring substrate 110 may be exposed by the bottom surface of the trench T. Referring to FIG. 11C, after forming the trench T, the trench T may be filled with a metal material to form the inter-substrate through electrodes 140a. In an embodiment, after sequentially depositing a barrier metal material and an electrode metal material to fill trench T, the barrier metal material and the electrode metal material located on the upper surface of the sealant 150 and the upper surface of the first semiconductor wafer 120 can be removed by a grinding process, and in this way, an inter-substrate electrode 140a having an electrode metal layer 142 and a barrier metal layer 144 can be formed in trench T. Referring to FIG. 11D, after forming the inter-substrate electrode 140a, a second redistribution substrate 130 can be formed. The second redistribution substrate 130 can be formed such that a substrate pad connected to the redistribution line is connected to the inter-substrate electrode 140a and is also connected to an upper pad of the post-wiring layer 127 of the first semiconductor wafer 120. Subsequently, a second semiconductor wafer 160 can be mounted on the second redistribution substrate 130, and a heat dissipation structure 200 can be stacked on the second semiconductor wafer 160. In addition, a memory device 300 can be mounted adjacent to the second semiconductor wafer 160 on the second redistribution substrate 130. Thereafter, by providing an external connection terminal 400 and a passive device 500 on the lower surface of the first redistribution substrate 110, the manufacturing of the semiconductor package 1000a shown in FIG. 5 can be completed. FIGS. 12A to 12E are schematic cross-sectional views of each stage in a method of manufacturing the semiconductor package 1000b shown in FIG. 6 according to an embodiment. In the description, reference will also be made to FIG. 6, and the description already given with reference to FIGS. 6 and 10A to 10G can be briefly elaborated or may not be repeated here. Referring to FIG. 12A, in a method of manufacturing a semiconductor package 1000b according to an embodiment, by the processes shown in FIGS. 10A to 10D, a first redistribution substrate 110 can be formed and a first semiconductor wafer 120, an inter-substrate electrode 140, and a sealant 150 can be formed on the first redistribution substrate 110. Referring to FIG. 12B, after forming the sealant 150, a film 180 can be bonded to a part of the upper surface of the first semiconductor wafer 120. The film 180 can be bonded to the upper surface of the first semiconductor wafer 120 to ensure an area for the second semiconductor wafer 160 in subsequent processes. Therefore, the film 180 can have a thickness similar to the thickness of the second semiconductor wafer 160. In an embodiment, the second semiconductor wafer 160 can be spaced apart from the second redistribution substrate 130a by a predetermined distance, and the width of the film 180 in the x direction can be greater than the width of the second semiconductor wafer 160 in the x direction. The film 180 can be bonded to the upper surface of the first semiconductor wafer 120 using, for example, an adhesive that can be easily removed. Referring to FIG. 12C, after bonding the film 180, a second redistribution substrate 130a can be formed. The second redistribution substrate 130a can be formed such that substrate pads connected to the redistribution lines are connected to the inter-substrate through electrodes 140 and are also connected to upper pads of the post-wiring layer 127 of the first semiconductor chip 120. In an embodiment, the film 180 can be present on the upper surface of the first semiconductor chip 120, and the second redistribution substrate 130a can be formed only on a portion of the upper surface of the first semiconductor chip 120 where the film 180 is absent. Referring to FIG. 12D, after forming the second redistribution substrate 130a, the film 180 on the first semiconductor chip 120 can be removed. Thereafter, the second semiconductor chip 160 can be mounted on the upper surface of the first semiconductor chip 120 where the film 180 has been removed. The second semiconductor chip 160 can be mounted on the first semiconductor chip 120 by using, for example, fine bumps. In an embodiment, the second semiconductor chip 160 can be mounted on the first semiconductor chip 120 by HB or by bonding using ACF. Referring to FIG. 12E, thereafter, the heat dissipation structure 200 can be stacked on the second semiconductor chip 160 and the heat dissipation structure 200 can be bonded to the second semiconductor chip 160 by using the bonding layer 210. Thereafter, the memory device 300 can be mounted adjacent to the heat dissipation structure 200 on the second redistribution substrate 130a. Subsequently, by providing the external connection terminals 400 and the passive devices 500 on the lower surface of the first redistribution substrate 110, the manufacturing of the semiconductor package 1000b shown in FIG. 6 can be completed. FIGS. 13A to 13C are schematic cross-sectional views of each stage in the method of manufacturing the semiconductor package 1000c shown in FIG. 7 according to an embodiment. In the description, reference will also be made to FIG. 7, and the description that has been given with reference to FIGS. 7 and 11A to 12E can be briefly elaborated or may not be repeated here. Referring to FIG. 13A, in the method of manufacturing the semiconductor package 1000c according to an embodiment, by the processes of FIGS. 10A and 10B, the first redistribution substrate 110 can be formed and the first semiconductor chip 120 can be mounted on the first redistribution substrate 110. In an embodiment, the seed metal may not be formed on the upper surface of the first redistribution substrate 110. Thereafter, as shown in FIG. 11A, the sealant 150 covering the side surfaces of the first semiconductor chip 120 can be formed. After forming the sealant 150, a plurality of trenches can be formed in the sealant 150 by a laser drilling process. The upper surface of the first rewiring substrate 110 can be exposed by the bottom surface of the trench. After forming the trench, the inter-substrate via electrode 140a can be formed by filling the trench with a metal material. The inter-substrate via electrode 140a can include an electrode metal layer 142 and a barrier metal layer 144 located in the trench. The method of forming the inter-substrate via electrode 140a can be the same as that described with reference to FIG. 11B. Referring to FIG. 13B, after forming the inter-substrate via electrode 140a, the film 180 can be bonded to a part of the upper surface of the first semiconductor wafer 120. The size, bonding method, and bonding position of the film 180 can be the same as those described with reference to FIG. 12B. Referring to FIG. 13C, after bonding the film 180, the second rewiring substrate 130a can be formed. The second rewiring substrate 130a can be formed such that the substrate pads connected to the rewiring lines are connected to the inter-substrate via electrode 140a and also connected to the upper pads of the post-wiring layer 127 of the first semiconductor wafer 120. In an embodiment, the second rewiring substrate 130a can be formed on only a part of the upper surface of the first semiconductor wafer 120 where the film 180 does not exist. Subsequently, the semiconductor package 1000c shown in FIG. 7 can be completed by the processes of FIGS. 12D to 12E. FIGS. 14A to 14E are schematic cross-sectional views of each stage in the method of manufacturing the semiconductor package 1000d shown in FIG. 8A according to an embodiment. In the description, reference will also be made to FIGS. 8A and 8B, and the description given with reference to FIGS. 8A and 8B and FIGS. 10A to 10G may be briefly described only or may not be repeated. Referring to FIG. 14A, in the method of manufacturing the semiconductor package 1000d according to an embodiment, the second semiconductor wafer 160 can be mounted on the first semiconductor wafer 120. The second semiconductor wafer 160 can be mounted on the first semiconductor wafer 120 by, for example, fine bumps. In an embodiment, the second semiconductor wafer 160 can be mounted on the first semiconductor wafer 120 by HB or by bonding using ACF. Thereafter, the interposer wafer 170 can be mounted on the first semiconductor wafer 120 adjacent to the second semiconductor wafer 160. The interposer wafer 170 can be mounted on the first semiconductor wafer 120 by fine bumps. In an embodiment, the interposer wafer 170 can also be mounted on the first semiconductor wafer 120 by HB or by bonding using ACF. By mounting the second semiconductor wafer 160 and the interposer wafer 170 on the first semiconductor wafer 120, a stacked wafer structure SC can be formed. Referring to FIG. 14B, after forming the stacked wafer structure SC, the stacked wafer structure SC can be mounted on the first rewiring substrate 110. The first redistribution substrate 110 may be formed before or together with the stacked wafer structure SC. In an embodiment, the installation of the stacked wafer structure SC may be implemented by a process of mounting the first semiconductor wafer 120 on the first redistribution substrate 110 using a flip-chip bonding structure with bumps 125, and in terms of method, the method of installing the stacked wafer structure SC may be substantially the same as the method of installing the first semiconductor wafer 120 shown in FIG. 10B. Referring to FIG. 14C, after installing the stacked wafer structure SC, the inter-substrate vias 140b and the sealant 150a may be formed by the processes described with reference to FIGS. 10C and 10D. In an embodiment, the stacked wafer structure SC may be mounted on the first redistribution substrate 110 instead of on the first semiconductor wafer 120, the size and pitch of the inter-substrate vias 140b may be increased, and the thickness of the sealant 150a may be increased. In an embodiment, the sealant 150a may fill the gap between the second semiconductor wafer 160 and the interposer wafer 170 on the first semiconductor wafer 120. Referring to FIG. 14D, after forming the sealant 150a, the second redistribution substrate 130 may be formed. The second redistribution substrate 130 may be formed such that the substrate pads connected to the redistribution lines are connected to the inter-substrate vias 140b, the upper pads of the post-wiring layer 127 of the first semiconductor wafer 120, and the upper pads 178 of the interposer wafer 170. Referring to FIG. 14E, after forming the second redistribution substrate 130, the heat dissipation structure 200 may be stacked on the second redistribution substrate 130 at a position corresponding to the second semiconductor wafer 160 using the adhesive layer 210. Subsequently, by mounting the memory device 300 adjacent to the heat dissipation structure 200 on the second redistribution substrate 130, and by providing the external connection terminals 400 and the passive devices 500 on the lower surface of the first redistribution substrate 110, the manufacturing of the semiconductor package 1000d shown in FIG. 8A may be completed. FIGS. 15A to 15C are schematic cross-sectional views of each stage in the method of manufacturing the semiconductor package 1000e shown in FIG. 9 according to an embodiment. In the description, reference will also be made to FIG. 9, and the description that has been given with reference to FIGS. 9, 11A to 11D, and 14A to 14E may be briefly described or may not be repeated here. Referring to FIG. 15A, in the method of manufacturing the semiconductor package 1000e according to an embodiment, the stacked wafer structure SC may be mounted on the first redistribution substrate 110 by the processes described with reference to FIGS. 14A and 14B. In an embodiment, the seed metal may not be formed on the upper surface of the first redistribution substrate 110. After mounting the stacked wafer structure SC, a sealant 150a may be formed to cover the side surfaces of the stacked wafer structure SC. The sealant 150a may fill the gap between the second semiconductor wafer 160 and the interposer wafer 170 on the first semiconductor wafer 120. The sealant 150a may cover the side surfaces of the stacked wafer structure SC, and the sealant 150a may have a thickness greater than the thickness of the sealant 150 of the semiconductor package 1000 shown in FIG. 1. Referring to FIG. 15B, after forming the sealant 150a, a plurality of trenches may be formed in the sealant 150a by a laser drilling process. The upper surface of the first redistribution substrate 110 may be exposed through the bottom surface of the trench. After forming the trench, the trench may be filled with a metal material to form an inter-substrate via 140c. The inter-substrate via 140c may include an electrode metal layer 142 and a barrier metal layer 144 located in the trench. In an embodiment, the sealant 150a may become thicker, the depth and width of the trench may increase, and thus the size and pitch of the inter-substrate via 140c may increase. Referring to FIG. 15C, after forming the inter-substrate via 140c, a second redistribution substrate 130 may be formed. The second redistribution substrate 130 may be formed such that the substrate pads connected to the redistribution lines are connected to the inter-substrate via 140c, the upper pads of the post-wiring layer 127 of the first semiconductor wafer 120, and the upper pads 178 of the interposer wafer 170. Thereafter, a heat dissipation structure 200 may be stacked on the second redistribution substrate 130 at a position corresponding to the second semiconductor wafer 160, and the heat dissipation structure 200 may be bonded to the second redistribution substrate 130 using an adhesive layer 210. Subsequently, by mounting a memory device 300 adjacent to the heat dissipation structure 200 on the second redistribution substrate 130, and providing external connection terminals 400 and passive devices 500 on the lower surface of the first redistribution substrate 110, the manufacturing of the semiconductor package 1000e shown in FIG. 9 may be completed. In summary, as the semiconductor package has high performance and high capacity, the power consumption of the semiconductor package also increases. Therefore, the heat dissipation characteristics corresponding to the size / performance of the semiconductor package have been considered. One or more embodiments may provide a semiconductor package including redistribution substrates on the top and bottom of a semiconductor wafer. One or more embodiments may provide a semiconductor package that minimizes the signal transmission path between semiconductor wafers in the semiconductor package and maximizes the heat dissipation characteristics. Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used in a general and descriptive sense only and are to be construed in a general and descriptive sense and not for a limiting purpose. In some cases, features, characteristics, and / or elements described in connection with a particular embodiment will be apparent to those of ordinary skill in the art as of the filing date of this application, and unless otherwise specifically stated, may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims. 1st-CH: First semiconductor wafer 1st-RDL, 110: First redistribution layer substrate 2nd-CH, 160, 325: Second semiconductor wafer 2nd-RDL, 130, 130a: Second redistribution layer substrate 100, 100a, 100b, 100c, 100d, 100e: Lower package 112: First body insulation layer 114: First redistribution line 120: Semiconductor wafer / First semiconductor wafer 121: Substrate 123: Device layer 125, 350, Bm: Bump 127: Post-wiring layer 129, 174, 330: Through electrode 140, 140a, 140b, 140c: Inter-substrate through electrode 142: Electrode metal layer 144: Barrier metal layer 150, 150a: Sealing agent 170: Interposer wafer 172: Silicon substrate 176: Lower pad 178: Upper pad 180: Film 200: Heat dissipation structure 210, 325: Adhesive layer 300, 300a, 300b: Memory device 310: Base die 310-1, 310-2, 310-3, 310-4: Memory die 320, 320-1, 320-2, 320-3: Core die 320-4: Top core die / Core die 330w: Wire 340: Internal sealant 400: External connection terminal 500: Passive device 510: Multi-layer ceramic capacitor (MLCC) 520: Si capacitor 1000, 1000a, 1000b, 1000c, 1000d, 1000e, Com.: Semiconductor package Cu-P: Through pillar HS: Heat sink Me: Memory element Mo: Sealing material / Sealant PD1, PD2: Passive component SB: Solder ball SC: Stacked die structure T: Channel TIM: Thermal interface material x: Direction By elaborating on the exemplary embodiments with reference to the accompanying drawings, each feature will be apparent to those skilled in the art. In the drawings: FIG. 1 is a cross-sectional view of a semiconductor package according to an embodiment. FIG. 2 is a cross-sectional view showing a first semiconductor chip in the semiconductor package shown in FIG. 1. FIGS. 3A and 3B are cross-sectional views showing the transmission path of a memory signal in a semiconductor package according to a comparative example and the transmission path of a memory signal in a semiconductor package according to an embodiment, respectively. FIGS. 4A to 4C are cross-sectional views showing the structure of a memory device in the semiconductor package shown in FIG. 1. FIGS. 5 to 7 are cross-sectional views of a semiconductor package according to an embodiment. FIG. 8A is a cross-sectional view of a semiconductor package according to an embodiment. FIG. 8B is a cross-sectional view showing an interposer chip in the semiconductor package shown in FIG. 8A according to an embodiment. FIG. 9 is a cross-sectional view of a semiconductor package according to an embodiment. FIGS. 10A to 10G are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 1 according to an embodiment. FIGS. 11A to 11D are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 5 according to an embodiment. FIGS. 12A to 12E are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 6 according to an embodiment. FIGS. 13A to 13C are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 7 according to an embodiment. FIGS. 14A to 14E are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 8A according to an embodiment. FIGS. 15A to 15C are schematic cross-sectional views of stages in a method of manufacturing the semiconductor package shown in FIG. 9 according to an embodiment. 100: Lower package 110: First redistribution substrate 112: First body insulating layer 114: First redistribution line 120: Semiconductor chip / First semiconductor chip 125, 350: Bump 130: Second redistribution substrate 140: Inter-substrate via electrode 150: Encapsulant 160: Second semiconductor chip 200: Heat dissipation structure 210: Adhesive layer 300: Memory device 400: External connection terminal 500: Passive device 510: Multi-layer ceramic capacitor (MLCC) 520: Si capacitor 1000: Semiconductor package x, y, z: Directions

Claims

1. A semiconductor package, comprising: First wiring board; A first semiconductor wafer is located on the first redistribution substrate; The second wiring substrate is located on the first semiconductor wafer; A through electrode is located on one side of the first semiconductor wafer on the first redistribution substrate and connects the first redistribution substrate to the second redistribution substrate; a second semiconductor wafer is located on the first semiconductor wafer; a heat dissipation structure is located on the second semiconductor wafer; and a memory device is located on one side of the second semiconductor wafer on the second redistribution substrate, wherein the first semiconductor wafer is mounted on the first redistribution substrate by a flip-chip structure including bumps, and the first semiconductor wafer includes a substrate, a device layer located below the substrate, a back wiring layer located above the substrate, and a through electrode penetrating the substrate to connect the back wiring layer to the device layer.

2. The semiconductor package as described in claim 1, wherein: The second redistribution substrate covers the entire upper surface of the first semiconductor wafer; and the second semiconductor wafer is located on the second redistribution substrate.

3. The semiconductor package as claimed in claim 2, wherein the memory device and the second semiconductor wafer are configured to exchange memory signals without passing through the first redistribution substrate.

4. The semiconductor package as described in claim 3, wherein: The memory device and the second semiconductor wafer are configured to exchange memory signals via the second redistribution substrate, the back wiring layer, the first through electrode, the device layer, the first through electrode, the back wiring layer and the second redistribution substrate.

5. The semiconductor package as described in claim 2, wherein: The second redistribution substrate covers a portion of the upper surface of the first semiconductor wafer; and the second semiconductor wafer is located on the first semiconductor wafer and adjacent to a side surface of the second redistribution substrate.

6. The semiconductor package of claim 5, wherein the memory device and the second semiconductor wafer are configured to exchange memory signals without passing through the first redistribution substrate.

7. The semiconductor package as described in claim 6, wherein: The memory device and the second semiconductor wafer are configured to exchange memory signals via the second redistribution substrate, the back wiring layer, the first through electrode, the device layer, the first through electrode, and the back wiring layer.

8. A semiconductor package, comprising: First wiring board; A stacked chip structure is located on the first wiring substrate; The second wiring substrate is located on the stacked wafer structure; A through electrode is provided on one side of the stacked wafer structure on the first redistribution substrate, connecting the first redistribution substrate to the second redistribution substrate; a heat dissipation structure is provided on the second redistribution substrate at a portion corresponding to the stacked wafer structure; and a memory device is provided on the second redistribution substrate at one side of the second semiconductor wafer. The stacked wafer structure includes a first semiconductor wafer, a second semiconductor wafer located on the first semiconductor wafer, and an interposer wafer located on the first semiconductor wafer and on one side of the second semiconductor wafer. The first semiconductor wafer is mounted on the first redistribution substrate via a flip-chip structure including bumps. The first semiconductor wafer includes a substrate, a device layer located below the substrate, a back wiring layer located above the substrate, and a first through electrode penetrating the substrate to connect the back wiring layer and the device layer.

9. The semiconductor package of claim 8, wherein the memory device is located on one side of the heat dissipation structure on the second redistribution substrate, wherein the memory device and the second semiconductor wafer are configured to exchange memory signals without passing through the first redistribution substrate.

10. The semiconductor package as claimed in claim 9, wherein: The memory device and the second semiconductor wafer are configured to exchange memory signals via the second redistribution substrate, the interposer wafer, the back wiring layer, the first through electrode, the device layer, the first through electrode, and the back wiring layer.

11. The semiconductor package of claim 8, further comprising a sealant located between the first redistribution substrate and the second redistribution substrate, wherein: The through electrode between the substrates penetrates the sealant, and the sealant is not present between the second semiconductor wafer and the second redistribution substrate, nor is the sealant present between the interposer wafer and the second redistribution substrate.

12. A semiconductor package, comprising: First wiring board; A first semiconductor wafer is located on the first redistribution substrate; The second wiring substrate is located on the first semiconductor wafer; A through electrode is located on one side of the first semiconductor wafer on the first redistribution substrate and connects the first redistribution substrate to the second redistribution substrate; a second semiconductor wafer is located on the first semiconductor wafer; and a memory device is located on one side of the second semiconductor wafer on the second redistribution substrate, wherein the memory device and the second semiconductor wafer are configured to exchange memory signals without passing through the first redistribution substrate. The first semiconductor wafer is mounted on the first redistribution substrate by a flip-chip structure including bumps. The first semiconductor wafer includes a substrate, a device layer located below the substrate, a back wiring layer located above the substrate, and a through electrode penetrating the substrate to connect the back wiring layer to the device layer.

13. The semiconductor package as claimed in claim 12, wherein: The second redistribution substrate covers the entire upper surface of the first semiconductor wafer, and the second semiconductor wafer is located on the second redistribution substrate.

14. The semiconductor package as claimed in claim 13, wherein: The second redistribution substrate covers a portion of the upper surface of the first semiconductor wafer, and the second semiconductor wafer is located on the first semiconductor wafer and adjacent to a side surface of the second redistribution substrate.

15. The semiconductor package of claim 12, further comprising an interposer wafer located on one side of the second semiconductor wafer on the first semiconductor wafer, wherein: The second semiconductor wafer is located on the first semiconductor wafer, and the second redistribution substrate covers the second semiconductor wafer and the interposer wafer.

16. The semiconductor package of claim 12 further includes a heat dissipation structure located on the second semiconductor wafer or on a portion of the second redistribution substrate corresponding to the second semiconductor wafer.

17. A method for manufacturing a semiconductor package, the method comprising: Fabrication of the first rewiring substrate; A first semiconductor chip is mounted on the first interconnect substrate; An inter-substrate through electrode is formed on one side of the first semiconductor wafer on the first redistribution substrate; the inter-substrate through electrode and the first semiconductor wafer are sealed with a sealant; a second redistribution substrate is formed on the first semiconductor wafer, the inter-substrate through electrode and the sealant; a second semiconductor wafer is mounted on the first semiconductor wafer or the second redistribution substrate; and a memory device is mounted on one side of the second semiconductor wafer on the second redistribution substrate, wherein the first semiconductor wafer is mounted on the first redistribution substrate by a flip-chip structure including bumps, and the first semiconductor wafer includes a substrate, a device layer located below the substrate, a back wiring layer located above the substrate, and a through electrode penetrating the substrate to connect the back wiring layer to the device layer.

18. The method as described in claim 17, further comprising: After mounting the second semiconductor wafer, a heat dissipation structure is stacked on the second semiconductor wafer, wherein: forming the second redistribution substrate includes forming the second redistribution substrate to cover the entire upper surface of the first semiconductor wafer, and mounting the second semiconductor wafer includes mounting the second semiconductor wafer on the portion of the second redistribution substrate corresponding to the first semiconductor wafer.

19. The method as described in claim 17, further comprising: Before forming the second redistribution substrate, the film is bonded to the portion of the first semiconductor wafer corresponding to the second semiconductor wafer; And after mounting the second semiconductor wafer, a heat dissipation structure is stacked on the second semiconductor wafer, wherein: sealing the inter-substrate through electrode and the first semiconductor wafer with the sealant includes exposing the upper surface of the inter-substrate through electrode and the upper surface of the first semiconductor wafer by means of the sealant; forming the second redistribution substrate includes forming the second redistribution substrate to cover the portion of the upper surface of the first semiconductor wafer other than the film; and mounting the second semiconductor wafer includes removing the film and mounting the second semiconductor wafer on the first semiconductor wafer.

20. A method for manufacturing a semiconductor package, the method comprising: Fabrication of the first rewiring substrate; A stacked chip structure is mounted on the first wiring substrate; An inter-substrate through electrode is formed on one side of the stacked wafer structure on the first rewiring substrate; the inter-substrate through electrode and the stacked wafer structure are sealed with a sealant; a second rewiring substrate is formed on the stacked wafer structure, the inter-substrate through electrode, and the sealant. The method includes stacking memory devices and heat dissipation structures on a second redistribution substrate, wherein mounting the stacked chip structure includes: mounting a second semiconductor chip on a first semiconductor chip; mounting an interposer chip on the first semiconductor chip on one side of the second semiconductor chip; and mounting the first semiconductor chip on the first redistribution substrate, wherein the memory devices are located on the second redistribution substrate at one side of the second semiconductor chip, the first semiconductor chip is mounted on the first redistribution substrate by a flip-chip structure including bumps, and the first semiconductor chip includes a substrate, a device layer located below the substrate, a back wiring layer located above the substrate, and a through electrode penetrating the substrate to connect the back wiring layer to the device layer.

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