Method and system for area-selective deposition

Abstract

A method includes: selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents the formation of at least one catalyst layer on the first conductive layer; and selectively forming at least one supplementary dielectric layer using the at least one catalyst layer. The at least one catalyst layer causes the formation of the at least one supplementary dielectric layer, and the at least one supplementary dielectric layer comprises a dielectric material having a dielectric constant less than or equal to about 4.

Description

Manufacturing of Electronic Devices Using Area Selective Deposition Embodiments of the present disclosure generally relate to the manufacturing of electronic components. Specifically, embodiments of the present disclosure relate to the manufacturing of electronic components using area selective deposition. Electronic component manufacturing equipment may include multiple chambers, such as a processing chamber and a load lock chamber. Such electronic component manufacturing equipment may employ a robotic device in a transfer chamber, which is configured to transport substrates between multiple chambers. In some cases, multiple substrates are transferred together. The processing chamber may be used in the electronic component manufacturing equipment to perform one or more processes on a substrate, such as a deposition process and an etching process. For many processes, gas flows into the processing chamber. Electronic components, such as semiconductor components, are manufactured by performing a series of operations, which may include deposition, oxidation, photolithography, ion implantation, etching, etc. to form many patterned layers. Generally, it is beneficial to align features between layers. In some cases, poor alignment of features (e.g., due to lithography and / or patterning limitations) may result in, for example, short circuits and / or capacitive coupling between vias and underlying wires. Such short circuits and / or capacitive coupling may impair the functionality of the manufactured electronic components. According to an embodiment, a method is provided. The method includes: selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer; selectively forming at least one catalyst layer on at least one passivation layer, wherein at least one passivation layer prevents the formation of at least one catalyst layer on the first conductive layer; and selectively forming at least one supplementary dielectric layer using at least one catalyst layer. At least one catalyst layer causes the formation of at least one supplementary dielectric layer, and at least one supplementary dielectric layer includes a dielectric material having a dielectric constant less than or equal to about 4. According to an embodiment, a system is provided. The system includes at least one chamber operatively coupled to at least one storage. The at least one chamber is configured to: selectively form at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer; selectively form at least one catalyst layer on at least one passivation layer, wherein at least one passivation layer prevents the formation of at least one catalyst layer on the first conductive layer; and selectively form at least one supplementary dielectric layer using at least one catalyst layer. At least one catalyst layer causes the formation of at least one supplementary dielectric layer, and at least one supplementary dielectric layer includes a dielectric material having a dielectric constant less than or equal to about 4. The embodiments described herein relate to the manufacture of electronic components using area-selective deposition. The electronic components may include dielectric materials and conductive layers. For example, the electronic components may include a dielectric layer and several conductive layers disposed in (e.g., within) the dielectric layer. More specifically, the electronic components may include several metallization levels, where each metallization level includes a corresponding set of conductive layers, and each pair of metallization levels is separated by a corresponding dielectric layer (e.g., an interlayer dielectric (ILD) layer). Each conductive layer may be formed within a corresponding trench. For example, the conductive layer may be a via. A via refers to an electrical connection or contact between wires within an electronic component. Each via may be used as a corresponding interconnect between at least two metallization levels. For example, a through-via is a via that is exposed at both ends of the component (i.e., the through-via is formed through each metallization level from the top to the bottom of the component). As another example, a buried via is a via that is not exposed at either end of the component (i.e., the buried via is used as an interconnect between internal metallization levels). As yet another example, a blind via is a via that is exposed at a single end of the component. Electronic component processing techniques may involve performing patterning (e.g., photolithography). For example, patterning may include multiple and repeated deposition and etching processes using a photomask ("mask") and a resist film, such as wet etching or dry etching (e.g., plasma etching). Illustratively, wires and vias may be formed using suitable patterning processes. For example, wires and vias may be formed using a single damascene process, during which the wires and vias are formed sequentially. As another example, wires and vias may be formed using a dual damascene process, during which the wires and vias may be formed simultaneously (e.g., by simultaneously filling both the vias and trenches with a conductive material). The wires and vias may include any suitable conductive material (e.g., metal). In one example, assume that the component includes a first metallization level that includes a first via disposed in an ILD layer. To pattern a second via of a second metallization level over the first metallization level, a dielectric material including a second ILD layer may be formed across the first metallization level using any suitable deposition process. The dielectric material may further include a dielectric cap that may be deposited across the first metallization level. The second ILD layer may be etched to form a trench. The dielectric cap may be used as an etch stop layer to define the bottom of the trench. The via opening may include the trench. For example, a portion of the dielectric cap may be removed using an etching process (e.g., an anisotropic etching process) to expose the first via. A conductive material may be formed within the via opening to form the second via. If the second via has a substantially correct edge placement relative to the first via (e.g., the via is centered relative to the first via), the second via can be considered an aligned via. However, as the size of electronic components shrinks (e.g., as the size of transistors decreases), process variations may occur during lithography / patterning (e.g., nanoscale patterning). An example of a process variation is poor mask alignment between the mask and the patterned substrate. During exposure to light, poor mask alignment may result in an edge placement error equal to the distance between the target position of the feature edge and the actual position of the feature edge. Edge placement errors may cause harmful effects, which may lead to a decrease in component performance, such as short circuits, increased resistance, capacitive coupling, etc. In the above example, poor mask alignment during the initial patterning of the trench in the second ILD layer may result in poor alignment of the second via relative to the first via. Specifically, it may result in an edge placement error relative to the edge of the second via. Therefore, during the formation of the via, the edge of the second via can be formed in the region between its corresponding wire and another adjacent wire on a portion of the dielectric layer. Such via misalignment (i.e., edge placement error) can lead to a short circuit or capacitive coupling between the first and second vias, which can be a function of the horizontal spacing between the first and second vias (e.g., the distance between the upper surface of the first via and the lower surface of the second via). As the transistor size becomes smaller (e.g., on the nanometer (nm) scale), the impact of via misalignment can become more pronounced. Thus, as the transistor element size is further reduced, it is important to maintain a minimum amount of spacing to prevent short circuits or capacitive coupling due to process variations that cause via misalignment. In some embodiments, a fully self-aligned via (FSAV) process can be employed to address via misalignment (i.e., edge placement error). An example of the FSAV process uses a recess method. During the recess method, after the trench in the first ILD layer is filled with a conductive material (e.g., metal) to form, for example, the first via, the conductive material can be recessed to a specific depth within its corresponding trench using an etching process. The second via can then be formed such that the upper surface of the first via is below the upper surface of the first ILD layer. Thus, if the second via is misaligned relative to the first via, the second via can have an edge formed on the dielectric layer, which is a certain distance above the upper surface of the first via. This can result in the upper surface of the first via and the lower surface of the second via being separated by a diagonal spacing. The diagonal spacing is a function of the horizontal spacing described above and the vertical distance between the upper surface of the first via and the lower surface of the second via. That is, the diagonal spacing has a greater length compared to the horizontal spacing, which can help prevent short circuits or capacitive coupling. However, the recessing method has several disadvantages. For example, the recessing method can exhibit poor uniformity, high conductor surface roughness, and material degradation over the wafer and across different pitch sizes. In addition, it may be difficult to etch some conductive materials to achieve recessing, such as for a first via (e.g., copper etching can be challenging). Another example of a method that can be used to address process variations, such as poor via alignment, is the area-selective deposition method. More specifically, the selective material deposition approach can include a dielectric-on-dielectric (DoD) selective deposition approach. For example, after a trench in a first ILD layer is filled with a conductive material to form a first via as described above, a supplementary dielectric layer can be selectively deposited on the exposed upper surface of the first ILD layer prior to the first conductive material. The selectivity can be defined as, for example, the ratio of the film thickness (e.g., the thickness of the supplementary dielectric layer) on a target surface (e.g., the first ILD layer) to the film thickness on a non-target surface (e.g., the conductive material). Other definitions of selectivity can be used. The supplementary dielectric layer can be formed to a height similar in magnitude to the depth achieved during the recessing method described above. Similar to the recessing method, if a second via is formed with poor alignment relative to the first via, the second via can have an edge formed on the supplementary dielectric layer that is a certain distance above the upper surface of the first via. Similar to the recessing method, the area-selective deposition method can result in the upper surface of the first via and the lower surface of the second via being separated by a diagonal spacing with a length greater than the horizontal spacing, which can help prevent short circuits or capacitive coupling. It may be beneficial to form a supplementary dielectric layer having a relatively low dielectric constant (i.e., a low-k dielectric material). For example, a low-k dielectric material can have a dielectric constant less than or equal to about 4. However, the area-selective deposition method is generally limited to forming a supplementary dielectric layer having a relatively high dielectric constant (i.e., a high-k dielectric material). Examples of such high-k dielectric materials include zinc oxide (ZnO), aluminum oxide (Al 2 O 3 ) etc. In addition, it is challenging to achieve a selectivity of greater than 10 nanometers (nm) for the dielectric material relative to the conductive material (e.g., metal) using conventional techniques. To address these and other drawbacks, the embodiments described herein can be used to fabricate electronic components using area-selective deposition. The embodiments described herein can be used to form electronic components that include at least one supplementary dielectric layer to address poor alignment (e.g., via misalignment). More specifically, at least one supplementary dielectric layer can be formed using an area-selective dielectric-on-dielectric (DoD) approach. In some embodiments, area-selective deposition enables FSAV leakage control with respect to vias formed during the FSAV process. In an example, forming an electronic component can include obtaining a substrate structure that includes at least one conductive layer disposed (e.g., within) a first ILD layer. For example, the at least one conductive layer can include a first via. The at least one conductive layer and the first ILD layer can form at least a portion of a first metallization level of the component. Examples of suitable conductive materials that can be used to form the at least one conductive layer include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN x ) etc. Forming the electronic component can further include selectively forming at least one supplementary dielectric layer on the first ILD layer. More specifically, each supplementary dielectric layer can be formed on the first ILD layer prior to the at least one conductive layer of the substrate structure (i.e., DoD selective deposition). In some embodiments, selectively forming the at least one supplementary dielectric layer includes: selectively forming a passivation layer on the first conductive material; selectively forming at least one catalyst layer on the first ILD layer; and selectively forming at least one supplementary dielectric layer using the at least one catalyst layer. More specifically, each catalyst layer can be formed using one or more catalyst layer precursors, and each passivation layer can include a material that can prevent the formation of each catalyst layer using the one or more catalyst layer precursors. In some embodiments, each supplementary dielectric layer includes a dielectric material having a low dielectric constant. For example, each supplementary dielectric layer can include a dielectric material having a dielectric constant less than or equal to about 4. Each catalyst layer is used to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can be used to achieve a suitably high growth per cycle (GPC) of a deposition process for forming each supplementary dielectric layer (e.g., catalytic growth). Each catalyst layer can include suitable chemicals to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can include strong reducing agents, metal hydrides, alkyl metals, aryl metals, silanes, etc. Each catalyst layer can be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer can be an aluminum (Al)-catalyst layer, a titanium (Ti)-catalyst layer, a hafnium (Hf)-catalyst layer, a zirconium (Zr)-catalyst layer, a tantalum (Ta)-catalyst layer, a boron (B)-catalyst layer, a germanium (Ge)-catalyst layer, a tin (Sn)-catalyst layer, a gallium (Ga)-catalyst layer, an indium (In)-catalyst layer, etc. As an illustrative example, the Al-catalyst layer can include Al 2 O 3 and one or more catalyst layer precursors can include one or more of trimethylaluminum (TMA), tris(neopentyl)aluminum, etc. Each catalyst layer and each supplementary dielectric layer can be formed by performing any suitable number of cycles of the corresponding deposition process to form each supplementary dielectric layer with a target thickness. In some embodiments, the deposition process is an atomic layer deposition (ALD) process. In some embodiments, the deposition process is a thermal ALD process. A thermal ALD process is an ALD process that uses thermal energy. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, selectively forming each supplementary dielectric layer includes regenerating each passivation layer after selectively forming each catalyst layer, and selectively forming each supplementary dielectric layer using each catalyst layer after regenerating each passivation layer. In some embodiments, selectively forming each supplementary dielectric layer includes regenerating each passivation layer after selectively forming each supplementary dielectric layer on each catalyst layer. Each passivation layer can be regenerated to further improve the selectivity of the catalyst layer and / or the supplementary dielectric layer. Forming the electronic component may further include forming a second ILD layer on the base structure and each supplementary dielectric layer, forming at least one opening in the second ILD layer, and forming at least one conductive layer in the at least one opening. The at least one conductive layer formed in the at least one opening and the second ILD layer may form at least a part of the second metallization level of the electronic component. For example, the at least one conductive layer formed in the at least one opening may include a second through hole formed in contact with the first through hole. In the case where the alignment of the second through hole with respect to the first through hole is poor, the corresponding supplementary dielectric layer may increase the diagonal distance between the first through hole and the second through hole. Thus, the supplementary dielectric layer may reduce or eliminate the influence regarding short circuit or capacitive coupling between the first through hole and the second through hole. Additional component processing steps may be performed to complete the formation of the electronic component. Further details regarding forming the electronic component, including selectively forming each supplementary dielectric layer, will be described below with reference to FIGS. 1A to 5. FIGS. 1A to 1F are cross-sectional views showing an example method of forming an electronic component ( "component") 100 using area-selective deposition according to some embodiments. As shown in FIG. 1A, a base structure 102 is obtained. The base structure 102 includes an ILD layer 110-1 and a conductive layer including a conductive layer 120 disposed (e.g., inside) in the ILD layer 110-1. For example, obtaining the base structure 102 may include forming the base structure 102. Forming the base structure 102 may include forming a plurality of grooves in the ILD layer 110-1 and forming a conductive material in the corresponding grooves of the plurality of grooves to form a conductive layer including the conductive layer 120. The ILD layer 110-1 and the conductive layer including the conductive layer 120 may define the first metallization level of the component 100. Although not illustrated in FIG. 1A, the base structure 102 may further include a substrate layer (e.g., a semiconductor wafer) as an initial layer of the component 100, and the first metallization level may be formed on the substrate layer. For example, the substrate layer may be a Si substrate layer. In some embodiments, the first metallization level is directly formed on the substrate layer. In some embodiments, one or more intermediate layers (e.g., one or more metallization levels) are disposed between the first metallization level and the substrate layer. Although not illustrated, the base structure 102 may include one or more additional layers such that the ILD layer 110-1 and the conductive layer including the conductive layer 120 are disposed on the one or more additional layers. For example, the component 100 may further include at least a substrate layer (e.g., a silicon (Si) substrate) (not illustrated) as an initial layer of the component. The ILD layer 110-1 may include any suitable dielectric material. In some embodiments, the ILD layer 110-1 may include an oxide (e.g., a metal oxide). Examples of suitable dielectric materials include SiO 2, carbon-doped silicon oxides (e.g., SiOC, SiCOH), etc. The conductive layer including the conductive layer 120 may include any suitable conductive material (e.g., metal). In some embodiments, the conductive layer includes a conductive material that includes a transition metal. Examples of suitable conductive materials that can be used to form the conductive layer including the conductive layer 120 include Cu, W, Co, Mo, Ru, TiN, TaN, MoN x etc. As shown in FIG. 1B, the passivation layer including the passivation layer 125 is selectively formed on the corresponding conductive layer in the conductive layer. For example, the passivation layer 125 may preferentially adsorb to the upper surface of the conductive layer 120 over the upper surface of the ILD layer 110-1. The passivation layer including the passivation layer 125 may include a material that is selected such that a catalyst layer and / or a supplementary dielectric layer can be selectively formed on the ILD layer 110-1 during a subsequent deposition process. The catalyst layer can be used to cause the formation of the supplementary dielectric layer (e.g., catalytic growth), which will be described in further detail below. More specifically, the passivation layer including the passivation layer 125 may include a material that is selected to prevent (e.g., block) the adsorption of the catalyst layer precursor during the deposition process of forming the catalyst layer and / or block the adsorption of the supplementary dielectric layer precursor during the deposition process of forming the supplementary dielectric layer (i.e., prevent the deposition precursor from nucleating on the first conductive material). In some embodiments, and as will be described in further detail below, the deposition process of forming the supplementary dielectric layer is an atomic layer deposition (ALD) process. For example, the ALD process may be a thermal ALD process. Thus, the passivation layer including the passivation layer 125 can prevent (e.g., block) the formation of the catalyst layer and / or the supplementary dielectric layer on the conductive layer including the conductive layer 125. Further details regarding the selective formation of the passivation layer including the passivation layer 125 will be described below with reference to FIGS. 2 to 5. As shown in FIG. 1C, after the selective formation of the passivation layer including the passivation layer 125 (and optional pre-cleaning), the catalyst layer including the catalyst layer 130 is selectively formed on the ILD layer 110-1. The passivation layer including the passivation layer 125 prevents (e.g., blocks) the adsorption of the catalyst precursor used to form the catalyst layer including the catalyst layer 130. Further details regarding the selective formation of the catalyst layer including the catalyst layer 130 will be described below with reference to FIGS. 2 to 5. As shown in Figure 1D, a supplementary dielectric layer including dielectric layer 140 is selectively formed on a catalyst layer including catalyst layer 130. Selectively forming the supplementary dielectric layer including dielectric layer 140 may include depositing a dielectric material using a deposition process. In some embodiments, the deposition process is an ALD process. For example, the ALD process may be a thermal ALD process. Other deposition processes may also be performed to produce the supplementary dielectric layer including dielectric layer 140. As described above, the catalyst layer including catalyst layer 130 is used to cause the formation (e.g., catalytic growth) of the supplementary dielectric layer including dielectric layer 140. The supplementary dielectric layer including dielectric layer 140 may include any suitable dielectric material. In some embodiments, the supplementary dielectric layer including dielectric layer 140 may include a low dielectric constant dielectric material. For example, the supplementary dielectric layer including dielectric layer 140 may include a dielectric material having a dielectric constant less than or equal to about 4. In some embodiments, the supplementary dielectric layer including dielectric layer 140 includes a silicate (i.e., a material including silicon (Si) and oxygen (O)). Examples of suitable dielectric materials that may be included in the supplementary dielectric layer including dielectric layer 140 include SiO X , SiOC, etc. The supplementary dielectric layer including dielectric layer 140 may be formed to have a target thickness. In some embodiments, the thickness of the supplementary dielectric layer including dielectric layer 140 is between about 5 nm and about 30 nm. In some embodiments, the thickness of the supplementary dielectric layer including dielectric layer 140 is between about 10 nm and about 20 nm. Further details regarding the selective formation of the supplementary dielectric layer including dielectric layer 140 will be described below with reference to Figures 2 to 5. As shown in Figure 1E, after selectively depositing the supplementary dielectric layer including dielectric layer 140 on ILD layer 110-1, ILD layer 110-2 may be formed. ILD layer 110-2 may include any suitable dielectric material. In some embodiments, ILD layer 110-2 includes an oxide. In some embodiments, ILD 110-2 includes a nitride. Examples of suitable dielectric materials include SiO 2 , carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si 3 N 4 , etc. In some embodiments, ILD layer 110-2 includes the same dielectric material as ILD layer 110-1. In some embodiments, ILD layer 110-2 includes a different dielectric material from ILD layer 110-1. Further details regarding the formation of ILD layer 110-2 will be described below with reference to Figure 2. As shown in FIG. 1F, the conductive layer 150 is formed to contact the conductive layer 120. Forming the conductive layer 150 may include forming an opening (e.g., a via opening) in the ILD layer 110-2 and forming a conductive material in the opening to form the conductive layer 150. The conductive layer 150 may include any suitable conductive material (e.g., metal). In some embodiments, the conductive layer 150 includes a transition metal. Examples of suitable conductive materials that may be used to form the conductive material 150 include Cu, W, Co, Mo, Ru, etc. In some embodiments, the conductive layer 150 may include the same material as the conductive layer 120. In some embodiments, the conductive material 150 may include a material different from the conductive layer 120. Further details regarding the formation of the conductive layer 150 will be described below with reference to FIG. 2. In this example, the conductive layer 150 is a second via that is misaligned with respect to a first via corresponding to the conductive layer 120. More specifically, the second via has an edge disposed offset from the center with respect to the first via on the dielectric layer 140. A diagonal distance exists between the first via and the second via. The diagonal distance has a length greater than a horizontal distance that would define the separation between the first via and the second via in the absence of the dielectric layer 140. Thus, forming the dielectric layer 140 can achieve FSAV leakage control to improve the performance of the component 100 by reducing short circuits or capacitive coupling between the first via and the second via. Further details regarding the manufacture of the component 100 will now be described below with reference to FIG. 2. FIG. 2 depicts an example method 200 of manufacturing an electronic component using area-selective deposition according to some embodiments. The method 200 may be performed within an electronic component processing system. More specifically, the method 200 may be performed within one or more processing chambers of an electronic component processing system. An example electronic component processing system will be described below with reference to FIG. 5. In step 210, a substrate structure including at least one conductive layer disposed on a first ILD layer is obtained. In some embodiments, the at least one conductive layer of the substrate structure is disposed within (e.g., in) the first ILD layer. The at least one conductive layer includes a first conductive layer. For example, the first conductive layer may be a via. The first conductive material and the first ILD layer may together form at least a portion of a first metallization level of the electronic component. The first metallization level may be formed on a substrate layer (e.g., a Si substrate layer) as an initial layer of the substrate structure. In some embodiments, the first metallization level is formed directly on the substrate layer. In some embodiments, one or more intermediate layers are disposed between the substrate layer and the first metallization level. In some embodiments, obtaining a substrate structure includes receiving a preformed substrate structure. In some embodiments, obtaining a substrate structure includes forming at least a portion of the substrate structure. For example, forming at least a portion of the substrate structure may include at least one of the following: forming one or more intermediate layers on a substrate layer, forming a first ILD layer on the substrate layer (e.g., directly on the substrate layer or on one or more intermediate layers), forming at least one opening (e.g., at least one trench) in the first ILD layer, or forming a conductive material in at least one trench to form at least one conductive layer including a first conductive layer. The first ILD layer may include any suitable dielectric material. In some embodiments, the first ILD layer includes a first silicate. For example, the first ILD layer may include SiO 2 . The first conductive material may include any suitable conductive material (e.g., a metal). In some embodiments, at least one conductive layer of the substrate structure includes a transition metal. Examples of suitable conductive materials that may be used to form at least one conductive layer of the substrate structure include Cu, W, Co, Mo, Ru, TiN, TaN, MoN x , etc. In step 220, at least one supplementary dielectric layer is selectively formed on the first ILD layer. In some embodiments, at least one supplementary dielectric layer includes a low dielectric constant dielectric material. In some embodiments, the low dielectric constant dielectric material has a dielectric constant less than or equal to about 4. In some embodiments, the first ILD layer includes a first silicate (e.g., SiO 2 ) and the supplementary dielectric layer includes a second silicate. For example, the first silicate may include silicon oxide (SiO X), and the second silicate can be a low dielectric constant dielectric silicate (i.e., a silicate having a dielectric constant less than or equal to about 4). Examples of low dielectric constant dielectric silicates include SiOx, silicon oxycarbide (SiOC), etc. At least one supplementary dielectric layer can be formed to have a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, selectively forming at least one supplementary dielectric layer includes using at least one catalyst layer to cause the formation of at least one supplementary dielectric layer. In some embodiments, selectively forming at least one supplementary dielectric layer includes selectively forming at least one passivation layer on at least one conductive layer of the substrate structure, selectively forming at least one catalyst layer on the ILD layer of the substrate structure, and selectively forming at least one supplementary dielectric layer on at least one catalyst layer. More specifically, at least one passivation layer can include a material selected to prevent (e.g., block) the adsorption of precursors during the formation of at least one catalyst layer and / or the adsorption of precursors during the formation of at least one supplementary dielectric layer. Each catalyst layer can include a suitable chemical substance to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can include a strong reducing agent, metal hydride, alkyl metal, aryl metal, silane, etc. Each catalyst layer can be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer can be an Al-catalyst layer, Ti-catalyst layer, Hf-catalyst layer, Zr-catalyst layer, Ta-catalyst layer, B-catalyst layer, Ge-catalyst layer, Sn-catalyst layer, Ga-catalyst layer, In-catalyst layer, etc. As an illustrative example, the Al-catalyst layer can include Al 2 O 3 . Further details regarding the selective formation of at least one supplementary dielectric layer on the first ILD layer will be described below with reference to FIGS. 3 to 5. In step 230, a second ILD layer is formed on the substrate structure and at least one supplementary dielectric layer. The second ILD layer can include any suitable dielectric material. In some embodiments, the second ILD layer can include an oxide. In some embodiments, the second ILD layer can include a nitride. Examples of suitable dielectric materials that can be used to form the second ILD layer include SiO 2 , carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si 3 N 4 etc. In some embodiments, the second ILD layer includes the same dielectric material as the first ILD layer. In some embodiments, the second ILD layer includes a dielectric material different from the first ILD layer. In step 240, at least one opening is formed in the second ILD layer. More specifically, at least one opening includes the upper surface of the second ILD layer to expose the upper surface of the first conductive material. Forming at least one opening may include forming at least one trench in the second ILD layer. For example, forming at least one trench may include performing an etching process. If the substrate structure does not include a dielectric cap, the dielectric cap includes an etch stop layer formed on the first ILD layer, then at least one trench may correspond to at least one opening. Alternatively, if the substrate structure further includes a dielectric cap disposed on the first ILD layer, forming the trench using an etching process may terminate at the etch stop layer. Thus, forming at least one opening may further include performing an additional etching process (e.g., an anisotropic etching process) to remove the dielectric cap. In some embodiments, at least one opening is a via opening. In some embodiments, at least one opening is formed by drilling through the first ILD layer. In step 250, at least one conductive layer is formed in at least one opening. More specifically, at least one conductive layer formed in at least one opening may include a second conductive layer formed to contact the first conductive layer. In some embodiments, the second conductive layer is a second via. At least one conductive layer formed in at least one opening may include any suitable conductive material (e.g., metal). Examples of suitable conductive materials that can be used to form at least one conductive layer in at least one opening include Cu, W, Co, Mo, Ru, TiN, TaN, MoN x etc. In some embodiments, at least one conductive layer formed in at least one opening includes the same material as at least one conductive layer disposed on the first ILD layer. In some embodiments, at least one conductive layer formed in at least one opening includes a material different from at least one conductive layer disposed on the first ILD layer. Further details regarding steps 210-250 are described above with reference to FIGS. 1A-1F and will now be described below with reference to FIGS. 3-5. FIGS. 3 to 4I are diagrams showing example methods 300-400I for selectively forming at least one supplementary dielectric layer during the manufacture of an electronic component according to some embodiments. For example, one or more of methods 300-400I may be used to implement step 220 of method 200 of FIG. 2. One or more of methods 300-400I may be executed within an electronic component processing system. More specifically, one or more of methods 300-400I may be executed within one or more processing chambers of an electronic component processing system. An example electronic component processing system will be described below with reference to FIG. 5. Figure 3 shows a flowchart of an exemplary method 300 for selectively forming at least one supplementary dielectric layer during the manufacture of an electronic component. At step 310, at least one passivation layer is selectively formed. More specifically, at least one passivation layer can be selectively formed on at least one conductive layer of the substrate structure by performing a passivation process prior to the ILD layer of the substrate structure. For example, at least one conductive layer of the substrate structure can be formed within the ILD layer of the substrate structure. In some embodiments, at least one conductive layer of the substrate structure includes at least one via. In some embodiments, at least one passivation layer is formed as a self-assembled monolayer (SAM). A SAM is a material layer with a single-molecule thickness formed by surface adsorption (e.g., chemisorption) during a deposition process. Performing the passivation process can include exposing the substrate structure to at least one passivating agent (i.e., passivant). At least one passivating agent is selected to selectively adsorb onto at least one conductive layer of the substrate structure prior to the ILD layer of the substrate structure. In some embodiments, at least one passivating agent includes a vapor-phase passivating agent. For example, at least one passivation layer can be formed as a SAM grown in the gas phase by at least one vapor-phase passivating agent. Examples of vapor-phase passivating agents that can be used to form at least one passivation layer include amines (e.g., N-ethyl ethylenediamine, N, N’, N, N, N’, N’-tetraethyl ethylenediamine and N, N, N’, N’-tetramethyl ethylenediamine), silanes (e.g., dodecylsilane and N-octylsilane), alkynes (e.g., 5-decyne), alcohols (e.g., 2,5-dimethyl-3-hexyne-2,5-diol), etc. The vapor-phase passivation process for forming at least one passivation layer can be performed using any suitable process parameters. In some embodiments, the vapor-phase passivation process can be performed at a pressure between about 1 torr and about 10 torr. In some embodiments, the dose time per cycle can be between about 0.1 s and about 2 s. In some embodiments, the number of cycles can be in the range of about 500 cycles to about 1,500 cycles. In some embodiments, at least one passivator includes a solution-phase passivator. For example, at least one passivation layer can be formed from at least one solution-phase passivator as a self-assembled monolayer (SAM) grown in solution phase. In some embodiments, at least one solution-phase passivator is an organophosphorus compound (i.e., a phosphorus-containing organic compound). For example, the passivation layer can include a monolayer of an organophosphorus compound. In some embodiments, the organophosphorus compound is an organophosphonic acid. For example, the passivation layer can include a monolayer of an organophosphonic acid. An example of an organophosphonic acid is octadecylphosphonic acid (ODPA). ODPA can be represented by the molecular / empirical formula of C 18 H 39 O 3 P and the condensed structural formula of CH 3 (CH 2 ) 16 CH 2 P(O)(OH 2 ). For example, the solution-phase passivator can include a 1:10 millimolar (mM) solution of ODPA in toluene (C 7 H 8 ). The substrate structure can be immersed in the solution for a certain length of time. For example, the length of time can be about 48 hours. A post-cleaning process (e.g., purification) can be performed after the immersion. A passivation process for selectively forming at least one passivation layer on at least one conductive layer of a substrate structure can be performed using any suitable process parameters. Examples of process parameters for performing the passivation process include temperature, passivating agent exposure time (e.g., the time of exposure to the passivating agent), pressure, etc. In some embodiments, the passivation process is performed at a temperature between about 100°C and about 350°C. In some embodiments, the passivation process is performed at a temperature between about 250°C and about 350°C. At a sufficiently high temperature, passivation degradation may occur (e.g., the temperature exceeds 350°C). Therefore, the passivation process can be performed at a temperature below a threshold temperature to maintain the quality of the passivation layer (e.g., less than or equal to about 350°C). In some embodiments, the passivation process is performed at a pressure between about 100 mTorr and about 10 mTorr. In some embodiments, the passivation process is performed at a pressure between about 500 mTorr and about 10 mTorr. In some embodiments, the passivation process is performed at a pressure between about 750 mTorr and about 10 mTorr. In some embodiments, the passivating agent exposure time is less than or equal to about 60 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 50 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 40 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 30 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 20 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 10 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 5 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 1 minute. In some embodiments, an optional pre-cleaning process is performed before selectively forming at least one passivation layer (e.g., before exposing the substrate structure to at least one passivating agent). The pre-cleaning process can improve the selectivity of the supplementary dielectric layer to be formed on the first ILD layer and / or reduce the selectivity of the supplementary dielectric layer to be formed on the first conductive material. The pre-cleaning process can include surface cleaning to remove the native oxide on the surface of at least one conductive layer. The pre-cleaning process can further remove contaminants from the surface of at least one conductive layer. The pre-cleaning process can further reduce the defect growth on at least one conductive layer. For example, the pre-cleaning process can include a thermal EtOH treatment, a hydrogen radical treatment, etc. In step 320, at least one catalyst layer is selectively formed. More specifically, each catalyst layer is selectively formed on the ILD layer of the substrate structure prior to each conductive layer of the substrate structure. Each passivation layer prevents the formation of each catalyst layer on each conductive layer. Each catalyst layer may include a suitable chemical substance to cause the formation of each supplementary dielectric layer. For example, each catalyst layer may include a strong reducing agent, metal hydride, alkyl metal, aryl metal, silane, etc. Each catalyst layer may be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer may be an Al-catalyst layer, Ti-catalyst layer, Hf-catalyst layer, Zr-catalyst layer, Ta-catalyst layer, B-catalyst layer, Ge-catalyst layer, Sn-catalyst layer, Ga-catalyst layer, In-catalyst layer, etc. As an illustrative example, the Al-catalyst layer may include Al 2 O 3 。 In some embodiments, at least one catalyst layer includes at least one catalyst layer single layer. In some embodiments, at least one catalyst layer includes at least one catalyst layer film. For example, the catalyst layer single layer may be an Al-catalyst layer, and the catalyst layer film may be an Al-containing film. In some embodiments, the Al-containing film includes Al 2 O 3 。For example, at least one catalyst layer precursor may include at least one of an Al-precursor or an O-precursor. Examples of Al-precursors include trimethylaluminum (TMA), tris(neopentyl)aluminum (TNpAl), etc. Examples of O-precursors include water (H 2 O), ozone (O 3 ), hydrogen peroxide (H 2 O 2 ), etc. The catalyst layer formation process can be carried out using any suitable process parameters. In some embodiments, the catalyst layer formation process is carried out at a temperature between about 20 °C (i.e., about room temperature) and about 600 °C. In some embodiments, the catalyst layer formation process is carried out at a temperature between about 100 °C and about 300 °C. In some embodiments, the catalyst layer formation process is carried out at a pressure between about 1 mTorr and about 760 torr (i.e., about 1 atmosphere). In some embodiments, the catalyst layer formation process is carried out at a pressure between about 1 torr and about 10 torr. In some embodiments, the feed time of at least one catalyst layer precursor is between about 0.1 s per cycle and about 60 s per cycle. For example, if at least one catalyst layer is formed as a single layer, the feed time of at least one catalyst layer precursor can be about 1 s to about 2 s. As another example, if at least one catalyst layer includes a film (e.g., Al 2 O 3 formed using a deposition process (e.g., ALD process), the feed time of each catalyst layer precursor (e.g., Al-precursor and O-precursor) can be about 0.1 s In step 330, at least one supplementary dielectric layer is selectively formed using at least one catalyst layer. Each catalyst layer is used to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can catalyze the growth of at least one supplementary dielectric layer (e.g., achieve a suitably high GPC for the deposition process used to form each supplementary dielectric layer). In some embodiments, at least one supplementary dielectric layer includes a low dielectric constant dielectric material. In some embodiments, the low dielectric constant dielectric material has a dielectric constant less than or equal to about 4. In some embodiments, at least one supplementary dielectric layer includes silicate. For example, at least one supplementary dielectric layer includes a low dielectric constant dielectric silicate (i.e., a silicate having a dielectric constant less than or equal to about 4). Examples of low dielectric constant dielectric silicates include SiO x 、SiOC, etc. At least one supplementary dielectric layer can be formed using any suitable supplementary dielectric layer formation process. In some embodiments, the supplementary dielectric layer formation process is an ALD process. For example, the ALD process can be a thermal ALD process. At least one supplementary dielectric layer can be formed by performing a suitable number of cycles of a passivation layer formation process, a catalyst layer formation process, and / or a supplementary dielectric layer formation process to achieve the target thickness of the at least one supplementary dielectric layer. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. For example, each cycle of the catalyst layer formation process can include a catalyst layer deposition precursor pulse and a purge gas pulse. As another example, each cycle of the supplementary dielectric layer formation process can include a supplementary dielectric layer deposition precursor pulse and a purge gas pulse. The purge gas can be any suitable inert gas. For example, the purge gas can be argon (Ar), nitrogen (N 2 ) etc. In some embodiments, the supplementary dielectric layer formation process utilizes at least one supplementary dielectric layer deposition precursor. For example, the at least one supplementary dielectric layer deposition precursor can include at least one deposition precursor that can form at least one supplementary dielectric layer including silicate. Examples of silicate include SiO x , SiOC, etc. In some embodiments, the at least one supplementary dielectric precursor has the following form: where each R is at least one of the following: an alkyl or alkoxy group (where the number of carbon (C) atoms is independently between 1-8), a hydrogen (H) group, an aldehyde group, a carboxyl group (e.g., carboxylic acid), an ether group, an alcohol group, a phenyl group, or other groups containing a combination of C, O, and H. In some embodiments, the at least one supplementary dielectric precursor has the following form: where each R is at least one of the following: an alkyl or alkoxy group (where the number of carbon atoms is independently between 1-8), a hydrogen (H) group, an aldehyde group, a carboxyl group (e.g., carboxylic acid), an ether group, an alcohol group, a phenyl group, or other groups containing a combination of C, O, and H, and . In some embodiments, the at least one supplementary dielectric layer includes SiO x , and the at least one supplementary dielectric layer precursor includes SiO x precursor. For example, the SiO x precursor can be an Al-catalyzed SiO xPrecursors. Al-catalyzed SiO x Examples of precursors include Si(OH)( t-BuO) 3 、Si(OH)( t-PeO) 3 and so on. In some embodiments, at least one supplementary dielectric layer comprises SiOC, and at least one supplementary dielectric layer precursor comprises a SiOC precursor. For example, the SiOC precursor can be an Al-catalyzed SiOC precursor. Examples of Al-catalyzed SiOC precursors include Si(OH)(Me)( t-BuO) 2 、Si(OH)(Et)( t-BuO) 2 、Si(OH)(Me)( t-PeO) 2 、Si(OH)(Et)( t-PeO) 2 、Si(OH)( i-Bu)( t-BuO) 2 and Si(OH)( i-Bu)( t-PeO) 2 . Thus, the SiOC precursor can form at least one supplementary dielectric layer that is doped with carbon to reduce the dielectric constant of the at least one supplementary dielectric layer. In some embodiments, forming at least one supplementary dielectric layer includes forming at least one substrate supplementary dielectric layer and using a doping agent to dope the at least one substrate supplementary dielectric layer. That is, at least one supplementary dielectric precursor can include a substrate supplementary dielectric layer precursor and a doping agent. The doping agent can be used to dope each substrate supplementary dielectric layer to reduce the dielectric constant. For example, at least one substrate supplementary dielectric layer can be formed using at least one SiO x precursor to form a layer comprising SiO xAt least one substrate-supplemental dielectric layer, and the at least one substrate-supplemental dielectric layer can be doped using at least one doping reagent to form at least one supplemental dielectric layer including SiOC. In some embodiments, the at least one doping reagent includes a silanol reagent. A silanol is a compound having an Si-O-H functional group. Examples of silanol reagents include diethyl(isopropyl)silanol, dimethylphenylsilanol, (4-methoxyphenyl)dimethylsilanol, diphenylsilanediol, methylsilanetriol, tert-butyldimethylsilanol, triethylsilanol, triisopropylsilanol, trimethylsilanol, triphenylsilanol, tris(tert-butoxy)silanol, tris(tert-pentyloxy)silanol, tris(trimethylsilyl)silanol, tris(trimethylsiloxy)silanol, tris(2-methoxyphenyl)silanol, 1,1,1,3,5,5,5-heptamethyltrisiloxane, etc. Thus, in this example, SiOC can be formed by doping carbon into SiO x rather than directly forming SiOC. The process parameters of the supplemental dielectric layer formation process (e.g., thermal ALD process) can depend on the supplemental dielectric layer precursor used to form the supplemental dielectric layer and the target thickness of the resulting supplemental dielectric layer. The target thickness can be achieved by performing a target number of deposition cycles. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the supplemental dielectric layer formation process is performed at a temperature between about 20 °C (i.e., about room temperature) and about 600 °C. In some embodiments, the supplemental dielectric layer formation process is performed at a temperature between about 100 °C and about 300 °C. In some embodiments, the supplemental dielectric layer formation process is performed at a pressure between about 1 mTorr and about 760 torr. In some embodiments, the supplemental dielectric layer formation process is performed at a pressure between about 1 torr and about 10 torr. A pressure high enough may be required to fully saturate the catalytic formation of the at least one supplemental dielectric layer. In some embodiments, the feed time of the at least one supplemental dielectric layer deposition precursor (e.g., silanol) is between about 0.1 s per cycle and about 60 s per cycle. In some embodiments, the feed time of the at least one supplemental dielectric layer deposition precursor (e.g., silanol) is between about 1 s and about 10 s. As mentioned above, the at least one passivation layer can prevent the adsorption of deposition precursors used to form the at least one catalyst layer and / or the at least one supplemental dielectric layer. Thus, due to the at least one passivation layer, a dielectric material of negligible thickness (e.g., a dielectric material with a low dielectric constant) can be formed on the at least one conductive layer during the supplemental dielectric layer deposition process (e.g., with a thickness less than about 1 nm) In some embodiments, selectively forming at least one passivation layer includes regenerating at least one passivation layer. More specifically, after selectively forming at least one catalyst layer, at least one passivation layer can be regenerated to address possible degradation of at least one passivation layer caused by the catalyst layer formation process. In some embodiments, an optional post-cleaning process is performed after forming at least one supplementary dielectric layer. Performing the post-cleaning process can include removing at least one passivation layer from the surface of at least one conductive layer. Performing the post-cleaning process can further include removing defects (e.g., dielectric material that may have been formed on at least one conductive layer during the deposition process). FIG. 4A is a diagram showing an example method 400A for selectively forming at least one supplementary dielectric (SD) layer, the method including a passivation layer formation step 410, a catalyst layer formation step of forming at least one catalyst layer, and an SD layer formation step of forming at least one SD layer using at least one catalyst layer. The catalyst layer formation step includes a catalyst layer precursor step 420 and a purification / pumping step 430. In some embodiments, the catalyst layer precursor step 420 is an Al-catalyst layer precursor step. The SD layer formation step includes an SD layer precursor formation step 440 and a purification / pumping step 450 such that X cycles are performed. The number of cycles (i.e., the value of X) can be selected such that at least one SD layer reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer includes a dielectric material with a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials with a low dielectric constant include SiO x , SiOC, etc. Thus, method 400A involves a single application of a passivation layer and a single application of a catalyst layer. FIG. 4B is a diagram showing an example method 400B for selectively forming at least one SD layer. Method 400B includes a passivation layer formation step 410, a catalyst layer formation step (including a catalyst layer precursor step 420 and a purification / pumping step 430 to form at least one catalyst layer), and an SD layer formation step (including an SD layer precursor step 440 and a purification / pumping step 450 to form at least one SD layer). In this example, the catalyst layer formation step and the SD layer formation step form a cycle (i.e., the catalyst layer formation step is repeated after the SD layer formation step) such that X cycles are performed. The number of cycles (i.e., The value of X) can be selected such that at least one SD layer reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer comprises a dielectric material having a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials having a low dielectric constant include SiO x , SiOC, etc. Thus, method 400B involves applying at least one passivation layer once and applying at least one catalyst layer multiple times. FIG. 4C is a flowchart showing an example method 400C for selectively forming at least one SD layer. Method 400C includes a passivation layer formation step 410, a catalyst layer formation step (including a catalyst layer precursor step 420 and a purge / pump step 430 to form at least one catalyst layer), and an SD layer formation step (including an SD layer precursor step 440 and a purge / pump step 450 to form at least one SD layer). In this example, the passivation layer step, the catalyst layer formation step, and the SD layer formation form a cycle (i.e., repeating the passivation layer formation step after the SD layer formation step), such that X cycles are performed. The number of cycles (i.e., the value of X) can be selected such that at least one SD layer formed during the SD layer formation step reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer comprises a dielectric material having a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials having a low dielectric constant include SiO x , SiOC, etc. Thus, method 400C involves applying at least one passivation layer multiple times and applying at least one catalyst layer multiple times. The 4D drawing shows a flowchart of an exemplary method 400D for selectively forming at least one SD layer. Method 400D includes a PL formation step 410 of forming at least one passivation layer (PL), a first CL formation step for forming at least one first catalyst layer (CL), a second CL layer formation step for forming at least one second CL, and an SD layer formation step including an SD layer precursor step 440 and a purification / pumping step 450 for forming at least one SD layer. More specifically, the first CL formation step includes a CL precursor 1 step 420-1, a purification / pumping step 430-1, a CL precursor 2 step 420-2, and a purification / pumping step 430-2. The second CL formation step includes a CL precursor 3 step 420-3 and a purification / pumping step 430-3. In some embodiments, the CL precursor 3 step 420-3 is the same as the CL precursor 1 step 420-1. For example, the CL precursor 3 step 420-3 can be performed to alkylate the surface of at least one first CL. In this example, steps 420-1 through 430-2 of the first CL formation step form a first cycle such that the first cycle is executed X 1 number of cycles. Additionally, steps 440 and 450 of the SD layer formation step form a second cycle such that the second cycle is executed X 2 number of cycles. In some embodiments, at least one first CL includes Al 2 O 3 and at least one second CL includes an Al-catalyst layer. For example, the CL precursor 1 step 420-1 can be an Al-catalyst layer precursor step, the CL precursor 2 step 420-2 can be an O-catalyst layer precursor step, and the CL precursor 3 step 420-3 can be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2 values) can be selected such that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer includes a dielectric material with a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials with a low dielectric constant include SiO x , SiOC, etc. Thus, method 400D involves applying at least one PL once, applying at least one first CL multiple times, applying at least one second CL once, and applying at least one SD layer multiple times. FIG. 4E is a flowchart showing an example method 400E for selectively forming at least one SD layer. Method 400E includes a PL formation step 410 of forming at least one PL, a first CL formation step including steps 420-1 to 430-2 of forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 of forming at least one second CL, and an SD layer formation step including steps 440 and 450 of forming at least one SD layer. In this example, steps 420-1 to 430-2 of the first CL formation step form a first cycle such that the X 1 number of cycles is executed. In addition, steps 420-3 and 430-3 of the second CL layer formation step and steps 440 and 450 of the SD layer formation step form a second cycle such that the X 2 number of cycles is executed. In some embodiments, at least one first CL includes Al 2 O 3 , and at least one second CL includes an Al-catalyst layer. For example, CL precursor 1 step 420-1 can be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 can be an O-catalyst layer precursor step, and CL precursor 3 step 4203 can be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2 values) can be selected such that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer formation step forms at least one SD layer including a dielectric material with a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials with a low dielectric constant include SiO x, SiOC, etc. Thus, method 400E involves applying at least one PL once, and applying at least one first CL, at least one second CL, and at least one SD layer multiple times (e.g., at least one second CL is regenerated after each SD layer is formed). FIG. 4F is a flowchart showing an exemplary method 400F for selectively forming at least one SD layer. Method 400F includes a PL forming step 410 of forming at least one PL, a first CL forming step including steps 420-1 to 420-2 of forming at least one first CL, a second CL layer forming step including steps 420-3 and 430-3 of forming at least one second CL, and an SD layer forming step including steps 440 and 450 of forming at least one SD layer. In this example, the PL forming step 410 and steps 420-1 to 430-2 of the first CL forming step form a first cycle, such that the X 1 number of cycles is executed. In addition, steps 440 and 450 of the SD layer forming step form a second cycle, such that the X 2 number of cycles is executed. In some embodiments, at least one first CL includes Al 2 O 3 , and at least one second CL includes an Al-catalyst layer. For example, CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2 values) can be selected such that at least one CL formed during the first CL forming step and at least one SD layer formed during the SD layer forming step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer forming step forms at least one SD layer including a dielectric material with a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials with a low dielectric constant include SiO x, SiOC, etc. Thus, method 400F involves applying at least one second CL once, and applying at least one passivation layer, at least one first CL, at least one second CL, and at least one SD layer multiple times (e.g., at least one PL is regenerated after each first / second CL layer formation cycle). FIG. 4G is a flowchart showing an example method 400G for selectively forming at least one SD layer. Method 400G includes a PL formation step 410 of forming at least one PLM, a first CL formation step including steps 420-1 to 420-2 of forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 of forming at least one second CL, and an SD layer formation step including steps 440 and 450 of forming at least one SD layer. In this example, the PL formation step 410 and steps 420-1 to 430-2 of the first CL formation step form a first cycle, such that X 1 cycles are performed. In addition, steps 420-3 and 430-3 of the second CL layer formation step and steps 440 and 450 of the SD layer formation step form a second cycle, such that X 2 cycles are performed. In some embodiments, at least one first CL includes Al 2 O 3 , and at least one second CL includes an Al-catalyst layer. For example, CL precursor 1 step 420-1 can be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 can be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 can be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2 values) can be selected such that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer formation step forms at least one SD layer including a dielectric material with a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials with a low dielectric constant include SiO x , SiOC, etc. Thus, method 400G involves applying at least one PL once, and applying at least one first CL, at least one second CL, and at least one SD layer multiple times (e.g., the second CL is regenerated after each SD layer is formed in a cycle). Figure 4H shows a flowchart of an exemplary method 400H for selectively forming at least one SD layer. Method 400H includes a PL formation step 410 of forming at least one PL, a first CL formation step including steps 420-1 to 420-2 of forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 of forming at least one second CL, and an SD layer formation step including steps 440 and 450 of forming at least one SD layer. In this example, steps 420-1 to 430-2 of the first CL formation step form a first cycle such that X 1 cycles are executed for the first cycle. In this example, an additional PL formation step 410 (e.g., regenerating at least one PL) is executed after X 1 cycles of the first cycle are executed. Additionally, steps 420-3 and 430-3 of the second CL formation step and steps 440 and 450 of the SD layer formation step form a second cycle such that X 2 cycles are executed for the second cycle. In some embodiments, at least one first CL includes Al 2 O 3 , and at least one second CL includes an Al-catalyst layer. For example, CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2The value) can be selected such that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer formation step forms at least one SD layer including a dielectric material having a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials having a low dielectric constant include SiO x , SiOC, etc. Thus, method 400H involves applying at least one PL once before the first CL formation step, applying at least one PL once after the first CL formation step, and applying at least one first CL, at least one second CL, and at least one SD layer multiple times (e.g., regenerating at least one second CL after each SD layer formation cycle). FIG. 4I is a flowchart showing an example method 400I for selectively forming at least one SD layer. Method 400I includes a PL formation step 410 of forming at least one PL, a first CL formation step including steps 420-1 to 420-2 of forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 of forming at least one second CL, and an SD layer formation step including steps 440 and 450 of forming at least one SD layer. In this example, the PL formation step 410 and steps 420-1 to 430-2 of the first CL formation step form a first cycle such that the first cycle is executed X 1 number of cycles. In this example, after executing the X 1 number of cycles of the first cycle, an additional PL formation step 410 (e.g., regenerating at least one PL) is executed. In addition, the additional PL formation step 410 and steps 420-3 and 430-3 of the second CL formation step and steps 440 and 450 of the SD layer formation step form a second cycle such that the second cycle is executed X 2 number of cycles. In some embodiments, at least one first CL includes Al 2 O 3, and at least one second CL includes an Al-catalyst layer. For example, the CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, the CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and the CL precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., X 1 and X 2 value) can be selected such that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer formation step forms at least one SD layer including a dielectric material having a low dielectric constant (e.g., a low dielectric constant dielectric silicate). Examples of dielectric materials having a low dielectric constant include SiO x , SiOC, etc. Thus, method 400I involves applying at least one PL multiple times before the first CL formation step (e.g., regenerating at least one PL after each first CL formation cycle), and applying at least one PL layer, at least one first CL, at least one second CL, and at least one SD layer multiple times after the first CL formation step (e.g., regenerating at least one PL and at least one second CL after each SD layer formation cycle). FIG. 5 is a block diagram of an example electronic component processing system ("system") 500 that can be used to manufacture electronic components using area-selective deposition according to some embodiments. For example, system 500 can be used to form component 100 described above with reference to FIGS. 1A-1D. As another example, system 500 can implement methods 200-400I described above with reference to FIGS. 2-4I. As shown in the figure, system 500 includes a passivation chamber 510, a transfer chamber 520, and a deposition chamber 530. Interface 540-1 can be disposed between the passivation chamber 310 and the transfer chamber 520, and interface 540-2 can be disposed between the transfer chamber 520 and the deposition chamber 530. In some embodiments, interfaces 540-1 and 540-2 are corresponding gate valves. The transfer chamber 520 can include a transfer robot (not shown). The transfer chamber 520, the passivation chamber 510, and the deposition chamber 530 can each be maintained under vacuum under controlled conditions (e.g., very low or no humidity). Although not shown, system 500 can further include at least one load lock chamber and at least one factory interface to enable substrates to move from the atmosphere to the transfer chamber 520. Thus, substrates can be transferred between chambers without breaking the vacuum and, therefore, without exposing the substrates to air and / or humidity. The passivation chamber 510 can passivate at least one conductive layer of a substrate structure by exposing the at least one conductive layer to a passivation agent. The passivation chamber 510 can be operatively coupled to at least one reservoir 512. In some embodiments, the at least one reservoir 512 includes at least one passivation agent reservoir for storing at least one passivation agent. In some embodiments, the at least one passivation agent reservoir stores a gaseous passivation agent. In some embodiments, the at least one passivation agent reservoir stores a solution-phase passivation agent. The at least one reservoir 512 can further include at least one purge gas reservoir for storing any suitable inert gas (e.g., Ar or N 2 ) for purging the passivation chamber 512 during the passivation process. Further details regarding passivating conductive materials with a passivation agent are described above with reference to FIGS. 1B and 2 through 4I. The deposition chamber 530 can be operatively coupled to at least one reservoir 532. The deposition chamber 530 can perform a deposition process for selectively forming a catalyst layer on a first ILD layer and / or a deposition process for selectively forming a supplementary dielectric layer on the first ILD layer. The at least one reservoir 532 can include at least one deposition precursor reservoir. The at least one deposition precursor reservoir can store any suitable deposition precursor for forming the catalyst layer and / or the supplementary dielectric layer. The at least one reservoir 532 can further include a purge gas reservoir for storing any suitable inert gas (e.g., Ar or N 2). After passivating at least one conductive layer, in some embodiments, the transfer robot may transfer the electronic component to the deposition chamber 530. Further details regarding the deposition process of selectively forming a catalyst layer on the first ILD layer and / or the deposition process of selectively forming a supplementary dielectric layer on the first ILD layer are described above with reference to FIGS. 1C-1D and FIGS. 2-4I. In some embodiments, the deposition process is performed in the passivation chamber 510 (i.e., the passivation chamber 510 is a processing chamber configured to perform the passivation process and the deposition process). In these embodiments, at least one reservoir 532 is operatively coupled to the passivation chamber 510. In some embodiments, the passivation process is performed in the deposition chamber 530 (i.e., the deposition chamber 530 is a processing chamber configured to perform the passivation process and the deposition process). In these embodiments, at least one reservoir 512 is operatively coupled to the deposition chamber 530. In some embodiments, the system 500 may optionally include a cleaning chamber 550 to perform an optional cleaning process (i.e., a pre-cleaning process) before passivation and / or an optional cleaning process (i.e., a post-cleaning process) after forming the supplementary dielectric layer. The interface 540-3 may be provided between the cleaning chamber 550 and the transfer chamber 520. In some embodiments, the cleaning chamber 550 is an in-situ cleaning chamber, and the interface 540-3 is a gate valve. In some embodiments, the cleaning chamber 550 is a non-in-situ cleaning chamber, and the interface 540-3 is a load-lock chamber. The cleaning chamber 550 may be operatively coupled to at least one reservoir 552. At least one reservoir 552 may include any suitable cleaning chemicals for performing the pre-cleaning and / or the post-cleaning. At least one reservoir 552 may further include a purge gas reservoir for storing a suitable inert gas (e.g., Ar or N 2 ). In some embodiments, the pre-cleaning process may be performed in the same chamber as the passivation (e.g., the passivation chamber 510 or the deposition chamber 530). In these embodiments, at least one reservoir 552 may be operatively coupled to the passivation chamber 510 and / or the deposition chamber 530. In some embodiments, the post-cleaning process may be performed in the passivation chamber 510 and / or the deposition chamber 530. In these embodiments, at least one reservoir 552 may be operatively coupled to the passivation chamber 510 and / or the deposition chamber 530. Further details regarding the execution of the cleaning process (e.g., the pre-cleaning process and / or the post-cleaning process) are described above with reference to FIG. 2. Further electronic component processing as described above with reference to FIGS. 1E-2 may be performed using one or more of the chambers 510-530 and 550. The foregoing description sets forth several specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be practiced without such specific details. In other instances, well-known components or methods have not been described in detail and are provided in a simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth are merely exemplary. Specific implementations may vary from these exemplary details and still be contemplated within the scope of the present disclosure. Throughout this specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification do not necessarily all refer to the same embodiment. Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". When the term "about" or "approximate" is used herein, this is intended to mean that the stated value is accurate within ±10%. Although the operations of the methods herein are illustrated and described in a particular order, the order of operations of each method may be changed such that certain operations may be performed in a reverse order, or such that certain operations may be performed at least partially concurrently with other operations. In another embodiment, the instructions or sub-operations of different operations may be in an intermittent and / or alternating fashion. It will be understood that the above description is intended to be illustrative and not restrictive. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Accordingly, the scope of the present disclosure should be determined with reference to the appended claims along with the full scope of equivalents to such claims. 100: Electronic component 110-1: ILD layer 110-2: ILD layer 120: Conductive layer 125: Passivation layer 130: Catalyst layer 140: Dielectric layer 150: Conductive layer 200: Method 210: Step 220: Step 230: Step 240: Step 250: Step 300: Method 310: Step 320: Step 330: Step 400A: Method 400B: Method 400C: Method 400D: Method 400E: Method 400F: Method 400G: Method 400H: Method 400I: Method 410: Step 420: Step 420-1: Step 420-2: Step 420-3: Step 430: Step 430-1: Step 430-2: Step 430-3: Step 440: Step 450: Step 500: System 510: Passivation chamber 512: Storage 520: Transfer chamber 530: Deposition chamber 532: Storage 540-1: Interface 540-2: Interface 540-3: Interface 550: Cleaning chamber 552: Storage The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate like elements. It should be noted that in the present disclosure, different references to "an" or "one" embodiment are not necessarily the same embodiment, and such references mean at least one. FIGS. 1A to 1F are cross-sectional views showing example methods of manufacturing an electronic component using area-selective deposition according to some embodiments. FIG. 2 is a flowchart of an example method of manufacturing an electronic component using area-selective deposition according to some embodiments. FIGS. 3 to 4I are diagrams of example methods of selectively forming at least one supplementary dielectric layer during the manufacture of an electronic component according to some embodiments. FIG. 5 is a block diagram of an example electronic component processing system that can be used to manufacture an electronic component using area-selective deposition according to some embodiments. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None 100: Electronic component 110-1: ILD layer 110-2: ILD layer 120: Conductive layer 130: Catalyst layer 140: Dielectric layer 150: Conductive layer

Claims

1. A method for region-selective deposition, comprising the steps of: selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively forming at least one catalyst layer on the first ILD layer, wherein the at least one passivation layer prevents the formation of the at least one catalyst layer on the first conductive layer; selectively forming at least one supplementary dielectric layer using the at least one catalyst layer, wherein the at least one catalyst layer causes the formation of the at least one supplementary dielectric layer, and wherein the at least one supplementary dielectric layer comprises a dielectric material having a dielectric constant less than or equal to about 4; forming a second ILD layer over the at least one supplementary dielectric layer and the at least one first conductive layer; and forming at least one second conductive layer in the second ILD layer in contact with the at least one first conductive layer, wherein the at least one first conductive layer comprises a first via, and the at least one second conductive layer comprises a second via in contact with the first via.

2. The method of claim 1, wherein the step of selectively forming the at least one passivation layer comprises the step of forming the at least one passivation layer using a vapor-phase passivating agent.

3. The method of claim 1, wherein the step of selectively forming the at least one passivation layer comprises the step of forming the at least one passivation layer using a solution-phase passivating agent.

4. The method of claim 1, wherein the at least one catalyst layer comprises at least one of the following: a metal catalyst layer or a class of metal catalyst layers.

5. The method of claim 4, wherein the step of selectively forming the at least one supplementary dielectric layer comprises the step of forming the at least one supplementary dielectric layer using a catalytic precursor.

6. The method of claim 1, wherein the at least one supplementary dielectric layer comprises a silicate.

7. The method of claim 6, wherein the silicate comprises at least one of the following: silicon oxide (SiOX) or silicon carbide (SiOC).

8. The method of claim 1, wherein the at least one supplementary dielectric layer has a thickness of about 10 nm to about 20 nm.

9. A system for region-selective deposition comprising at least one chamber operatively coupled to at least one reservoir, the at least one chamber being configured to: selectively form at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively form at least one catalyst layer on the first ILD layer, wherein the at least one passivation layer prevents the formation of the at least one catalyst layer on the first conductive layer; selectively form at least one supplementary dielectric layer using the at least one catalyst layer, wherein the at least one catalyst layer causes the formation of the at least one supplementary dielectric layer, and wherein the at least one supplementary dielectric layer comprises a dielectric material having a dielectric constant less than or equal to about 4; form a second ILD layer over the at least one supplementary dielectric layer and the at least one first conductive layer; and form at least one second conductive layer in contact with the at least one first conductive layer within the second ILD layer, wherein the at least one first conductive layer comprises a first via, and the at least one second conductive layer comprises a second via in contact with the first via.

10. The system of claim 9, wherein the at least one storage device maintains at least one of the following: a vapor-phase passivating agent for selectively forming the at least one passivation layer, or a solution-phase passivating agent for selectively forming the at least one passivation layer.

11. The system of claim 9, wherein the at least one storage device holds at least one catalyst layer precursor for selectively forming the at least one catalyst layer.

12. The system of claim 9, wherein the at least one catalyst layer comprises at least one of the following: a metal catalyst layer or a class of metal catalyst layers.

13. The system of claim 9, wherein the at least one chamber is configured to form the at least one supplementary dielectric layer using a catalytic precursor.

14. The system of claim 9, wherein the at least one supplementary dielectric layer comprises a silicate, wherein the at least one reservoir holds a silanol, and wherein the at least one chamber is configured to use the silanol as a deposition precursor to form the at least one supplementary dielectric layer.

15. The system of claim 14, wherein the silicate comprises at least one of the following: silicon oxide (SiOX) or silicon carbide (SiOC).

16. The system of claim 9, wherein the at least one supplementary dielectric layer has a thickness between about 10 nm and about 20 nm.

Images