Electronic device

Abstract

This application relates to an electronic device, including a substrate, a first conductive layer, an electronic unit, a sensing unit, and a sensing unit driving circuit. The first conductive layer is disposed on the substrate and includes a first gate and a line segment, with the line segment connected to the first gate. The electronic unit and the sensing unit are respectively disposed on the substrate. The sensing unit driving circuit is disposed on the substrate and electrically connected to the electronic unit and the sensing unit. The sensing unit driving circuit includes a first transistor, the first transistor having a first gate, and the outline of the first gate being different from the outline of the line segment.

Description

Technical Field

[0001] This application relates to an electronic device, particularly an electronic device having display and sensing functions. Prior Technology

[0002] Some electronic devices require both display and sensing functions. However, current display and sensing circuits are two separate circuits, which occupy a lot of space and result in low space utilization. As a result, current electronic devices on the market cannot have both high-resolution display and high-precision sensing functions.

[0003] Therefore, a novel electronic device is needed to improve the above problems. Summary of the Invention

[0004] This application provides an electronic device comprising a substrate, a first conductive layer, an electronic unit, a sensing unit, and a sensing unit driving circuit. The first conductive layer is disposed on the substrate and includes a first gate and a line segment, with the line segment connected to the first gate. The electronic unit and the sensing unit are respectively disposed on the substrate. The sensing unit driving circuit is disposed on the substrate and electrically connected to the electronic unit and the sensing unit. The sensing unit driving circuit includes a first transistor, the first transistor having a first gate, and the outline of the first gate being different from the outline of the line segment. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Figure 2 is a schematic diagram of a corner area of ​​an electronic device according to an embodiment of this application. Figure 3 is a schematic diagram of the basic driving circuit of an electronic device according to an embodiment of this application. Figure 4 is a detailed circuit diagram of an electronic device according to an embodiment of this application. Figure 5 is a signal timing diagram corresponding to the circuit structure in Figure 4. Figure 6 is a schematic diagram of the wiring configuration of an electronic device according to an embodiment of this application. Figure 7 is a schematic diagram of the detailed circuit structure of an electronic device according to another embodiment of this application. Figure 8 is a signal timing diagram corresponding to the circuit structure in Figure 7. Figure 9 is a schematic diagram of the wiring configuration of the reset transistor of an electronic device according to an embodiment of this application. Figure 10 is a schematic diagram of the wiring configuration of the reset transistor of an electronic device according to another embodiment of this application. Figure 11 is a schematic diagram of the wiring configuration of the reset transistor of an electronic device according to another embodiment of this application. Figure 12 is a schematic diagram of the wiring configuration of the reset transistor of an electronic device according to another embodiment of this application. Figure 13 is a cross-sectional view of a reset transistor according to an embodiment of this application. Figure 14 is a cross-sectional view of a reset transistor according to another embodiment of this application. Figure 15 is a cross-sectional view of a reset transistor according to another embodiment of this application. Figure 16 is a schematic diagram of the circuit structure of an electronic device according to another embodiment of this application. Figure 17 is a schematic diagram of the circuit structure of an electronic device according to another embodiment of this application. Implementation

[0006] The exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0007] Throughout this specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that sensing device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "containing," "including," and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0008] The terms “approximately,” “substantially,” or “roughly” are generally interpreted as being within 10% of a given value or range, or as being within 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0009] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify components do not inherently imply any prior ordinal number for that component, nor do they represent the order of one component with another, or the order of manufacture. These ordinal numbers are used solely to clearly distinguish one named component from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claim.

[0010] In this application, the terms "given range is from the first value to the second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between.

[0011] Furthermore, the control method disclosed in this application can be used in vehicles equipped with electronic devices, wherein the electronic devices may include automotive devices, imaging devices, assembly devices, backlight devices, antenna devices, splicing devices, touch displays, curved displays, or free-shape displays, but are not limited thereto. Electronic devices may include, for example, liquid crystals, light-emitting diodes, fluorescent, phosphorescent, other suitable display media, or combinations thereof, but are not limited thereto. Display devices may be non-emissive or self-emissive. Antenna devices may be liquid crystal antenna devices or non-liquid crystal antenna devices, and sensing devices may be sensing capacitive, light, heat, or ultrasonic waves, but are not limited thereto. Splicing devices may include, for example, display splicing devices or antenna splicing devices, but are not limited thereto. It should be noted that the electronic devices may be any arrangement or combination of the foregoing, but are not limited thereto. Furthermore, the electronic devices may be bendable or flexible. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, light source systems, and shelving systems to support display devices, antenna devices, or splicing devices.

[0012] It should be understood that the features described below can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of this application. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0013] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this application, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this application.

[0014] In addition, the word "adjacent" in the specification and request items is used to describe mutual proximity, and the two adjacent items may or may not be in contact.

[0015] Furthermore, descriptions such as "when..." or "...when" in this application indicate states such as "at present, before, or after," and are not limited to simultaneous occurrences; this is stated in advance. Descriptions such as "set on..." in this application indicate the corresponding positional relationship between two elements, and do not limit whether the two elements are in contact, unless specifically limited; this is stated in advance. Moreover, when this application describes multiple functions, the use of the word "or" between functions indicates that the functions can exist independently, but does not preclude the simultaneous existence of multiple functions.

[0016] Figure 1 is a schematic diagram of an electronic device 1 according to an embodiment of this application. As shown in Figure 1, the electronic device 1 has an active area AA and a peripheral area PA. The active area AA is a light-emitting area, which includes a main area A, a plurality of peripheral areas B and a plurality of corner areas C. The peripheral areas B may, for example, surround the main area A. In one embodiment, the corner areas C may, for example, be an arc-shaped structure, but are not limited thereto.

[0017] Figure 2 is a schematic enlarged view of an outer region Z of an electronic device 1 according to an embodiment of this application, and please refer to Figure 1 simultaneously. As shown in Figure 2, the electronic device 1 may include a substrate 10, a plurality of electronic units 25, and a plurality of sensing units 35. The electronic units 25 and sensing units 35 are respectively disposed on the substrate 10. Furthermore, in the outer region Z of the electronic device 1, the active region AA may include a main region A and a corner region C, and the main region A and / or the corner region C may be provided with electronic units 25 and / or sensing units 35 as needed. Similarly, the peripheral region B (not shown) may be provided with sensing units 35 as needed, or may not be provided with sensing units 35. The corner region C may be located between the main region A and the peripheral region PA.

[0018] In one embodiment, the electronic unit 25 can be used to transmit electromagnetic waves, such as light, but is not limited thereto. In one embodiment, the electronic unit 25 is, for example, a light-emitting unit or a display unit. When the electronic unit 25 is a light-emitting unit, it may be, for example, an organic light-emitting diode (OLED), but is not limited thereto. When the electronic unit 25 is a display unit, it may be, for example, a thin-film transistor (TFT) or a liquid crystal, but is not limited thereto. For ease of explanation, the following examples will use an organic light-emitting diode as the electronic unit 25.

[0019] In one embodiment, the sensing unit 35 can be used to receive electromagnetic waves, such as light, but not limited thereto. In one embodiment, the sensing unit 35 can be a light sensing unit, such as, but not limited to, an organic photodiode (OPD). Multiple sensing units 35 can be used to sense, for example, ambient light or fingerprints, and are not limited thereto.

[0020] In one embodiment, the electronic units 25 and sensing units 35 may be arranged in an alternating manner in the main area A and / or corner area C, but in practice, they can be arbitrarily configured as needed. In one embodiment, the area of ​​the main area A may be different from the area of ​​the corner area C. In one embodiment, the shape of the main area A may be different from the shape of the corner area C. In one embodiment, the size of the electronic units 25 and / or sensing units 35 in the main area A may be different from the size of the electronic units 25 and / or sensing units 35 in the corner area C. For example, the size of the electronic units 25 in the main area A may be smaller than the size of the electronic units 25 in the corner area C, and the size of the sensing units 35 in the main area A may be smaller than the size of the sensing units 35 in the corner area C, but this is not a limitation.

[0021] Please refer to Figures 1 and 2 simultaneously. In one embodiment, the active area AA of the electronic device 1 (including the main area A and the corner area C) is provided with both an electronic unit 25 and a sensing unit 35, while the peripheral area B (e.g., multiple sides) of the electronic device 1 is provided with a sensing unit 35. This enables the simultaneous sensing of multiple fingerprints, thereby improving the accuracy of the sensing.

[0022] Next, the basic driving method of the electronic unit 25 and the sensing unit 35 will be described. Figure 3 is a schematic diagram of the basic driving circuit of the electronic device 1 according to an embodiment of this application, and please refer to Figures 1 and 2 simultaneously. In particular, Figure 3 shows the basic driving circuit of a single electronic unit 25 and sensing unit 35, and those skilled in the art can infer the state of multiple electronic units 25 and sensing units 35 from it. More specifically, the electronic device 1 may have multiple sets of scanning columns (not shown in the figure), each set of scanning columns having at least one electronic unit, and the electronic unit 25 in Figure 3 is, for example, the electronic unit in the Nth set of scanning columns.

[0023] As shown in Figure 3, in one embodiment, the electronic device 1 may include an electronic unit driving circuit 20 disposed on the substrate 10, and the electronic unit driving circuit 20 is electrically connected to the electronic unit 25. The electronic unit driving circuit 20 may, for example, be located in the active region AA. The electronic unit driving circuit 20 may include a driving transistor T1, a data writing transistor T2, a reset transistor T3, a transistor T4, a transistor T5, and a switching transistor T6, but is not limited thereto, wherein at least one of the aforementioned transistors T1 to T6 may be electrically connected to the electronic unit 25. The driving transistor T1 may include a first terminal a1, a second terminal b1, and a control terminal c1, wherein the first terminal a1 may be a drain or a source, the second terminal b1 may be a drain or a source, and the control terminal c1 may be a gate. Transistor T2 for writing data may include a first terminal a2, a second terminal b2, and a control terminal c2, wherein the first terminal a2 may be a drain or a source, the second terminal b2 may be a drain or a source, and the control terminal c2 may be a gate. Transistor T3 for resetting data may include a first terminal a3, a second terminal b3, and a control terminal c3, wherein the first terminal a3 may be a drain or a source, the second terminal b3 may be a drain or a source, and the control terminal c3 may be a gate. Transistor T4 may include a first terminal a4, a second terminal b4, and a control terminal c4, wherein the first terminal a4 may be a drain or a source, the second terminal b4 may be a drain or a source, and the control terminal c4 may be a gate. Transistor T5 may include a first terminal a5, a second terminal b5, and a control terminal c5, wherein the first terminal a5 may be a drain or a source, the second terminal b5 may be a drain or a source, and the control terminal c5 may be a gate. The switching transistor T6 may include a first terminal a6, a second terminal b6 and a control terminal c6, wherein the first terminal a6 may be a drain or a source, the second terminal b6 may be a drain or a source, and the control terminal c6 may be a gate.

[0024] In one embodiment, the materials of the driving transistor T1, the data writing transistor T2, the transistor T4, and the transistor T5 may include polysilicon, such as low-temperature polysilicon (LTPS), and the materials of the reset transistor T3 and the switching transistor T6 may include metal oxides, such as indium gallium zinc oxide (IGZO), but are not limited thereto.

[0025] Furthermore, the electronic device 1 may include a sensing unit driving circuit 30 disposed on the substrate 10 and electrically connected to the electronic unit 25 and the sensing unit 35. The sensing unit driving circuit 30 may, for example, be located in the active region AA. The sensing unit driving circuit 30 may include a driving transistor ST1, a reset transistor ST2, and a data transmission transistor ST3, but is not limited thereto. The driving transistor ST1 may include a first terminal as1, a second terminal bs1, and a control terminal cs1, wherein the first terminal as1 may be a drain or a source, the second terminal bs1 may be a drain or a source, and the control terminal cs1 may be a gate. The reset transistor ST2 may include a first terminal as2, a second terminal bs2, and a control terminal cs2, wherein the first terminal as2 may be a drain or a source, the second terminal bs2 may be a drain or a source, and the control terminal cs2 may be a gate. The data transmission transistor ST3 may include a first terminal as3, a second terminal bs3 and a control terminal cs3, wherein the first terminal as3 may be a drain or a source, the second terminal bs3 may be a drain or a source, and the control terminal cs3 may be a gate.

[0026] In one embodiment, the amplifying transistor ST1 may be made of polysilicon, such as LTPS, the resetting transistor ST2 may be made of metal oxide, such as IGZO, and the data transmission transistor ST3 may be made of polysilicon (such as LTPS) or metal oxide (such as IGZO), but is not limited thereto.

[0027] In another embodiment, the electronic device 1 may further include multiple driving units SN(N), SN_I(NX), SN_I(N), and EM(N) disposed on the substrate 10, wherein SN_I(NX) and SN_I(N) are the same driving unit but drive different scan columns. The driving units SN(N), SN_I(NX), SN_I(N), and EM(N) may be located, for example, in the outer region Z outside the active region AA, such as the peripheral region PA, but are not limited thereto. In one embodiment, the driving units SN(N), SN_I(NX), SN_I(N), and EM(N) may be, for example, gate drivers of the aforementioned transistors T1~T6 or ST1~ST3, but are not limited thereto.

[0028] Furthermore, when the electronic unit driving circuit 20 and the sensing unit driving circuit 30 shown in Figure 3 correspond to the Nth group of scanning columns of the electronic device 1, generally speaking, the driving unit SN(N) can be, for example, a gate driver that drives the LTPS transistors in the Nth group of scanning columns to write data, EM(N) can be, for example, a gate driver that drives the LTPS transistors in the Nth group of scanning columns to emit light, the driving unit SN_I(N) can be, for example, a gate driver that drives the IGZO transistors in the Nth group of scanning columns to turn on, the driving unit SN(NX) can be, for example, a gate driver that drives the LTPS transistors in the first X groups of scanning columns (each group contains at least one scanning column) to write data, and the driving unit SN_I(NX) can be, for example, a gate driver that drives the IGZO transistors in the first X groups of scanning columns to turn on, where X can be a positive integer greater than or equal to 1 (X≧1). For ease of explanation, X is 1 in the following examples. It should be noted that, in this application, in order to integrate the electronic unit driving circuit 20 and the sensing unit driving circuit 30, the transistors of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 in the Nth group of scanning columns will not only be driven by the driving units SN(N), EM(N) and SN_I(N), but may also be driven by the driving units SN(NX) and SN_I(NX) corresponding to the first X groups of scanning columns, and may even be driven by the driving units corresponding to the last Y groups of scanning columns (each group contains at least one scanning column) (e.g., SN(N+Y), SN_I(N+Y, shown in Figures 5, 7, and 8), where Y can be a positive integer greater than or equal to 0 (Y≧0).

[0029] In another embodiment, the driving units SN(N), SN_I(NX), SN_I(N) and EM(N) may each include a transistor, or the driving units SN(N), SN_I(NX), SN_I(N) and EM(N) may each be regarded as a transistor.

[0030] Next, the details of the electronic unit drive circuit 20 will be explained.

[0031] In one embodiment, the first terminal a1 of the driving transistor T1 is electrically connected to the second terminal b2 of the data writing transistor T2 and the second terminal b4 of the transistor T4. The second terminal b1 of the driving transistor T1 is electrically connected to the first terminal a5 of the transistor T5, and the control terminal c1 of the driving transistor T1 is electrically connected to the first terminal a6 of the switching transistor T6. The first terminal a2 of the data writing transistor T2 is electrically connected to a data line DL, and the control terminal c2 of the data writing transistor T2 is electrically connected to the driving unit SN (N). The first terminal a3 of the reset transistor T3 is electrically connected to the control terminal c1 of the driving transistor T1 and forms a capacitor with a high potential Vdd. The second terminal b3 of the reset transistor T3 is electrically connected to an initial signal Vini, and the control terminal c3 of the reset transistor T3 is electrically connected to the driving unit SN_I (NX). The first terminal a4 of the transistor T4 is electrically connected to the high potential Vdd, and the control terminal c4 of the transistor T4 is electrically connected to the driving unit EM (N). The second terminal b5 of transistor T5 can be electrically connected to electronic unit 25, and the control terminal c5 of transistor T5 can be electrically connected to driving unit EM(N). The second terminal b6 of switching transistor T6 can be electrically connected to the first terminal a5 of transistor T5, and the control terminal c6 of switching transistor T6 can be electrically connected to driving unit SN_I(N). In one embodiment, a high potential Vdd can be used to adjust the luminous brightness of electronic unit 25. One end of electronic unit 25 is electrically connected to the second terminal b5 of transistor T5, and the other end of electronic unit 25 is electrically connected to a low potential Vss.

[0032] Next, the details of the sensing unit drive circuit 30 will be explained.

[0033] In one embodiment, the first terminal as1 of the amplifying transistor ST1 is electrically connected to a high potential Vdd, the second terminal bs1 of the amplifying transistor ST1 is electrically connected to the first terminal as3 of the data transmission transistor ST3, and the control terminal ac1 of the amplifying transistor ST1 is electrically connected to the second terminal bs2 of the reset transistor ST2. The first terminal as2 of the reset transistor ST2 is electrically connected to the initial signal Vini, and the control terminal cs2 of the reset transistor ST2 is electrically connected to the drive unit SN_I (NX). The second terminal bs3 of the data transmission transistor ST3 is electrically connected to a signal readout line RL. Furthermore, when the material of the data transmission transistor ST3 contains metal oxide, the control terminal cs3 of the data transmission transistor ST3 is electrically connected to the drive unit SN_I (N), and when the material of the data transmission transistor ST3 contains polysilicon, the control terminal cs3 of the data transmission transistor ST3 is electrically connected to the drive unit SN (N). It should be noted that Figure 3 shows the state of the data transmission transistor ST3, which is made of polycrystalline silicon. Therefore, the control terminal CS3 of the data transmission transistor ST3 can be electrically connected to the drive unit SN(N).

[0034] Therefore, the drive unit SN_I(NX) can be used to control the reset transistor T3 and the reset transistor ST2. Here, "control" means, for example, controlling the transistors to turn on or off. In other words, the drive unit SN_I(NX) can control a signal S SN_I(NX) to be transmitted to the reset transistor T3 and the reset transistor ST2, where the signal S SN_I(NX) can be considered, for example, a reset signal. The drive unit SN_I(N) can be used to control the switching transistor T6 and the data transmission transistor ST3 (when its material includes IGZO). In other words, the drive unit SN_I(N) can control a signal S SN_I(N) to be transmitted to the switching transistor T6 and the data transmission transistor ST3 (IGZO). The drive unit SN(N) can be used to control the data writing transistor T2 and the data transmission transistor ST3 (when its material includes LTPS). In other words, the drive unit SN(N) can control a signal S SN(N) to be transmitted to the data writing transistor T2 and the data transmission transistor ST3 (LTPS). The drive unit EM(N) can be used to control transistors T4 and T5. In other words, the drive unit EM(N) can control a signal S EM(N) to be transmitted to transistors T4 and T5, where the signal S EM(N) can be regarded, for example, as a switching signal.

[0035] Figure 4 is a detailed circuit diagram of an electronic device according to an embodiment of this application. Please also refer to Figures 1 to 3. Since the circuit structures of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 are already shown in Figure 3, Figure 4 simplifies the circuit structures of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 for clarity. Since Figure 4 uses the data transmission transistor ST3 as an example where the material contains polycrystalline silicon, the driving unit SN(N) can control the data transmission transistor ST3 to turn on or off.

[0036] As shown in Figure 4, the electronic device 1 may include a driving unit SN(N), a driving unit SN_I(N), a driving unit SN_I(N-1), and a driving unit EM(N). The driving unit SN_I(N-1) can be used to control the reset transistor T3 of the electronic unit driving circuit 20 and the reset transistor ST2 of the sensing unit driving circuit 30. The driving unit SN(N) can be used to control the data writing transistor T2 of the electronic unit driving circuit 20 and the data transmission transistor ST3 of the sensing unit driving circuit 30.

[0037] Although reset transistor T3 and reset transistor ST2 can share the same drive unit SN (NX), they may need to be turned on at different times. Therefore, in one embodiment, the electronic device 1 may further include a transistor T7 disposed on the substrate 10. Transistor T7 can be electrically connected between reset transistor ST2 and reset transistor ST3. For example, a first terminal a7 of transistor T7 can be electrically connected to the drive unit SN_I (NX) and reset transistor T3, and a second terminal b7 of transistor T7 can be electrically connected to reset transistor ST2. Furthermore, a control terminal c7 of transistor T7 can be electrically connected to a reset control signal Sreset. Therefore, the potential of the reset control signal Sreset can be used to control the switching on or off of transistor T7. Therefore, when transistor T7 is off, the signal S SN_I(NX) provided by the drive unit SN_I(NX) can be transmitted to the electronic unit drive circuit 20 but not to the sensing unit drive circuit 30. When transistor T7 is on, the signal S SN_I(NX) provided by the drive unit SN_I(NX) can be transmitted to the sensing unit drive circuit 30 through transistor T7. Thus, the switching times of reset transistor T3 and reset transistor ST2 can be controlled.

[0038] In one embodiment, although the data transmission transistor ST3 and the data writing transistor T2 can share the same driving unit SN(N), the data writing transistor T2 and the data transmission transistor ST3 may need to be turned on at different times. Therefore, the electronic device 1 may also include a transistor T8, wherein a first terminal a8 of the transistor T8 is electrically connected to the driving unit SN(N) and the data writing transistor T2, a second terminal b8 of the transistor T8 is electrically connected to the data transmission transistor ST3, and a control terminal c8 of the transistor T8 is electrically connected to a readout control signal Sread, wherein the potential of the readout control signal Sread can be used to control the transistor T8 to be turned on or off. Therefore, when transistor T8 is off, the signal S SN(N) provided by the driving unit SN(N) can be transmitted to the electronic unit driving circuit 20 but not to the sensing unit driving circuit 30. When transistor T8 is on, the signal S SN(N) provided by the driving unit SN(N) can be transmitted to the sensing unit driving circuit 30. Thus, the switching timing of data writing transistor T2 and data transmission transistor ST3 can be controlled.

[0039] It should be noted that in another embodiment, when the data transmission transistor ST3 is an IGZO transistor, the switching transistor T6 (shown in FIG3) and the data transmission transistor ST3 can share the driving unit SN_I(N). In this case, the first terminal a8 of the transistor T8 can be electrically connected to the driving unit SN_I(N) and the switching transistor T6, for example, and is not limited thereto.

[0040] Figure 5 is the signal timing diagram corresponding to the circuit structure in Figure 4. Please also refer to Figure 3.

[0041] In one embodiment, the electronic device 1 can execute a display mode and a sensing mode, wherein the time for executing the display mode once is defined as a display frame TA, and the time for executing the sensing mode once is defined as a sensing frame TB. In one embodiment, the display mode may include a reset phase, a data writing phase, and a light emission phase, while the sensing mode may include a reset phase and a data transmission phase.

[0042] As shown in Figure 5, the display frame TA can contain multiple sub-periods, such as ta1~ta3, and the sensing frame TB can contain multiple sub-periods, such as tb1~tb2. Furthermore, in the example of Figure 5, the execution time of the sensing mode is later than that of the display mode. For example, the first sensing frame TB can be followed by the first display frame TA and at least partially overlap with the second display frame TA.

[0043] Furthermore, in the example of Figure 5, signals SSN_I(NX) and SSN_I(N) are set to turn on the transistor when the voltage is high, while signals SSN(N), SEM(N), reset control signal Sreset, and readout control signal Sread are set to turn on the transistor when the voltage is low, but in reality, it is not limited to this.

[0044] First, let's explain the operation of the display mode, taking the first display frame TA as an example.

[0045] During the first sub-period ta1 of display frame TA, the signal S SN_I(NX) provided by the driving unit SN_I(NX) changes from a low potential to a high potential (which can be regarded as the transistor of the driving unit SN_I(NX) being turned on; therefore, the first sub-period ta1 of display frame TA can be considered as an on-time t11 of the transistor of the driving unit SN_I(NX)). This causes the reset transistor T3 of the electronic unit driving circuit 20 to turn on and receive the initial signal Vini. At this time, the other transistors are in the off state, so the reset phase of the display mode can be executed. It should be noted that since the reset control signal Sreset is at a high potential at this time, the transistor T7 is off, so the control terminal cs2 of the reset transistor ST2 does not receive the signal S SN_I(NX), and therefore the reset transistor ST2 is off.

[0046] During the second sub-period ta2 of display frame TA, the signal S SN_I(N) provided by the driving unit SN_I(N) changes from a low potential to a high potential (which can be considered as the transistor of the driving unit SN_I(N) being turned on, therefore the second sub-period ta2 of display frame TA can be considered as an on-time t12 of the transistor of the driving unit SN_I(N)), causing the switching transistor T6 of the electronic unit driving circuit 20 to turn on. At the same time, the signal S SN(N) provided by the driving unit SN(N) changes from a high potential to a low potential (which can also be considered as the transistor of the driving unit SN(N) being turned on, therefore the second sub-period ta2 of display frame TA can be considered as an on-time t13 of the transistor of the driving unit SN(N)), causing the data writing transistor T2 of the electronic unit driving circuit 20 to turn on and receive the data signal Data. At this time, the other transistors are in a closed state, so the data writing phase of the display mode can be executed. It should be noted that since the readout control signal Sread is at a high potential at this time, transistor T8 is turned off. Consequently, the control terminal cs3 of data transmission transistor ST3 does not receive the signal S SN(N), so data transmission transistor ST3 is also turned off.

[0047] During the third sub-period ta3 of the display frame TA, the signal S EM(N) provided by the driving unit EM(N) changes from a high potential to a low potential (which can be regarded as the transistor of the driving unit EM(N) being turned on, so the third sub-period ta3 of the display frame TA can be an on period t14 of the transistor of the driving unit EM(N), causing the transistors T4 and T5 of the electronic unit driving circuit 20 to turn on. At the same time, the driving transistor T1 is turned on by the influence of transistors T4 and T5. At this time, the remaining transistors are in the off state, so the light-emitting stage of the display mode can be executed.

[0048] Next, the operation process of the sensing mode will be explained.

[0049] During the first sub-period tb1 of the sensing frame TB, the signal S SN_I(NX) provided by the driving unit SN_I(NX) changes from a low potential to a high potential (which can be regarded as the transistor of the driving unit SN_I(NX) being turned on, so the first sub-period tb1 of the sensing frame TB can be regarded as an on period t11 of the transistor of the driving unit SN_I(NX)). At the same time, the reset control signal Sreset changes from a high potential to a low potential, so the transistor T7 turns on. At this time, the control terminal cs2 of the reset transistor ST2 can receive the driving unit signal S SN_I(NX), so the reset transistor ST2 can turn on and receive the initial signal Vini. Therefore, the reset phase of the sensing mode can be executed. Furthermore, the sensing unit 35 can sense the signal, and the amplifying transistor ST1 can be turned on under the influence of the reset transistor ST2, thereby amplifying the signal sensed by the sensing unit 35.

[0050] During the second sub-period tb2 of the sensing frame TB, the signal S SN(N) provided by the driving unit SN(N) changes from a high potential to a low potential (which can be regarded as the transistor of the driving unit SN(N) being turned on; therefore, the second sub-period tb2 of the sensing frame TB can be regarded as an on-time t13 of the transistor of the driving unit SN(N)). At the same time, the readout control signal Sread changes from a high potential to a low potential, so the transistor T8 turns on. Consequently, the control terminal cs3 of the data transmission transistor ST3 can receive the signal S SN_I(NX) and turn on, thus transmitting the signal sensed by the sensing unit 35 to the signal readout line RL. Therefore, the data transmission phase of the sensing mode can be executed.

[0051] Furthermore, although in the example of Figure 5, transistors T7 and T8 are turned on during different sub-periods of the sensing frame TB, in another embodiment, transistors T7 and T8 can also be turned on at the same time point, for example, they can both be turned on during the first sub-period tb1 of the sensing frame TB. For example, the reset control signal Sreset and the readout control signal Sread both change from high potential to low potential during the first sub-period tb1 of the sensing frame TB.

[0052] Furthermore, although in the example of Figure 5, the sensing mode is executed later than the display mode, in another embodiment, the sensing mode and the display mode can be executed simultaneously, that is, the display frame TA and the sensing frame TB can also be synchronized. In this case, during the first display sub-period ta1, the reset control signal Sreset can change from a high potential to a low potential, at which time transistor T7 turns on, and subsequently reset transistors T3 and ST2 can turn on simultaneously. During the second display sub-period ta2, the read control signal Sread can change from a high potential to a low potential, at which time transistor T8 turns on, and subsequently data write transistor T2 can receive the data signal Data. Data transmission transistor ST3, amplification transistor ST1, switching transistor T6, and data write transistor T2 can be turned on simultaneously, and are not limited to this.

[0053] Next, the wiring layout of electronic device 1 will be described. Figure 6 is a schematic diagram of the wiring layout of electronic device 1 according to an embodiment of this application, which corresponds to the circuit structure of Figures 3 and 4. Figure 6 shows the wiring layout from a top view. It should be noted that Figure 6 uses a data transmission transistor ST3 made of polysilicon as an example, therefore, the control terminal CS3 of the data transmission transistor ST3 can be electrically connected to the drive unit SN(N).

[0054] [Reset the wiring configuration of transistor ST2 and transistor T7]

[0055] As shown in Figure 6, the electronic device 1 includes a first conductive layer 40 disposed on a substrate 10. The first conductive layer 40 may include a sub-conductive layer 41. The sub-conductive layer 41 includes a line segment 41a and a gate 41b, wherein the line segment 41a connects to the gate 41b, and the gate 41b may, for example, overlap with a region of a semiconductor layer 70. The reset transistor ST2 of the sensing unit driving circuit 30 may have a gate 41b. In one embodiment, the electronic device 1 includes a second conductive layer 50 disposed on the substrate 10, and the second conductive layer 50 is disposed on the first conductive layer 40 in the Z direction. The second conductive layer 50 may include a sub-conductive layer 51 disposed on the sub-conductive layer 41 in the Z direction. The sub-conductive layer 51 may include a gate 51b, wherein the gate 51b may, for example, overlap with a region of the semiconductor layer 70. The reset transistor ST2 has a gate 51b. The gate 41b of sub-conductive layer 41 and the gate 51b of sub-conductive layer 51 may at least partially overlap in the Z direction. In one embodiment, sub-conductive layers 41 and 51 may receive the signal S SN_I(NX) from the driving unit SN_I(NX) through a first metal layer 81. In one embodiment, the gate 41b of sub-conductive layer 41 may be, for example, a bottom gate, and the gate 51b of sub-conductive layer 51 may be, for example, a top gate, and the gates 41b and 51b may form the gate of the reset transistor ST2 (i.e., the control terminal cs2 in FIG3).

[0056] Viewed from a top-down direction (e.g., the -Z direction in Figure 6), the outline of the gate 41b of the sub-conductive layer 41 differs from the outline of the line segment 41a. In this context, "different outlines" means, for example, that they are not proportionally scaled. Conversely, if they are proportionally scaled, they are considered to have the same outline. In one embodiment, the gate 41b has a width L2-1, and the difference between the outline of the gate 41b and the outline of the line segment 41a means that the width L2-1 of the gate 41b is different from the width Lline of the line segment 41a. In one embodiment, the width L2-1 of the gate 41b may be greater than the width Lline of the line segment 41a (L2-1>Lline), thereby reducing the leakage current of the reset transistor ST2. In one embodiment, the ratio of the width Lline of line segment 41a to the width L2-1 of gate 41b can satisfy the equation: 0.3 times the width L2-1 of gate 41b < this ratio < 0.7 times the width L2-1 of gate 41b (0.3 × L2-1 < Line / L2-1 < 0.7 × L2-1), but is not limited thereto. Furthermore, in one embodiment, the profile of gate 41b is different from the profile of gate 51b; for example, gate 51b may have a width L2-2, and the width L2-1 of gate 41b is different from the width L2-2 of gate 51b. In one embodiment, the width L2-1 of gate 41b is greater than the width L2-2 of gate 51b (L2-1 > L2-2), but is not limited thereto.

[0057] In one embodiment, the electronic device 1 further includes a semiconductor layer 70 disposed on the substrate 10. The semiconductor layer 70 may be made of metal oxide (e.g., IGZO) and / or polysilicon (e.g., LTPS), but is not limited thereto. The reset transistor ST2 may include a first semiconductor 71, wherein the first semiconductor 71 may be, for example, at least a portion of the semiconductor layer 70, but is not limited thereto. One end 71a of the first semiconductor 71 may be electrically connected to the initial signal Vini through a third conductive layer 61, and the other end 71b of the first semiconductor 71 may be electrically connected to the amplifying transistor ST1 through a sixth metal layer 86.

[0058] Accordingly, the gates 41b and 51b of the sub-conductive layer 41 and 51 can serve as the control terminal cs2 of the reset transistor ST2. The first semiconductor 71 can at least partially overlap with the gates 41b and 51b to serve as the channel of the reset transistor ST2. One end 71a of the first semiconductor 71 can serve as the first end as2 of the reset transistor ST2, and the other end 71b of the first semiconductor 71 can serve as the second end bs2 of the reset transistor ST2, and the process is not limited thereto. Furthermore, since the first semiconductor 71 can overlap with the gate 41b, the channel length of the reset transistor ST2 can be considered to be equal to the width L2-1 of the gate 41b. The channel width of the reset transistor ST2 can be equal to the width W2-1 of the first semiconductor 71.

[0059] In one embodiment, sub-conductive layers 41 and 51 are electrically connected to transistor T7. In one embodiment, transistor T7 may be formed of a third metal layer 83 and a fourth metal layer 84, wherein the third metal layer 83 may, for example, contain an LTPS semiconductor, and the fourth metal layer 84 may be a conductive layer, serving as the gate (i.e., control terminal c7) of transistor T7. Thus, the signal SN_I(NX) provided by the drive unit SN_I(NX) can be controlled to enter sub-conductive layers 41 and 51 by turning transistor T7 on or off. In one embodiment, the third metal layer 83 may be electrically connected to sub-conductive layers 41 and 51 via bridging. In one embodiment, the third metal layer 83 may be electrically connected to sub-conductive layers 42 and 52 via bridging.

[0060] Therefore, the structure of the reset transistor ST2 can be understood.

[0061] [Wiring configuration of amplifying transistor ST1, data transmission transistor ST3, and transistor T8]

[0062] In one embodiment, the electronic device 1 may further include a fourth conductive layer 62, wherein the fourth conductive layer 62 may include a sub-conductive layer 621 and a sub-conductive layer 622. The fourth conductive layer 62 can be used to receive the signal S SN(N) transmitted by the driving unit SN(N). In addition, the electronic device 1 may also include a fifth conductive layer 63. The fifth conductive layer 63 may be located on a different layer from the fourth conductive layer 62 in the Z direction, but is not limited thereto. One end 63a of the fifth conductive layer 63 may be electrically connected to the signal readout line RL, and the other end 63b of the fifth conductive layer 63 may be electrically connected to a high potential Vdd. In one embodiment, the sub-conductive layer 622 of the fourth conductive layer 62 and the fifth conductive layer 63 may form a data transmission transistor ST3, wherein the sub-conductive layer 622 of the fourth conductive layer 62 may serve as the control terminal cs3 of the data transmission transistor ST3, one end 63a of the fifth conductive layer 63 may serve as the second terminal bs3 of the data transmission transistor ST3, and a portion of the fifth conductive layer 63 may serve as the first terminal ass3 of the data transmission transistor ST3. In one embodiment, a portion of the fifth conductive layer 63 can serve as a channel for the amplifying transistor ST1. In another embodiment, another portion of the fifth conductive layer 63 can serve as a channel for the data transmission transistor ST3.

[0063] In one embodiment, the sub-conductive layer 622 of the fourth conductive layer 62 can be electrically connected to the transistor T8. In one embodiment, the transistor T8 can be formed of a seventh metal layer 87 and an eighth metal layer 88, wherein the seventh metal layer 87 may, for example, contain LTPS or IGZO semiconductors, and the eighth metal layer 88 can be a conductive layer, serving as the gate (i.e., control terminal c8) of the transistor T8. Thus, the signal SN(N) provided by the driving unit SN(N) can be controlled to enter the sub-conductive layer 622 of the fourth conductive layer 62 by turning the transistor T8 on or off.

[0064] In addition, in one embodiment, the electronic device 1 may further include a sixth conductive layer 64. In the Z direction, the fifth conductive layer 63 and the sixth conductive layer 64 may be located in different layers. The fifth conductive layer 63 may be electrically connected to the reset transistor ST2 through the sixth metal layer 86. The sixth conductive layer 64 and the fifth conductive layer 63 may form an amplifying transistor ST1, wherein the sixth conductive layer 64 may serve as the control terminal cs1 of the amplifying transistor ST1, a portion of the fifth conductive layer 63 may serve as the second terminal bs1 of the amplifying transistor ST1, and the other terminal 63b of the fifth conductive layer 63 may serve as the first terminal as1 of the amplifying transistor ST1.

[0065] Thus, the structure of the amplifying transistor ST1 and the data transmission transistor ST3 can be understood.

[0066] [Reset the wiring configuration of transistor T3]

[0067] In one embodiment, the first conductive layer 40 may further include a sub-conductive layer 42. The sub-conductive layer 42 may include a line segment 42a and a gate 42b, with the line segment 42a connected to the gate 42b. The reset transistor T3 of the electronic unit driving circuit 20 has a gate 42b. The second conductive layer 50 may further include a sub-conductive layer 52, which is disposed on the sub-conductive layer 42 in the Z direction. The sub-conductive layer 52 may include a gate 52b. The reset transistor T3 has a gate 52b, and the gate 52b is electrically connected to the electronic unit 25. Furthermore, in the Z direction, the gate 42b of the sub-conductive layer 42 and the gate 52b of the sub-conductive layer 52 may at least partially overlap. In one embodiment, the sub-conductive layers 42 and 52 may receive the signal SN_I(NX) from the driving unit SN_I(NX) through a first metal layer 81. Sub-conductive layers 42 and 52 can be electrically connected to sub-conductive layers 41 and 51 through transistor T7. In one embodiment, gate 42b can be, for example, a bottom gate, and gate 52b can be, for example, a top gate, and gates 42b and 52b can form the gate (i.e., control terminal c3) of reset transistor T3. In addition, in one embodiment, line segment 41a can also be connected to gate 42b, but is not limited thereto. In another embodiment, electronic device 1 may also include another conductive layer (not shown) disposed on substrate 10, which may have a connection portion (not shown), and gates 41b and 52b can be electrically connected through the connection portion, but is not limited thereto; furthermore, in the Z direction, the other conductive layer may be located below gate 41b and line segment 41a, but may also be located between gate 41b (or line segment 41a) and gate 52b.

[0068] Segment 41a and segment 42a may have the same length. Viewed from a top-down direction (e.g., the -Z direction in Figure 6), the outline of gate 42b differs from that of segment 42a (or segment 41a). For example, gate 42b may have a width L1-1, segment 42a (or segment 41a) may have a width Lline, and the width L2-2 of gate 42b may differ from the width Line of segment 42a (or segment 41a). In one embodiment, the width L1-1 of gate 42b may be greater than the width Lline of segment 42a (L1-1>Lline), thereby reducing the leakage current of the reset transistor T3. In one embodiment, the ratio of the width Lline of line segment 42a to the width L1-1 of gate 42b can satisfy the equation: 0.3 times the width L1-1 of gate 42b < this ratio < 0.7 times the width L1-1 of gate 42b (0.3 × L2-1 < Line / L1-1 < 0.7 × L2-1), but is not limited thereto. Furthermore, in one embodiment, line segment 42a may have the same width Lline as line segment 41a, therefore the width L1-1 of gate 42b may also be greater than the width Lline of both line segments 41a and 41b. Additionally, in one embodiment, viewed from a top-down direction (e.g., the -Z direction in FIG6), the profile of gate 42b may also differ from the profile of gate 52b; for example, gate 52b may have a width L1-2, and the width L1-1 of gate 42b is different from the width L1-2 of gate 52b. In one embodiment, the width L1-1 of gate 42b may be greater than the width L1-2 of gate 52b (L1-1>L1-2). Furthermore, viewed from a top-down direction (e.g., the -Z direction in FIG6), the profile of gate 52b may also differ from line segments 41a, 42a, or 52a. In one embodiment, the width L1-1 of gate 52b may be less than or equal to the width Lline of line segments 41a, 42a, or 52a (L1-1≦Lline), but is not limited thereto.

[0069] Furthermore, in one embodiment, the reset transistor T3 may include a second semiconductor 72, wherein the second semiconductor 72 may be, for example, at least a portion of the semiconductor layer 70, but is not limited thereto. One end 72a of the second semiconductor 72 may be electrically connected to the initial signal Vini through the third conductive layer 61, and an extension 72c of the second semiconductor 72 may be electrically connected to the driving transistor T1 through a fifth metal layer 85.

[0070] Accordingly, the gates 42b and 52b of the sub-conductive layer 42 and 52b of the sub-conductive layer 52 can serve as the control terminal c3 of the reset transistor T3. The second semiconductor 72 can at least partially overlap with the gates 42b and 52b to serve as the channel of the reset transistor T3. One end 72a of the second semiconductor 72 can serve as the second end b3 of the reset transistor T3, and the extended portion 72c of the second semiconductor 72 can serve as the first end a3 of the reset transistor T3, and is not limited thereto. Furthermore, since the second semiconductor 72 can overlap with the gate 42b, the channel length of the reset transistor T3 can be considered to be equal to the width L1-1 of the gate 42b. The channel width of the reset transistor T3 can be equal to the width W1-1 of the second semiconductor 72.

[0071] Therefore, the structure of the reset transistor T3 can be understood.

[0072] [Wiring configuration for switching transistor T6]

[0073] In one embodiment, the first conductive layer 40 may further include a sub-conductive layer 43. Sub-conductive layers 41, 42, and 43 may be separated from each other, but are not limited thereto. Sub-conductive layer 43 may include a line segment 43a and a gate 43b, with line segment 43a connected to gate 43b. The switching transistor T6 of the electronic unit driving circuit 20 has gate 43b. The second conductive layer 50 may further include a sub-conductive layer 53, which is disposed on sub-conductive layer 43 in the Z direction. Sub-conductive layer 53 may include a gate 53b. The switching transistor T6 has gate 53b. Furthermore, in the Z direction, the gate 43b of sub-conductive layer 43 and the gate 53b of sub-conductive layer 53 may at least partially overlap. In one embodiment, sub-conductive layers 43 and 53 may receive the signal SN_I(N) from the driving unit SN_I(N) through a second metal layer 82. In one embodiment, gate 43b may be, for example, a bottom gate, and gate 53b may be, for example, a top gate, and gates 43b and 53b may form the gate of the switching transistor T6 (i.e., the control terminal c6 of FIG3).

[0074] In one embodiment, the relationship between the outline of the gate 43b of the sub-conductive layer 43 and the outline of the line segment 43a, viewed from a top view (e.g., the -Z direction in FIG6), is analogous to the description of the relationship between the outline of the gate 41b of the sub-conductive layer 41 and the outline of the line segment 41a, and therefore will not be described in detail. Line segment 43a and line segment 41a may have the same width Lline. Furthermore, viewed from a top view (e.g., the -Z direction in FIG6), the outline of the gate 43b may be different from the outline of the gate 53b.

[0075] In one embodiment, the extension 72c of the second semiconductor 72 can serve as the first terminal a6 of the switching transistor T6, and the other end 72b of the second semiconductor 72 relative to terminal 72a can serve as the second terminal b6 of the switching transistor T6. The other end 72b of the second semiconductor 72 can be electrically connected to transistor T5 (not shown in the figure). The gate 43b of the sub-conductive layer 43 and the gate 53b of the sub-conductive layer 53 can serve as the control terminal c6 of the switching transistor T6, but are not limited thereto. Thus, the structure of the switching transistor T6 can be understood.

[0076] [Wiring configuration of other transistors (T1, T2, T4, and T5) in the electronic unit drive circuit 20]

[0077] In one embodiment, the electronic device 1 may further include a seventh conductive layer 65, an eighth conductive layer 66, and a ninth conductive layer 67. The seventh conductive layer 65 can be used to receive the signal S EM(N) transmitted by the driving unit EM(N). In the Z direction, the eighth conductive layer 66 and the ninth conductive layer 67 may be disposed on different layers. The ninth conductive layer 67 may have a first end 67a, a second end 67b, and a third end 67c, wherein the first end 67a may be electrically connected to the electronic unit 25, the second end 67b may be electrically connected to a high potential 67b, and the third end 67c may be electrically connected to a data line DL. The ninth conductive layer 67 may also have an intermediate portion 67d, which may at least partially overlap with the eighth conductive layer 66.

[0078] In one embodiment, a portion of the ninth conductive layer 67 and the eighth conductive layer 66 can be used to form a driving transistor T1. In one embodiment, the ninth conductive layer 67 and the seventh conductive layer 61 can be used to form transistors T4 and T5, wherein the second end 67b of the ninth conductive layer 67 can serve as the first end a4 of transistor T4, and the first end 67a of the ninth conductive layer 67 can serve as the second end b5 of transistor T5. In one embodiment, the sub-conductive layer 621 of the fourth conductive layer 62 and the ninth conductive layer 67 can be used to form a data writing transistor T2, wherein the third end 67c of the ninth conductive layer 67 can serve as the first end a2 of the data writing transistor T2.

[0079] In one embodiment, a portion of the ninth conductive layer 67 can serve as a channel for driving transistor T1. In another embodiment, another portion of the ninth conductive layer 67 can serve as a channel for transistor T4, and yet another portion of the ninth conductive layer 67 can serve as a channel for transistor T5.

[0080] Thus, the structure of the driving transistors T1, T2, T4 and T5 can be understood.

[0081] Next, the size relationship between the transistors will be described.

[0082] In one embodiment, the materials of the amplifying transistor ST1 and the data transmission transistor ST3 may include LTPS, the material of the reset transistor ST2 may include IGZO, and the driving transistor T1 may have a channel length LT1, and the amplifying transistor ST1 may have a channel length LST1. In one embodiment, the driving transistor T1 and the amplifying transistor ST1 may be electrically connected to different high potentials Vdd. In one embodiment, when the driving transistor T1 and the amplifying transistor ST1 are electrically connected to the same high potential Vdd, the channel length LT1 of the driving transistor T1 may be equal to the channel length LST1 of the amplifying transistor ST1 (LT1 = LST1). In one embodiment, when the driving transistor T1 and the amplifying transistor ST1 are electrically connected to different high potentials Vdd, the channel length LT1 of the driving transistor T1 may be greater than the channel length LST1 of the amplifying transistor ST1 (LT1 > LST1), thereby reducing the leakage current of the sensing unit driving circuit 30. In addition, in one embodiment, the channel length LST1 of the amplifying transistor ST1 may be greater than the channel length L2-1 of the reset transistor ST2 (LST1 > L2-1), thereby reducing the leakage current of the sensing unit driving circuit 30.

[0083] In one embodiment, the materials of the amplifying transistor ST1 and the data transmission transistor ST3 may include LTPS, the material of the reset transistor ST2 may include IGZO, and the data transmission transistor ST3 may have a channel length LST3 and a channel width WST3. In one embodiment, the channel length LST3 of the data transmission transistor ST3 may be greater than the channel length L2-1 of the reset transistor ST2 (LST3 > L2-1). In one embodiment, the channel width WST3 of the data transmission transistor ST3 may be smaller than the channel width W2-1 of the reset transistor ST2 (WST3 < W2-1). Thereby, the leakage current of the sensing unit driving circuit 30 can be reduced.

[0084] In one embodiment, the material of the amplifying transistor ST1 may include LTPS, the materials of the reset transistor ST2 and the data transmission transistor ST3 may include IGZO, and the data transmission transistor ST3 may have a channel length L ST3 and a channel width W ST3. In one embodiment, the channel length L ST3 of the data transmission transistor ST3 may be greater than the channel length L2-1 of the reset transistor ST2 (L ST3 > L2-1). In one embodiment, the channel width W ST3 of the data transmission transistor ST3 may be less than the channel width W2-1 of the reset transistor ST2 (W ST3 < W2-1). Thereby, the leakage current of the sensing unit driving circuit 30 can be reduced.

[0085] Thereby, the wiring configuration of the electronic device 1 can be understood.

[0086] In this application, when the materials of the amplifying transistor ST1, the reset transistor ST2, and / or the data transmission transistor ST3 of the sensing unit driving circuit 30 change, the circuit structure between the sensing unit driving circuit 30 and the driving unit will also change. Next, different circuit structures will be described.

[0087] FIG. 7 is a schematic diagram of the detailed circuit structure of the electronic device 1 according to another embodiment of this application. Please also refer to FIGS. 1 to 6. Since the features of the example in FIG. 7 can generally apply to the description of the example in FIG. 4, the following mainly focuses on the differences for description. [[ID=​​​​​The difference between the example in Figure 7 and the example in Figure 4 is that the electronic device 1 further includes a driving unit SN(N+Y) disposed in the peripheral area B, where Y can be, for example, 1. The driving unit SN(N+Y) is electrically connected to the first terminal a8 of the transistor T8, and the second terminal b8 of the transistor T8 is electrically connected to the data transmission transistor ST3. Therefore, the transistor T8 is driven by the driving unit SN(N+Y). For example, the driving unit SN(N+Y) can provide a signal S SN(N+Y). When the transistor T8 is turned on, the signal S SN(N+Y) can enter the control terminal cs3 of the data transmission transistor ST3, thereby turning on the data transmission transistor ST3. In one embodiment, the driving unit SN(N+Y) may include a transistor, or it may be a transistor itself. In other words, the driving unit SN(N+Y) can control the transmission of the signal S SN(N+Y) to the data transmission transistor ST3, where the signal S SN(N+Y) can be regarded as a readout signal.

[0090] Figure 8 is a signal timing diagram corresponding to the circuit structure in Figure 7. In the example in Figure 8, the operation process of the display mode is the same as that in the example in Figure 5, so the following mainly focuses on the sensing mode.

[0091] As shown in Figure 8, during the first sub-period tb1 of the sensing frame TB, the signal S SN_I(NX) provided by the driving unit SN_I(NX) changes from a low potential to a high potential, and simultaneously the reset control signal Sreset changes from a high potential to a low potential. Therefore, transistor T7 turns on, and the control terminal cs2 of the reset transistor ST2 can receive the driving unit signal S SN_I(NX) and turn on, thus enabling the reset phase to be executed. Furthermore, the amplifying transistor ST1 can be turned on under the influence of the reset transistor ST2, thereby amplifying the signal sensed by the sensing unit 35. At this time, the readout control signal Sread remains at a high potential, therefore transistor T8 is turned off.

[0092] During the second sub-period tb2 of the sensing frame TB, the signal S SN_I(NX) provided by the driving unit SN_I(NX) changes from a high potential to a low potential, causing the reset transistor ST2 to turn off. At this time, the signal S SN(N+Y) provided by the driving unit SN(N+Y) remains at a low potential, and the readout control signal Sread remains at a high potential, so the transistor T8 remains off. During the third sub-period tb3 of the sensing frame TB, the signal S SN(N+Y) provided by the driving unit SN(N+Y) changes from a low potential to a high potential (which can be regarded as the transistor of the driving unit SN(N+Y) being turned on, so the third sub-period tb3 of the sensing frame TB can be considered as an on period t15 of the transistor of the driving unit SN(N+Y), and at the same time, the readout control signal Sread changes from a high potential to a low potential, so the transistor T8 turns on, and thus the control terminal cs3 of the data transmission transistor ST3 can receive the signal S SN(N+Y) and turn on, so the data transmission phase of the sensing mode can be executed. It should be noted that at least one turn-on period t15 of the transistor of the driving unit SN(N+Y) and at least one turn-on period t14 of the transistor of the driving unit EM(N) may not overlap, but are not limited thereto.

[0093] In one embodiment, the duration of a sensing frame TB may be greater than that of a display frame TA (TB>TA), but is not limited thereto. In one embodiment, when the duration of a sensing frame TB is greater than that of a display frame TA (TB>TA), the sensing frame TB may at least partially overlap with the next sensing frame TB, but is not limited thereto.

[0094] In another embodiment, the duration of a display frame TA may also be greater than the duration of a sensing frame TB (TA>TB), and one of the display frames TA may at least partially overlap with multiple sensing frames TB.

[0095] In another embodiment, the time length of a sensing frame TB may also be greater than the time length of a sensing frame TA (TB>TA), and one of the sensing frames TB may at least partially overlap with multiple display frames TA.

[0096] Therefore, the examples in Figures 7 and 8 can be understood.

[0097] Besides the example in Figure 7, the circuit structure of the electronic device 1 of this application may also have different embodiments, which will be illustrated in the following text (please refer to the examples in Figure 4 or Figure 7).

[0098] In one embodiment, the amplifying transistor ST1 of the sensing unit driving circuit 30 may be made of LTPS, and the reset transistor ST2 and data transmission transistor ST3 may be made of IGZO. In this case, the driving unit SN_I (NX) can be electrically connected to the control terminal cs2 of the reset transistor ST2 via transistor T7, and the driving unit SN_I (N) can be electrically connected to the control terminal cs3 of the data transmission transistor ST3 via transistor T8. Therefore, the reset transistor ST2 can be driven by the driving unit SN_I (NX), and the data transmission transistor ST3 can be driven by the driving unit SN_I (N).

[0099] In one embodiment, the amplifying transistor ST1 of the sensing unit driving circuit 30 may be made of LTPS, and the reset transistor ST2 and data transmission transistor ST3 may be made of IGZO. The electronic device 1 also includes a driving unit SN_I(N+Y). In this case, the driving unit SN_I(NX) can be electrically connected to the control terminal cs2 of the reset transistor ST2 through transistor T7, and the driving unit SN_I(N+Y) can be electrically connected to the control terminal cs3 of the data transmission transistor ST3 through transistor T8. Therefore, the reset transistor ST2 can be driven by the driving unit SN_I(NX), and the data transmission transistor ST3 can be driven by the driving unit SN_I(N+Y).

[0100] In one embodiment, the amplifying transistor ST1, the reset transistor ST2, and the data transmission transistor ST3 of the sensing unit driving circuit 30 are all made of LTPS. Therefore, in this embodiment, the material of the reset transistor ST2 can be different from that of the reset transistor ST3. In this case, the driving unit SN (NX) can be electrically connected to the control terminal cs2 of the reset transistor ST2 through transistor T7, and the driving unit SN (N) can be electrically connected to the control terminal cs3 of the data transmission transistor ST3 through transistor T8. Therefore, the reset transistor ST2 can be driven by the driving unit SN (N), and the data transmission transistor ST3 can be driven by the driving unit SN_I (N).

[0101] In one embodiment, the amplifying transistor ST1 and the data transmission transistor ST3 of the sensing unit driving circuit 30 are made of LTPS, the reset transistor ST2 is made of IGZO, and the electronic device 1 may not include transistors T7 and T8. In this case, the electronic device 1 may include at least two driving units SN_I (NX), one for driving the reset transistor T3 in the electronic unit driving circuit 20, and the other for driving the reset transistor ST2 in the sensing unit driving circuit 30. Furthermore, the electronic device 1 may also include at least two driving units SN (N), one for driving the data writing transistor T2 in the electronic unit driving circuit 20, and the other for driving the data transmission transistor ST3 in the sensing unit driving circuit 30.

[0102] In one embodiment, the amplifying transistor ST1, the reset transistor ST2, and the data transmission transistor ST3 of the sensing unit driving circuit 30 are all made of LTPS, and the electronic device 1 may not include transistors T7 and T8. In this case, the electronic device 1 may include a driving unit SN(NX) (not shown) for driving the reset transistor ST2 in the sensing unit driving circuit 30. In addition, the electronic device 1 may also include at least two driving units SN(N), one for driving the data writing transistor T2 in the electronic unit driving circuit 20, and the other for driving the data transmission transistor ST3 in the sensing unit driving circuit 30.

[0103] Thus, various embodiments of the circuit structure of electronic device 1 can be understood. It should be noted that the circuit structure of this application is not limited thereto.

[0104] The wiring configuration of the reset transistors T2 and ST2 in the electronic device 1 of this application may have other variations besides the embodiment shown in FIG6, which will be described next.

[0105] Figure 9 is a schematic diagram of the wiring configuration of reset transistors T3 and ST2 in an electronic device 1 according to an embodiment of this application. Please also refer to Figures 1 to 8. For clarity, Figure 9 only shows the wiring configuration of reset transistors T3 and ST2. The wiring configuration of other transistors can be found in the example in Figure 6.

[0106] As shown in Figure 9, in one embodiment, the channel width W1-1 of the reset transistor T3 is different from the channel width W2-1 of the reset transistor ST2. In one embodiment, the channel width W1-1 of the reset transistor T3 may be greater than the channel width W2-1 of the reset transistor ST2 (W1-1>W2-1), and is not limited thereto. In one embodiment, the channel length L1-1 of the reset transistor T3 is different from the channel length L2-1 of the reset transistor ST2. In one embodiment, the channel width L2-1 of the reset transistor ST2 may be greater than the channel length L1-1 of the reset transistor T3 (L2-1>L1-1), and is not limited thereto. With the above configuration, the sensing unit driving circuit 30 of this application can have a lower leakage current or can improve the sensing accuracy.

[0107] Figure 10 is a schematic diagram of the wiring configuration of reset transistors T3 and ST2 in electronic device 1 according to another embodiment of this application. Please also refer to Figures 1 to 9. For clarity, Figure 10 only shows the wiring configuration of reset transistors T3 and ST2. The wiring configuration of other transistors can be referred to the example in Figure 6.

[0108] As shown in Figure 10, the reset transistor ST2 may include a plurality of sub-transistors, such as sub-transistors ST21 and ST22, wherein sub-transistors ST21 and ST22 may be electrically connected, for example, connected in series. In one embodiment, the sub-conductive layer 41 may further include a gate 41c, wherein sub-transistor ST21 may include gates 41b and 51, and ST22 may include gates 41c and 51. Furthermore, a portion of the first semiconductor 71 may serve as a channel for sub-transistor ST21, and another portion of the first semiconductor 71 may serve as a channel for sub-transistor ST22.

[0109] In one embodiment, the sub-transistor ST21 may have a channel length L2-1 and a channel width W2-1, and the sub-transistor ST22 may have a channel length L3-1 and a channel width W3-1. In one embodiment, at least one of the channel length L2-1 of the sub-transistor ST21 and the channel length L3-1 of the sub-transistor ST22 may be greater than the channel length L1-1 of the reset transistor T3 (L2-1>L1-1, or L3-1>L1-1, or L2-1>L1-1 and L3-1>L1-1). In one embodiment, at least one of the channel width W2-1 of the sub-transistor ST21 and the channel width W3-1 of the sub-transistor ST22 may be less than the channel width W1-1 of the reset transistor T3 (W2-1<W1-1, or W3-1<W1-1, or W2-1<W1-1 and W3-1<W1-1). With the above configuration, the sensing unit driving circuit 30 of the present application may have a lower leakage current.

[0110] FIG. 11 is a schematic diagram of the wiring configuration of the reset transistor T3 and ST2 of the electronic device 1 according to another embodiment of the present application. Please also refer to FIGS. 1 to 10. For clarity of features, FIG. 11 only shows the wiring configuration of the reset transistor T3 and ST2, and the wiring configuration of the remaining transistors can be referred to the content of the example in FIG. 6.

[0111] As shown in FIG. 11, the semiconductor layer 70 may include a patterned portion 70p. The first semiconductor 71 of the reset transistor ST2 and the second semiconductor 72 of the reset transistor T3 may share the patterned portion 70p. For example, when the materials of the first semiconductor 71 and the second semiconductor 72 are the same, such as both being IGZO, the first semiconductor 71 and the second semiconductor may be connected together. In one embodiment, the reset transistor ST2 and the reset transistor T3 may share the same end, for example, may share the source electrode, and the other ends (such as the drain) of the reset transistor ST2 and the reset transistor T3 are respectively disposed in the sensing unit driving circuit 30 and the electronic unit driving circuit 20. In addition, the patterned portion 70p may extend to the sensing unit driving circuit 30 and be connected to the first semiconductor 71, and the patterned portion 70p may extend to the electronic unit driving circuit 20 and be connected to the second semiconductor 72.

[0112] FIG. 12 is a schematic diagram of the wiring configuration of the reset transistor T3 and ST2 of the electronic device 1 according to another embodiment of the present application. Please also refer to FIGS. 1 to 11. For clarity of features, FIG. 12 only shows the wiring configuration of the reset transistor T3 and ST2, and the wiring configuration of the remaining transistors can be referred to the content of the example in FIG. 6. <000​As shown in Figure 11, the semiconductor layer 70 may include a patterned portion 70p, and the first semiconductor 71 of the reset transistor ST2 and the second semiconductor 72 of the reset transistor T3 may share the patterned portion 70p. In one embodiment, the reset transistor ST2 and the reset transistor T3 may share the same end, for example, they may share the same source, while the other ends (e.g., drains) of the reset transistor ST2 and the reset transistor T3 are respectively disposed in the sensing unit driving circuit 30 and the electronic unit driving circuit 20. Furthermore, a portion of the patterned portion 70p may extend into the sensing unit driving circuit 30 to form the first semiconductor 71, and a portion of the patterned portion 70p may extend into the electronic unit driving circuit 20 to form the second semiconductor 72, thereby allowing the reset transistor ST2 and the reset transistor T3 to share the same channel.

[0114] Therefore, it is understood that various wiring configurations for resetting transistors T3 and ST2 can be understood, and this application is not limited thereto.

[0115] Next, the structures of reset transistors T3 and ST2 will be explained.

[0116] Figure 13 is a cross-sectional view of reset transistors T3 and ST2 according to an embodiment of this application, wherein the left half is used to show at least a portion of the cross-sectional structure of reset transistor T3, and the right half is used to show at least a portion of the cross-sectional structure of reset transistor ST2.

[0117] As shown in Figure 13, the electronic device 1 may include a plurality of insulating layers, such as insulating layers 91-99. The electronic device 1 may also include a drain electrode 101 and a source electrode 102. The positions of the drain electrode 101 and the source electrode 102 in Figure 13 are merely examples; in practice, their positions can be interchanged. Furthermore, the electronic device 1 may also include a drain electrode 111 and a source electrode 112. The positions of the drain electrode 111 and the source electrode 112 in Figure 13 are merely examples; in practice, their positions can be interchanged. Additionally, the first semiconductor 71 may include a first sublayer 711 and a second sublayer 712.

[0118] Regarding the reset transistor T3. In one embodiment, in the Z direction, insulating layer 92 may be disposed on insulating layer 91, insulating layer 93 may be disposed on insulating layer 92, insulating layer 94 may be disposed on insulating layer 93, gate 42b and insulating layer 95 may be disposed on insulating layer 94, second semiconductor 72 and insulating layer 96 may be disposed on gate 42b and insulating layer 95, gate 52b and insulating layer 97 may be disposed on second semiconductor 72 and insulating layer 96, drain electrode 101, source electrode 102 and insulating layer 98 may be disposed on gate 52b and insulating layer 97, and insulating layer 99 may be disposed on drain electrode 101, source electrode 102 and insulating layer 98. Furthermore, drain electrode 101 may be electrically connected to second semiconductor 72 through conductive material 103, and source electrode 102 may be electrically connected to second semiconductor 72 through conductive material 104.

[0119] Regarding the reset transistor ST2. In one embodiment, in the Z direction, the gate 41b and the insulating layer 95 may be disposed on the insulating layer 94. The first sub-layer 711, the second sub-layer 712, and the insulating layer 96 of the first semiconductor 71 may be disposed on the gate 41b and the insulating layer 95, wherein the second sub-layer 712 may be disposed on the first sub-layer 711. The gate 51b and the insulating layer 97 may be disposed on the first sub-layer 711, the second sub-layer 712, and the insulating layer 96. The drain electrode 111, the source electrode 112, and the insulating layer 98 may be disposed on the gate 51b and the insulating layer 97. The insulating layer 99 may be disposed on the drain electrode 111, the source electrode 112, and the insulating layer 98. Furthermore, the drain electrode 111 may be electrically connected to the second sub-layer 712 through a conductive material 113, and the source electrode 112 may be electrically connected to the second sub-layer 712 through a conductive material 114.

[0120] In one embodiment, the materials of the first semiconductor 71 and the second semiconductor 72 may include IGZO, wherein the electron mobility of the first sublayer 711 of the first semiconductor 71 is higher than that of the second sublayer 712, but this is not limited to this embodiment. In one embodiment, the electron mobility of the first sublayer 711 of the first semiconductor 71 is higher than that of the second semiconductor 72, but this is not limited to this embodiment.

[0121] Furthermore, in one embodiment, compared to the example in FIG13, the first semiconductor 71 may also be adjusted to include another second sublayer 712 (not shown), wherein in the Z direction, the first sublayer 711 may be disposed between the two second sublayers 712. The electron mobility of the first sublayer 711 may be higher than that of the two second sublayers 712.

[0122] In addition, in one embodiment, compared with the example of FIG. 13, the first semiconductor 71 can also be adjusted such that in the Z direction, the first sub-layer 711 with higher electron mobility is disposed above the second sub-layer 712 with lower electron mobility.

[0123] Furthermore, in one embodiment, according to requirements, the second semiconductor 72 can also have multiple sub-layers similar to the aforementioned first semiconductor 71, and the electron mobilities between the multiple sub-layers can be different. Alternatively, it can also be designed such that the second semiconductor 72 has multiple sub-layers while the first semiconductor 71 has a single layer.

[0124] FIG. 14 is a cross-sectional view of the reset transistors T3 and ST2 according to another embodiment of the present application. Some features of FIG. 14 can be applied to the description of FIG. 13, so the following mainly focuses on the differences for description.

[0125] As shown in FIG. 14, the reset transistor ST2 can further include an oxide-assisted semiconductor layer 713. In one embodiment, in the Z direction, the gate 41b, the oxide-assisted semiconductor layer 713, and the insulating layer 95 can be disposed above the insulating layer 94, where the oxide-assisted semiconductor layer 713 can be disposed above the insulating layer 95, and the first semiconductor 71 and the insulating layer 96 can be disposed above the gate 41b, the oxide-assisted semiconductor layer 713, and the insulating layer 95.

[0126] In one embodiment, in the Z direction, the oxide-assisted semiconductor layer 713 has a thickness d1, and the first semiconductor 71 has a thickness d2, where the thickness d1 of the oxide-assisted semiconductor layer 713 can be less than the thickness d2 of the first semiconductor 71 (d1 < d2), and it is not limited thereto. In one embodiment, the oxide component (such as concentration) of the oxide-assisted semiconductor layer 713 can be less than that of the first semiconductor 71, but it is not limited thereto. The oxide-assisted semiconductor layer 713 can supplement oxygen vacancies to the first semiconductor 71, so that the threshold voltage of the reset transistor ST2 can be more accurate, and thus leakage current can be reduced.

[0127] In one embodiment, compared with the example of FIG. 14, the oxide-assisted semiconductor layer 713 can also be adjusted to be disposed at the gate 51b, for example, it can be disposed below the gate 51b in the Z direction, but it is not limited thereto.

[0128] In one embodiment, according to requirements, it can also be designed such that the second semiconductor 72 has an oxide-assisted semiconductor layer while the first semiconductor 71 does not have an oxide-assisted semiconductor layer.

[0129] Figure 15 is a cross-sectional view of reset transistors T3 and ST2 according to another embodiment of this application. Some features of Figure 15 are applicable to the description of Figure 14, so the following description mainly focuses on the differences.

[0130] As shown in Figure 15, the electronic device 1 may also include another oxide-assisted semiconductor layer 714. In the Z direction, the oxide-assisted semiconductor layer 713 may be disposed above the gate 41b, facing upward toward the first semiconductor 71, while the oxide-assisted semiconductor layer 714 may be disposed below the gate 51, facing downward toward the first semiconductor 71. This allows for more precise control of the threshold voltage of the reset transistor ST2.

[0131] In one embodiment, depending on the requirements, the second semiconductor 72 may be designed to have an oxide-assisted semiconductor layer while the first semiconductor 71 does not have an oxide-assisted semiconductor layer.

[0132] Therefore, the structure of the reset transistors T3 and ST2 can be understood. This application is not limited to the above embodiments.

[0133] The electronic device 1 of this application may also have different circuit structures. For example, the data line DL and the data readout line RL may be integrated together, and the same signal line may be used to transmit data signals or sensing signals.

[0134] Figure 16 is a schematic diagram of the circuit structure of electronic device 1 according to another embodiment of this application, and please also refer to Figures 1 to 15.

[0135] As shown in Figure 16, the electronic device 1 may include a plurality of array units p, each array unit p may be, for example, an electronic unit driving circuit 20 or a sensing unit driving circuit 30.

[0136] The electronic device 1 may also include a plurality of gate lines SL, each gate line SL being used to transmit a drive signal. A portion of the drive signal can be used to drive the IGZO transistors in the electronic unit drive circuit 20 or the sensing unit drive circuit 30, such as drive signals S SN_I(N-1), S SN_I(N), S SN_I(N+1), S SN_I(N+2), etc., and is not limited thereto. Another portion of the drive signal can be used to drive the LTPS transistors in the electronic unit drive circuit 20 or the sensing unit drive circuit 30, such as drive signals S SN(N-1), S SN(N), S SN(N+1), S SN(N+2), etc., and is not limited thereto. In one embodiment, each scan line SL can be electrically connected to one of the driving electronic unit driving circuits 20 and one of the sensing unit driving circuits 30 through one end of a transistor SW. For example, the scan line SL can be electrically connected to a first end of the transistor SW, and the first end of the transistor SW can be further electrically connected to one of the driving electronic unit driving circuit 20 and the sensing unit driving circuit 30, while the second end of the transistor SW can be electrically connected to the other of the driving electronic unit driving circuit 20 and the sensing unit driving circuit 30. In this way, by turning the transistor SW on or off, the driving signal to be transmitted to the driving electronic unit driving circuit 20 or the sensing unit driving circuit 30 can be controlled, and it is not limited to this.

[0137] The electronic device 1 may further include a plurality of integrated signal lines DR, each integrated signal line DR being used to transmit data signals to the electronic unit driving circuit 20 and to transmit sensing signals from the sensing unit driving circuit 30. Therefore, each integrated signal line DR may be electrically connected to a plurality of electronic unit driving circuits 20 and sensing unit driving circuits 30. In one embodiment, each integrated signal line DR may be electrically connected to a first end (e.g., drain / source) of a transistor CKDR, and the other end (e.g., source / drain) of the transistor CKDR may be electrically connected to an integrated control terminal DRM, thereby, when the transistor CKDR is turned on, the data signal Data provided by the integrated control terminal DRM may be transmitted to the electronic unit driving circuit 20 via the transistor CKDR and the integrated signal line DR, or the sensing signal transmitted by the sensing unit driving circuit 30 may be transmitted to the integrated control terminal DRM via the integrated signal line DR and the transistor CKDR, and is not limited thereto.

[0138] Furthermore, in one embodiment, the electronic unit driving circuit 20 may include a transistor MD, and the sensing unit driving circuit 30 may include a transistor MR, wherein one end (e.g., drain or source) of the transistor MD and one end (e.g., drain or source) of the MR may be electrically connected to the integrated signal line DR, respectively. Therefore, in display mode, the transistor MD can be turned on, allowing the electronic unit driving circuit 20 to receive data signals (Data) from the integrated signal line DR, while the transistor MR can be turned off, preventing the sensing unit driving circuit 30 from receiving data signals (Data). In sensing mode, the transistor MR can be turned on, allowing the sensing unit driving circuit 30 to transmit sensing signals through the integrated signal line DR, while the transistor MD can be turned off, preventing the electronic unit driving circuit 20 from receiving sensing signals. This allows for the integration of the data line DL and the data readout line RL. In one embodiment, the material of the transistor MD or MR may include LTPS, IGZO, or holmium manganese oxide (HoMnO3, HMO), and is not limited to these.

[0139] Furthermore, in one embodiment, multiple integrated signal lines (DRs) can share a single integrated control unit (DRM). For example, the integrated control unit (DRM) may include a multiplexer (not shown), thereby enabling simultaneous electrical connection to multiple integrated signal lines (DRs). In one embodiment, three integrated signal lines (DRs) can share a single integrated control unit (DRM), but this is not a limitation. In one embodiment, the operating timing of each integrated control unit (DRM) can be staggered through timing control, but this is not a limitation. In one embodiment, each integrated control unit (DRM) may include at least one transistor (not shown), and the material of the at least one transistor may include LTPS or HMO, but is not limited to these.

[0140] Figure 17 is a schematic diagram of the circuit structure of electronic device 1 according to another embodiment of this application. Some features of the example in Figure 17 can be described using the example in Figure 16, so the following description mainly focuses on the differences.

[0141] As shown in Figure 17, each gate line SL of the electronic device 1 can be electrically connected to multiple electronic unit driving circuits 20 and sensing unit driving circuits 30 through multiplexing. For example, the gate line SL1 of the IGZO transistor can be electrically connected to multiple electronic unit driving circuits 20 through a multiplexer MI1, and can be electrically connected to multiple sensing unit driving circuits 30 through a multiplexer MI2. The gate line SL1 of the LTPS transistor can be electrically connected to multiple electronic unit driving circuits 20 through a multiplexer ML1, and can be electrically connected to multiple sensing unit driving circuits 30 through a multiplexer ML2.

[0142] In one embodiment, each gate line SL_I corresponding to an IGZO transistor can be electrically connected to a first terminal (e.g., drain or source) of a transistor SW1 and a multiplexer MI1, while the second terminal of transistor SW1 can be electrically connected to multiplexer MI2. Therefore, by controlling the opening or closing of transistor SW1, the drive signal transmitted by the gate line SL_I can be determined to enter multiplexer MI1 or multiplexer MI2, thereby driving the electronic unit drive circuit 20 or the sensing unit drive circuit 30, and so on. In one embodiment, multiplexer MI1 may include multiple transistors (e.g., CKI1, CKI2, CKI3, but not limited thereto), each electrically connected to a different electronic unit drive circuit 20. In one embodiment, multiplexer MI2 may include multiple transistors (e.g., CKIS1, CKIS2, CKIS3, but not limited thereto), each electrically connected to a different sensing unit drive circuit 30.

[0143] In one embodiment, the gate line SLL of each corresponding LTPS transistor can be electrically connected to a first terminal (e.g., drain or source) of a transistor SW2 and a multiplexer ML1, while the second terminal (e.g., source or drain) of transistor SW2 can be electrically connected to multiplexer ML2. Therefore, by controlling the opening or closing of transistor SW2, the drive signal transmitted by the gate line SLL can be determined to enter multiplexer ML1 or multiplexer ML2, thereby driving the electronic unit drive circuit 20 or the sensing unit drive circuit 30, and is not limited thereto. In one embodiment, multiplexer ML1 may include multiple transistors (e.g., CKL1, CKL2, CKL3, and not limited thereto), which are electrically connected to different electronic unit drive circuits 20. In one embodiment, multiplexer ML2 may include multiple transistors (e.g., CKLS1, CKLS2, CKLS3, and not limited thereto), which are electrically connected to different sensing unit drive circuits 30.

[0144] In one embodiment, the transistor SW1 or SW2 may be made of LTPS, IGZO, or HMO, and is not limited thereto. In one embodiment, multiplexers MI1, MI2, ML1, or ML2 may include multiple transistors, wherein the transistors may be made of LTPS or HMO, and is not limited thereto.

[0145] Furthermore, in this embodiment, the electronic unit driving circuit 20 can be electrically connected to the data line DL, and the sensing unit driving circuit 30 can be electrically connected to the data readout line RL. However, in other embodiments, the structure of FIG16 can also be adopted, so that the data line DL and the data readout line RL are integrated into an integrated signal line DR, but it is not limited to this.

[0146] Thus, different embodiments of the circuit structure of the electronic device 1 of this application can be understood. It should be noted that this application is not limited thereto.

[0147] In one embodiment, the present application may determine whether a product falls within the scope of protection of the present application by at least the presence or absence of components, component configuration, mechanical observation and / or operation of the product in dispute, and is not limited thereto.

[0148] Details or features of the various embodiments of this application may be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0149] Therefore, this application can provide an electronic device with display and sensing functions. Since the display circuit and the sensing circuit can be integrated, the electronic device of this application can provide high-resolution display function and high-precision sensing function.

[0150] The above embodiments are merely illustrative examples for ease of explanation. The scope of rights claimed in this application shall be determined by the claims of the patent application, and not limited to the above embodiments.

[0151] 1: Electronic devices AA: Active Zone A: Main area B: Surrounding Area C: Corner Area PA: Outer Zone Z: Outer region 10:Substrate 25: Electronic Unit 35: Sensing Unit 20-electronic unit drive circuit 30: Sensing unit drive circuit T1: Driving transistor T2: Data writing transistor T3: Reset Transistor T4, T5: Transistors T6: Switching transistor ST1: Driver Transistor ST2: Reset Transistor ST3: Data Transmission Transistor a1~a8, as1~as3, 67a: First end b1~b8, bs1~bs3, 67b: Second end c1~c8, cs1~cs3: Control terminals SN(N), SN_I(NX), SN_I(N), SN(N+Y), SN_I(N+Y), EM(N): drive unit DL: Data Line RL: Data Reading Line T7, T8, SW, CKDR, MD, MR, SW1, SW2, CKI1, CKI2, CKI3, CKIS1, CKIS2, CKIS3, CKL1, CKL2, CKL3, CKLS1, CKLS2, CKLS3: Transistors TA: Display Frame TB: Sensor Frame ta1~ta3, tb1~tb3: Sub-periods t11~t15: During the opening period 40: First conductive layer 41, 51, 621, 622, 42, 52, 43, 53: Sub-conductive layers 41a, 42a, 52a, 43a, 53a: line segments 41b, 51b, 42b, 52b, 43b, 53b: Gate 50: Second conductive layer 81: First metal layer L2-1, Lline, L2-2, W2-1, L1-1, L1-2, W1-1: Width 70: Semiconductor layer 71: First Semiconductor 71a, 63a, 72a: One end 71b, 63b, 72b: The other end 67c: Third end 72c: Extension 67d: Middle part 61: Third conductive layer 86: Sixth Metal Layer 83: Third metal layer 84: Fourth metal layer 62: Fourth conductive layer 63: Fifth conductive layer 87: Seventh Metal Layer 88: Eighth Metal Layer 64: Sixth conductive layer 81: First metal layer 72: Second Semiconductor 85: Fifth metal layer 65: Seventh conductive layer 66: Eighth conductive layer 67: Ninth conductive layer LT1, LST1, LST3, L2-1, L3-1: Channel length WST3, W2-1, W3-1: Channel width ST21, ST22: Transistors 70p: Pattern Section 91~99: Insulation layer 101, 111: Drain electrodes 102, 112: Source electrodes 711: First Sublayer 712: Second Sublayer 713, 714: Oxide-assisted semiconductor layer d1, d2: thickness SL, SLI, SLL: Gate wires DR: Integrated Signal Line DRM: Integrated Control Terminal MI1, MI2, ML1, ML2: Multiplexers

Claims

1. An electronic device, characterized in that it comprises: a substrate; a first conductive layer disposed on the substrate and including a first gate and a line segment, wherein the line segment is connected to the first gate; an electronic unit and a sensing unit respectively disposed on the substrate; and a sensing unit driving circuit disposed on the substrate and electrically connected to the electronic unit and the sensing unit; wherein, The sensing unit driving circuit includes a first transistor having a first gate, and the outline of the first gate is different from the outline of the line segment, and the difference between the outline of the first gate and the outline of the line segment means that the width of the first gate is different from the width of the line segment.

2. The electronic device as claimed in claim 1, wherein a ratio of the width of the line segment to the width of the first gate satisfies the equation: 0.3 times the width of the first gate < the ratio < 0.7 times the width of the first gate.

3. The electronic device as claimed in claim 1, further comprising a semiconductor layer and an electronic unit driving circuit disposed on the substrate, wherein the electronic unit driving circuit includes a second transistor electrically connected to the electronic unit, wherein the semiconductor layer includes a patterned portion, the first transistor includes a first semiconductor, the second transistor includes a second semiconductor, and the first semiconductor and the second semiconductor share the patterned portion.

4. The electronic device as claimed in claim 3, wherein the semiconductor layer is made of a metal oxide.

5. The electronic device of claim 1, further comprising a second conductive layer disposed on the first conductive layer, wherein the second conductive layer includes a second gate, and the first transistor has the second gate, the second gate of the first transistor at least partially overlapping the first gate of the first transistor.

6. The electronic device as claimed in claim 5, wherein the profile of the first gate is different from the profile of the second gate.

7. The electronic device as claimed in claim 6, wherein the difference between the profile of the first gate and the profile of the second gate means that a width of the first gate is different from a width of the second gate.

8. The electronic device of claim 1, further comprising an electronic unit driving circuit disposed on the substrate, wherein the first conductive layer includes a second gate, and the electronic unit driving circuit includes a second transistor having the second gate, and a profile of the second gate being different from the profile of the line segment.

9. The electronic device of claim 8, further comprising a third transistor disposed on the substrate, wherein the electronic device further comprises an active region and a peripheral region adjacent to the active region, the sensing unit driving circuit and the electronic unit driving circuit are disposed in the active region, the third transistor is disposed in the peripheral region, and the third transistor controls a signal to the first transistor and the second transistor.

10. The electronic device of claim 9, further comprising a fourth transistor disposed on the substrate, wherein the fourth transistor is electrically connected between the first transistor and the second transistor, and the signal is transmitted to the first transistor via the fourth transistor.

11. The electronic device as claimed in claim 8, wherein the line segment is connected to the second gate.

12. The electronic device of claim 1, further comprising an electronic unit driving circuit disposed on the substrate, the electronic unit driving circuit including a second transistor electrically connected to the electronic unit, and the electronic device further including a third transistor and a fourth transistor disposed on the substrate, wherein the electronic device further includes an active region and a peripheral region, the sensing unit driving circuit and the electronic unit driving circuit being disposed in the active region, the third transistor and the fourth transistor being disposed in the peripheral region, and the third transistor controlling a first signal to the first transistor, and the fourth transistor controlling a second signal to the second transistor.

13. The electronic device as claimed in claim 12, wherein the first signal is a reset signal and the second signal is a switch signal.

14. The electronic device of claim 13, further comprising a fifth transistor disposed on the substrate and located in the peripheral region, wherein the sensing unit driving circuit includes a sixth transistor, the fifth transistor controlling a readout signal to the sixth transistor during a plurality of first open periods, the fourth transistor controlling a switch signal to the second transistor during a plurality of second open periods, and at least one of the plurality of first open periods not overlapping with at least one of the plurality of second open periods.

15. The electronic device of claim 1, further comprising a second conductive layer and an electronic unit driving circuit disposed on the substrate, wherein the second conductive layer includes a second gate, the electronic unit driving circuit includes a second transistor having the second gate, and the second gate is electrically connected to the electronic unit.

16. The electronic device of claim 15, wherein a profile of the second gate is different from the profile of the line segment.

17. The electronic device of claim 16, wherein the profile of the second gate differs from the profile of the line segment in that a width of the second gate is smaller than a width of the line segment.

18. The electronic device of claim 15, wherein the first transistor and the second transistor are semiconductors of different materials.

19. The electronic device of claim 15, further comprising another conductive layer disposed on the substrate, wherein the other conductive layer includes a connection portion, and the first gate and the second gate are electrically connected through the connection portion.

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