Methods of patterning metal-oxide photoresists

Abstract

The embodiments disclosed herein include methods for dry developing metal oxide photoresists. In one embodiment, a method for patterning a metal oxide photoresist (such as a Sn-based photoresist) includes depositing the metal oxide photoresist on a substrate, exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure to form exposed and unexposed areas, and developing the exposed metal oxide photoresist using an electron donor ligand-based dry etching process.

Description

Dry Development for Metal Oxide Photoresist This application claims priority to U.S. Provisional Application No. 63 / 528,196, filed on Jul. 21, 2023, the entire content of which is incorporated herein by reference. Embodiments of the present disclosure relate to the field of semiconductor processing, and more particularly to methods for performing dry development on metal oxide photoresists. In the semiconductor industry, lithography has been used for decades to create 2D and 3D patterns in microelectronic components. The lithography process involves spin coating and depositing a film (photoresist), irradiating the film with a selected pattern using an energy source (exposure), and removing (etching) the exposed (positive) or unexposed (negative) areas of the film by dissolving them in a solvent. Baking will be performed to remove the remaining solvent. The photoresist should be a radiation-sensitive material, and upon irradiation, the exposed portions of the film undergo a chemical transformation, thereby causing a change in solubility between the exposed and unexposed regions. Utilizing this solubility change, the exposed or unexposed regions of the photoresist are removed (etched). Then, the photoresist is developed, and the pattern is transferred to the underlying film or substrate through etching. After transferring the pattern, the remaining photoresist is removed, and repeating this process multiple times can result in 2D and 3D structures for microelectronic components. In the lithography process, several properties are very important. Such important properties include sensitivity, resolution, lower line-edge roughness (LER), etch resistance, and the ability to form thinner layers. When the sensitivity is higher, the energy required to change the solubility of the deposited film is lower. This can enable higher efficiency of the lithography process. Resolution and LER determine how narrow features can be achieved in the lithography process. Pattern transfer requires a material with higher etch resistance to form deep structures. A material with higher etch resistance also enables thinner films. Thinner films can improve the efficiency of the lithography process. Embodiments disclosed herein include a method for patterning a metal oxide photoresist using a dry development process. In one embodiment, a method includes depositing a metal oxide photoresist on a substrate, exposing the metal oxide photoresist using extreme ultra-violet (EUV) exposure to form exposed and unexposed regions, and developing the exposed metal oxide photoresist using an electron donor ligand-based dry etching process. In one embodiment, another method includes depositing a metal oxide photoresist on a substrate, exposing the metal oxide photoresist using extreme ultra-violet (EUV) exposure to form exposed and unexposed regions, treating the exposed metal oxide photoresist using a fluorination process, and developing the exposed and fluorinated metal oxide photoresist using an electron donor ligand-based dry etching process. The embodiments may also include a method that includes depositing a metal oxide photoresist on a substrate, exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure to form an exposed region and an unexposed region, and developing the exposed metal oxide photoresist by cycling (1) treating the exposed metal oxide photoresist using a fluorination process and (2) using an electron donor ligand-based dry etching process. Methods for developing positive or negative metal oxide photoresists are described herein. In the following description, numerous specific details are set forth, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes and material systems for depositing positive or negative metal oxide photoresists, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects such as integrated circuit manufacturing are not described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Additionally, it should be noted that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. To provide context, there are inefficiencies in photoresist systems for extreme ultraviolet (EUV) lithography. That is, existing photoresist material systems for EUV lithography require high doses to provide the desired solubility conversion to allow development of the photoresist material. Traditionally, carbon-based films known as chemically amplified photoresists (CARs) have been used as photoresists. However, the latest organic-inorganic hybrid materials (metal-oxides) have been used as photoresists using extreme ultraviolet (EUV) radiation. Such materials typically include metals (such as Sn, Hf, Zr), oxygen, and carbon. In the lithography industry, the transition from deep ultraviolet (DUV) to extreme ultraviolet (EUV) has facilitated narrow features with high aspect ratios. Metal-oxide-based organic-inorganic hybrid materials have been shown to have lower line edge roughness (LER) and higher resolution, which are required for forming narrow features. Additionally, such films have higher sensitivity and etch resistance properties and can be implemented to fabricate relatively thin films. Currently, organotin oxides have entered the mainstream semiconductor manufacturing process flow to alleviate the low absorption rate of organic resist films to extreme ultraviolet (EUV) radiation, which will lead to poor sensitivity and inability to cope with harsh development and etching conditions. However, the corresponding lithography performance needs to achieve better line width roughness (LWR) metrics (LER is one of the most critical performance metrics that needs to be improved in EUV lithography) to achieve high-resolution patterning. Wet development is a conventional technique for developing a resist in a track process. The developer interacts with the Sn-based resist at the cluster level, so partially exposed PR at the edges may / may not dissolve (determined by the degree of exposure experienced). Therefore, in development, the cluster size limits the resolution, leading to roughness problems. According to one or more embodiments of the present disclosure, a dry development technique is implemented to provide atomic-level interaction with the PR rather than cluster-level interaction. According to one or more embodiments of the present disclosure, dry development is performed on a metal oxide photoresist (e.g., Sn PR is described as an exemplary film). Volatile organic molecules and inorganic molecules are used to etch the Sn-O-based film. Embodiments may include targeting the formation of a known stable volatile Sn precursor from the SnO photoresist. The method can be implemented in two ways: (1) reacting a ligand with the SnOC photoresist (e.g., Figure 4, described below), (2) converting SnOC to SnFx and then reacting SnFx with the ligand (the reactivity of SnFx must be greater than that of SnOx, Ediss(Sn-F) = 467 Kj / mol and Ediss(Sn-O) 548 Kj / mol) (e.g., Figure 5, described below). Advantages of implementing the embodiments described herein may include enabling a path for atomic-level photoresist (PR) development in the gas phase. Atomic-level photoresist development can replace wet development or can be used as post-dry development after wet development to finely etch the remaining portions in the clusters that were not removed and leave partial clusters. To provide more background, Figure 1A shows several cross-sectional views representing various operations in a patterning process of a positive photoresist material formed using a process described herein, according to one embodiment of the present disclosure. Referring to part (a) of Figure 1A, the starting structure 100 includes a positive photoresist layer 104 above a substrate or lower layer 102. In one embodiment, the positive photoresist layer 104 is deposited using dry or wet deposition. Referring to part (b) of Figure 1A, the starting structure 100 is irradiated 106 at selected locations to form an irradiated photoresist layer 104A having an irradiated region 105B and an unirradiated region 105A. Referring to part (c) of Figure 1A, a removal or etching process 108 is used to provide a developed photoresist layer in the unirradiated region 105A. Referring to part (d) of Figure 1A, an etching process 110 using the unirradiated region 105A as a mask is used to pattern the substrate or lower layer 102 to form a patterned substrate or patterned lower layer 102A including etched features 112. Referring again to FIG. 1A, the positive photoresist 104 is a radiation-sensitive material, and upon irradiation, the exposed portion of the film undergoes a chemical transformation, thereby causing a change in solubility between the exposed and unexposed regions. Utilizing the solubility change, the exposed regions of the positive photoresist are removed (etched). Then, the positive photoresist is developed, and the pattern is transferred to the underlying film or substrate through etching. After transferring the pattern, the remaining positive photoresist is removed. This process can be repeated multiple times, and 2D and 3D structures can be fabricated, for example, for microelectronic components. To provide more background, FIG. 1B shows several cross-sectional views representing various operations in a patterning process using a negative photoresist material formed by the process described herein, according to an embodiment of the present disclosure. Referring to part (a) of FIG. 1B, the starting structure 100 includes a negative photoresist layer 103 above a substrate or underlying layer 102. In one embodiment, the negative photoresist layer 103 is deposited by dry or wet deposition. Referring to part (b) of FIG. 1B, the starting structure 100 is irradiated 106 at selected locations to form an irradiated photoresist layer 103A having an irradiated region 105B and an unirradiated region 105A. Referring to part (c) of FIG. 1B, a removal or etching process 108 is used to provide a developed photoresist layer of the irradiated region 105B. Referring to part (d) of FIG. 1B, an etching process 110 using the irradiated region 105B as a mask is used to pattern the substrate or underlying layer 102 to form a patterned substrate or patterned underlying layer 102A including etched features 112. Referring again to FIG. 1B, the negative photoresist 103 is a radiation-sensitive material, and upon irradiation, the exposed portion of the film undergoes a chemical transformation, thereby causing a change in solubility between the exposed and unexposed regions. Utilizing the solubility change, the unexposed regions of the negative photoresist are removed (etched). Then, the negative photoresist is developed, and the pattern is transferred to the underlying film or substrate through etching. After transferring the pattern, the remaining negative photoresist is removed. This process can be repeated multiple times, and 2D and 3D structures can be fabricated, for example, for microelectronic components. As will be described in more detail below, both positive resists and negative resists can be metal oxide photoresist films. In some cases, the same material system can be used for positive resists and negative resists. That is, dry or wet deposition using EUV exposure can be used to form positive resists and negative resists. As described above, volatile organic molecules and inorganic molecules can be used to etch metal oxide films (such as Sn-O-based films). It should be understood that amine-based, oxygen-based, and alkyl-based Sn precursors can be stable and volatile. In one embodiment, the development method effectively provides reverse engineering to remove SnOx to become SnRx(NR'2)y, Sn(NR-CR'-NR)x, SnRx, Sn(OR)x species. For example, using NH 4 O and / or NH 4 Br as an etchant to etch the Sn film can effectively develop the film. Amines and halides form volatile Sn species when reacting with SnO 2 or SnF 4 films. NH 4 Cl and / or NH 4 Br can be delivered to the gas phase of the etching chamber to etch the Sn film. It should be understood that the reaction of metal oxide photoresists, such as tin oxide-based photoresists, can be developed (etched) by effectively forming volatile metal compounds and volatilizing these compounds as by-products of the development process. As exemplary volatile species, FIGS. 2A-2C show volatile Sn-based compounds produced by performing a dry development process on an Sn-based photoresist according to an embodiment of the present disclosure. Specifically, FIG. 2A is a schematic diagram 200 of volatile compounds (a), (b), (c), (d), and (e) of N-containing Sn. FIG. 2B is a schematic diagram 210 of volatile compounds (a) and (b) of O-containing Sn. FIG. 2C is a schematic diagram 220 of volatile compounds (a) and (b) of C-containing Sn. Referring again to FIGS. 2A-2C, these are fully coordinated Sn centers with stable and volatile ligands (these are characterized Sn complexes used as CVD / ALD precursors). In other embodiments, mixed ligands and oxygen or alkyl Sn centers, such as still volatile SnO(NR 2 ) 2 or SnR(NR 2 ) 3 species) can be used. As an exemplary etch ligand, FIG. 3 is a schematic diagram 300 of ligands (a), (b), (c), (d), (e), (f), and (g) according to an embodiment of the present disclosure. These ligands are non-limiting examples of stable ligands with reasonable boiling points that can be transported in the gas phase as reactants to remove the more reactive SnOC species in the tin oxide-based photoresist film. In one embodiment, one or more such ligands are delivered to the PR-coated wafer in the chamber after exposure to EUV light. The Sn in the unexposed region reacts with the incoming ligand, and the PR effectively etches and patterns the surface based on the mask used for EUV exposure. In some embodiments, hexafluoroacetylacetone (hfacH) (i.e., ligand (g)) has been shown to be able to form a high contrast between the exposed and unexposed regions. The benefits of using hfacH may be more pronounced at higher temperatures and / or pressures. Fluorination treatment before applying the ligand can also improve the etch selectivity of hfacH. It should be understood that increasing the temperature and / or pressure can also improve the etch selectivity of ligands (a)-(f). As a first exemplary process flowchart, FIG. 4 shows several cross-sectional views representing various operations in a method of patterning a photoresist layer according to an embodiment of the present disclosure. Referring to FIG. 4, a method 400 of patterning a metal oxide photoresist (such as an Sn-based photoresist) includes (a) depositing a metal oxide photoresist 406 on a substrate 402 (with an optional underlying layer 404 therebetween). The method further includes (b) exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure 408 to form an exposed region 410 and an unexposed region 412. The method further includes (c) developing the exposed metal oxide photoresist 406A using a dry etch process 414 based on an electron donor ligand. For example, this process can produce volatile by-products such as exemplary SnOyLx. In one embodiment, the electron donor ligand is a ligand as shown in FIGS. 2A-2C and FIG. 3 and can be a Lewis base ligand. In one embodiment, developing the exposed metal oxide photoresist 406A can be performed under any suitable processing conditions. For example, the chamber pressure can be up to 25 Torr, 10 Torr, or 1 Torr. The temperature in the chamber (such as the substrate temperature) can be between 50°C and 200°C. In one embodiment, the chemical soak time can be up to 10 minutes, 30 minutes, or 1 hour. In some embodiments, it has been shown that higher temperatures and / or higher pressures can improve the etch selectivity between the exposed region 410 and the unexposed region 412. In one embodiment, the developed and exposed metal oxide photoresist 406A further includes performing a wet development process before performing the dry etching process 414 based on an electron donor ligand. In another embodiment, the developed and exposed metal oxide photoresist 406A does not include using a wet development process and the dry etching process 414 based on an electron donor ligand together. In one embodiment, the metal oxide photoresist 406 is a positive photoresist. In another embodiment, the metal oxide photoresist 406 is a negative photoresist. In one embodiment, the developed and exposed metal oxide photoresist 406A includes removing the unexposed region 412 as described herein. However, in another embodiment, the developed and exposed metal oxide photoresist 406A includes removing the exposed region 410. As a second exemplary process flowchart, FIG. 5 shows several cross-sectional views that represent various operations in a method of patterning a photoresist layer according to another embodiment of the present disclosure. Referring to FIG. 5, a method 500 of patterning a metal oxide photoresist (such as an Sn-based photoresist) includes (a) depositing a metal oxide photoresist 506 (with an optional underlying layer 504 therebetween) on a substrate 502. The method further includes (b) exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure 508 to form an exposed region 510 and an unexposed region 512. The method further includes (c) treating the exposed metal oxide photoresist 506A using a fluorination process 514 to form a fluorinated unexposed region 512A. The method further includes (d) developing the exposed and fluorinated metal oxide photoresist 506B using a dry etching process 516 based on an electron donor ligand. For example, the process can provide volatile by-products such as the exemplary SnFzOyLx. In one embodiment, the electron donor ligand is the ligand shown in FIGS. 2A-2C and FIG. 3 and can be a Lewis base ligand. In one embodiment, the developed, exposed, and fluorinated metal oxide photoresist 506B can be performed under any suitable processing conditions. For example, the chamber pressure can be up to 25 Torr, 10 Torr, or 1 Torr. The temperature inside the chamber (such as the substrate temperature) can be between 50°C and 200°C. In one embodiment, the chemical soak time can be up to 10 minutes, 30 minutes, or 1 hour. In some embodiments, it has been demonstrated that higher temperatures and / or higher pressures can improve the etching selectivity between the exposed region 510 and the fluorinated unexposed region 512A. In some cases, it has been demonstrated that the fluorination process can further improve the etching selectivity between the exposed region 510 and the fluorinated unexposed region 512A. In one embodiment, the developed, exposed, and fluorinated metal oxide photoresist 506B further includes a wet development process before performing a dry etching process 516 based on an electron donor ligand. In another embodiment, the developed, exposed, and fluorinated metal oxide photoresist 506B does not include using a wet development process and a dry etching process 516 based on an electron donor ligand together. In one embodiment, the metal oxide photoresist 506 is a positive photoresist. In another embodiment, the metal oxide photoresist 506 is a negative photoresist. In one embodiment, the developed, exposed, and fluorinated metal oxide photoresist 506B includes removing the fluorinated unexposed region 512A, as described herein. However, in another embodiment, the developed, exposed, and fluorinated metal oxide photoresist 506B includes removing the exposed region 510. In one embodiment, referring again to FIG. 5, the exposed metal oxide photoresist 506A is processed using a fluorination process 514 and a dry etching process 516 based on an electron donor ligand is cycled 599 two or more times to complete the dry development process. According to one embodiment of the present disclosure, a positive or negative photoresist is obtained by using a specific type of R group in a metal precursor or a plasma-assisted deposition method. It should be understood that the lithography industry generally uses positive PRs for processing, but almost all new metal oxide PRs are negative PRs. The embodiments described herein can be implemented for dry development of both positive and negative PRs. In another aspect, for the exposure environment, when the photoresist is exposed to an energy source (such as EUV), the exposure chamber (environment) can be oxygen-containing or inert. In one embodiment, exposure is performed in a vacuum state when using an oxygen source (such as O 2 、H 2 O、CO 2 、CO、NO 2 or NO). In one embodiment, the repetition of EUV exposure and oxygen exposure can be performed 1 to 100 times. In another aspect, post-annealing is performed in an oxygen-containing environment. In one embodiment, the oxygen source is O 3 、NO 2 、NO or O 2 ,which can be used to form a plasma, and / or can be combined with N 2, used in combination with Ar or He. In one embodiment, the post-annealing is carried out at a temperature in the range of 25 - 200 °C. In one embodiment, the post-annealing is performed at a pressure of less than 200 Torr. In a specific embodiment, ozone (O 3 ) is used as the oxygen source gas, and the post-annealing is carried out at a temperature in the range of 25 - 250 °C and a pressure of less than 200 Torr. Regarding the deposition of metal oxide photoresist, according to one embodiment of the present disclosure, in a first method, the chemical vapor deposition (CVD) method for forming a positive or negative photoresist includes: (A) vaporizing one or more metal precursors and one or more oxidants into a vacuum chamber, wherein the substrate wafer is maintained at a predetermined substrate temperature. The substrate temperature can vary from 0 °C to 500 °C. When the precursors / oxidants are vaporized into the chamber, they can be diluted with an inert gas (such as Ar, N 2 , He). Due to the reactivity of the precursors and oxidants, a metal oxide film is deposited on the wafer. The vaporization into the chamber can be carried out by simultaneously vaporizing all the precursors, or by alternately pulsing the metal precursors and oxidants. This process can be described as thermal CVD. (B) Plasma can also be turned on during the process, and then the process can be described as plasma-enhanced (PE)-CVD. Examples of plasma sources include CCP, ICP, remote plasma, microwave plasma. (C) The photoresist film deposition can be carried out by thermal deposition followed by plasma treatment. In this case, a thermal deposition film is first formed, and then a plasma treatment operation is performed. The plasma treatment may involve plasma from an inert gas (such as Ar, N 2 , He), or these gases can be mixed with O 2 , CO 2 , CO, NO, NO 2 , H 2 O. These processes can be carried out in a cyclic manner; thermal deposition is followed by plasma treatment, and this cycle is repeated, or the deposition part is completed, and then a single plasma treatment (post-treatment) is performed. It is also possible to follow PECVD with plasma treatment. In any case, in one embodiment, the post-annealing is carried out in an oxygen-containing environment. In one embodiment, ozone (O 3 ) is used as the oxygen source gas, and the post-annealing is carried out at a temperature in the range of 25 - 250 °C and a pressure of less than 200 Torr. In a second method, according to an embodiment of the present disclosure, an atomic layer deposition (ALD) method for forming a positive or negative photoresist includes: (A) vaporizing a metal precursor into a vacuum chamber, wherein a substrate wafer is maintained at a predetermined substrate temperature. The substrate temperature can vary from 0°C to 500°C. Then, an inert gas purge is provided to remove by-products and excess metal precursor. Then, one or more oxidants are vaporized into the chamber. The oxidant reacts with the surface-absorbed metal precursor. Then, an inert gas purge is applied to remove by-products and unreacted oxidant. This cycle can be repeated to achieve the desired thickness. When the precursor or oxidant is vaporized into the chamber, it can be diluted with an inert gas (such as Ar, N 2 , He). This process can be described as thermal ALD. Using this method, more than one metal can be incorporated into the film by pulsing an additional metal precursor into the ALD cycle. Additionally, different oxidants can be pulsed after the first oxidant. (B) Plasma can be turned on during the oxidant pulse, and then the process can be described as PE-ALD. (C) Additionally, deposition can be carried out by thermal ALD followed by plasma treatment. In this case, a thermal deposition film is first formed, and then a plasma treatment operation is performed. The plasma treatment may involve plasma from an inert gas (such as Ar, N 2 , He), or these gases can be mixed with O 2 , CO 2 , CO, NO, NO 2 , H 2 O. These processes can be performed in a cyclic manner; X thermal ALD cycles (X = 1 - 5000) followed by plasma treatment and repeated the number of times required for the entire cycle, or the deposition part is completed and then a plasma treatment is carried out once. It is also possible to have PE-ALD followed by plasma treatment. In any case, in one embodiment, post-annealing is performed in an oxygen-containing environment. In one embodiment, ozone (O 3 ) is used as the oxygen source gas, and post-annealing is carried out at a temperature in the range of 25 - 250°C under a pressure of less than 200 Torr. In a third method, according to an embodiment of the present disclosure, an atomic layer deposition (ALD) or chemical vapor deposition (CVD) method for forming a positive or negative photoresist includes providing a composition gradient throughout the film. For example, the first few nanometers of the film have a different composition from the rest of the film. The main part of the film can be optimized for dose, but for a different composition near the interface layer to change adhesion, sensitivity to EUV photons, sensitivity to developing chemicals, thereby improving post-lithography profile control (especially scum) and defects and resist collapse / drop-off. The gradient can be optimized for the pattern type, for example, pillars that require increased adhesion and line / space patterns that can reduce adhesion to improve dose. In one embodiment, the vacuum deposition process relies on a chemical reaction between a metal precursor and an oxidant. The metal precursor and the oxidant are vaporized into a vacuum chamber. In some embodiments, the metal precursor and the oxidant are provided together into the vacuum chamber. In other embodiments, the metal precursor and the oxidant are provided into the vacuum chamber in alternating pulses. After forming a positive or negative metal-oxide photoresist film with a desired thickness, the process may stop. In one embodiment, after forming a positive or negative metal-oxide photoresist film with a desired thickness, an optional plasma treatment operation may be performed. In one embodiment, a cycle including a metal precursor vapor pulse and an oxidant vapor pulse can be repeated a plurality of times to provide a positive or negative metal-oxide photoresist film with a desired thickness. In one embodiment, the cycle order can be switched. For example, first pulse the oxidant vapor, and then pulse the metal precursor vapor. In one embodiment, the pulse duration of the metal precursor vapor can be substantially similar to the pulse duration of the oxidant vapor. In other embodiments, the pulse duration of the metal precursor vapor can be different from the pulse duration of the oxidant vapor. In one embodiment, the pulse duration can be between 0 seconds and 1 minute. In a specific embodiment, the pulse duration can be between 1 second and 5 seconds. In one embodiment, the same process gas is used for each iteration of the cycle. In other embodiments, the process gas can be changed between cycles. For example, the first cycle can use a first metal precursor vapor, and the second cycle can use a second metal precursor vapor. Subsequent cycles can continue to alternate between the first metal precursor vapor and the second metal precursor vapor. In one embodiment, multiple oxidant vapors can be alternated between cycles in a similar manner. In one embodiment, an optional plasma treatment operation can be performed after each cycle. That is, each cycle can include a metal precursor vapor pulse, an oxidant vapor pulse, and a plasma treatment. In an alternative embodiment, an optional plasma treatment operation can be performed after a plurality of cycles. In yet another embodiment, an optional plasma treatment operation can be performed after all cycles are completed (i.e., as a post-treatment). In one embodiment, the vacuum chamber employed in the dry development process is any suitable chamber capable of providing a sub-atmospheric pressure. In one embodiment, the vacuum chamber may include temperature control features for controlling the chamber wall temperature and / or for controlling the substrate temperature. In one embodiment, the vacuum chamber may further include features for providing plasma within the chamber. A suitable vacuum chamber is described in more detail below with reference to FIG. 6. FIG. 6 is a schematic diagram of a vacuum chamber according to an embodiment of the present disclosure, the vacuum chamber being configured to perform dry development of a metal oxide photoresist. The vacuum chamber 600 includes a grounded chamber 605. A substrate 610 is loaded through an opening 615 and clamped onto a temperature-controlled chuck 620. In one embodiment, the substrate 610 can be temperature-controlled during the dry development process. For example, the temperature of the substrate 610 can be between approximately -40 degrees Celsius and 200 degrees Celsius. In a particular embodiment, the substrate 610 can be maintained at a temperature between room temperature and 150 °C. Process gases are supplied from a gas source 644 through respective mass flow controllers 649 into the interior of the chamber 605. In certain embodiments, a gas distribution plate 635 is used to distribute the process gases 644, such as ligands and inert gases. The chamber 605 is evacuated via an exhaust pump 655. In one embodiment, one or more process gases are contained / stored in one or more ampoules. In one embodiment, the dry development process is a chemical vapor condensation process, and the temperature of the one or more ampoules is maintained higher than the temperature of the substrate, such as 25 degrees Celsius or more higher than the temperature of the substrate. When RF power is applied during the processing of the substrate 610, a plasma is formed on the substrate 610 in the chamber processing region. A bias power RF generator 625 is coupled to the temperature-controlled chuck 620. If needed, the bias power RF generator 625 can provide bias power to excite the plasma. For example, the low frequency of the bias power RF generator 625 is between 2 MHz and 60 MHz, and in a particular embodiment, in the 13.56 MHz band. In certain embodiments, the vacuum chamber 600 includes a third bias power RF generator 626 having a frequency in the approximately 2 MHz band, connected to the same RF match 627 as the bias power RF generator 625. A source power RF generator 630 is coupled through a match (not shown) to a plasma generating element (such as the gas distribution plate 635) to provide source power to excite the plasma. The frequency of the source RF generator 630 can be between 100 MHz and 180 MHz, for example, in a particular embodiment, in the 162 MHz band. Since the substrate diameter progresses over time from 150 mm, 200 mm, 300 mm, etc., in this technology, the source power of the plasma etching system and the bias power to the substrate area are typically normalized. The vacuum chamber 600 is controlled by a controller 670. The controller 670 may include a CPU 672, a memory 673, and an I / O interface 674. The CPU 672 may perform processing operations within the vacuum chamber 600 according to instructions stored in the memory 673. For example, one or more processes (such as processes 120 and 440 described above) may be executed by the controller 670 in the vacuum chamber. In another aspect, embodiments disclosed herein include a processing tool that includes a configuration particularly suitable for optimizing dry development. For example, the processing tool may include a pedestal for supporting a temperature-controlled wafer. In some embodiments, the temperature of the pedestal may be maintained between about -40°C and about 300°C. Additionally, an edge purge flow and a shadow ring may be provided around the perimeter of the posts supporting the substrate. The edge purge flow and the shadow ring prevent positive or negative metal oxide photoresist from depositing along the edges or back of the wafer. In one embodiment, the pedestal may also provide any desired chuck structure, such as, but not limited to, a vacuum chuck, a monopole chuck, or a bipolar configuration, depending on the operating procedures of the processing tool. In some embodiments, the processing tool may be suitable for deposition processes without plasma. Alternatively, the processing tool may include a plasma source to enable plasma-enhanced operations. Additionally, while the embodiments disclosed herein are particularly suitable for depositing positive or negative metal-oxide photoresists for EUV patterning, it should be understood that the embodiments are not limited to such configurations. For example, the processing tools described herein are suitable for depositing any positive or negative photoresist material for any lithography system using a dry development process. Referring now to FIG. 7, a cross-sectional view of a processing tool 700 according to an embodiment is shown. In one embodiment, the processing tool 700 may include a chamber 705. The chamber 705 may be any suitable chamber capable of supporting a sub-atmospheric pressure (e.g., a vacuum pressure). In one embodiment, an exhaust port (not shown) including a vacuum pump may be coupled to the chamber 705 to provide a sub-atmospheric pressure. In one embodiment, a lid may seal the chamber 705. For example, the lid may include a showerhead assembly 740 or a similar assembly. The showerhead assembly 740 may include fluid passages to enable processing gases and / or inert gases to flow into the chamber 705. In some embodiments where the processing tool 700 is suitable for plasma-enhanced operations, the showerhead assembly 740 may be electrically coupled to a radio frequency source and a matching circuit system 750. In yet another embodiment, the tool 700 may be configured in a radio frequency bottom-fed configuration. That is, the pedestal 730 is connected to the radio frequency source, and the showerhead assembly 740 is grounded. In such embodiments, a filter circuit system may still be connected to the pedestal. In one embodiment, a precursor gas is stored in an ampoule 799. In one embodiment, a movable post for supporting a wafer 701 is provided in a chamber 705. In one embodiment, the wafer 701 can be any substrate on which a positive or negative metal oxide photoresist material is deposited. For example, the wafer 701 can be a 300 mm wafer or a 450 mm wafer, although other wafer diameters can also be used. Additionally, the wafer 701 can be replaced with a substrate having a non-circular shape in some embodiments. The movable post can include a support post 714 extending from the chamber 705. The support post 714 can have a port to provide electrical and fluid paths from outside the chamber 705 to various components of the post. In one embodiment, the post can include a bottom plate 710. The bottom plate 710 can be grounded. As will be described in more detail below, the bottom plate 710 can include fluid channels to allow an inert gas to flow to provide an edge purge flow. In one embodiment, an insulating layer 715 is placed on the bottom plate 710. The insulating layer 715 can be any suitable dielectric material. For example, the insulating layer 715 can be a ceramic plate or the like. In one embodiment, a susceptor 730 is placed on the insulating layer 715. The susceptor 730 can include a single material, or the susceptor 730 can be formed of different materials. In one embodiment, the susceptor 730 can be used to hold the wafer 701 using any suitable chucking system. For example, the susceptor 730 can be a vacuum chuck or a monopole chuck. In embodiments where no plasma is generated in the chamber 705, the susceptor 730 can employ a bipolar chuck configuration. The susceptor 730 can include a plurality of cooling channels 731. The cooling channels 731 can be connected to fluid inputs and fluid outputs (not shown) passing through the support post 714. In one embodiment, the cooling channels 731 allow the temperature of the wafer 701 to be controlled during operation of the processing tool 700. For example, the cooling channels 731 can allow the temperature of the wafer 701 to be controlled between approximately -40 °C and approximately 300 °C. In one embodiment, the susceptor 730 is connected to ground through a filtering circuitry 745, thereby enabling a DC and / or RF bias of the susceptor relative to ground. In one embodiment, an edge ring 720 surrounds the periphery of the insulating layer 715 and the susceptor 730. The edge ring 720 can be a dielectric material, such as ceramic. In one embodiment, the edge ring 720 is supported by the bottom plate 710. The edge ring 720 can support a shadow ring 735. The inner diameter of the shadow ring 735 is smaller than the diameter of the wafer 701. Thus, the shadow ring 735 prevents positive or negative metal oxide photoresist from depositing on a portion of the outer edge of the wafer 701. A gap is provided between the shadow ring 735 and the wafer 701. This gap prevents the shadow ring 735 from contacting the wafer 701 and provides an outlet for the edge purge flow, which will be described in more detail below. In one embodiment, a dual-channel showerhead can be used for positive or negative metal oxide photoresist manufacturing processes. Although the shadow ring 735 provides some protection for the top surface and edges of the wafer 701, the processing gas can flow / diffuse downward along the path between the edge ring 720 and the wafer 701. Accordingly, embodiments disclosed herein can include a fluid path between the edge ring 720 and the base 730 to effect an edge purge flow. Providing an inert gas in the fluid path increases the local pressure in the fluid path and prevents the processing gas from reaching the edges of the wafer 701. Accordingly, deposition of positive or negative metal oxide photoresist along the edges of the wafer 701 is prevented. Referring now to FIG. 8, an enlarged cross-sectional view of a portion of a post 860 in a processing tool according to one embodiment is shown. In FIG. 8, only the left edge of the post 860 is shown. However, it is to be understood that the right edge of the post 860 can be substantially a mirror image of the left edge. In one embodiment, the post 860 can include a bottom plate 810. An insulating layer 815 can be disposed on the bottom plate 810. In one embodiment, the base 830 can include a first portion 830A and a second portion 830B. Cooling channels 831 can be placed in the second portion 830B. The first portion 830A can include features for clamping a wafer 801. In one embodiment, an edge ring 820 surrounds the bottom plate 810, the insulating layer 815, the base 830, and the wafer 801. In one embodiment, the edge ring 820 is spaced apart from other components of the post 850 to provide a fluid path 812 from the bottom plate 810 to the top side of the post 860. For example, the fluid path 812 can exit the post between the wafer 801 and the shadow ring 835. In a particular embodiment, the inner surface of the fluid path 812 includes the edges of the insulating layer 815, the edges of the base 830 (i.e., the first portion 830A and the second portion 830B), and the edge of the wafer 801. In one embodiment, the outer surface of the fluid path 812 includes the inner edge of the edge ring 820. In one embodiment, when the fluid path 812 extends to the edge of the wafer 801, it can also continue through the top surface of a portion of the base 830. Accordingly, when an inert gas (e.g., helium, argon, etc.) flows through the fluid path 812, the processing gas is prevented from flowing / diffusing downward along one side of the wafer 801. In one embodiment, the width W of the fluid path 812 is minimized to prevent plasma ignition along the fluid path 812. For example, the width W of the fluid path 812 can be approximately 1 mm or less. In one embodiment, a seal 817 blocks the fluid path 812 from exiting the bottom of the post 860. The seal 817 can be placed between the edge ring 820 and the bottom plate 810. The seal 817 can be a flexible material, such as gasket material or the like. In a particular embodiment, the seal 817 includes polysiloxane. In one embodiment, a channel 811 is provided in a bottom plate 810. The channel 811 conveys an inert gas from the center of a column 860 to an inner edge of an edge ring 820. It should be understood that only a part of the channel 811 is shown in FIG. 8. A more comprehensive illustration of the channel 811 is provided below with respect to FIG. 10B. In one embodiment, the edge ring 820 and the shadow ring 835 may have features adapted to align the shadow ring 835 relative to the wafer 801. For example, a notch 821 in a top surface of the edge ring 820 may interface with a protrusion 836 on a bottom surface of the shadow ring 835. The notch 821 and the protrusion 836 may have tapered surfaces to roughly align the two components sufficiently to provide more precise alignment when the edge ring 820 contacts the shadow ring 835. In an additional embodiment, alignment features (not shown) may also be provided between the base 830 and the edge ring 820. The alignment features between the base 830 and the edge ring 820 may include tapered notch and protrusion structures similar to the alignment features between the edge ring 820 and the shadow ring 835. Now referring to FIGS. 9A and 9B, a pair of cross-sectional views depicting portions of a processing tool with a base located at different positions (Z direction) according to an embodiment are shown. In FIG. 9A, the position of the base is at a lower position within the chamber. The position of the base in FIG. 9A is the position where a wafer is inserted or removed from the chamber through a slit valve. In FIG. 9B, the base is located at an elevated position within the chamber. The position of the base in FIG. 9B is the position where the wafer is processed. Now referring to FIG. 9A, a cross-sectional view of a movable column 960 located at a first position according to an embodiment is shown. As shown in FIG. 9A, the column includes a bottom plate 910, an insulating layer 915, a base 930 (i.e., a first portion 930A and a second portion 930B), and an edge ring 920. These components are substantially similar to the components with similar names described above. For example, a cooling channel 931 may be provided in the second portion 930B of the base 930, a channel 911 may be provided in the bottom plate 910, and a seal 917 may be provided between the edge ring 920 and the bottom plate 910. As shown in FIG. 9A, a wafer 901 is placed on a top surface of the base 930. The wafer 901 may be inserted into the chamber through a slit valve (not shown). Additionally, a shadow ring 935 is shown at an elevated position above the edge ring 920. Since the inner diameter of the shadow ring 935 is smaller than the diameter of the wafer 901, the wafer 901 needs to be placed on the base before the shadow ring 935 contacts the edge ring 920. In one embodiment, the shadow ring 935 is supported by the chamber liner 970. The chamber liner 970 can surround the outer peripheral edge of the post 960. In one embodiment, the bracket 971 is located on the top surface of the chamber liner 970. The bracket 971 is configured to hold the shadow ring 935 in a raised position above the edge ring 920 when the post 960 is in the first position. In one embodiment, the shadow ring 935 includes a protrusion 936 for aligning with the notch 921 in the edge ring 920. Referring now to FIG. 9B, a cross-sectional view of the post 960 after engaging the shadow ring 935 is shown according to one embodiment. As shown, the post 960 moves in the vertical direction (i.e., the Z direction) until the shadow ring 935 engages the edge ring 920. Further vertical displacement of the post 960 lifts the shadow ring 935 off the bracket 971 on the chamber liner 970. In one embodiment, due to the alignment features in the shadow ring 935 and the edge ring 920 (i.e., the notch 921 and the protrusion 936), the shadow ring 935 is correctly aligned. In an additional embodiment, alignment features (not shown) can also be provided between the base 930 and the edge ring 920. The alignment features between the base 930 and the edge ring 920 can include tapered notches and protrusion frameworks similar to the alignment features between the edge ring 920 and the shadow ring 935. When in the second position, the wafer 901 can be processed. Specifically, the processing can include depositing a positive or negative metal oxide photoresist material on the top surface of the wafer 901. For example, the process can be a dry development process with or without plasma assistance. In a particular embodiment, the positive or negative photoresist is a metal-oxide positive or negative photoresist suitable for EUV patterning. However, it should be understood that the positive or negative photoresist can be any type of positive or negative photoresist, and the patterning can include any lithography system. During the deposition of the positive or negative metal oxide photoresist onto the wafer 901, an inert gas can flow along the fluid channel between the inner surface of the edge ring 910, the insulating layer 915, the base 930, and the outer surface of the wafer 901. Thus, deposition of the positive or negative metal oxide photoresist along the edge or back surface of the wafer 901 is substantially eliminated. In one embodiment, the wafer temperature 901 can be maintained between approximately -40°C and approximately 200°C by the cooling channels 931 in the second portion of the base 930 B of the base 930. Referring now to FIG. 10A, a cross-sectional view of a processing tool 1000 according to an additional embodiment is shown. As shown in FIG. 10A, the column includes a bottom plate 1010. The bottom plate 1010 may be supported by struts 1014 that extend out of the chamber. That is, in some embodiments, the bottom plate 1010 and the struts 1014 may be discrete components rather than a single integral component as shown in FIG. 7. The struts 1014 may have a central channel for routing electrical connections and fluids such as cooling fluid and inert gas for purging fluid. In one embodiment, an insulating layer 1015 is disposed on the bottom plate 010, and a susceptor 1030 (i.e., a first part 1030A and a second part 1030B) is disposed on the insulating layer 1015. In one embodiment, a coolant channel 1031 is provided in the second part 1030B of the susceptor 1030. A wafer 1001 is disposed on the susceptor 1030. In one embodiment, an edge ring 1020 is provided around the bottom plate 1010, the insulating layer 1015, the susceptor 1030, and the wafer 1001. The edge ring 1020 can be coupled to the bottom plate 1013 through a fastening mechanism 1013, such as bolts, pins, screws, or the like. In one embodiment, a seal 1017 prevents the purge gas from discharging from the bottom of the column through the gap between the bottom plate 1010 and the edge ring 1020. In the illustrated embodiment, the susceptor 1030 is in a first position. Accordingly, the shadow ring 1035 is supported by the bracket 1071 and the chamber liner 1070. When the susceptor 1030 is vertically displaced, the edge ring 1020 will engage the shadow ring 1035 and lift the shadow ring 1035 off the bracket 1071. Referring now to FIG. 10B, a cross-sectional view of the chamber 1000 according to an additional embodiment is shown. In the illustration of FIG. 10B, the insulating layer 1015 and the susceptor 1030 are omitted to more clearly view the structure of the bottom plate 1010. As shown, the bottom plate 1010 may include a plurality of channels 1011 that provide fluid routing from the center of the bottom plate 1010 to the edge of the bottom plate 1010. In the illustrated embodiment, a plurality of first channels connect the center of the bottom plate 1010 to a first annular channel, and a plurality of second channels connect the first annular channel to the outer edge of the bottom plate 1010. In one embodiment, the first channels and the second channels are offset from each other. Although the specific configuration of the channels 1011 is as shown in FIG. 10B, it should be understood that any channel configuration can be used to route the inert gas from the center of the bottom plate 1010 to the edge of the bottom plate 1010. FIG. 11 shows a schematic diagram of a machine in the exemplary form of a computer system 1100, where a set of instructions can be executed to cause the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, or the Internet. The machine can operate as a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein. The exemplary computer system 1100 includes a processor 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and secondary memory 1118 (e.g., a data storage device), which communicate with each other via a bus 1130. Processor 1102 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, processor 1102 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processor 1102 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processor 1102 is configured to execute processing logic 1126 to perform the operations described herein. Computer system 1100 may also include a network interface device 1108. Computer system 1100 may also include a video display unit 1110 (such as a liquid crystal display (LCD), a light emitting diode (LED) display, or a cathode ray tube (CRT)), an alphanumeric input device 1112 (such as a keyboard), a cursor control device 1114 (such as a mouse), and a signal generation device 1116 (such as a speaker). Secondary memory 1118 may include machine-accessible storage media (more specifically, computer-readable storage media) 1132, on which one or more sets of instructions (such as software 1122) are stored, which instructions embody any one or more of the methods or functions described herein. During execution of computer system 1100, software 1122 may also reside, completely or at least partially, within main memory 1104 and / or processor 1102, which also constitute machine-readable storage media. Software 1122 may also be sent or received via network interface device 1108 over network 1120. Although the machine-accessible storage medium 1132 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated cache memories and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of this disclosure. Thus, the term "machine-readable storage medium" should include, but is not limited to, solid-state memories as well as optical and magnetic media. In accordance with one embodiment of the present disclosure, instructions are stored on a machine-accessible storage medium that cause a data processing system to perform a method of dry developing a positive or negative metal oxide photoresist layer. A method of dry developing a positive or negative photoresist is hereby disclosed. 100: Wafer 102: Substrate or lower layer 102A: Patterned substrate or patterned lower layer 103A: Irradiated photoresist layer 104: Positive photoresist 104A: Irradiated photoresist layer 105A: Non-irradiated area 105B: Irradiated area 106: Irradiation 108: Removal or etching process 110: Etching process 112: Etching feature 200: Schematic diagram 210: Schematic diagram 220: Schematic diagram 300: Schematic diagram 400: Method 402: Substrate 404: Bottom layer 406: Metal oxide photoresist 406A: Metal oxide photoresist 408: Extreme ultraviolet (EUV) exposure 410: Exposure area 412: Non-exposed area 414: Dry etching process based on electron donor ligands 502: Substrate 504: Bottom layer 506: Metal oxide photoresist 506A: Exposed metal oxide photoresist 506B: Exposed and fluorinated metal oxide photoresist 508: Extreme ultraviolet (EUV) exposure technique 510: Exposure area 512: Non-exposed area 512A: Fluorinated non-exposed area 514: Fluorination process 516: Dry etching process based on electron donor ligands 600: Vacuum chamber 605: Chamber 610: Substrate 615: Opening 620: Temperature-controlled chuck 625: Bias power RF generator 626: Third bias power RF generator 627: RF matching 630: Source power RF generator 635: Gas distribution plate 644: Gas source 649: Mass flow controller 655: Gas distribution plate 670: Controller 672: CPU 673: Memory 674: I / O interface 700: Processing tool 701: Wafer 705: Chamber 710: Bottom plate 714: Post insulation layer 715: Insulation layer 720: Edge ring 730: Base 731: Cooling channel 735: Shadow ring 740: Process 745: Filter circuit system 750: Matching circuit system 799: Ampoule 801: Wafer 810: Bottom plate 811: Channel 812: Fluid path 815: Insulation layer 817: Seal 820: Edge ring 821: Notch 830A: First part 830B: Second part 831: Cooling channel 835: Shadow ring 836: Protrusion 860: Post 901: Wafer 910: Bottom plate 911: Channel 915: Insulation layer 917: Seal 920: Edge ring 921: Notch 930A: First part 930B: Second part 931: Cooling channel 935: Shadow ring 936: Protrusion 960: Movable post 970: Chamber liner 971: Bracket 1000: Processing tool 1001: Wafer 1010: Substrate 1011: Channel 1013: Fastening mechanism 1014: Post 1017: Insulation layer 1020: Edge ring 1030A: First part 1030B: Second part1031: Cooling liquid channel 1035: Shadow ring 1070: Chamber 1071: Bracket 1100: Computer system 1102: Processor 1104: Main memory 1106: Static memory 1108: Network interface device 1110: Video display unit 1112: Alphanumeric input device 1114: Cursor control device 1116: Signal generation device 1118: Secondary memory 1120: Network 1122: Software 1126: Processing logic 1130: Bus 1132: Machine-accessible storage medium W: Wall Figure 1A shows several cross-sectional views representing various operations in a patterning process using a positive photoresist material formed by the process described herein, according to an embodiment of the present disclosure. Figure 1B shows several cross-sectional views representing various operations in a patterning process using a negative photoresist material formed by the process described herein, according to an embodiment of the present disclosure. Figures 2A - 2C show possible volatile Sn-based compounds resulting from performing a dry development process on a Sn-based photoresist, according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of ligands according to an embodiment of the present disclosure, which are non-limiting examples of stable ligands having reasonable boiling points and can be transported in the gas phase as reactants to remove the more reactive SnOC species in a tin oxide-based photoresist film. Figure 4 shows several cross-sectional views representing various operations in a method of patterning a photoresist layer, according to an embodiment of the present disclosure. Figure 5 shows several cross-sectional views representing various operations in a method of patterning a photoresist layer, according to another embodiment of the present disclosure. Figure 6 is a cross-sectional view of a processing tool that can be used to implement the dry development process described herein, according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view of a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate through a dry development process, according to an embodiment of the present disclosure. Figure 8 is an enlarged view of the edge of a movable column of a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate through a dry development process, according to an embodiment of the present disclosure. Figure 9A is an enlarged view of the edge of a movable column of a processing tool, where the shadow ring is not engaged with the edge ring, according to an embodiment of the present disclosure. Figure 9B is an enlarged view of the edge of a movable column of a processing tool, where the shadow ring is engaged with the edge ring, according to an embodiment of the present disclosure. FIG. 10A is a cross-sectional view of a processing tool for depositing a positive or negative metal oxide photoresist layer on a substrate through a dry development process according to an embodiment of the present disclosure. FIG. 10B is a cross-sectional view of a processing tool for removing a pedestal to expose a channel in a bottom plate according to an embodiment of the present disclosure. FIG. 11 shows a block diagram of an exemplary computer system according to an embodiment of the present disclosure. Domestic deposit information (please note in the order of depository institution, date, number) None Foreign deposit information (please note in the order of depositing country, institution, date, number) None 100: Wafer 102: Substrate or lower layer 102A: Patterned substrate or patterned lower layer 103A: Irradiated photoresist layer 104: Positive photoresist 104A: Irradiated photoresist layer 105A: Non-irradiated area 105B: Irradiated area 106: Irradiation 108: Removal or etching process 110: Etching process 112: Etching feature

Claims

1. A method for patterning a metal oxide photoresist, comprising the steps of: depositing the metal oxide photoresist on a substrate; exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure to form exposed areas and unexposed areas; and developing the exposed metal oxide photoresist using an electron donor ligand-based dry etching process, wherein the electron donor ligand-based dry etching process includes using at least one NH4X as an etchant, where X is a halogen.

2. The method of claim 1, wherein the step of developing the exposed metal oxide photoresist further comprises the step of performing a wet development process prior to performing the electron donor ligand-based dry etching process.

3. The method of claim 1, wherein the step of developing the exposed metal oxide photoresist does not include the step of using a wet development process and the electron donor ligand-based dry etching process together.

4. The method of claim 1, wherein the metal oxide photoresist is a positive photoresist or a negative photoresist.

5. The method of claim 1, wherein the step of developing the exposed metal oxide photoresist includes the step of removing the unexposed area.

6. The method of claim 1, wherein the step of developing the exposed metal oxide photoresist includes the step of removing the exposed area.

7. A method for patterning a metal oxide photoresist, comprising the steps of: depositing the metal oxide photoresist on a substrate; exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure to form exposed and unexposed areas; treating the exposed metal oxide photoresist using a fluorination process; and developing the exposed and fluorinated metal oxide photoresist using an electron donor ligand-based dry etching process, wherein the electron donor ligand-based dry etching process includes using at least one NH4X as an etchant, where X is a halogen.

8. The method of claim 7, wherein the step of developing the exposed and fluorinated metal oxide photoresist further comprises the step of performing a wet development process prior to performing the electron donor ligand-based dry etching process.

9. The method of claim 7, wherein the step of developing the exposed and fluorinated metal oxide photoresist does not include the step of using a wet development process and the electron donor ligand-based dry etching process together.

10. The method of claim 7, wherein the metal oxide photoresist is a positive photoresist or a negative photoresist.

11. The method of claim 7, wherein the step of developing the exposed and fluorinated metal oxide photoresist includes the step of removing the unexposed area.

12. The method of claim 7, wherein the step of developing the exposed and fluorinated metal oxide photoresist includes the step of removing the exposed area.

13. A method for patterning a metal oxide photoresist, comprising the steps of: depositing the metal oxide photoresist on a substrate; exposing the metal oxide photoresist using extreme ultraviolet (EUV) exposure to form exposed and unexposed areas; and developing the exposed metal oxide photoresist by cyclically (1) processing it using a fluorination process and (2) developing it using an electron donor ligand-based dry etching process, wherein the electron donor ligand-based dry etching process includes using at least one NH4X as an etchant, where X is a halogen.

14. The method of claim 13, wherein the step of developing the exposed metal oxide photoresist does not include the step of using a wet development process.

15. The method of claim 13, wherein the metal oxide photoresist is a positive photoresist or a negative photoresist.

16. The method of claim 13, wherein the step of developing the exposed metal oxide photoresist includes the step of removing the unexposed area.

17. The method of claim 13, wherein the step of developing the exposed metal oxide photoresist includes the step of removing the exposed area.

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