Chip package structure and method for forming the same

Abstract

A wafer package structure is provided. The wafer package structure includes a carrier substrate. The wafer package structure includes a wafer structure above the carrier substrate. The wafer structure includes a semiconductor substrate and a device layer. The semiconductor substrate has a front surface and a rear surface opposite to the front surface, the front surface facing the carrier substrate, and the device layer is located between the front surface and the carrier substrate. The wafer package structure includes a heat sink above the rear surface of the semiconductor substrate. The heat sink has a flat portion and a first protrusion below the flat portion, and the first protrusion extends from the rear surface into the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure and a forming method thereof, and in particular to a chip packaging structure with a lid and a forming method thereof. Prior Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of ICs. Each generation's circuits are smaller and more complex than the previous one. However, these advances have increased the complexity of IC processes and manufacturing.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or circuit) that can be created using a manufacturing process) has decreased. This scaling down of processes generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the Invention

[0004] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure above the carrier substrate. The chip structure includes a semiconductor substrate and a device layer. The semiconductor substrate has a front surface and a back surface opposite the front surface. The front surface faces the carrier substrate, and the device layer is interposed between the front surface and the carrier substrate. The chip packaging structure includes a heat dissipation cover above the back surface of the semiconductor substrate. The heat dissipation cover has a flat plate portion and a first protrusion below the flat plate portion. The first protrusion extends from the back surface into the semiconductor substrate.

[0005] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure on the carrier substrate. The chip structure includes a substrate and a device layer arranged along a front surface of the substrate facing the carrier substrate, the substrate having sidewalls forming a recess along a rear surface of the substrate opposite the front surface. The chip packaging structure includes a thermally conductive layer disposed between the sidewalls of the substrate. The first thermal conductivity of the thermally conductive layer is greater than the second thermal conductivity of the substrate. The chip packaging structure includes a heat dissipation cover on the rear surface of the substrate and above the thermally conductive layer. The heat dissipation cover includes a protrusion extending outward from a lower surface of the heat dissipation cover toward the thermally conductive layer.

[0006] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes forming a chip structure having a device layer arranged along the front surface of a substrate, the device layer having a hot spot region; etching the rear surface of the substrate to form a recess above the hot spot region; and bonding the front surface of the chip structure to a carrier substrate. The method also includes bonding a heat dissipation cover to the rear surface of the substrate. The heat dissipation cover has a flat plate portion and a protruding portion below the flat plate portion. The flat plate portion is above the rear surface of the substrate, and the protruding portion is within the recess on the rear surface of the substrate. Simple diagram description

[0007] The aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practices, various components are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity of illustration. 1A through 1D are cross-sectional views illustrating various stages of a process for forming a chip package structure according to some embodiments. FIG. 1A-1 is an enlarged cross-sectional view showing a portion of the wafer structure of FIG. 1A according to some embodiments. 1A-2 are top views of the wafer structure of FIG. 1A according to some embodiments. FIG. 1B-1 is an enlarged cross-sectional view showing a portion of the chip package structure of FIG. 1B according to some embodiments. FIG. 1B-2 is a top view of the chip package structure of FIG. 1B according to some embodiments. FIG. 1C-1 is a top view of the chip package structure of FIG. 1C according to some embodiments. FIG. 1D-1 is a top view of the chip package structure of FIG. 1D according to some embodiments. FIG. 2A is a cross-sectional view of a chip package structure according to some embodiments. FIG. 2B is a top view of the chip package structure of FIG. 2A according to some embodiments. FIG. 3A is a cross-sectional view of a chip package structure according to some embodiments. FIG. 3B is a top view of the chip package structure of FIG. 3A according to some embodiments. FIG. 4A is a cross-sectional view of a chip package structure according to some embodiments. FIG. 4B is a top view of the chip package structure of FIG. 4A according to some embodiments. 5A and 5B are cross-sectional views illustrating various stages of a process for forming a chip package structure according to some embodiments. 6A and 6B are cross-sectional views illustrating various stages of a process for forming a chip package structure according to some embodiments. FIG. 6A-1 is a top view of the chip package structure of FIG. 6A according to some embodiments. FIG. 6B-1 is a top view of the chip package structure of FIG. 6B according to some embodiments. Implementation Method

[0008] The following disclosure provides many different embodiments or examples for implementing various components of the subject matter of the invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these specific examples are merely examples and are not intended to be limiting. For example, if the disclosure describes forming a first component over or on a second component, this may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which other components are formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, the disclosure may repeat reference numerals and / or characters throughout the various examples. This repetition does not in itself limit the relationship between the various embodiments and / or configurations discussed, but is provided for the purpose of simplicity and clarity.

[0009] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0010] Those skilled in the art will understand that the term "substantially" in this specification, such as "substantially flat" or "substantially coplanar," can be used to define the same. In some embodiments, the adjective "substantially" can be removed. Where applicable, the term "substantially" can also include embodiments with "entirely," "completely," "all," and the like. The term "substantially" can vary across different technologies and is within the range of deviations understood by those skilled in the art. For example, the term "substantially" can also refer to a specific 90% or higher, such as a specific 95% or higher, particularly a specific 99% or higher, including a specific 100%, but the present disclosure is not limited thereto. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from the specific alignment and can include, for example, deviations of up to 10°. The word “substantially” does not exclude “completely”, for example a composition “substantially free” of Y may be completely free of Y.

[0011] The term "approximately" can vary across technologies and is within the range of deviations understood by those of ordinary skill in the art. The term "approximately" in conjunction with a specific distance or dimension should be interpreted as not excluding minor deviations from the specific distance or dimension. For example, the term "approximately" may include deviations of up to 10% of the specified value, but the disclosure is not limited thereto. The term "approximately" in relation to a value x may mean x ± 5 or 10% of the specified value, but the disclosure is not limited thereto.

[0012] Some embodiments of the present disclosure have been described. Other operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Other components may be added to the chip packaging structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed in terms of operations performed in a specific order, these operations may be performed in another logical order.

[0013] As the size of components within integrated circuits (ICs) (e.g., transistors, interconnects, etc.) continues to decrease, ICs generate more heat. IC manufacturers have developed solutions to help dissipate this heat. Existing solutions typically focus on uniform heat dissipation (e.g., substantially homogeneous heat dissipation across the chip). However, it is recognized that different devices within an IC may generate different amounts of heat. For example, high-performance computing (HPC) products may generate more heat than other devices within the IC. This uneven heat generation within an IC can lead to the formation of local hot spots. If heat cannot be effectively dissipated from these local hot spots, it can lead to performance degradation, reliability issues, and even chip failure.

[0014] The present disclosure relates to a chip packaging structure configured to improve heat dissipation from a localized hotspot on an integrated chip (e.g., an area of the chip containing a high-performance computing product). In some embodiments, the chip packaging structure includes a chip structure disposed above a carrier substrate. The chip structure includes a semiconductor substrate having a front surface and a rear surface opposite the front surface. The front surface faces the carrier substrate. A device layer is located between the front surface and the carrier substrate. A heat dissipation cover is disposed along the rear surface of the semiconductor substrate. The heat dissipation cover includes a flat plate portion and a protrusion extending outward from the flat plate portion. The protrusion extends from the rear surface into the semiconductor substrate and toward a localized hotspot within the device layer. Because the protrusion is in close proximity to the localized hotspot, the protrusion can improve heat dissipation from the localized hotspot.

[0015] Figures 1A through 1D are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments. As shown in Figure 1A , according to some embodiments, a chip structure 110 is provided. According to some embodiments, chip structure 110 includes a semiconductor substrate 111, a device layer 112, a thermally conductive plug 113, and a conductive pillar 114.

[0016] According to some embodiments, a semiconductor substrate 111 has a front surface 111a and a rear surface 111b opposite the front surface 111a. According to some embodiments, a device layer 112 is formed above the front surface 111a. According to some embodiments, a thermally conductive plug 113 is formed in the semiconductor substrate 111. According to some embodiments, a conductive pillar 114 is formed above the device layer 112.

[0017] The semiconductor substrate 111 includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the semiconductor substrate 111 is formed of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0018] In some other embodiments, the semiconductor substrate 111 is formed of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination thereof. The semiconductor substrate 111 may further include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0019] In some embodiments, the device layer 112 includes various device elements and interconnect structures (not shown). Examples of the various device elements include active elements, passive elements, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on the front surface 111a of the semiconductor substrate 111. According to some embodiments, passive elements include resistors, capacitors, or other suitable devices.

[0020] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel field effect transistors (PFETs), and / or n-channel field effect transistors (NFETs). In various embodiments, the MOSFETs may include planar field effect transistors (PFETs), fin field effect transistors (FinFETs), gate-all-around transistors (e.g., nanowire transistors), and / or the like.

[0021] Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form various device elements. FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0022] In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 111. The isolation features are used to surround the active region and electrically isolate various device elements formed in and / or above the semiconductor substrate 111 in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0023] According to some embodiments, the device layer 112 has a hotspot region 10. According to some embodiments, the device components in the hotspot region 10 include, for example, high-performance computing (HPC) components or other components that tend to generate more heat.

[0024] According to some embodiments, when device elements of device layer 112 operate, the temperature of device layer 112 in hot spot region 10 is higher than the temperature of device layer 112 in other regions.

[0025] According to some embodiments, in some embodiments, the interconnect structure of device layer 112 includes a dielectric layer, a wiring layer, conductive vias, and a conductive pad. According to some embodiments, the wiring layer, the conductive vias, and the conductive pads are located in the dielectric layer. According to some embodiments, the conductive vias electrically connect between wiring layers, between wiring layers and conductive pads, and between wiring layers and device components.

[0026] According to some embodiments, the dielectric layer is formed of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or an oxide derived from tetraethyl orthosilicate (TEOS)), an oxynitride-containing material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0027] Alternatively, according to some embodiments, the dielectric layer includes a low-k (low dielectric constant) material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0028] The dielectric layer is formed using a chemical vapor deposition (CVD) process such as a low-pressure CVD process, a plasma-enhanced CVD process, or a high-density plasma CVD process, an atomic layer deposition (ALD) process, a spin-on process, a physical vapor deposition (PVD) process, or other suitable processes.

[0029] According to some embodiments, the wiring layers, conductive vias, and conductive pads are formed of a conductive material, such as a metal (eg, copper, aluminum, or tungsten) or an alloy thereof.

[0030] According to some embodiments, FIG. 1A-1 is an enlarged cross-sectional view showing a portion 20 of the wafer structure 110 of FIG. According to some embodiments, as shown in FIG. 1A and FIG. 1A-1 , the thermal plug 113 does not pass through the semiconductor substrate 111 .

[0031] According to some embodiments, a portion 111P of the semiconductor substrate 111 is located between the thermal plug 113 and the device layer 112. According to some embodiments, the thermal conductivity of the thermal plug 113 is greater than the thermal conductivity of the semiconductor substrate 111.

[0032] According to some embodiments, each thermal plug 113 includes an insulating layer 113a and a conductive pillar 113b. According to some embodiments, the insulating layer 113a surrounds the conductive pillar 113b. According to some embodiments, the insulating layer 113a separates the conductive pillar 113b from the semiconductor substrate 111.

[0033] According to some embodiments, the conductive pillar 113b is electrically insulated from the semiconductor substrate 111. According to some embodiments, the insulating layer 113a separates the conductive pillar 113b from the device layer 112. According to some embodiments, the conductive pillar 113b is electrically insulated from the device layer 112.

[0034] According to some embodiments, the insulating layer 113a is formed of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or an oxide derived from tetraethoxysilane (TEOS)), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0035] Alternatively, according to some embodiments, the insulating layer 113a includes a low-k dielectric material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. According to some embodiments, the conductive pillars 113b are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0036] According to some embodiments, forming the thermal plug 113 includes: partially removing the semiconductor substrate 111 to form a hole 111t in the semiconductor substrate 111; depositing an insulating material layer (not shown) on the rear surface 111b of the semiconductor substrate 111 and in the hole 111t; forming a conductive layer (not shown) over the insulating material layer and in the hole 111t; and removing the conductive layer and the insulating material layer outside the hole 111t.

[0037] According to some embodiments, as shown in FIG. 1A-1 , the insulating material layer remaining in the hole 111 t forms the insulating layer 113 a of the thermal plug 113 . According to some embodiments, the conductive layer remaining in the hole 111 t forms the conductive pillar 113 b of the thermal plug 113 .

[0038] The insulating material layer is formed using a chemical vapor deposition (CVD) process such as a low pressure CVD process, a plasma-assisted CVD process, or a high density plasma CVD process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes.

[0039] According to some embodiments, a plating process such as an electroplating process or a deposition process such as a physical vapor deposition process is used.

[0040] According to some embodiments, FIG. 1A-2 is a top view of the chip structure 110 of FIG. According to some embodiments, FIG. 1A is a cross-sectional view of the chip package structure taken along section line II' in FIG. 1A-2. According to some embodiments, as shown in FIG. 1A, FIG. 1A-1, and FIG. 1A-2, the thermal plugs 113 are arranged in an array (e.g., arranged in rows and columns with substantially equal spacing). In some other embodiments (not shown), the thermal plugs 113 are randomly arranged (e.g., spaced at unequal distances from each other).

[0041] According to some embodiments, as shown in FIG. 1A , conductive pillars 114 are formed above conductive pads of device layer 112. According to some embodiments, conductive pillars 114 are electrically connected to the conductive pads. According to some embodiments, conductive pillars 114 are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0042] According to some embodiments, FIG. 1B-1 is an enlarged cross-sectional view of a portion 20 of the chip structure 110 of FIG. 1B . According to some embodiments, FIG. 1B-2 is a top view of the chip package structure of FIG. 1B . According to some embodiments, FIG. 1B is a cross-sectional view of the chip package structure taken along section line II' in FIG. 1B-2 .

[0043] According to some embodiments, as shown in FIG. 1B , FIG. 1B-1 , and FIG. 1B-2 , the upper portion of semiconductor substrate 111 and thermal plugs 113 are removed to form recesses 111 c in semiconductor substrate 111. Recesses 111 c are formed by the sidewalls and horizontally extending surface of the semiconductor substrate. According to some embodiments, recesses 111 c expose the top surface 113 t of each thermal plug 113. According to some embodiments, thermal plugs 113 are located below recesses 111 c.

[0044] According to some embodiments, as shown in FIG. 1B and FIG. 1B-2 , after the removal process, semiconductor substrate 111 has a thick portion 111 k and a thin portion 111 n. According to some embodiments, thin portion 111 n is located below recess 111 c. According to some embodiments, thin portion 111 n is thinner than thick portion 111 k.

[0045] According to some embodiments, the thick portion 111k continuously surrounds the thin portion 111n. According to some embodiments, the thermal plug 113 penetrates the thin portion 111n. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0046] According to some embodiments, as shown in FIG. 1B , solder bumps 130 are formed on conductive pillars 114. According to some embodiments, solder bumps 130 are formed of tin (Sn) or another suitable conductive material having a melting point lower than that of conductive pillars 114. According to some embodiments, solder bumps 130 are formed using a plating process such as an electroplating process.

[0047] According to some embodiments, as shown in FIG. 1B , the chip structure 110 is bonded to a carrier substrate 120 (e.g., a wiring substrate) via solder bumps 130. According to some embodiments, the front surface 111 a of the semiconductor substrate 111 faces the carrier substrate 120. According to some embodiments, the device layer 112 is between the front surface 111 a and the carrier substrate 120.

[0048] According to some embodiments, the carrier substrate 120 includes a dielectric layer, a conductive pad, a wiring layer, and conductive vias (not shown). According to some embodiments, the conductive pad is embedded in the dielectric layer. According to some embodiments, the solder bump 130 is bonded to the conductive pad of the carrier substrate 120.

[0049] According to some embodiments, the wiring layers and the conductive vias of the carrier substrate 120 are formed in the dielectric layer of the carrier substrate 120. According to some embodiments, the conductive vias electrically connect between different wiring layers and between the wiring layers and the conductive pads.

[0050] According to some embodiments, the dielectric layer is formed of an insulating material, such as a polymer material (e.g., polybenzoxazole or polyimide), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, or the like. According to some embodiments, the dielectric layer is formed using a lamination process (or deposition process), a photolithography process, and an etching process.

[0051] According to some embodiments, the conductive pad is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the wiring layer is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the conductive via is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0052] In some embodiments, the conductive pads, wiring layers, and conductive vias are formed of the same material. In some other embodiments, the conductive pads, wiring layers, and conductive vias are formed of different materials.

[0053] According to some embodiments, as shown in FIG. 1B , an underfill layer UF is formed between the wafer structure 110 and the carrier substrate 120. According to some embodiments, the underfill layer UF surrounds the solder bumps 130 and the conductive pillars 114. According to some embodiments, the underfill layer UF is formed of an insulating material such as a polymer material.

[0054] According to some embodiments, FIG. 1C-1 is a top view of the chip package structure of FIG. According to some embodiments, FIG. 1C is a cross-sectional view of the chip package structure taken along section line II' in FIG. According to some embodiments, as shown in FIG. 1C and FIG. 1C-1, an adhesive layer 140 is formed over the carrier substrate 120. According to some embodiments, the adhesive layer 140 has an opening 142. According to some embodiments, the chip structure 110 is located in the opening 142.

[0055] According to some embodiments, the adhesive layer 140 is formed of a polymer material such as epoxy or silicone. According to some embodiments, the adhesive layer 140 is formed using a dispensing process.

[0056] According to some embodiments, as shown in FIG. 1C and FIG. 1C-1 , a ring structure 150 is disposed above the adhesive layer 140 . According to some embodiments, the ring structure 150 has a top surface 151 . In some embodiments, the top surface 151 is higher than the back surface 111 b of the semiconductor substrate 111 . In some embodiments, the top surface 151 is substantially flush with the back surface 111 b of the semiconductor substrate 111 . In some embodiments, the top surface 151 is lower than the back surface 111 b of the semiconductor substrate 111 .

[0057] According to some embodiments, the ring structure 150 has an opening 152 located above the opening 142 of the adhesive layer 140. According to some embodiments, the wafer structure 110 is located in the opening 152.

[0058] According to some embodiments, the ring structure 150 is formed of a rigid material, such as a metal (eg, copper or iron), an alloy thereof (eg, stainless steel), or another suitable material that is more rigid than the carrier substrate 120 .

[0059] According to some embodiments, as shown in FIG. 1C and FIG. 1C-1 , an adhesive layer 160 is formed on the annular structure 150 , and a thermal conductive layer 170 is formed on the rear surface 111 b of the semiconductor substrate 111 .

[0060] According to some embodiments, the adhesive layer 160 is formed of a combination of a polymer and a metal (e.g., silver paste) or a polymer (e.g., epoxy or silicone). According to some embodiments, the adhesive layer 160 is formed using a dispensing process.

[0061] According to some embodiments, the thermal conductivity of thermal conductive layer 170 is greater than the thermal conductivity of semiconductor substrate 111. According to some embodiments, thermal conductive layer 170 is formed from a polymer material including silicone or epoxy. According to some embodiments, the polymer material is doped with particles formed from aluminum oxide or zinc oxide. According to some embodiments, thermal conductive layer 170 is formed using a dispensing process.

[0062] According to some embodiments, as shown in FIG. 1C and FIG. 1C-1 , a thermally conductive layer 180 is formed in the recess 111 c of the semiconductor substrate 111 . According to some embodiments, the thermally conductive layer 180 is in thermal contact with the semiconductor substrate 111 and the thermally conductive plug 113 . According to some embodiments, the thermally conductive layer 180 is in direct contact with the semiconductor substrate 111 and the thermally conductive plug 113 .

[0063] According to some embodiments, the thermal conductivity of the heat-conducting layer 180 is greater than the thermal conductivity of the semiconductor substrate 111. According to some embodiments, the thermal conductivity of the heat-conducting layer 180 is greater than the thermal conductivity of the heat-conducting layer 170.

[0064] As a result, according to some embodiments, the heat conducting layer 180 can quickly conduct the heat generated by the hot spot area 10 to the heat dissipation cover, and then the heat dissipation cover is bonded to the heat conducting layers 170 and 180 .

[0065] According to some embodiments, the adhesion of the thermal conductive layer 170 to the semiconductor substrate 111 and the heat dissipation cover subsequently bonded to the thermal conductive layers 170 and 180 is greater than the adhesion of the thermal conductive layer 180. As a result, according to some embodiments, the thermal conductive layer 170 can securely fix the heat dissipation cover above the semiconductor substrate 111.

[0066] According to some embodiments, thermally conductive layer 180 has a top surface 182. According to some embodiments, top surface 182 faces away from carrier substrate 120. According to some embodiments, top surface 182 is lower than rear surface 111b of semiconductor substrate 111. In other embodiments, top surface 182 may be substantially coplanar with rear surface 111b or located above rear surface 111b. In some such embodiments, thermally conductive layer 180 laterally contacts both semiconductor substrate 111 and thermally conductive layer 170.

[0067] According to some embodiments, thermally conductive layers 170 and 180 are formed of different materials. In some embodiments, thermally conductive layer 180 is formed of a solid material. In other embodiments, thermally conductive layer 180 is formed of a liquid material at room temperature (e.g., between approximately 70 degrees Fahrenheit and approximately 100 degrees Fahrenheit). Because thermally conductive layer 180 is disposed within a recess capable of accommodating a liquid material, thermally conductive layer 180 can be a liquid material.

[0068] According to some embodiments, the solid material includes tin (Sn), indium (In), bismuth (Bi), or alloys thereof. According to some embodiments, the liquid material includes gallium (Ga), alloys thereof, or a resin material containing gallium (Ga) or alloys thereof.

[0069] According to some embodiments, if thermally conductive layer 180 is formed of a solid material, a metal sheet is placed in recess 111c to form thermally conductive layer 180. According to some embodiments, the metal sheet may be slightly narrower than recess 111c. According to some embodiments, if thermally conductive layer 180 is formed of a liquid material, a dispensing process is used to form thermally conductive layer 180.

[0070] According to some embodiments, FIG. 1D-1 is a top view of the chip package structure of FIG. According to some embodiments, FIG. 1D is a cross-sectional view of the chip package structure along section line II' in FIG. According to some embodiments, as shown in FIG. 1D and FIG. 1D-1, heat dissipation cover 190 is bonded to ring structure 150 and semiconductor substrate 111 via adhesive layer 160, thermal conductive layer 170, and thermal conductive layer 180. In this step, according to some embodiments, chip package structure 100 is substantially formed.

[0071] According to some embodiments, the heat dissipation cover 190 has a flat plate portion 192 and a protrusion 194. According to some embodiments, the protrusion 194 protrudes outward from the lower surface of the flat plate portion 192 to below the flat plate portion 192. According to some embodiments, the flat plate portion 192 is located above the rear surface 111b of the semiconductor substrate 111.

[0072] According to some embodiments, the flat plate portion 192 is located above the heat conducting layer 170. According to some embodiments, the heat conducting layer 170 is located between the semiconductor substrate 111 and the flat plate portion 192 of the heat dissipation cover 190.

[0073] According to some embodiments, protrusion 194 passes through heat conductive layer 170. According to some embodiments, thickness T194 of protrusion 194 is greater than thickness T170 of heat conductive layer 170. According to some embodiments, protrusion 194 extends from rear surface 111 b into semiconductor substrate 111.

[0074] According to some embodiments, protrusion 194 is partially located in recess 111 c of semiconductor substrate 111. According to some embodiments, protrusion 194 contacts the sidewalls of thermally conductive layer 170 and the inner wall s1 of recess 111 c of semiconductor substrate 111. According to some embodiments, if thermally conductive layer 180 is formed of a liquid material, protrusion 194 can seal thermally conductive layer 180 in recess 111 c.

[0075] According to some embodiments, protrusion 194 is located above thermally conductive layer 180. According to some embodiments, protrusion 194 is in thermal contact with thermally conductive layer 180. According to some embodiments, protrusion 194 is in direct contact with thermally conductive layer 180. According to some embodiments, a thickness T194 of protrusion 194 is greater than a thickness T180 of thermally conductive layer 180.

[0076] According to some embodiments, the thermal conductive layer 180 is between the semiconductor substrate 111 and the protrusion 194. According to some embodiments, the thickness T111n of the thin portion 111n of the semiconductor substrate 111 is greater than the thickness T180 of the thermal conductive layer 180. According to some embodiments, if the thickness T111n is less than the thickness T180, the thin portion 111n may be too thin and easily damaged.

[0077] According to some embodiments, the protrusion 194 is above the thin portion 111n of the semiconductor substrate 111. According to some embodiments, the thermally conductive layer 180 is between the thin portion 111n and the protrusion 194.

[0078] According to some embodiments, the thermal conductivity of the heat dissipation cover 190 is greater than the thermal conductivity of the semiconductor substrate 111. According to some embodiments, the thermal conductivity of the heat dissipation cover 190 is greater than the thermal conductivity of the heat conductive layer 180.

[0079] According to some embodiments, the thermal conductivity of heat dissipation cover 190 is greater than that of thermal conductive layer 170. According to some embodiments, heat dissipation cover 190 having high thermal conductivity has a protrusion 194 proximate to hot spot region 10 to quickly conduct heat generated by hot spot region 10. By quickly conducting heat generated by hot spot region 10, protrusion 194 of heat dissipation cover 190 can promote heat dissipation from hot spot region 10, thereby resolving uneven heat generation at specific locations within semiconductor substrate 111 (for example, in high-performance computing products).

[0080] The thermal conductivity of the thermally conductive layer 180 and the thermally conductive plug 113 is greater than that of the semiconductor substrate 111, and they are also located close to the hotspot region 10, thereby further enhancing heat dissipation in the hotspot region. Therefore, according to some embodiments, the protrusion 194, the thermally conductive layer 180, and the thermally conductive plug 113 can improve the heat dissipation efficiency of the chip package structure 100.

[0081] According to some embodiments, the heat dissipation cover 190 is formed of a high thermal conductivity material, such as a metal material (aluminum or copper), an alloy material (eg, stainless steel), or aluminum-silicon carbide (AlSiC).

[0082] According to some embodiments, the bonding process includes an annealing process. According to some embodiments, during the annealing process, adhesive layers 140 and 160 and thermally conductive layer 170 are cured. According to some embodiments, if thermally conductive layer 180 is formed of a solid material (e.g., a metal sheet), the solid material is reflowed during the annealing process to conform to the shape of recess 111 c. According to some embodiments, as shown in FIG. 1D-1 , protrusion 194 has a square shape.

[0083] According to some embodiments, FIG. 2A is a cross-sectional view of a chip package structure 200. According to some embodiments, FIG. 2B is a top view of the chip package structure 200 in FIG. 2A is a cross-sectional view of the chip package structure 200 taken along section line II' in FIG. 2B.

[0084] According to some embodiments, as shown in FIG. 2A and FIG. 2B , chip package structure 200 is similar to chip package structure 100 of FIG. 1D , except that heat dissipation cover 190 further includes protrusion 196 and chip package structure 200 further includes thermally conductive layer 210. According to some embodiments, device layer 112 further includes hot spot region 10A.

[0085] According to some embodiments, protrusion 196 is below flat plate portion 192. According to some embodiments, protrusion 196 is separate from protrusion 194. According to some embodiments, protrusion 196 is above hot spot area 10A.

[0086] According to some embodiments, the protrusion 196 passes through the heat conductive layer 170. According to some embodiments, the protrusion 196 extends from the rear surface 111b to the semiconductor substrate 111.

[0087] According to some embodiments, thermally conductive layer 210 is located in recess 111d of semiconductor substrate 111. According to some embodiments, protrusion 196 is partially located in recess 111d. According to some embodiments, protrusion 196 is in thermal contact with thermally conductive layer 210. According to some embodiments, protrusion 196 is in direct contact with thermally conductive layer 210. According to some embodiments, as shown in FIG. 2B , protrusion 196 has a square shape.

[0088] It should be understood that although FIG. 2A and FIG. 2B illustrate a semiconductor substrate 111 having two hotspot regions, the disclosed chip package structure is not limited to having two protrusions that enhance heat dissipation within the two hotspot regions. Rather, the disclosed chip package structure may have additional protrusions that enhance heat dissipation within additional hotspot regions.

[0089] According to some embodiments, FIG. 3A is a cross-sectional view of a chip package structure 300. According to some embodiments, FIG. 3B is a top view of the chip package structure 300 in FIG. 3A is a cross-sectional view of the chip package structure 300 taken along section line II' in FIG. 3B.

[0090] According to some embodiments, as shown in FIG3A and FIG3B , chip package structure 300 is similar to chip package structure 200 of FIG2A and FIG2B , except that protrusion 194 extends across hotspot regions 10 and 10A of device layer 112. According to some embodiments, as shown in FIG3B , protrusion 194 has a strip shape. In some embodiments (not shown), thermal vias 113 may be arranged in an array above hotspot regions 10 and 10A, separated by a distance greater than the spacing between thermal vias within the array.

[0091] According to some embodiments, FIG. 4A is a cross-sectional view of a chip package structure 400. According to some embodiments, FIG. 4B is a top view of the chip package structure 400 of FIG. According to some embodiments, FIG. 4A is a cross-sectional view of the chip package structure 400 taken along section line II' in FIG. 4B. According to some embodiments, as shown in FIG. 4A and FIG. 4B, the chip package structure 400 is similar to the chip package structure 200 of FIG. 2A and FIG. 2B, except that the protrusion 194 and the hot spot area 10 have an annular shape.

[0092] According to some embodiments, FIG. 5A and FIG. 5B are cross-sectional views of various stages of a process for forming a chip package structure 500. According to some embodiments, as shown in FIG. 5A , a chip structure 510 is provided. According to some embodiments, chip structure 510 includes a substrate 514, a device layer 515, a thermally conductive plug 113, and conductive pillars 516.

[0093] According to some embodiments, substrate 514 has a front surface 514a and a rear surface 514b opposite front surface 514a. According to some embodiments, device layer 515 is formed above front surface 514a. According to some embodiments, thermally conductive plug 113 is formed in substrate 514. According to some embodiments, conductive pillar 516 is formed above device layer 515.

[0094] According to some embodiments, the substrate 514 includes a lower semiconductor layer 511, an upper semiconductor layer 512, and a bonding layer 513. According to some embodiments, the bonding layer 513 is located between the lower semiconductor layer 511 and the upper semiconductor layer 512.

[0095] The lower semiconductor layer 511 or the upper semiconductor layer 512 includes, for example, a semiconductor wafer (e.g., a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the lower semiconductor layer 511 and the upper semiconductor layer 512 are formed of an elementary semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0096] In some other embodiments, the lower semiconductor layer 511 and the upper semiconductor layer 512 are formed of compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide; alloy semiconductors such as SiGe or GaAsP, or combinations thereof. According to some embodiments, the bonding layer 513 is formed of an oxide-containing material (e.g., silicon oxide).

[0097] According to some embodiments, forming the substrate 514 and the thermal plug 113 includes: providing a lower semiconductor layer 511 and a dielectric layer 513a (e.g., an oxide layer) above the lower semiconductor layer 511; providing an upper semiconductor layer 512 and a dielectric layer 513b (e.g., an oxide layer) above the upper semiconductor layer 512; bonding the upper semiconductor layer 512 to the lower semiconductor layer 511 via the dielectric layers 513b and 513a; forming the thermal plug 113 in the substrate 514; and partially removing the upper semiconductor layer 512, the bonding layer 513, and the thermal plug 113 in the upper semiconductor layer 512 and the bonding layer 513 to form a recess 111c in the substrate 514.

[0098] According to some embodiments, the dielectric layers 513a and 513b together form the bonding layer 513. According to some embodiments, the bonding process for bonding the dielectric layers 513a and 513b includes an oxide fusion bonding process.

[0099] In some embodiments, device layer 515 includes various device elements and interconnect structures (not shown). Examples of various device elements include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on front surface 514a of substrate 514. Passive devices may include resistors, capacitors, or other suitable passive devices.

[0100] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.

[0101] Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form various device elements. FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0102] In some embodiments, isolation features (not shown) are formed in the lower semiconductor layer 511. The isolation features are used to surround the active region and electrically isolate various device elements formed in and / or above the lower semiconductor layer 511 in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0103] According to some embodiments, device layer 515 has a hotspot region 10. According to some embodiments, device components in hotspot region 10 include, for example, high-performance computing (HPC) components or other components that tend to generate more heat.

[0104] According to some embodiments, when device elements of device layer 515 are operated, the temperature of device layer 515 in hot spot region 10 is higher than the temperature of device layer 515 in other regions.

[0105] According to some embodiments, in some embodiments, the interconnect structure of the device layer 515 includes a dielectric layer, a wiring layer, a conductive via, and a conductive pad. According to some embodiments, the wiring layer, the conductive via, and the conductive pad are located in the dielectric layer.

[0106] According to some embodiments, the conductive vias electrically connect between wiring layers, between wiring layers and conductive pads, and between wiring layers and device components.

[0107] According to some embodiments, the dielectric layer is formed of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or an oxide derived from tetraethoxysilane (TEOS)), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0108] Alternatively, according to some embodiments, the dielectric layer includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0109] The dielectric layer is formed using a chemical vapor deposition (CVD) process such as a low pressure CVD process, a plasma-assisted CVD process, or a high density plasma CVD process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable processes.

[0110] According to some embodiments, the wiring layers, conductive vias, and conductive pads are formed of a conductive material, such as a metal (eg, copper, aluminum, or tungsten) or an alloy thereof.

[0111] According to some embodiments, conductive pillars 516 are formed above the conductive pads of device layer 515. According to some embodiments, conductive pillars 516 are electrically connected to the conductive pads. According to some embodiments, conductive pillars 516 are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0112] According to some embodiments, as shown in FIG. 5B , steps 1B to 1D are performed to form carrier substrate 120, solder bumps 130, adhesive layer 140, ring structure 150, adhesive layer 160, thermally conductive layer 170, thermally conductive layer 180, and heat dissipation cover 190. According to some embodiments, during this step, chip package structure 500 is substantially formed.

[0113] According to some embodiments, thermal conductive layer 180 is formed in recess 111 c. According to some embodiments, thermal conductive layer 180 is in upper semiconductor layer 512 and passes through bonding layer 513. According to some embodiments, thermal conductive layer 180 is in thermal contact with lower semiconductor layer 511, upper semiconductor layer 512, and bonding layer 513. According to some embodiments, thermal conductive layer 180 is in direct contact with lower semiconductor layer 511, upper semiconductor layer 512, and bonding layer 513.

[0114] According to some embodiments, FIG. 6A and FIG. 6B are cross-sectional views of various stages of a process for forming a chip package structure. According to some embodiments, FIG. 6A-1 is a top view of the chip package structure of FIG. 6A. According to some embodiments, FIG. 6A is a cross-sectional view of the chip package structure taken along section line II' in FIG. 6A-1.

[0115] According to some embodiments, after the step of FIG. 1B , as shown in FIG. 6A and FIG. 6A-1 , an adhesive layer 160 is formed on the ring structure 150 , and an adhesive layer 610 is formed on the rear surface 111 b of the semiconductor substrate 111 .

[0116] According to some embodiments, the adhesive layer 610 has a ring shape. According to some embodiments, the adhesive layer 610 has an opening 612. According to some embodiments, the opening 612 exposes a portion of the back surface 111b of the semiconductor substrate 111.

[0117] According to some embodiments, the adhesive layer 610 is formed of a combination of a polymer and a metal (eg, silver paste) or a polymer (eg, epoxy or silicone). According to some embodiments, the adhesive layer 610 is formed using a dispensing process.

[0118] According to some embodiments, as shown in FIG6A and FIG6A-1, a heat conducting layer 620 is formed in the opening 612 of the adhesive layer 610 and above the rear surface 111b of the semiconductor substrate 111. According to some embodiments, the heat conducting layer 620 has a ring shape.

[0119] According to some embodiments, the heat conductive layer 620 has an opening 622 above the recess 111c of the semiconductor substrate 111. According to some embodiments, the heat conductive layer 620 is formed of graphite or a polymer material doped with carbon fillers.

[0120] According to some embodiments, as shown in FIG. 6A and FIG. 6A-1 , a thermal conductive layer 180 is formed in the recess 111 c of the semiconductor substrate 111 .

[0121] According to some embodiments, FIG. 6B-1 is a top view of the chip package structure of FIG. According to some embodiments, FIG. 6B is a cross-sectional view of the chip package structure along section line II' in FIG.

[0122] According to some embodiments, as shown in FIG. 6B and FIG. 6B-1 , heat dissipation cover 190 is bonded to ring structure 150 and semiconductor substrate 111 via adhesive layers 160 and 610, thermal conductive layer 620, and thermal conductive layer 180. According to some embodiments, in this step, chip package structure 600 is substantially formed.

[0123] According to some embodiments, the thermal conductivity of the heat conducting layer 620 is greater than the thermal conductivity of the adhesive layer 610. According to some embodiments, the adhesion of the adhesive layer 610 to the semiconductor substrate 111 and the heat dissipation cover 190 is greater than the adhesion of the heat conducting layer 620.

[0124] The processes and materials used to form chip package structures 200, 300, 400, 500, and 600 may be similar or identical to the processes and materials used to form chip package structure 100, as described above. Elements denoted by the same or similar reference numerals as those shown in FIG. 1A to FIG. 6B-1 have the same or similar structures and materials. Therefore, their detailed descriptions will not be repeated here.

[0125] According to some embodiments, a chip package structure and a method for forming the same are provided. The method forms a heat dissipation cover having a protrusion extending toward a hot spot region of a device layer. Because the protrusion is located near the hot spot region, it can quickly conduct heat generated by the hot spot region.

[0126] The method (for forming a chip package structure) further forms a thermally conductive layer within the substrate of the chip structure and below the protrusion, with the thermally conductive layer being close to the hotspot area. Therefore, the thermally conductive layer can quickly conduct heat generated in the hotspot area to the heat dissipation cover, thereby improving the heat dissipation efficiency of the chip package structure.

[0127] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure above the carrier substrate. The chip structure includes a semiconductor substrate and a device layer. The semiconductor substrate has a front surface and a back surface opposite the front surface. The front surface faces the carrier substrate, and the device layer is interposed between the front surface and the carrier substrate. The chip packaging structure includes a heat dissipation cover above the back surface of the semiconductor substrate. The heat dissipation cover has a flat plate portion and a first protrusion below the flat plate portion. The first protrusion extends from the back surface into the semiconductor substrate.

[0128] In some embodiments, the chip package structure further includes a first heat conductive layer interposed between the semiconductor substrate of the chip structure and the flat plate portion of the heat dissipation cover. In some embodiments, the first protrusion of the heat dissipation cover passes through the first heat conductive layer. In some embodiments, the chip package structure further includes a second heat conductive layer interposed between the semiconductor substrate of the chip structure and the first protrusion of the heat dissipation cover. In some embodiments, the semiconductor substrate of the chip structure has a thick portion and a thin portion, the thin portion being thinner than the thick portion, and the first protrusion of the heat dissipation cover is above the thin portion. In some embodiments, the thick portion surrounds the thin portion of the semiconductor substrate of the chip structure. In some embodiments, the chip package structure further includes a heat conductive layer interposed between the thin portion of the semiconductor substrate of the chip structure and the first protrusion of the heat dissipation cover. In some embodiments, the chip package structure further includes a heat conductive plug penetrating into the portion of the semiconductor substrate of the chip structure, wherein the heat conductive plug is electrically insulated from the device layer. In some embodiments, the thermal plug includes a conductive pillar and an insulating layer wrapped around the conductive pillar, wherein the insulating layer separates the conductive pillar from the device layer and the semiconductor substrate of the chip structure. In some embodiments, the chip package structure further includes a thermally conductive layer and an adhesive layer. The thermally conductive layer is interposed between the semiconductor substrate of the chip structure and the flat plate portion of the heat dissipation cover, and the adhesive layer surrounds the thermally conductive layer and is interposed between the semiconductor substrate of the chip structure and the flat plate portion of the heat dissipation cover. In some embodiments, the heat dissipation cover further includes a second protrusion, the second protrusion being below the flat plate portion and spaced apart from the first protrusion, and the second protrusion extending from the rear surface into the semiconductor substrate.

[0129] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a carrier substrate. The chip packaging structure includes a chip structure on the carrier substrate. The chip structure includes a substrate and a device layer arranged along a front surface of the substrate facing the carrier substrate, the substrate having sidewalls forming a recess along a rear surface of the substrate opposite the front surface. The chip packaging structure includes a thermally conductive layer disposed between the sidewalls of the substrate. The first thermal conductivity of the thermally conductive layer is greater than the second thermal conductivity of the substrate. The chip packaging structure includes a heat dissipation cover on the rear surface of the substrate and above the thermally conductive layer. The heat dissipation cover includes a protrusion extending outward from a lower surface of the heat dissipation cover toward the thermally conductive layer.

[0130] In some embodiments, the thermally conductive layer has a top surface facing away from the carrier substrate and is lower than the rear surface of the substrate of the wafer structure. In some embodiments, the substrate includes a lower semiconductor layer, an upper semiconductor layer, and a bonding layer interposed between the lower and upper semiconductor layers, and the thermally conductive layer is embedded in the upper semiconductor layer and passes through the bonding layer. In some embodiments, the thermally conductive layer contacts the lower semiconductor layer, the upper semiconductor layer, and the bonding layer.

[0131] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes forming a chip structure having a device layer arranged along the front surface of a substrate, the device layer having a hot spot region; etching the rear surface of the substrate to form a recess above the hot spot region; and bonding the front surface of the chip structure to a carrier substrate. The method also includes bonding a heat dissipation cover to the rear surface of the substrate. The heat dissipation cover has a flat plate portion and a protruding portion below the flat plate portion. The flat plate portion is above the rear surface of the substrate, and the protruding portion is within the recess on the rear surface of the substrate.

[0132] In some embodiments, the method further includes forming a first thermally conductive layer in a recessed portion of the rear surface of the substrate before bonding the heat dissipation cover to the rear surface of the substrate, wherein the protruding portion of the heat dissipation cover is above the first thermally conductive layer. In some embodiments, the method further includes forming a second thermally conductive layer above the rear surface of the substrate before bonding the heat dissipation cover to the rear surface of the substrate, wherein the flat portion of the heat dissipation cover is above the second thermally conductive layer. In some embodiments, the substrate of the wafer structure includes a lower semiconductor layer, an upper semiconductor layer, and a bonding layer between the lower and upper semiconductor layers, the first thermally conductive layer being in the upper semiconductor layer and passing through the bonding layer. In some embodiments, the wafer structure further includes a thermally conductive plug penetrating into a portion of the substrate below the recess, wherein the thermally conductive plug is electrically insulated from the device layer.

[0133] The foregoing disclosure summarizes the components of various embodiments to facilitate a better understanding of the present disclosure by those skilled in the art. Those skilled in the art will readily appreciate that they can readily design or modify other processes and structures based on this disclosure to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements may be made to the present disclosure without departing from the spirit and scope of this disclosure.

[0134] 10,10A: Hotspot 100, 200, 300, 400, 500, 600: Chip packaging structure 110,510: Chip structure 111:Semiconductor substrate 111a, 514a: front surface 111b, 514b: rear surface 111c,111d: concave part 111k:Thickness 111n: thin part 111P,20:Part 111t: Hole 112: Device layer 113: Thermal plug 113a: Insulation layer 113b: Conductive column 113b,114,516: conductive pillars 120: Carrier substrate 130:Solder bump 140,160,610: Adhesive layer 142,152,612,622: Opening 150: Ring structure 151,182: Top surface 170,180,210,620: thermal conductive layer 190: Radiator cover 192: Flat plate 194,196: protrusion 511: lower semiconductor layer 512: upper semiconductor layer 513: bonding layer 513a, 513b: dielectric layer 514:Substrate 515: Device layer I-I': hatching line s1: inner wall T111n, T170, T180, T194: thickness UF: bottom fill layer

Claims

1. A chip packaging structure, comprising: One substrate; A wafer structure is disposed above a carrier substrate, wherein the wafer structure includes a semiconductor substrate and a device layer, the semiconductor substrate having a front surface and a rear surface opposite to the front surface, the front surface facing the carrier substrate, and the device layer being disposed between the front surface and the carrier substrate, wherein the semiconductor substrate has a thick portion and a thin portion, the thin portion being thinner than the thick portion, and the thick portion surrounding the thin portion; a thermally conductive plug is inserted into the thin portion of the semiconductor substrate of the wafer structure, wherein the thermally conductive plug is electrically insulated from the device layer; and a heat sink is disposed above the rear surface of the semiconductor substrate, wherein the heat sink has a flat plate portion and a first protrusion below the flat plate portion, and the first protrusion extends from the rear surface into the semiconductor substrate, wherein the first protrusion is above the thin portion.

2. The wafer packaging structure as described in claim 1 further includes: A first thermally conductive layer is located between the semiconductor substrate of the wafer structure and the plate portion of the heat sink.

3. The wafer package structure as described in claim 2, wherein the first protrusion of the heat sink passes through the first thermally conductive layer.

4. The wafer packaging structure as described in claim 2 further includes: A second thermally conductive layer is located between the semiconductor substrate of the wafer structure and the first protrusion of the heat sink.

5. The wafer packaging structure as described in claim 1, further comprising: A thermally conductive layer is disposed between the thin portion of the semiconductor substrate of the wafer structure and the first protrusion of the heat sink.

6. The wafer package structure as claimed in claim 1, wherein the thermal plug includes a conductive post and an insulating layer surrounding the conductive post, and the insulating layer separates the conductive post from the device layer and the semiconductor substrate of the wafer structure.

7. The wafer package structure as described in claim 1, further comprising: A thermally conductive layer is disposed between the semiconductor substrate of the wafer structure and the plate portion of the heat sink. An adhesive layer surrounds the thermally conductive layer and is located between the semiconductor substrate of the wafer structure and the plate portion of the heat sink.

8. The wafer package structure as claimed in claim 1, wherein the heat sink further has a second protrusion below the flat portion and spaced apart from the first protrusion, and the second protrusion extends from the rear surface into the semiconductor substrate.

9. A chip packaging structure, comprising: One substrate; A wafer structure above a carrier substrate, wherein the wafer structure includes a substrate and a device layer arranged along a front surface of the substrate facing the carrier substrate, the substrate having a sidewall forming a recess along a rear surface of the substrate opposite to the front surface, wherein the substrate has a thick portion and a thin portion, the thin portion being thinner than the thick portion, the thick portion surrounding the thin portion, and the thin portion being located below the recess; a thermally conductive plug inserted into the thin portion of the substrate of the wafer structure, wherein the thermally conductive plug is electrically insulated from the device layer; a thermally conductive layer disposed between the sidewalls of the substrate, wherein a first thermal conductivity of the thermally conductive layer is greater than a second thermal conductivity of the substrate; and a heat sink above the rear surface of the substrate and the thermally conductive layer, wherein the heat sink includes a protrusion extending outward from a lower surface of the heat sink toward the thermally conductive layer, wherein the protrusion is above the thin portion.

10. The wafer package structure as claimed in claim 9, wherein the thermally conductive layer has a top surface facing away from the carrier substrate, and the top surface is lower than the rear surface of the substrate of the wafer structure.

11. The wafer package structure as claimed in claim 9, wherein the substrate includes a lower semiconductor layer, an upper semiconductor layer, and a bonding layer between the lower semiconductor layer and the upper semiconductor layer, and the thermally conductive layer is embedded in the upper semiconductor layer and passes through the bonding layer.

12. A method for forming a wafer package structure, comprising: A wafer structure is formed having a device layer arranged along a front surface of a substrate, the device layer having a hot spot region; A thermally conductive plug is formed in the substrate; a rear surface of the substrate is etched to form a recess above the hot spot area, wherein the substrate has a thick portion and a thin portion, the thin portion being thinner than the thick portion, the thick portion surrounding the thin portion, and the thin portion being located below the recess, wherein the thermally conductive plug is inserted into the thin portion, and the thermally conductive plug is electrically insulated from the device layer; the front surface of the wafer structure is bonded to a carrier substrate; and a heat sink is bonded to the rear surface of the substrate, wherein the heat sink has a flat portion and a protrusion below the flat portion, the flat portion being above the rear surface of the substrate, and the protrusion being in the recess of the rear surface of the substrate.

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