Semiconductor device and method for forming the same

Abstract

An apparatus and related method include a plurality of first nanostructures formed in a first stack. The apparatus also includes a plurality of second nanostructures formed in a second stack. The apparatus further includes a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure comprising a first semiconductor having silicon and germanium. The apparatus also includes a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor, wherein the germanium concentration of the second semiconductor exceeds the germanium concentration of the first semiconductor.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and more particularly to complementary field effect transistors and methods for forming the same. Prior Art

[0002] The demand for computing power in electronic devices, including smartphones, tablet computers, desktop computers, laptop computers, and many other types of electronic devices, has continued to grow. Integrated circuits provide computing power for these electronic devices. One way to increase computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that can be included in a given area of a semiconductor substrate.

[0003] Complementary field effect transistors (CFETs) can be used to increase the density of transistors in integrated circuits. CFETs can include vertically stacked N-type transistors and P-type transistors. The gate electrodes of the N-type and P-type transistors can be electrically shorted together. Summary of the invention

[0004] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed in a first stack; a plurality of second nanostructures formed in a second stack; a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure including a first semiconductor having silicon and germanium; and a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor, wherein the germanium concentration of the second semiconductor exceeds the germanium concentration of the first semiconductor.

[0005] According to some other embodiments, a method for forming a semiconductor device is provided. The method includes forming a first semiconductor nanostructure corresponding to a channel region of a first transistor; forming a second semiconductor nanostructure on the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure, the sacrificial source / drain structure including a first semiconductor having a first germanium concentration; and forming a second source / drain structure adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor, the second semiconductor having a second germanium concentration exceeding the first germanium concentration.

[0006] According to some other embodiments, a method for forming a semiconductor device is provided. The method includes forming a first semiconductor nanostructure corresponding to a channel region of a first semiconductor transistor; forming a second semiconductor nanostructure on the first semiconductor nanostructure and corresponding to a channel region of a second transistor; forming a first source / drain structure adjacent to the first semiconductor nanostructure; and before forming the first source / drain structure: forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure; and replacing the sacrificial source / drain structure with a second source / drain structure, wherein the germanium concentration of the second source / drain structure exceeds the germanium concentration of the sacrificial source / drain structure. Simple diagram description

[0007] Through the following detailed description in conjunction with the accompanying drawings, the aspects of the embodiments of the present invention can be better understood. It should be emphasized that, according to standard practices in the industry, many components are not drawn to scale. In fact, the sizes of various components may be arbitrarily increased or decreased for the sake of clarity of discussion. 1A-1F are cross-sectional views of an integrated circuit including a CFET at various processing stages according to some embodiments. 2A and 2B are cross-sectional views of an integrated circuit at various processing stages according to some embodiments. 3A-3J are cross-sectional views of an integrated circuit at various processing stages according to some embodiments. FIG. 4 is a flow chart of a process for forming an integrated circuit according to some embodiments. Implementation

[0008] In the following description, many thicknesses and materials of various layers and structures within the IC die are described. Specific dimensions and materials are provided by way of example for various embodiments. In view of the embodiments of the present invention, one of ordinary skill in the art will appreciate that other dimensions and materials may be used in many cases without departing from the scope of the embodiments of the present invention.

[0009] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to be limiting. For example, the description of a first component formed on or above a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present invention may reuse reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0010] In addition, spatially relative terms, such as "under", "beneath", "below", "above", "above" and similar terms may be used herein to facilitate description of the relationship between one (or some) element or component and another (or some) element or component as shown in the figure. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted herein. When the device is oriented in a different orientation (rotated 90 degrees or at other orientations), the spatially relative adjectives used herein should be interpreted based on the oriented orientation.

[0011] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present invention. However, one of ordinary skill in the art will appreciate that embodiments of the present invention may be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of embodiments of the present invention.

[0012] Unless the context requires otherwise, throughout this specification and the claims that follow, the word "include" and variations such as "include" and "comprising" should be interpreted in an open, inclusive sense, that is, meaning "including, but not limited to."

[0013] The use of ordinal numbers such as first, second, and third does not necessarily indicate a hierarchical sense of order but may simply distinguish multiple instances of an action or structure.

[0014] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular component, structure, or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the phrases "in one embodiment," "in an embodiment," or "in some embodiments" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular components, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0015] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in its sense including "and / or" unless the content clearly dictates otherwise.

[0016] As used in this specification and the appended claims, the terms "fill", "fills", "filling" and "filled" include both partially filled and completely filled (or filled, etc.). For example, a conductive layer may be said to "fill" an opening, which may include the conductive layer contacting adjacent walls of the opening, or the conductive layer being present in the opening with one or more layers of different materials between the conductive layer and the adjacent walls of the opening.

[0017] As used in this specification and the appended claims, the terms "surround", "surrounds", "surrounding" and "surrounded" include both completely surrounding and partially surrounding (or surrounded, etc.). For example, a "surrounded" six-sided volume (such as a rectangular prism) includes being completely surrounded by a material on all six sides, or may be partially surrounded such that one or more of the six sides are not completely surrounded by the material and are at least partially exposed.

[0018] In many CFETs, SiGe is used as source / drain (S / D). To avoid damaging the epitaxial layer during the formation of the wafer, a SiB layer (formed in the channel adjacent to the epitaxial layer) and a lower Ge composition SiGe layer (L1) are grown before growing a high Ge layer (L2).

[0019] In the embodiment of the present invention, the source / drain can be made of pure germanium or a high concentration germanium layer to replace the silicon germanium layer. The replacement can occur after the source / drain epitaxial process of growing the upper source / drain, the lower source / drain, or both.

[0020] Using pure Ge or high Ge% SiGe (e.g. 75%~100% Ge) as source / drain can increase the lattice constant and significantly increase the strain applied to the channel, thereby increasing the drive current. Using pure Ge or high Ge% SiGe (e.g. 75%~100% Ge) as source / drain can reduce the source / drain contact resistance and generate current boost.

[0021] 1A-1F are cross-sectional views of an integrated circuit 100 including a CFET at various processing stages according to some embodiments. For clarity of illustration, some components may be omitted from the view in the drawings.

[0022] FIG. 4 is a flow chart of a method 1000 for forming an integrated circuit device or a portion thereof from a workpiece according to one or more aspects of an embodiment of the present invention. Method 1000 is merely an example and is not intended to limit embodiments of the present invention to those explicitly depicted in method 1000. Additional actions may be provided before, during, and after method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For example, action 1020 may be eliminated or may be performed after action 1060. For simplicity, not all actions are described in detail herein. Method 1000 is described below in conjunction with partial perspective views and / or cross-sectional views of a workpiece at different stages of manufacture according to an embodiment of method 1000 as shown in FIGS. 1A to 3H. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. It should be noted that since the workpiece may be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0023] The integrated circuit 100 includes a complementary field effect transistor (CFET) 102. The CFET 102 includes a transistor 20A of a first conductivity type and a transistor 20B of a second conductivity type. The transistor 20A is vertically stacked on the transistor 20B. The CFET 102 uses an isolation structure 126 to separate the stacked channel region of the transistor 20A from the stacked channel region of the transistor 20B to improve the electrical characteristics of the CFET 102. In other words, a hybrid nanostructure (e.g., a hybrid sheet) including the stacked channel region of the transistor 20A, the isolation structure 126, and the stacked channel region of the transistor 20B is formed.

[0024] The CFET transistor 20A may correspond to a gate all around transistor. The gate all around transistor structure may be patterned by any suitable method. For example, the patterning of the structure may use one or more photolithography processes, including double patterning or multiple patterning processes. Generally, the double patterning or multiple patterning process combines a photolithography process with a self-aligned process, which allows the production of patterns having, for example, pitches that are smaller than those obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the gate all around structure may then be patterned using the remaining spacers. In addition, the gate all around CFET 102 may include a plurality of semiconductor nanostructures corresponding to the channel region of the CFET 102. The semiconductor nanostructures may include nanosheets, nanowires, or other types of nanostructures. The fully wound gate structure can also be called a nanostructured transistor.

[0025] The view of FIG. 1A is an X-view of integrated circuit 100, where the X-axis is the horizontal axis, the Z-axis is the vertical axis, and the Y-axis extends into and out of the drawing. As used herein, the term "X-view" corresponds to a cross-sectional view where the X-axis is the horizontal dimension and the Z-axis is the vertical dimension. As used herein, the term "Y-view" corresponds to a cross-sectional view where the Y-axis is the horizontal dimension and the Z-axis is the vertical dimension.

[0026] The integrated circuit 100 includes a substrate 101. The substrate 101 may include a semiconductor layer, a dielectric layer, or a combination of a semiconductor layer and a dielectric layer. In addition, conductive structures may be formed in the substrate 101 as backside conductive vias and interconnects, as will be described in more detail below. In some embodiments, the substrate 101 includes a single crystalline semiconductor layer on at least a surface portion. The substrate 101 may include a single crystalline semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0027] In some embodiments, the substrate 101 may include a dielectric layer, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or other dielectric materials. In some embodiments, the substrate 101 may include a shallow trench isolation region formed in the semiconductor layer. Various configurations of the substrate 101 may be utilized without departing from the scope of the embodiments of the present invention. In some embodiments, the substrate 101 is not present, such as when the substrate 101 is removed prior to forming the backside interconnect structure.

[0028] Transistor 20B is formed over substrate 101. In the view of FIG. 1A, integrated circuit 100 is flipped over, corresponding to processing performed through the back side of integrated circuit 100. Transistor 20A is located over transistor 20B. In some embodiments, transistor 20A is an N-type transistor and transistor 20B is a P-type transistor. In some embodiments, transistor 20A may be a P-type transistor and transistor 20B may be an N-type transistor.

[0029] The transistor 20A includes a plurality of semiconductor nanostructures 106. The semiconductor nanostructures 106 are stacked in a vertical direction or in a Z direction. In the example of FIG. 1A, two stacked semiconductor nanostructures 106 are depicted. However, in practice, three or more stacked semiconductor nanostructures 106 may exist without departing from the scope of the embodiments of the present invention. In addition, in some embodiments, only a single semiconductor nanostructure 106 and a single semiconductor nanostructure 107 may exist. The semiconductor nanostructure 106 corresponds to the channel region of the transistor 20A. The semiconductor nanostructure 106 may be a nanosheet, a nanowire, or other types of nanostructures.

[0030] The transistor 20B includes a plurality of semiconductor nanostructures 107. The semiconductor nanostructures 107 are stacked in a vertical direction or in a Z direction. In the example of FIG. 1A , there are three stacked semiconductor nanostructures 107. However, in practice, there may be only two stacked semiconductor nanostructures 107 or more than three stacked semiconductor nanostructures 107 without departing from the scope of the embodiments of the present invention. The semiconductor nanostructure 107 corresponds to the channel region of the transistor 20B. The semiconductor nanostructure 107 may be a nanosheet, a nanowire, or another type of nanostructure. The number of semiconductor nanostructures 107 may be the same as the number of semiconductor nanostructures 106 or may be different from the number of semiconductor nanostructures 106.

[0031] Semiconductor nanostructures 106 and 107 may include Si, SiGe, Ge, SiGeSn, GeSn, or other semiconductor materials. In the non-limiting example described herein, semiconductor nanostructure 106 is silicon. The vertical thickness of semiconductor nanostructure 106 may be 2 nm to 5 nm. Semiconductor nanostructures 106 may be separated from each other by 4 nm to 10 nm in the vertical direction. Other thicknesses and materials may be used for semiconductor nanostructure 106 without departing from the scope of embodiments of the present invention. Semiconductor nanostructure 107 may have the same material and size as semiconductor nanostructure 106 or a different semiconductor material than semiconductor nanostructure 106.

[0032] Transistors 20A and 20B include gate dielectrics. The gate dielectrics include an interfacial gate dielectric layer 108 and a high-k gate dielectric layer 110. The interfacial gate dielectric layer 108 is a low-k gate dielectric layer. For example, the interfacial gate dielectric layer 108 may be a thin oxide layer of the underlying material of the semiconductor nanostructures 106 and 107. The interfacial gate dielectric layer 108 contacts the semiconductor nanostructures 106 and 107. The high-k gate dielectric layer 110 contacts the interfacial gate dielectric layer (low-k gate dielectric layer) 108. The interfacial gate dielectric layer 108 is between the semiconductor nanostructure 106 and the high-k gate dielectric layer 110 and between the semiconductor nanostructure 107 and the high-k gate dielectric layer 110.

[0033] The interface gate dielectric layer 108 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The interface gate dielectric layer 108 may include a relatively low dielectric constant dielectric relative to a high dielectric constant dielectric (such as hafnium oxide or other high dielectric constant dielectric materials that may be used in the gate dielectric of a transistor). The interface gate dielectric layer 108 may include a native oxide layer grown on the surface of the semiconductor nanostructures 106 and 107. The interface gate dielectric layer 108 may have a thickness of 0.4 nm to 2 nm. Other materials, configurations, and thicknesses may be used for the interface gate dielectric layer 108 without departing from the scope of embodiments of the present invention.

[0034] The high-k gate dielectric layer comprises one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials and / or combinations thereof. The thickness of the high-k dielectric is in the range of about 1 nm to about 3 nm. Other thicknesses, deposition processes and materials may be used for the high-k gate dielectric layer without departing from the scope of the embodiments of the present invention. The high-k gate dielectric layer may comprise a first layer and a second layer, the first layer comprising HfO2 having a dipole doping including La and Mg, and the second layer comprising a crystalline higher-k ZrO layer.

[0035] The transistor 20A includes a gate metal 112. The gate metal 112 surrounds the semiconductor nanostructure 106. The gate metal 112 contacts the high-k gate dielectric layer 110. The gate metal 112 corresponds to the gate electrode of the transistor 20A. In the example where the transistor 20A is an N-type transistor, the gate metal 112 may include a material that produces a beneficial work function with the semiconductor nanostructure 106. In some embodiments, the gate metal 112 includes titanium aluminum, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials. In some embodiments, the gate metal 112 surrounds the semiconductor nanostructure 106 on four sides (e.g., top, bottom, left, and right). In some embodiments, such as in a forksheet transistor, the gate metal 112 may surround the semiconductor nanostructure 106 on three sides, while the gate metal 112 is substantially absent on the fourth side. For example, the gate metal 112 may be present on the outer edge of the fourth side and may occupy less than about 5% of the area of the fourth side.

[0036] FIG. 1A illustrates a single gate metal 112. However, in practice, the gate electrode from transistor 20A may include multiple metal layers. For example, gate metal 112 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. Gate metal 112 may include a gate fill material that fills the remaining volume between semiconductor nanostructures 106 after depositing the one or more liner layers. Various materials, combinations of materials, and configurations may be used for gate metal 112 without departing from the scope of embodiments of the present invention.

[0037] The transistor 20B includes a gate metal 113. The gate metal 113 surrounds the semiconductor nanostructure 107. The gate metal 113 contacts the high-k gate dielectric layer 110. The gate metal 113 corresponds to the gate electrode of the transistor 20B. In the example where the transistor 20B is a P-type transistor, the gate metal 113 may include a material that produces a beneficial work function with the semiconductor nanostructure 107. In one example, the gate metal 113 includes titanium nitride, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive materials. In some embodiments, the gate metal 113 is or includes one or more materials different from the gate metal 112.

[0038] FIG. 1A shows a single gate metal 113. However, in practice, the gate electrode of transistor 20B may include multiple metal layers that wrap around semiconductor nanostructure 107. For example, gate metal 112 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. Gate metal 113 may include a gate fill material that fills the remaining volume between semiconductor nanostructures 107 after depositing one or more liner layers. Various materials, combinations of materials, and configurations may be used for gate metal 113 without departing from the scope of embodiments of the present invention.

[0039] Transistor 20A includes source / drain regions 116. Source / drain regions 116 contact each semiconductor nanostructure 106. Each semiconductor nanostructure 106 extends along the X direction between source / drain regions 116. Source / drain regions 116 include semiconductor material. Transistor 20B includes sacrificial source / drain regions 117. Sacrificial source / drain regions 117 contact each semiconductor nanostructure 107. Each semiconductor nanostructure 107 extends along the X direction between sacrificial source / drain regions 117. Sacrificial source / drain regions 117 include semiconductor material.

[0040] In the example where transistor 20A is an N-type transistor and transistor 20B is a P-type transistor, source / drain region 116 may be doped with an N-type dopant species. The N-type dopant species may include P, As, or other N-type dopant species. In the case of a P-type transistor, sacrificial source / drain region 117 may be doped with a P-type dopant species. The P-type dopant species may include B or other P-type dopant species. Doping may be performed in-situ during the epitaxial growth process of source / drain region 117. Source / drain regions 116 and 117 may include other materials and structures without departing from the scope of embodiments of the present invention. Generally speaking, since sacrificial source / drain region 117 is sacrificial, in many embodiments, sacrificial source / drain region 117 is not doped with dopant species, which is beneficial for reducing process steps. In some embodiments, the sacrificial source / drain region 117 may be doped with one or more appropriate dopants when it is beneficial to increase the etching selectivity of the sacrificial source / drain region 117 relative to its adjacent structures and / or devices.

[0041] As used herein, the term "source / drain region" may refer to a source region or a drain region, either individually or collectively, depending on the context. Thus, one of the source / drain regions 116 may be a source region, while the other source / drain region 116 may be a drain region, or vice versa. Furthermore, in some cases, one or both of the source / drain regions 116 may be shared with one or more laterally adjacent transistors.

[0042] Each of transistors 20A and 20B includes an inner spacer 114. The inner spacer 114 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or other dielectric materials without departing from the scope of the present invention. In one example, the inner spacer 114 includes silicon carbonitride.

[0043] The inner spacer 114 of transistor 20A physically separates the gate metal 112 from the source / drain regions 116. This prevents shorts between the gate metal 112 and the source / drain regions 116. The inner spacer 114 of transistor 20B physically separates the gate metal 113 from the sacrificial source / drain regions 117. This prevents shorts between the gate metal 113 and replacement or "active" source / drain regions formed in subsequent operations.

[0044] Transistor 20A may include source / drain contacts 124. Each source / drain contact 124 is located above a corresponding source / drain region 116 and is electrically connected to or in contact with the corresponding source / drain region 116, and optionally in contact with a sacrificial source / drain region 117. An electrical signal may be applied to the source / drain region 116 via the source / drain contacts. The source / drain contacts 124 may include silicide (not separately depicted for simplicity of illustration). The silicide is formed on top of the source / drain region 116. The silicide may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides. As shown in FIG. 1A, the source / drain contact 124 may extend completely through one of the source / drain regions 116 and land on the sacrificial source / drain region 117 above it. In some embodiments, one or more of the source / drain regions 116 or the sacrificial source / drain regions 117 do not have a source / drain contact 124 connected or in contact therewith. In some embodiments, both source / drain contacts 124 extend completely through the corresponding source / drain regions 116 to land on the corresponding sacrificial source / drain regions 117.

[0045] The source / drain contacts 124 may be or include a conductive layer, a barrier layer, or both on a silicide. The barrier layer may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The conductive layer may include conductive materials such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contacts 124 without departing from the scope of embodiments of the present invention.

[0046] The transistor 20A includes a sidewall spacer 131. The sidewall spacer 131 is located adjacent to the uppermost portion of the gate metal 112 and electrically isolates the gate metal 112 from the source / drain contact 124. The sidewall spacer 131 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, or other dielectric materials. Other thicknesses and materials may be used for the sidewall spacer 131 without departing from the scope of the embodiments of the present invention.

[0047] Transistor 20A may include a gate cap metal (not separately depicted for simplicity of illustration) located on the uppermost portion of gate metal 112. In some embodiments, the gate cap metal includes tungsten, fluorine-free tungsten, or other suitable conductive materials. The gate cap metal may have a height of 1 nm to 10 nm. Other configurations, materials, and thicknesses may be used for the gate cap metal without departing from the scope of embodiments of the present invention.

[0048] The operation of CFET 102 may be generally described with reference to FIG. 1A , but it should be noted that source / drain region 117 is replaced by source / drain region 117′ in subsequent operations, and source / drain region 117′ is pure Ge or high concentration source / drain region 117′ (see, for example, FIG. 1D ). The operation of CFET 102 may be performed by applying voltage to source / drain region 116 / 117′ and gate metal 112 / 113. Voltage may be applied to source / drain region 116 / 117′ via source / drain contacts 124 / 125. Voltage may be applied to gate metal 112 / 113 via a gate contact not shown in FIG. 1A . Although not apparent in the view of FIG. 1A , gate metal 112 and gate metal 113 may be shorted together. Thus, gate metal 112 and gate metal 113 may collectively correspond to the gate metal of CFET 102 . The voltage applied to the gate metal 112 / 113 can turn on the transistor 20A and turn off the transistor 20B, or can turn on the transistor 20B and turn off the transistor 20A. When the gate metal 112 / 113 is shorted together, the source / drain region 116 is not shorted together with the source / drain region 117'. Depending on the specific circuit configuration, current can be selectively enabled or disabled to flow through the source / drain regions 116 and 117', respectively.

[0049] As previously mentioned, it may be beneficial to obtain the desired work function of transistors 20A and 20B by using different materials for gate metals 112 and 113. One possible way to form gate metals 112 / 113 is to first deposit gate metal 113 around all semiconductor nanostructures 106 and 107, and then perform a timed etch to remove gate metal 113 from around semiconductor nanostructure 106. Gate metal 112 is then deposited around semiconductor nanostructure 106 after the timed etch of gate metal 113. However, one disadvantage of this process is that, in some cases, gate metal 113 directly below the lowest semiconductor nanostructure 106 may not be completely removed. This can interfere with the work function of transistor 20A, thereby affecting the threshold voltage of transistor 20A in an undesirable manner.

[0050] CFET 102 avoids or reduces the possibility of work function interference by utilizing an isolation structure 126 between semiconductor nanostructure 106 and semiconductor nanostructure 107. More specifically, isolation structure 126 is located directly between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 107. Isolation structure 126 may include upper and lower semiconductor layers 127 and a dielectric layer 129 located between the upper and lower semiconductor layers 127. Various structures and compositions may be used for isolation structure 126 without departing from the scope of embodiments of the present invention.

[0051] The dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric material, or other dielectric materials. The dielectric layer 129 may have a length in the X direction of 15 nm to 30 nm. The length in this range may be sufficient to match or exceed the length of the semiconductor nanostructures 106 and 107 in the X direction. However, depending on the length of the semiconductor nanostructures 106 and 107, a larger or smaller length of the dielectric layer 129 may be selected. The dielectric layer 129 may have a height in the Z direction of 5 nm to 25 nm. These dimensions may be sufficient to ensure that there is no possibility of work function interference from the gate metal 113 with the semiconductor nanostructure 106. In addition, these dimensions may provide reduced gate-to-drain capacitance. Other materials, dimensions, and configurations may be used for the dielectric layer 129 without departing from the scope of embodiments of the present invention. The dielectric layer 129 may be referred to as a dielectric nanostructure. The dielectric nanostructure may include a dielectric nanosheet, a dielectric nanowire, or other types of dielectric nanostructures.

[0052] Each semiconductor layer 127 may have a vertical thickness of 1 nm to 5 nm. The semiconductor layer 127 may include silicon or other suitable semiconductor materials. Other materials and dimensions may be used for the semiconductor layer 127 without departing from the scope of embodiments of the present invention.

[0053] Although FIG. 1A illustrates a single dielectric layer 129, in practice, the dielectric layer 129 may include multiple layers of different dielectric materials between the semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be located in contact with each semiconductor layer 127. A second dielectric layer of silicon nitride may be located between the upper and lower portions of the first dielectric layer. Various configurations of dielectric barriers between the top semiconductor nanostructure 107 and the bottom semiconductor nanostructure 106 may be utilized without departing from the scope of embodiments of the present invention.

[0054] The formation of the device 100 depicted in FIG. 1A may include forming nanostructure channels 106, 107, which corresponds to action 1010 of FIG. 4. In some embodiments, the formation of the device 100 further includes forming a source / drain region 116 adjacent to the nanostructure channel 106, which corresponds to action 1020 of FIG. 4. The formation of the device 100 includes forming a sacrificial source / drain region 117 adjacent to the nanostructure channel 107.

[0055] In FIGS. 1A-1F , the sacrificial source / drain region 117 is replaced by a replacement source / drain region 117′, which can increase strain in the semiconductor nanostructure or channel 107. Increasing strain can improve the drive current that can be conducted through the channel 107. In some embodiments, the replacement source / drain region 117′ includes pure or high concentration germanium instead of SiGe, which can reduce the source / drain contact resistance, which can also increase current conduction. Throughout the description, the replacement source / drain region 117′ can be referred to as a second source / drain region 117′ or an active source / drain region 117′.

[0056] In FIG. 1A , a first opening 57 is formed to expose the upper surface of the sacrificial source / drain region 117. The first opening 57 can be formed, for example, through the interlayer dielectric that is partially or completely removed in the cross-sectional view of FIG. 1A . As shown, when the first opening 57 is formed, the interlayer dielectric is completely removed. The formation of the first opening 57 can be via a suitable etching operation, such as wet etching, dry etching, or atomic layer etching (ALE), which is selective to the material of the interlayer dielectric without substantially attacking the material of the dielectric layer 130.

[0057] In some embodiments, after forming the first opening 57, the profile of the upper surface of the sacrificial source / drain region 117 is concave. In some embodiments, the profile of the upper surface is flat. In some embodiments, the depth D1 between the uppermost layer of the upper surface of the sacrificial source / drain region 117 and the lowermost layer of the upper surface can be in the range of about 0 nm to about 15 nm. That is, the depth D1 can measure the depth of the concavity of the sacrificial source / drain region 117 after forming the first opening 57. This concavity may be caused by over-etching the material of the sacrificial source / drain region 117 when removing the interlayer dielectric above the sacrificial source / drain region 117.

[0058] In FIG. 1B , an oxidation process is performed to form a porous oxide layer 1172 on the exposed upper surface of the sacrificial source / drain region 117 , corresponding to action 1040 of FIG. 4 . The thickness of the porous oxide layer 1172 may be in the range of about 0.8 nm to about 2 nm, for example, about 1 nm. The formation of the porous oxide layer 1172 may include thermal oxidation, in which the SiGe sacrificial source / drain region 117 is exposed to oxygen or water vapor at a high temperature. The thermal oxidation process may cause silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO 2). Because germanium oxidizes differently from silicon, less stable germanium oxide (GeOx) may be formed that may volatilize at the oxidation temperature, affecting the uniformity and quality of the porous oxide layer 1172. That is, the holes present in the porous oxide layer 1172 extend entirely through the porous oxide layer 1172 , so that the sacrificial source / drain region 117 is at least partially exposed through the porous oxide layer 1172 .

[0059] In FIG. 1C , the sacrificial source / drain region 117 is removed to form an opening 117H, corresponding to action 1050 of FIG. 4 . The removal of the sacrificial source / drain region 117 may be performed via a suitable etching operation, which may include a chlorine-based etchant, a fluorine-based etchant, or a similar etchant. The etchant may be a gas that can penetrate the porous oxide layer 1172 and etch the SiGe of the sacrificial source / drain region 117 , so that the sacrificial source / drain region 117 is removed and an opening 117H is formed. The opening 117H may inherit the shape of the sacrificial source / drain region 117 , as shown in FIG. 1C . In some embodiments, as described with reference to FIGS. 2A and 2B , some over-etching may occur, which removes the end of the nanostructure 107 .

[0060] In FIG. 1D , after forming the opening 117H, a replacement or “active” source / drain region 117′ is formed in the opening 117H through the porous oxide layer 1172, corresponding to action 1060 of FIG. 4 . The formation of the replacement source / drain region 117′ may be by a suitable epitaxial growth operation, which grows the material of the replacement source / drain region 117′ in the opening 117H. The replacement source / drain region 117′ may be or include one or more semiconductor materials, which may include SiGe, Ge, GeSn, SiGeSn. In the replacement source / drain region 117′, the concentration of germanium (“germanium concentration”) may be in the range of about 75% to 100% (i.e., pure Ge). The epitaxial growth of Ge or SiGe in the source / drain opening may be by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or similar operations. In chemical vapor deposition, a gas containing selected elements (e.g., germane for Ge, silane for Si, and optionally diborane, phosphine, TMGa, TEGa, AsH 3, or TBA for doping) is introduced into a reaction chamber. The device 100 can be heated to a high temperature so that the gas reacts or decomposes to form the epitaxial layer. Chemical vapor deposition is beneficial for good uniformity and control of the layer composition. Molecular beam epitaxy can provide the benefit of increased precision, where the elements are evaporated in a high vacuum environment and then condensed on the heated device 100. Molecular beam epitaxy can provide excellent control of the thickness and composition of the epitaxial layer replacing the source / drain region 117' at the atomic level, which is beneficial for nanoscale devices.

[0061] In chemical vapor deposition and molecular beam epitaxy, the porous oxide layer 1172 is permeable to gases (e.g., germane, silane, diborane, phosphine, and the like) so that the gases can react or decompose at the nanostructure 107 in the opening 117H. That is, the exposed side surfaces of the ends of the nanostructure 107 can have semiconductor material grown thereon. As shown by the dashed lines in FIG. 1D , during the growth process, growth can initially occur to form a first region 117A on the ends of the nanostructure 107. Then, as the process continues over time, growth can continue such that the first regions 117A expand and eventually merge to form second regions 117B. Finally, growth continues until the second regions 117B on either side of the opening 117H merge with each other and contact at least the nanostructure 107, the inner spacer 114, the source / drain contacts 124 (when present), the dielectric layer 130, and the porous oxide layer 1172. In some embodiments, due to the growth profile of the semiconductor material in the opening 117H, one or more air gaps may be formed in the corner regions of the replacement source / drain regions 117 ′. The formation of the air gaps is described in more detail with reference to FIG. 1F .

[0062] In some embodiments, as described above, dopants are introduced in situ to replace the source / drain region 117'. In some embodiments, the dopants include B, Ga, P, As, or similar materials. During the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsine, tertiarybutylarsine, or similar materials may be gaseously flowed to in situ dope the replacement source / drain region 117'. In some embodiments, the replacement source / drain region 117' may be doped in a subsequent operation, such as by implanting one or more of B, Ga, P, As, or similar materials.

[0063] In FIG. 1E , after forming the replacement source / drain region 117′, source / drain contacts 125 may be formed on the replacement source / drain region 117′, corresponding to action 1070 in FIG. 4 . Each source / drain contact 125 is located on a corresponding replacement source / drain region 117′ and is electrically connected to the corresponding replacement source / drain region 117′. An electrical signal may be applied to the replacement source / drain region 117′ via the source / drain contact 125 .

[0064] The source / drain contacts 125 may be or include one or more conductive layers located on the silicide 121. For example, the barrier layer or liner may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The conductive fill layer may be located on the barrier layer or liner and may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contacts 125 without departing from the scope of embodiments of the present invention.

[0065] The source / drain contact 125 may include a silicide 121. The silicide 121 is formed at the interface between the replacement source / drain region 117' and the source / drain contact 125. The silicide 121 may reduce the source / drain contact resistance. In some embodiments, the silicide 121 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or a similar material. In some embodiments, the silicide 121 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or a similar material. The silicide 121 may be an alloy between the source / drain contact 125 and the replacement source / drain region 117', which may be a mixture of one or more of Ti, Ru, Mo, Ni, Co, W or similar materials and one or more of Ge, SiGe, SiGeSn, GeSn or similar materials. The silicide 121 may have a thickness ranging from about 1 nm to about 10 nm. A thickness below about 1 nm may result in insufficient reduction of contact resistance. A thickness above about 10 nm may result in an electrical short circuit with the nanostructure 107. In some embodiments, the silicide 121 is present below the dielectric layer 130 and contacts the dielectric layer 130. As shown in FIG. 1E, in some embodiments, a backside silicide 121B is present at the interface between the source / drain region 117' and the source / drain contact 124. Backside silicide 121B may be similar in most respects to silicide 121 , but may be formed during the growth of the semiconductor material of source / drain regions 117 ′ rather than during the formation of source / drain contacts 125 .

[0066] FIG. 1F illustrates optional air gaps 117G1, 117G2 that may exist in the corner regions of the source / drain region 117'. The first air gap 117G1 may exist adjacent to the inner spacer 114 and the silicide 121 proximate to the substrate 101. The second air gap 117G2 may exist adjacent to the inner spacer 114 and the source / drain contact 124 proximate to the isolation structure 126. As previously described with reference to FIG. 1D, during the growth process of the source / drain region 117', growth may initially occur on the ends of the nanostructure 107 to form a first region 117A depicted by a first dashed line. Then, as the process continues over time, growth may continue such that the first region 117A expands and eventually merges to form a second region 117B. Finally, growth continues until the second regions 117B on either side of the opening 117H merge with each other and contact at least the nanostructure 107 , the inner spacer 114 , the source / drain contacts 124 (when present), the dielectric layer 130 , and the porous oxide layer 1172 .

[0067] In some embodiments, the growth of the source / drain region 117' may be terminated before its semiconductor material reaches the uppermost portion of the inner spacer 114 adjacent to the substrate 101, resulting in the formation of an air gap 117G1. The height of the air gap 117G1 in the Z-axis direction may range from 0 nm to about 5 nm.

[0068] The formation of the air gap 117G2 may be due to the merging or protrusion of semiconductor materials that occurs before filling the small lateral space between the inner spacer 114 and the source / drain contact 124 adjacent to the isolation structure 126, resulting in the air gap 117G2. The height of the air gap 117G2 in the Z-axis direction may range from 0 nm to about 5 nm.

[0069] In some embodiments, air gap 117G1 is present, but air gap 117G2 is not present. In some embodiments, air gap 117G2 is present, but air gap 117G1 is not present. In some embodiments, air gaps 117G1 and 117G2 are both present or not present.

[0070] In some embodiments, due to the merging of semiconductor materials of the source / drain region 117', a seam 117S may exist. The seam 117S may be an air gap as shown, or may be a visible interface extending substantially along a vertical direction (eg, the Z-axis direction).

[0071] As shown in FIG. 1F , when the lower side of the replacement source / drain region 117′ is adjacent to the interlayer or interlevel dielectric 128 and the dielectric layer 130, for example, when no source / drain contact 124 extends through the interlayer dielectric 128 to electrically connect with the replacement source / drain region 117′, the growth of the replacement source / drain region 117′ may be different from that in the region of the device 100 where the source / drain contact 124 extends through the interlayer dielectric 128. For example, the second air gap 117G2, the seam 117S, or both may not exist in such a region, as shown.

[0072] 2A and 2B are cross-sectional views of the integrated circuit 100 at various processing stages according to some embodiments.

[0073] FIG. 2A illustrates an embodiment in which, after forming the porous oxide layer 1172, the opening 117H is formed by removing the sacrificial source / drain region 117 through the porous oxide layer 1172. As described with reference to FIG. 1C, an etchant gas may penetrate through the holes of the porous oxide layer 1172 to react with and remove the semiconductor material (e.g., SiGe) of the sacrificial source / drain region 117'. In some embodiments, as shown in FIG. 2A, during the removal of the sacrificial source / drain region 117', some overetching may occur, wherein the end of the nanostructure 107 is removed or recessed. The removal of the end of the nanostructure 107 may produce a recess 107R such that the side surface of the nanostructure 107 is recessed back from the side surface of the inner spacer 114. In some embodiments, the length of the recess 107R, such as the distance in the X-axis direction between the side surface of the inner spacer 114 and the nanostructure 107 therebetween, may be in the range of about 0.5 nm to about 3 nm. Since the nanostructure 107 is recessed during the replacement of the sacrificial source / drain region 117 with the active source / drain region 117′, the width of the nanostructure 107 in the X-axis direction may be shorter than the width of the nanostructure 106 in the X-axis direction. The width difference between the nanostructure 107 and the nanostructure 106 may be in the range of about 1 nm to about 4 nm. That is, the width of the nanostructure 106 unrelated to the replacement of the source / drain region 116 may exceed the width of the nanostructure 107 related to the replacement of the source / drain region 117 by about 1 nm to about 4 nm.

[0074] In FIG. 2B , after forming the opening 117H having the recess 117R, the source / drain region 117′ is formed in the opening 117H through the porous oxide layer 1172. The formation of the source / drain region 117′ in FIG. 2B is similar in most respects to that described with reference to FIG. 1D , except that the source / drain region 117′ in FIG. 2B is formed in the recess 117R and has a portion extending into the space of the recess 117R vertically between the inner spacers 114. As discussed with reference to FIG. 2A , due to the partial etching of the end of the nanostructure 107, the width of the nanostructure 106 may exceed the width of the nanostructure 107. Similarly, due to the reduction in the width of the nanostructure 107 relative to the nanostructure 106, the width of the source / drain region 117′ may exceed the width of the source / drain region 116. For example, the width of the source / drain region 117 ′ may exceed the width of the source / drain region 116 by about 1 nm to about 4 nm.

[0075] In the description with reference to FIGS. 1D and 2B , the source / drain region 117′ is formed by passing a precursor gas of its semiconductor material and optionally its dopants through the holes in the porous oxide layer 1172. In some embodiments, the porous oxide layer 1172 may be removed before forming the source / drain region 117′. For example, a suitable etching operation, such as dry etching or vapor etching, may be performed to remove the material of the porous oxide layer 1172, and then a cleaning operation may be performed to remove any residue of the porous oxide layer 1172, followed by forming the source / drain region 117′.

[0076] In some embodiments, instead of filling the recess 117R with the high Ge concentration semiconductor material, the recess 117R may be filled with another semiconductor material (eg, SiB) before growing the high Ge concentration semiconductor material.

[0077] In the embodiments described with reference to FIGS. 1A-2B , the source / drain region 116 and the sacrificial source / drain region 117 are formed before the sacrificial source / drain region 117 is replaced by the active source / drain region 117′. In some embodiments, the sacrificial source / drain region 117 is formed before the source / drain region 116. As such, the replacement of the sacrificial source / drain region 117 by the active source / drain 11′ can occur before the source / drain region 116 is formed.

[0078] 3A-3J are schematic cross-sectional side views illustrating a process for forming the device 100, wherein the sacrificial source / drain region 117 is replaced before forming the source / drain region 116. For simplicity, FIGS. 3A-3E depict partial views of the device 100.

[0079] In FIG. 3A , before forming source / drain region 116, a sacrificial source / drain region 117 is formed in source / drain opening 77, extending through nanostructure 106, isolation structure 126, and nanostructure 107 and landing on substrate 101. In some embodiments, source / drain opening 77 extends into substrate 101 when initially formed, such that the upper surface of substrate 101 below source / drain opening 77 is recessed. The recessed portion may be regrown with undoped silicon to form semiconductor region 101A, which may have a horizontal upper surface that is substantially coplanar with the upper surface of substrate 101 and the lower surface of bottommost inner spacer 114. Semiconductor region 101A may be advantageous in providing a substantially flat surface from which sacrificial source / drain region 117 may be grown in addition to growing from the side surfaces of nanostructure 107 exposed by source / drain opening 77.

[0080] To avoid growing sacrificial source / drain regions 117 on nanostructure 106, dielectric layer 130 may be present on and completely cover the side surfaces of nanostructure 106. Dielectric layer 130 may also cover the side surfaces of semiconductor layer 127 of isolation structure 126. For example, dielectric layer 130 may be a thin conformal layer extending from sidewall spacers 131 to a height between the upper and lower surfaces of uppermost inner spacer 114 located between uppermost nanostructure 107 and isolation structure 126.

[0081] The formation of the sacrificial source / drain region 117 may be performed by a suitable epitaxial growth operation of growing the material of the sacrificial source / drain region 117 in the source / drain opening 77. The sacrificial source / drain region 117 may be or include one or more semiconductor materials, which may include SiGe, Ge, GeSn, SiGeSn. In the sacrificial source / drain region 117, the concentration of germanium may be less than about 40%, less than about 30%, less than about 20%, or other values. A germanium concentration of the sacrificial source / drain region 117 greater than about 40% may result in the diffusion of germanium into the nanostructure 107. The epitaxial growth of the semiconductor material in the source / drain opening may be performed via chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or similar operations.

[0082] In some embodiments, dopants are introduced in situ into the sacrificial source / drain regions 117, as described with reference to FIG. 1D. In some embodiments, the dopants include B, Ga, P, As, or similar materials. During the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsine, tertiary butyl arsine, or similar materials may be gaseously flowed to in situ dope the sacrificial source / drain regions 117. In some embodiments, the sacrificial source / drain regions 117 may be doped in a subsequent operation, such as by implanting one or more of B, Ga, P, As, or similar materials.

[0083] As shown in FIG. 3B , after forming the sacrificial source / drain region 117, an interlayer dielectric (ILD) 300, an etch stop layer (ESL) 310, or both are formed on and laterally adjacent to the sacrificial source / drain region 117. The interlayer dielectric 300 may then be etched back and the etch stop layer 310 may be penetrated to expose the upper surface of the sacrificial source / drain region 117. FIG. 3B schematically depicts this via dashed lines. For example, the material of the interlayer dielectric 300 above the dashed lines in FIG. 3B may be removed by the etch back operation.

[0084] In FIG. 3C , after forming the sacrificial source / drain region 117, the interlayer dielectric 300, and the etch stop layer 310 and recessing the interlayer dielectric 300, a porous oxide layer 1174 is formed on the exposed upper surface of the sacrificial source / drain region 117. The porous oxide layer 1174 can be similar in most respects to the porous oxide layer 1172 described with reference to FIG. 1B . In some embodiments, the porous oxide layer 1174 is substantially flat due to the flat surface of the sacrificial source / drain region 117.

[0085] In FIG. 3C , an oxidation process is performed to form a porous oxide layer 1174 on the exposed upper surface of the sacrificial source / drain region 117. The thickness of the porous oxide layer 1174 may be in the range of about 0.8 nm to about 2 nm, for example, about 1 nm. The formation of the porous oxide layer 1174 may include thermal oxidation, in which the SiGe sacrificial source / drain region 117 is exposed to oxygen or water vapor at a high temperature. The thermal oxidation process may cause the silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO 2). Because germanium oxidizes differently from silicon, less stable germanium oxide (GeOx) may be formed that may volatilize at the oxidation temperature, affecting the uniformity and quality of the porous oxide layer 1174. That is, the holes present in the porous oxide layer 1174 extend entirely through the porous oxide layer 1174, so that the sacrificial source / drain region 117 is at least partially exposed through the porous oxide layer 1174. When the dielectric layer 130 covers the nanostructure 106 , an oxide layer is generally not grown on the nanostructure 106 during the growth of the porous oxide layer 1174 on the sacrificial source / drain region 117 .

[0086] In FIG. 3D , opening 117H is formed by removing sacrificial source / drain region 117 through porous oxide layer 1174. Removal of sacrificial source / drain region 117 may be similar in most respects to that described with reference to FIG. 1C . Removal of sacrificial source / drain region 117 may be by an appropriate etching operation, which may include a chlorine-based etchant, a fluorine-based etchant, or the like. The etchant may be a gas that may penetrate porous oxide layer 1174 and etch SiGe of sacrificial source / drain region 117 such that sacrificial source / drain region 117 is removed and opening 117H is formed. Opening 117H may inherit the shape of sacrificial source / drain region 117, as shown in FIG. 3D . In some embodiments, as described with reference to FIGS. 2A and 2B , some overetching may occur that removes the ends of nanostructure 107 .

[0087] In FIG. 3E , source / drain regions 117 ′ are formed through porous oxide layer 1174. The formation of source / drain regions 117 ′ may be similar in most respects to that described with reference to FIG. 1D . For example, after forming openings 117H, source / drain regions 117 ′ are formed through porous oxide layer 1174 in openings 117H. The formation of replacement source / drain regions 117 ′ may be by a suitable epitaxial growth operation of growing a material of replacement source / drain regions 117 ′ in openings 117H. Replacement source / drain regions 117 ′ are or include one or more semiconductor materials, which may include SiGe, Ge, GeSn, SiGeSn. In replacement source / drain regions 117 ′, the concentration of germanium may be in the range of about 75% to 100% (i.e., pure Ge). Epitaxial growth of Ge or SiGe in the source / drain openings may be by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or similar operations. In chemical vapor deposition, a gas containing selected elements (e.g., germanium for Ge, silane for Si, and optionally diborane, phosphine, TMGa, TEGa, AsH 3, or TBA for doping) is introduced into a reaction chamber. The device 100 can be heated to a high temperature so that the gas reacts or decomposes to form the epitaxial layer. Chemical vapor deposition is beneficial for good uniformity and control of the layer composition. Molecular beam epitaxy can provide the benefit of increased precision, where the elements are evaporated in a high vacuum environment and then condensed on the heated device 100. Molecular beam epitaxy can provide excellent control of the thickness and composition of the epitaxial layer replacing the source / drain region 117' at the atomic level, which is beneficial for nanoscale devices.

[0088] In chemical vapor deposition and molecular beam epitaxy, the porous oxide layer 1174 is permeable to precursor gases (e.g., germane, silane, diborane, phosphine, and the like) so that the precursor gases can react or decompose at the nanostructure 107 in the opening 117H. That is, the exposed side surfaces of the ends of the nanostructure 107 can have semiconductor material grown thereon. In some embodiments, dopants are introduced in situ to replace the source / drain regions 117'. In some embodiments, the dopants include B, Ga, P, As, or the like. During the growth process, diborane, phosphine, trimethylgallium, triethylgallium, arsine, tertiary butyl arsine, or the like can be gaseously flowed to in situ dope the replacement source / drain regions 117'. In some embodiments, the replacement source / drain regions 117' can be doped in a subsequent operation, such as by implanting one or more of B, Ga, P, As, or the like.

[0089] In some embodiments, as described with reference to FIGS. 1A-2B , the porous oxide layer 1174 may be removed prior to forming the source / drain regions 117 ′.

[0090] In FIG. 3F , the porous oxide layer 1174 is removed and a dielectric isolation layer 150 is formed in the source / drain opening 77 on the source / drain region 117 ′. In some embodiments, the dielectric isolation layer 150 is formed of a dielectric material, such as SiN, SiCN, SiCON, or a similar material. The dielectric isolation layer 150 may be formed by a suitable deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a similar process. After the material of the dielectric isolation layer 150 is deposited, its excess material above the source / drain opening 77 may be removed by one or more removal operations (e.g., chemical mechanical polishing). The upper surface of the dielectric isolation layer 150 may initially be coplanar with the upper surfaces of the sidewall spacers 131 and the interlayer dielectric 128.

[0091] Then, in FIG. 3G , the dielectric isolation layer 150 is etched back to a height below the nanostructure 106 to expose the nanostructure 106 for subsequent epitaxial growth of the source / drain region 116. The etch back can be performed by a suitable etching operation, such as wet etching or dry etching, which is selective to the material of the dielectric isolation layer 150 and substantially does not attack the nanostructure 106, the inner spacer 114, and the sidewall spacer 131. In some embodiments, the dielectric isolation layer 150 comprises the same material as the dielectric layer 130, so that the dielectric layer 130 and the dielectric isolation layer 150 are etched back at the same time to substantially the same height as the dielectric isolation layer 150. In some embodiments, when the dielectric isolation layer 150 and the dielectric layer 130 comprise different materials, the dielectric layer 130 can be etched back after the dielectric isolation layer 150.

[0092] Then, in FIGS. 3H and 3I, source / drain regions 116 are formed adjacent to nanostructure 106. The formation of source / drain regions 116 is similar in most respects to the formation of sacrificial source / drain regions 117 and source / drain regions 117' described with reference to FIGS. 1A, 1D, 2B, 3A, and 3E, except that source / drain regions 116 may be N-type source / drain regions 116, rather than source / drain regions 117', which are P-type source / drain regions 117', providing a beneficial compressive strain to nanostructure 107 due to its high Ge concentration semiconductor material.

[0093] In FIGS. 3H and 3I, after forming the source / drain region 116, a source / drain contact 124 is formed on the source / drain region 116 and optionally on the source / drain region 117' via extension through the dielectric isolation layer 150. The formation of the source / drain contact 124 may be similar in most respects to the formation of the source / drain contact 125. The source / drain contact 124 (labeled as 124' in FIG. 3I) extending to the source / drain region 117' via extension through the dielectric isolation layer 150 may be referred to as an MDLI ("source / drain contact interconnect" or "source / drain contact region interconnect").

[0094] After or before forming the source / drain contacts 125, as shown in FIG. 3I, a vertical isolation structure 260 may be formed to physically isolate the first pair of source / drain regions 116, 117' offset from each other along the Y-axis direction from the second pair of source / drain regions 116, 117'. FIG. 3I also shows that the dielectric isolation layer 150 may extend along the Y-axis direction and may vertically isolate the source / drain region 116 from the source / drain region 117'.

[0095] FIG. 3J illustrates that air gaps 117G1, 117G2 may be formed adjacent to the source / drain region 117', as described with reference to FIG. 1F. That is, embodiments in which the dielectric isolation layer 150 is formed after forming the replacement source / drain region 117' and before forming the source / drain region 116 may include the air gaps 117G1, 117G2 described with reference to FIG. 1F.

[0096] Embodiments of the present invention provide several advantages. By forming a second source / drain structure with a high Ge concentration after forming the active gate, diffusion of germanium into the nanostructure channel can be prevented, and adjacent structures (such as the active gate) are in place, which provides additional support for the increased strain during the formation of the second source / drain structure. Substitution with pure Ge or high Ge concentration semiconductor materials (such as SiGe) can increase the lattice constant, which increases strain and drive current. Pure Ge or high Ge concentration semiconductor materials can also have reduced source / drain contact resistance, which can lead to an increase in current output.

[0097] In some embodiments, a device includes: a plurality of first nanostructures formed in a first stack. The device also includes a plurality of second nanostructures formed in a second stack. The device also includes a first source / drain structure adjacent to the plurality of first nanostructures, the first source / drain structure including a first semiconductor having silicon and germanium. The device also includes a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the plurality of second nanostructures, the second source / drain structure having a second semiconductor, wherein a germanium concentration of the second semiconductor exceeds a germanium concentration of the first semiconductor.

[0098] In some embodiments, the germanium concentration in the second semiconductor exceeds about 75%.

[0099] In some embodiments, the germanium concentration in the second semiconductor without dopants is 100%.

[0100] In some embodiments, the second semiconductor includes silicon germanium, pure germanium, germanium tin, or silicon germanium tin.

[0101] In some embodiments, the second semiconductor is doped with B, Ga, P, or As at a dopant concentration ranging from about 1e19 / cm 3 to about 5e21 / cm 3.

[0102] In some embodiments, the air gap is located adjacent to the second source / drain structure.

[0103] In some embodiments, the device further includes an inner spacer adjacent to one of the second nanostructures, a side surface of one of the second nanostructures being recessed a first distance from a side surface of the inner spacer, wherein the second source / drain structure extends a first distance through the side surface of the inner spacer to contact one of the second nanostructures.

[0104] In some embodiments, the first distance is in a range from about 0.5 nm to about 2 nm.

[0105] In some embodiments, the device further includes a first silicide contacting the first source / drain structure; and a second silicide contacting the second source / drain structure, the germanium concentration of the second silicide exceeding the germanium concentration of the first silicide.

[0106] In some embodiments, the width of the first nanostructure exceeds the width of the second nanostructure by about 1 nanometer to about 4 nanometers.

[0107] In some embodiments, a method includes: forming a first semiconductor nanostructure corresponding to a channel region of a first semi-transistor. The method also includes forming a second semiconductor nanostructure above the first semiconductor nanostructure and corresponding to a channel region of a second transistor. The method also includes forming a first source / drain structure adjacent to the first semiconductor nanostructure. The method also includes forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure, the sacrificial source / drain structure including a first semiconductor having a first germanium concentration. The method also includes forming a second source / drain structure adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor, the second semiconductor having a second germanium concentration exceeding the first germanium concentration.

[0108] In some embodiments, replacing the sacrificial source / drain structure includes: forming a porous oxide layer on the upper surface of the sacrificial source / drain structure; and removing the sacrificial source / drain structure by etching through the porous oxide layer.

[0109] In some embodiments, replacing the sacrificial source / drain structure includes: forming an opening by removing the sacrificial source / drain structure, the opening having a first height; and forming a second source / drain structure by growing a second semiconductor in the opening, the second semiconductor having a second height not exceeding the first height.

[0110] In some embodiments, the method further includes: forming a source / drain contact on the second source / drain structure, with an air gap between the second source / drain structure and the source / drain contact.

[0111] In some embodiments, replacing the sacrificial source / drain structure includes: forming an opening by removing the sacrificial source / drain structure; forming a groove by removing the end of the second semiconductor nanostructure during the removal of the sacrificial source / drain structure; and forming a second source / drain structure by growing a second semiconductor in the opening, including growing the second semiconductor in the groove.

[0112] In some embodiments, the method further comprises: before forming the second source / drain structure, forming a sacrificial gate encapsulating and surrounding the second semiconductor nanostructure; and forming an active gate by replacing the sacrificial gate.

[0113] In some embodiments, a method includes: forming a first semiconductor nanostructure corresponding to a channel region of a first transistor. The method also includes forming a second semiconductor nanostructure above the first semiconductor nanostructure and corresponding to a channel region of a second transistor. The method also includes forming a first source / drain structure adjacent to the first semiconductor nanostructure. The method also includes before forming the first source / drain structure. The method also includes forming a sacrificial source / drain structure adjacent to the second semiconductor nanostructure. The method also includes replacing the sacrificial source / drain structure with a second source / drain structure, the germanium concentration of the second source / drain structure exceeding the germanium concentration of the sacrificial source / drain structure.

[0114] In some embodiments, replacing the sacrificial source / drain structure includes: forming a porous layer on the sacrificial source / drain structure; forming an opening by removing the sacrificial source / drain structure through the porous layer; and forming a second source / drain structure in the opening.

[0115] In some embodiments, forming the opening includes forming a groove by etching the second semiconductor nanostructure; and forming the second source / drain structure includes forming the second source / drain structure in the groove.

[0116] In some embodiments, forming a second source / drain structure includes partially filling the opening with the second source / drain structure, and the method further includes: forming a source / drain contact on the second source / drain structure, and an air gap exists between the source / drain contact and the second source / drain structure.

[0117] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the various aspects of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present invention, and they can make various changes, substitutions and adjustments without violating the spirit and scope of the embodiments of the present invention.

[0118] 20A, 20B: Transistor 57: First Opening 77: Source / Drain Opening 100: Integrated Circuit 101: Base 101A: Semiconductor Area 102: Complementary Field Effect Transistor 106,107:Nanostructure 107R: Groove 108:interface gate dielectric layer 110: High dielectric constant gate dielectric layer 112,113: Gate Metal 114:Internal spacer 116,117,117': source / drain region 117A: District 1 117B: District 2 117G1,117G2: Air Gap 117H: Open 117R: Groove 117S:Seam 121: Silicide 121B: Backside silicide 124,124',125: source / drain contacts 126: Isolation Structure 127: Semiconductor layer 128,300:Interlayer dielectric 129,130: Dielectric layer 131: Sidewall spacer 150: Dielectric isolation layer 260: Vertical isolation structure 310: Etching stop layer 1000:Method 1010,1020,1030,1040,1050,1060,1070: Action 1172,1174:Porous oxide layer D1: Depth X,Y,Z: Direction

Claims

1. A semiconductor device, comprising: A plurality of first nanostructures are formed in a first stack; A plurality of second nanostructures are formed in a second stack; A first source / drain structure adjacent to the first nanostructures, the first source / drain structure including a first semiconductor having silicon and germanium; and a second source / drain structure vertically stacked above the first source / drain structure and adjacent to the second nanostructures, the second source / drain structure having a second semiconductor, wherein the germanium concentration of the second semiconductor exceeds the germanium concentration of the first semiconductor.

2. The semiconductor device as claimed in claim 1, wherein the germanium concentration in the second semiconductor exceeds about 75% or is 100% dopant-free.

3. The semiconductor device as claimed in claim 1 or 2, wherein the second semiconductor comprises silicon germanium, pure germanium, germanium tin, or silicon germanium tin.

4. The semiconductor device as claimed in claim 1 or 2, wherein the second semiconductor is doped with B, Ga, P or As at a dopant concentration ranging from about 1e19 / cm3 to about 5e21 / cm3.

5. The semiconductor device as described in claim 1 or 2, further comprising: An inner spacer is adjacent to one of the second nanostructures, one side surface of one of the second nanostructures being recessed by a first distance from one side surface of the inner spacer, wherein the second source / drain structure extends the first distance through the side surface of the inner spacer to contact one of the second nanostructures.

6. The semiconductor device as claimed in claim 5, wherein the first distance is in the range of about 0.5 nm to about 2 nm.

7. The semiconductor device as described in claim 1 or 2, further comprising: A first silicon compound contacts the first source / drain structure; And a second silicide, in contact with the second source / drain structure, wherein the germanium concentration of the second silicide exceeds the germanium concentration of the first silicide.

8. The semiconductor device as claimed in claim 1 or 2, wherein the width of the first nanostructures exceeds the width of the second nanostructures by about 1 nanometer to about 4 nanometers.

9. A method for forming a semiconductor device, comprising: A first semiconductor nanostructure is formed corresponding to a channel region of a first transistor; A second semiconductor nanostructure is formed on the first semiconductor nanostructure and corresponding to a channel region of a second transistor; a first source / drain structure is formed adjacent to the first semiconductor nanostructure, the first source / drain structure including a first semiconductor having a first germanium concentration; a sacrificial source / drain structure is formed adjacent to the second semiconductor nanostructure; and a second source / drain structure is formed adjacent to the second semiconductor nanostructure by replacing the sacrificial source / drain structure with a second semiconductor having a second germanium concentration exceeding the first germanium concentration.

10. A method of forming a semiconductor device as claimed in claim 9, wherein replacing the sacrificial source / drain structure comprises: An opening is formed by removing the sacrificial source / drain structure, the opening having a first height; And by growing the second semiconductor in the opening to form the second source / drain structure, the second semiconductor having a second height not exceeding the first height.

11. A method of forming a semiconductor device as claimed in claim 10, wherein replacing the sacrificial source / drain structure comprises: The opening is formed by removing the sacrificial source / drain structure; During the removal of the sacrificial source / drain structure, a groove is formed by removing one end of the second semiconductor nanostructure; and the second source / drain structure is formed by growing the second semiconductor in the opening, including growing the second semiconductor in the groove.

12. The method of forming a semiconductor device as described in any one of claims 9 to 11 further includes: Before forming the second source / drain structure, a sacrificial gate is formed that covers and surrounds the second semiconductor nanostructure; And an active gate is formed by replacing the sacrificial gate.

13. A method for forming a semiconductor device, comprising: A first semiconductor nanostructure is formed corresponding to a channel region of a first transistor; A second semiconductor nanostructure is formed on the first semiconductor nanostructure and corresponding to a channel region of a second transistor; a first source / drain structure is formed adjacent to the first semiconductor nanostructure; and before forming the first source / drain structure: a sacrificial source / drain structure is formed adjacent to the second semiconductor nanostructure; and the sacrificial source / drain structure is replaced with a second source / drain structure, wherein the germanium concentration of the second source / drain structure exceeds the germanium concentration of the first source / drain structure.

14. A method of forming a semiconductor device as described in claim 13, wherein replacing the sacrificial source / drain structure comprises: A porous layer is formed on this sacrificial source / drain structure; An opening is formed by removing the sacrificial source / drain structure through the porous layer; And the second source / drain structure is formed in the opening.

15. A method of forming a semiconductor device as claimed in claim 14, wherein forming the second source / drain structure includes partially filling the opening with the second source / drain structure, the method further comprising: A source / drain junction is formed on the second source / drain structure, and an air gap exists between the source / drain junction and the second source / drain structure.

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