Bow mitigation in high aspect ratio oxide and nitride etches

Abstract

Semiconductor processing methods may include forming a plasma effluent. The plasma effluent may subsequently contact a carbon-containing hard mask and an oxide cap. The plasma effluent, passing through one or more slots in the carbon-containing hard mask, may etch one or more features in the oxide cap. The etching may create a tapered profile for the one or more features in the oxide cap. The one or more features may be characterized by a critical dimension at the bottom of the one or more features. The critical dimension may be less than or about 80% of the width of the one or more slots.

Description

Technical Field

[0001] This application claims the benefit of priority of U.S. Non - Provisional Application No. 18 / 482,384, filed on October 6, 2023, with the title "BOW MITIGATION IN HIGH ASPECT RATIO OXIDE AND NITRIDE ETCHES", which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present invention relates to semiconductor systems, processes, and equipment. More specifically, the present invention relates to etching processes in semiconductor manufacturing. Background Art

[0003] Integrated circuits are fabricated by processes that create a complex patterned material layer on a substrate surface. Creating a patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for various purposes, including transferring a pattern in a photoresist to an underlying layer, thinning a layer, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than another, facilitating, for example, a pattern transfer process. Due to the diversity of materials, circuits, and processes, etching processes have been developed with selectivity for various materials.

[0004] When etching features with a high aspect ratio, such as 3D NAND flash memories, bowing can occur. Significant bowing can lead to mechanical and / or structural instability in structures formed using high aspect ratio features. Furthermore, significant bowing can cause the critical dimensions between structures to become too wide to meet the specifications of a particular semiconductor design. Similarly, significant bowing can cause the final semiconductor device to become non - functional, reducing the yield during the manufacturing process.

[0005] Accordingly, there is a need for improved systems and methods that can be used to produce high - quality components and structures. These and other needs are met by the present invention. Summary of the Invention

[0006] In some embodiments, a semiconductor processing method may include forming a plasma effluent; contacting a carbon-containing hard mask with an oxide cap with the plasma effluent in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more gaps that permit the plasma effluent to enter the oxide cap; and etching one or more features that partially penetrate the oxide cap with the plasma effluent passing through the one or more gaps of the carbon-containing hard mask to create a tapered profile for the one or more features, the one or more features being characterized by a critical dimension at the bottom of the one or more features, wherein the critical dimension is less than or about 80% of the width of the one or more gaps.

[0007] In some embodiments, a semiconductor processing method may include forming a plasma effluent of a carbon- and fluorine-containing precursor; contacting a carbon-containing hard mask with an oxide cap with the plasma effluent in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more gaps that permit the plasma effluent to enter the oxide cap; and etching one or more features that partially penetrate the oxide cap with the plasma effluent passing through the one or more gaps of the hard mask to create a tapered profile for the one or more features, the one or more features being characterized by a critical dimension of less than or about 100 nm at the bottom of the one or more features.

[0008] In some embodiments, a semiconductor processing method may include forming a plasma effluent of a carbon- and fluorine-containing precursor; contacting a carbon-containing hard mask with an oxide cap with the plasma effluent in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more gaps that permit the plasma effluent to enter the oxide cap; etching one or more features that partially penetrate the oxide cap with the plasma effluent passing through the one or more gaps of the hard mask to create a tapered profile for the one or more features, the one or more features being characterized by a critical dimension at the bottom of the one or more features, wherein the tapered profile of the one or more features is characterized by a cone angle of less than or about 20 degrees; and using a main etch to etch the oxide cap and the plurality of alternating material layers such that the one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels.

[0009] In any embodiment, any and all of the following features may be implemented in any combination and without limitation. The critical dimension may be less than or about 70% of the width of one or more gaps. One or more features may be characterized by a critical dimension of less than or about 50 nm. The tapered profile of one or more features may be characterized by a cone angle of less than or about 30 degrees. The semiconductor processing method may further include etching one or more gaps in a carbon-containing hard mask to expose an oxide cap. The semiconductor processing method may further include etching one or more recesses in the oxide cap through one or more gaps, wherein one or more features are later formed within the one or more recesses. The semiconductor processing method may further include using a main etch to etch the oxide cap and a plurality of alternating material layers such that one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels. One or more channels may define a first stack and a second stack. A second critical dimension between the first stack and the second stack may be less than or about 130% of the critical dimension. The second critical dimension may be the maximum distance between the first stack and the second stack. The second critical dimension may be less than or about 65 nm. One or more gaps may be characterized by a width of less than or about 100 nm. The carbon- and fluorine-containing precursor may include CF4. Plasma effluent may be generated at a plasma power of about 5000 W or less. The bias voltage of the power supply of the semiconductor processing chamber may be about 5000 volts or less. Brief Description of the Drawings

[0010] By reference to the remainder of the specification and the drawings, the nature and advantages of various embodiments may be further understood, wherein like reference numerals indicate like components in several of the figures. In some instances, sub-labels are associated with the reference numerals to indicate one of a plurality of like components. When referring to a reference numeral without specifying an existing sub-label, it is intended to refer to all such plurality of like components.

[0011] FIG. 1 shows a diagrammatic cross-sectional view of an exemplary processing chamber according to some embodiments of the present invention.

[0012] FIG. 2 shows operations in a semiconductor processing method according to some embodiments of the present invention.

[0013] FIGS. 3A-3C show exemplary diagrammatic cross-sectional structures produced according to some embodiments of the present invention.

[0014] Several illustrations are included as subject matter. It will be understood that the illustrations are for illustrative purposes and are not to be taken as to scale unless expressly indicated as such. Additionally, as subject matter, the illustrations are provided to aid understanding and may not include all aspects or information compared to real-world representations, and may include exaggerated material for illustrative purposes.

[0015] In the accompanying illustrations, like parts and / or features may have the same element symbols. Further, various parts of the same type may be distinguished by a letter following the element symbol, the letter being used to distinguish similar parts. If only the primary element symbol is used in the description, the description may apply to any of the similar parts having the same primary element symbol, regardless of the letter. Embodiments

[0016] A breakthrough step between carbon mask etching and main channel hydrogen and fluorine-based etching in manufacturing a 3D NAND structure can be used to reduce bowing during main channel etching. The breakthrough step can include carbon and fluorine-based etching to create a tapered profile in an oxide cap between a carbon mask and an alternating layer of oxide and nitride in the 3D NAND structure. In some examples, the breakthrough step can be used to reduce the critical dimension in the oxide cap by 50% when compared to the critical dimension after carbon mask etching. In some examples, the breakthrough step can be used to adjust the critical dimension to a specific value to form a stack having a specific critical dimension during main channel etching.

[0017] During main channel etching in a 3D NAND manufacturing process, the channel is formed as a high aspect ratio feature. In the prior art, main channel etching causes bowing in the oxide and nitride layers, which increases the critical dimension between stacks. The increased critical dimension reduces yield as it causes mechanical and / or structural failures. Additionally, the increased critical dimension between stacks impedes the use of specific designs and additional technologies in the 3D NAND structure.

[0018] The present invention overcomes these problems by introducing a new step, a breakthrough step, during the processing of 3D NAND manufacturing. The breakthrough step can be after the carbon mask etching and can be before the main channel etching. The breakthrough step can create a tapered profile in the oxide cap with a specific critical dimension, especially a critical dimension smaller than the previous critical dimension created in the oxide cap by the carbon mask etching. By creating a tapered profile with a smaller critical dimension in the oxide cap, the critical dimensions in the oxide and nitride layers can be reduced and less bowing occurs. In addition, forming a smaller critical dimension in the oxide cap can be used to control the critical dimensions in the oxide and nitride layers such that the main channel etching can be adjusted with less consideration of the critical dimensions in the oxide and nitride layers. In this way, the parameters of the main channel etching can be focused on other design requirements rather than the critical dimensions in the oxide and nitride layers. Therefore, using the breakthrough step can also result in improved main channel etching. The breakthrough step can include forming a plasma effluent from carbon- and fluorine-containing precursors to etch the oxide cap.

[0019] Although the remaining disclosure will routinely specify particular semiconductor processing methods that utilize the disclosed techniques and will describe a semiconductor processing chamber, it can be readily understood that the described processing can be performed in any number of semiconductor processing chambers. Accordingly, the present invention should not be regarded as limited to use only in these particular deposition processes or chambers. Before describing a method of semiconductor processing in accordance with the present invention, the disclosure will discuss a possible chamber that can be used to perform the processes of embodiments in accordance with the present invention.

[0020] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 102 in a processing chamber 100. The exemplary processing chamber 100 is suitable for performing patterning processes, however, it will be understood that aspects of the present invention can be performed in any number of chambers and a substrate support in accordance with the present invention can be included in an etching chamber, a deposition chamber, a processing chamber, or any other process chamber. The plasma processing chamber 100 can include a chamber body 105 that defines a chamber volume 101 in which a substrate can be processed. The chamber body 105 can have sidewalls 112 and a bottom 118 that are coupled to ground 126. The sidewalls 112 can have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limited and are generally correspondingly larger than the size of the substrate 102 being processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, etc., as well as display or solar cell substrates.

[0021] The chamber body 105 may support the chamber lid assembly 110 to enclose the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. The substrate access port 113 may be formed through a sidewall 112 of the chamber body 105 to facilitate transfer of the substrate 102 into and out of the plasma processing chamber 100. The access port 113 may be coupled to a transfer chamber and / or other chambers of the previously described substrate processing system. The pumping port 145 may be formed through a sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to evacuate and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0022] The gas distribution plate 160 may be coupled to the chamber body 105 by a gas line 167 to supply process gas into the chamber volume 101. The gas distribution plate 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases, such as may be utilized for any number of processes. An example process gas is HF gas. Other examples of process gases that may be provided by the gas distribution plate 160 include, but are not limited to, hydrocarbon gases including methane, silicon tetrafluoride, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. Additionally, the process gas may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as any number of additional precursors such as H2, NH3, H2O, H2O2, NF3, F2, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, CHF3, CF3I, BCl3, PF3, PH3, SO2, and COS, etc.

[0023] Valve 166 can control the flow of process gas from sources 161, 162, 163, 164 of gas distribution plate 160 and can be managed by controller 165. The flow of gas supplied from gas distribution plate 160 to chamber body 105 can include a combination of gases from one or more sources. Cover assembly 110 can include nozzle 114. Nozzle 114 can be one or more ports for guiding process gas from sources 161, 162, 164, 163 of gas distribution plate 160 into chamber volume 101. After the process gas is introduced into plasma processing chamber 100, the gas can be energized to form plasma. An antenna 148, such as one or more inductor coils, can be provided adjacent to plasma processing chamber 100. Antenna power supply 142 can supply power to antenna 148 through matching circuit 141 to inductively couple energy, such as RF energy, to the process gas to maintain the plasma formed by the process gas in chamber volume 101 of plasma processing chamber 100. Alternatively, or in addition to antenna power supply 142, processing electrodes under and / or above substrate 102 can be used to capacitively couple RF power to the process gas to maintain plasma within chamber volume 101. The operation of power supply 142 can be controlled by a controller such as controller 165, which also controls the operation of other components in plasma processing chamber 100.

[0024] Substrate support pedestal 135 can be disposed in chamber volume 101 to support substrate 102 during processing. Substrate support pedestal 135 can include an electrostatic chuck 122 for holding substrate 102 during processing. Electrostatic chuck (「ESC」) 122 can use electrostatic attraction to hold substrate 102 to substrate support pedestal 135. ESC 122 can be powered by RF power supply 125 integrated with matching circuit 124. ESC 122 can include electrode 121 embedded in a dielectric body. Electrode 121 can be coupled to RF power supply 125 and can provide a bias voltage to ESC 122 and substrate 102 located on the pedestal, the bias voltage attracting plasma ions formed by the process gas in chamber volume 101. RF power supply 125 can cycle on and off, or pulse, during the processing of substrate 102. ESC 122 can have isolator 128 to make the sidewalls of ESC 122 less attractive to plasma to extend the maintenance life cycle of ESC 122. In addition, substrate support pedestal 135 can have a cathode pad 136 to protect the sidewalls of substrate support pedestal 135 from the plasma gas and extend the time between maintenance of plasma processing chamber 100.

[0025] The electrode 121 can be coupled to the power supply 150. The power supply 150 can provide a clamping voltage of about 5000 volts to about -5,000 volts to the electrode 121. The power supply 150 can also include a system controller for controlling the operation of the electrode 121, by guiding a DC current to the electrode 121 for clamping and releasing the substrate 102. For example, similar to the RF power supply 125, the power supply 150 can provide a bias voltage to the ESC 122 and the substrate 102 located on the pedestal, and the bias voltage attracts plasma ions formed by the processing gas in the chamber volume 101. The power supply 150 can be cycled on and off, or pulsed, during the processing of the substrate 102. In an embodiment, the power supply 150 can supply RF power, DC current or voltage, for clamping and / or biasing, or a combination of the foregoing. In additional embodiments, multiple power supplies can be provided to supply RF power and DC current or voltage for clamping and / or biasing. The ESC 122 can include a heater disposed within the pedestal and connected to the power supply for heating the substrate, and the cooling base 129 that supports the ESC 122 can include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 102 disposed thereon. The ESC 122 can be set to perform within the temperature range required by the thermal budget of the components fabricated on the substrate 102. For example, the ESC 122 can be set to maintain the substrate 102 at a temperature of about -150° C or lower to about 500° C or higher, depending on the processing performed.

[0026] The cooling base 129 can be provided to assist in controlling the temperature of the substrate 102. To mitigate processing drift and time, during the time period that the substrate 102 is in the cleaning chamber, the temperature of the substrate 102 can be maintained substantially constant by the cooling base 129. In some embodiments, the temperature of the substrate 102 can be maintained between about -150° C and about 500° C during subsequent cleaning processes, although any temperature can be utilized. The cover ring 130 can be disposed on the ESC 122 and along the perimeter of the substrate support pedestal 135. The cover ring 130 can be provided to confine the etching gas to the desired portion of the exposed top surface of the substrate 102, while shielding the top surface of the substrate support pedestal 135 from the plasma environment within the plasma processing chamber 100. The lift pins can be selectively actuated through the substrate support pedestal 135 to lift the substrate 102 above the substrate support pedestal 135 to facilitate access to the substrate 102 by a transfer robot or other suitable transfer mechanism as described above.

[0027] The controller 165 can be utilized to control the processing sequence, regulate the gas flow entering the plasma processing chamber 100 from the gas distribution plate 160, and other processing parameters. When implemented by the CPU, the software routine transforms the CPU into a dedicated computer such as a controller, which can control the plasma processing chamber 100 so that the processing is performed according to the present invention. The software routine can also be stored and / or implemented by a second controller, which can be associated with the plasma processing chamber 100.

[0028] The previously described chamber can be used in performing exemplary methods, including etching methods and processing methods. Turning to FIG. 2 shows exemplary operations in method 200 according to an embodiment of the present invention. Before the first operation of the method, the substrate can be processed in one or more ways (e.g., front-end process, deposition, etching, polishing, cleaning, or any other operation) before being placed in the processing area of the chamber capable of performing method 200. Some or all of these operations can be performed in the previously described chamber or system tool, or can be performed in different chambers on the same system tool, which can include the chamber in which the operations of method 200 are performed.

[0029] Method 200 can include several optional operations, which may or may not be explicitly associated with some embodiments of the method according to the present invention. For example, many operations are described to provide a broader scope of structure formation, but are not critical to the present invention, or can be performed by alternative methods to be further discussed later. Method 200 can be illustrated graphically in the operations shown in FIGS. 3A - 3C, and these drawings will be described in connection with the operations of method 200. It will be understood that FIGS. 3A - 3C only illustrate partial graphical views, and the substrate can contain any number of structural segments having aspects as depicted in the drawings, and alternative structural aspects that can still benefit from the operations of the present invention.

[0030] Method 200 can include or not include optional operations to develop the semiconductor structure 300 to a specific manufacturing operation. It will be understood that method 200 can be performed on any number of semiconductor structures 300, and FIG. 3A illustrates an exemplary structure on which an etching process can be performed. As shown in FIG. 3A, the processed semiconductor structure 300 can include alternating material layers 306 of oxide material 302 and nitride material 304. The oxide cap 308 can cover the alternating material layers 306. The mask 310 (which can also be referred to as a hard mask) can cover the oxide cap 308. In some instances, the alternating material layer can cover the substrate.

[0031] The alternating material layer 306 may include an oxide material 302 and a nitride material 304. The oxide material 302 may be any type of oxide, such as silicon oxide, silicon oxynitride, and the like. The nitride material 304 may be any nitride, such as silicon nitride. In some examples, the oxide material 302 may have a thicker layer than the nitride material 304. In some examples, the nitride material 304 may have a thicker layer than the oxide material 302. In some examples, the alternating material layer 306 may be characterized by a thickness less than or about 15000 nm, less than or about 14000 nm, less than or about 13000 nm, less than or about 12000 nm, less than or about 11000 nm, less than or about 10000 nm, less than or about 9000 nm, less than or about 8000 nm, less than or about 7000 nm, less than or about 6000 nm, less than or about 5000 nm, less than or about 4000 nm, less than or about 3000 nm, less than or about 2000 nm, less than or about 1000 nm, or less. In some examples, the alternating material layer 306 may be characterized by a thickness greater than or about 1000 nm, greater than or about 2000 nm, greater than or about 3000 nm, greater than or about 4000 nm, greater than or about 5000 nm, greater than or about 6000 nm, greater than or about 7000 nm, greater than or about 8000 nm, greater than or about 9000 nm, greater than or about 10000 nm, greater than or about 11000 nm, greater than or about 12000 nm, greater than or about 13000 nm, greater than or about 14000 nm, greater than or about 15000 nm, or greater. In some examples, each layer of the oxide material 302 may be characterized by a thickness less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. In some examples, each layer of the nitride material 304 may be characterized by a thickness less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less.

[0032] The oxide cap 308 may cover the alternating material layer 306. The oxide cap 308 can be any type of oxide. In some examples, the oxide cap 308 can be silicon oxide. In some examples, the oxide cap 308 may cover the oxide material 302 of the alternating material layer 306. In some examples, the oxide cap 308 may cover the nitride material 304 of the alternating material layer 306. In some examples, the oxide cap can be characterized as having a thickness less than or about 300 nm, less than or about 290 nm, less than or about 280 nm, less than or about 270 nm, less than or about 260 nm, less than or about 250 nm, less than or about 240 nm, less than or about 230 nm, less than or about 220 nm, less than or about 210 nm, less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, or less.

[0033] The mask 310 may cover the oxide cap 308. The mask 310 can be a carbon-containing mask. The mask 310 can be a hard mask. The mask 310 can be silicon carbide, amorphous carbon, or any other type of carbon-containing mask. In some examples, the mask 310 can be characterized as having a thickness less than or about 5000 nm, less than or about 4900 nm, less than or about 4800 nm, less than or about 4700 nm, less than or about 4600 nm, less than or about 4500 nm, less than or about 4400 nm, less than or about 4300 nm, less than or about 4200 nm, less than or about 4100 nm, less than or about 4000 nm, less than or about 3900 nm, less than or about 3800 nm, less than or about 3700 nm, less than or about 3600 nm, less than or about 3500 nm, less than or about 3400 nm, less than or about 3300 nm, less than or about 3200 nm, less than or about 3100 nm, less than or about 3000 nm, less than or about 2900 nm, less than or about 2800 nm, less than or about 2700 nm, less than or about 2600 nm, less than or about 2500 nm, less than or about 2400 nm, less than or about 2300 nm, less than or about 2200 nm, less than or about 2100 nm, less than or about 2000 nm, or less.

[0034] The semiconductor structure 300 of FIG. 3A can be created by a mask etch of mask 310. For example, the mask etch can etch mask 310 and oxide cap 308 to form one or more slits 312 in mask 310, as shown in FIG. 3A. The mask etch can also expose oxide cap 308 and form one or more features 314 in oxide cap 308 by etching oxide cap 308. The one or more features 314 can be characterized by a depth 316 and a critical dimension 318. In some instances, the critical dimension 318 can be a substantially same width such as the distance between adjacent portions of mask 310. In some instances, the critical dimension 318 can be substantially the width of one or more slits 312. In some instances, the depth of the one or more features 314 from the mask etch may not be sufficient to expose the alternating material layer 306. In some instances, the critical dimension 318 can be characterized as a width less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. In some instances, the depth 316 can be characterized as a depth less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less.

[0035] Operation 202 can be an optional operation of method 200. In some instances, method 200 can begin with operation 202. Operation 202 can include etching mask 310 and oxide cap 308 with a mask etch. The mask etch can etch mask 310 and oxide cap 308 to form one or more slits 312 and one or more features 314. The mask etch can include any suitable material for etching carbon-containing materials. In some instances, the mask etch can be plasma etch, wet etch, dry etch, or any other suitable etch.

[0036] In some instances, method 200 may begin at operation 204. At operation 204, method 200 may include forming a plasma effluent 350 of a carbon- and fluorine-containing precursor. In some instances, method 200 may begin at operation 204. In some instances, the method may begin at operation 202. For example, the carbon- and fluorine-containing precursor may include CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, CH3F, CH2F2, CHF3, and CF3I. In some instances, the breakthrough step may be referred to as starting at operation 204 and ending at operation 208.

[0037] The plasma effluent formed from the carbon- and fluorine-containing precursor may be formed locally in the processing region or formed in a remote plasma system. That is, the plasma effluent may be generated in the processing region of a semiconductor processing chamber that houses the semiconductor structure 300. Alternatively, the plasma effluent may be generated remotely and provided to the processing region of a semiconductor processing chamber that houses the semiconductor structure 300. For example, plasma processing may be generated by a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP) with or without one or more carrier gases such as argon (Ar), helium (He), NH3, nitrogen (N2), H2, or a mixture of the foregoing. The plasma effluent may be a low-order plasma to limit the amount of bombardment, sputtering, and surface modification. In an embodiment, the plasma power may be less than or about 5,000 W, less than or about 4,750 W, less than or about 4,500 W, less than or about 4,250 W, less than or about 4,000 W, less than or about 3,750 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, or less, although the plasma power may also be included in a range between any two of these recited numbers or in a smaller range encompassed by any of the recited ranges. By utilizing low-order plasma power, the plasma effluent may be better controlled for delivery through the slit 312 of the mask 310 while limiting sputtering of the mask 310 and other exposed surfaces.

[0038] During operation 204, the volume ratio of the carbon- and fluorine-containing precursors relative to other gases can be less than or about 20:1. In some examples, the volume ratio of the hydrogen- and fluorine-containing precursors relative to other gases can be less than or about 15:1, less than or about 10:1, less than or about 5:1, less than or about 4:1, less than or about 3:1, less than or about 2:1, less than or about 1:1, or a range of volume ratios such as 1:1 to 20:1, 10:1 to 15:1, or 1:1 to 5:1. In some examples, there can be substantially no other gases during the formation of the plasma effluent. In some examples, when forming the plasma effluent, there is one or more carrier gases. The volume ratio of the hydrogen- and fluorine-containing precursors can affect the corresponding critical dimension 320. For example, increasing the volume ratio of the hydrogen- and fluorine-containing precursors can result in a smaller critical dimension 320.

[0039] In operation 206, method 200 can include contacting the hard mask 310 and the oxide cap 308 with the plasma effluent in the processing region of the semiconductor processing chamber. In operation 208, the contact of the oxide cap 308 with the plasma effluent can cause the etching of the oxide cap 308, as shown in FIG. 3B. The etching of the oxide cap 308 (and potentially other layers) can be referred to as a breakthrough step or breakthrough etch. The plasma effluent can etch a tapered profile into the oxide cap 308, with a critical dimension 320 at the bottom of the tapered profile of one or more features 314 in the oxide cap 308. The critical dimension 320 can be less than the width of one or more gaps 312 and / or the width of one or more features at the top of the oxide cap 308. In some examples, the hard mask 310 can also be etched by the plasma effluent. In some examples, the oxide cap 308 can be etched such that the alternating material layer 306 is not exposed. In some examples, the oxide cap 308 is etched such that the alternating material layer 306 is not etched. In some examples, the oxide cap 308 can be etched such that one or more features 314 do not extend through the oxide cap 308. In some examples, the oxide cap 308 can be etched such that one or more features 314 expose the alternating material layer 306. In some examples, the breakthrough etch can extend one or more features 314 into the alternating material layer 306 such that the critical dimension 320 can be formed by etching the alternating material layer 306. The etch time of operation 208 can affect the corresponding critical dimension 320. For example, increasing the etch time can result in a smaller critical dimension 320.

[0040] In some instances, the critical dimension 320 may be characterized as a percentage dimension of the width of one or more of the slots 312 and / or one or more features at the top of the oxide cap 308. In some instances, the critical dimension 320 may be characterized as a percentage of the width of one or more of the slots 312 and / or the width of one or more features at the top of the oxide cap 308, such that the critical dimension 320 is less than or about 95% of the width of one or more of the slots 312, and / or the width of one or more features at the top of the oxide cap 308, less than or about 90%, less than or about 85%, less than or about 80%, less than or about 75%, less than or about 70%, less than or about 65%, less than or about 60%, less than or about 55%, less than or about 50%, less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, less than or about 5%, or less. The percentage may range between 5% and 95%, or any combination of sub-ranges (e.g., 32 - 58%), or any percentage in between (e.g., 6.2% and 83.9%).

[0041] In some instances, the critical dimension 320 may be characterized by a width. In some instances, the critical dimension 320 may be characterized as having a width less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. The width may range between 10 nm and 200 nm, or any combination of sub-ranges (e.g., 73 nm to 144 nm), or any value in between (e.g., 27 nm and 166 nm).

[0042] In some examples, the critical dimension 320 can be characterized as a width reduction compared to the width of one or more gaps 312 and / or the width of one or more features at the top of the oxide cap 308. In some examples, the critical dimension 320 can be characterized as a width reduction compared to the width of one or more gaps 312 and / or the width of one or more features at the top of the oxide cap 308 that is less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or smaller. The width reduction compared to the width of one or more gaps 312 and / or the width of one or more features at the top of the oxide cap 308 can be in the range between 10 nm and 200 nm, or any combination of sub-ranges therein (e.g., 73 nm to 144 nm), or any value therebetween (e.g., 27 nm and 166 nm).

[0043] In some examples, the tapered profile of one or more features 314 can be characterized as a taper angle relative to the bottom of the tapered profile of the one or more features 314 in the oxide cap 308. In some examples, the taper angle relative to the bottom of the tapered profile of the one or more features 314 in the oxide cap 308 can be characterized as an angle of about or less than 85 degrees, about or less than 80 degrees, about or less than 75 degrees, about or less than 70 degrees, about or less than 65 degrees, about or less than 60 degrees, about or less than 55 degrees, about or less than 50 degrees, about or less than 45 degrees, about or less than 40 degrees, about or less than 35 degrees, about or less than 30 degrees, about or less than 25 degrees, about or less than 20 degrees, about or less than 15 degrees, about or less than 10 degrees, about or less than 5 degrees, or smaller. The angle can be in the range between 5 degrees and 85 degrees, or any combination of sub-ranges therein (e.g., 42 degrees to 66 degrees), or any angle therebetween (e.g., 33 degrees and 72 degrees).

[0044] Operation 210 can be an optional operation of method 200. In operation 210, the oxide, cap, and oxide material 302 and nitride 304 of the alternating material layer 306 can be etched. For example, a main etch (also referred to as a main channel etch) can be used to etch through the oxide cap 308, the oxide material 302 and nitride 304 of the alternating material layer 306. The main etch can be a hydrogen and fluorine-based etch. In some examples, the main etch can be plasma etch, wet etch, dry etch, or any other suitable etch. After the main etch has been applied to the semiconductor structure 300, one or more features 312 can extend through the mask 310, the oxide cap 308, and the alternating material layer 306 to form one or more channels. One or more channels can be characterized by a high aspect ratio of depth to width such that the depth of the channel is significantly greater than the width. For example, the aspect ratio of one or more channels can be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater. In some examples, one or more channels can be characterized by a bowing between adjacent stacked alternating material layers 306. The bowing can refer to a dish-shaped horizontal recess along the sidewalls of the channel in the alternating material layer 306. The horizontal recess can be characterized by a bow depth from the face of the channel to the most recessed point of the horizontal recess. A critical dimension 322 between the most recessed points of adjacent horizontal recesses can be used to characterize this channel. The above breakthrough step can cause the critical dimension 322 to become smaller. For example, for every 1 nm of taper (e.g., the taper can refer to the difference between the width at the top of the feature 314 and the critical dimension 320) from the top of the feature 314 to the critical dimension 320 during operation 208, the critical dimension 322 can be reduced by less than or about 1 nm. In some examples, for every 1 nm of taper from the top of the feature 314 to the critical dimension 320 during operation 208, the critical dimension 322 can be reduced by less than or about 0.9 nm, less than or about 0.8 nm, less than or about 0.7 nm, less than or about 0.6 nm. In some examples, for every 1 nm of taper from the top of the feature 314 to the critical dimension 320 during operation 208, the critical dimension 322 can be reduced by greater than or about 1 nm, greater than or about 1.1 nm, greater than or about 1.2 nm, greater than or about 1.3 nm, greater than or about 1.4 nm, greater than or about 1.5 nm, greater than or about 1.6 nm, greater than or about 1.7 nm, greater than or about 1.8 nm, greater than or about 1.9 nm, greater than or about 2.0 nm, or greater.

[0045] In some instances, the critical dimension 322 can be characterized as a percentage dimension of one or more of the gaps 312 and / or the width of one or more features at the top of the oxide cap 308. In some instances, the critical dimension 322 can be characterized as a percentage of the width of one or more of the gaps 312 and / or the width of one or more features at the top of the oxide cap 308 such that the critical dimension 320 is less than or about 200% of the width of one or more of the gaps 312 and / or the width of one or more features at the top of the oxide cap 308, less than or about 195%, less than or about 190%, less than or about 185%, less than or about 180%, less than or about 175%, less than or about 170%, less than or about 165%, less than or about 160%, less than or about 155%, less than or about 150%, less than or about 145%, less than or about 140%, less than or about 135%, less than or about 130%, less than or about 125%, less than or about 120%, less than or about 115%, less than or about 110%, less than or about 105%, less than or about 100%, or less. The percentage can range between 100% and 130%, or any combination of ranges therein (e.g., 102 - 107%), or any percentage therebetween (e.g., between 113% and 104%).

[0046] In some instances, the critical dimension 322 can be characterized by a width. In some instances, the critical dimension 322 can be characterized as having a width that is less than or about 250 nm, less than or about 240 nm, less than or about 230 nm, less than or about 220 nm, less than or about 210 nm, less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. The width can range between 10 nm and 250 nm, or any combination of ranges therein (e.g., 48 nm to 212 nm), or any value therebetween (e.g., between 63 nm and 222 nm).

[0047] In some instances, the critical dimension 322 can be characterized as a width difference from the width of one or more of the slits 312 and / or the width of one or more features at the top of the oxide cap 308. The critical dimension 322 can be greater than the width of one or more of the slits 312 and / or the width of one or more features at the top of the oxide cap 308. In some instances, the critical dimension 322 can be characterized as having a width difference from the width of one or more of the slits 312 and / or the width of one or more features at the top of the oxide cap 308 that is less than or about 250 nm, less than or about 240 nm, less than or about 230 nm, less than or about 220 nm, less than or about 210 nm, less than or about 200 nm, less than or about 190 nm, less than or about 180 nm, less than or about 170 nm, less than or about 160 nm, less than or about 150 nm, less than or about 140 nm, less than or about 130 nm, less than or about 120 nm, less than or about 110 nm, less than or about 100 nm, less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. The width difference from the width of one or more of the slits 312 and / or the width of one or more features at the top of the oxide cap 308 can be in the range between 10 nm and 250 nm, or any sub-range combination therein (e.g., 10 nm to 30 nm), or any value therebetween (e.g., 66 nm and 213 nm).

[0048] During any of operations 204, 206, and / or 208 of method 200, a bias voltage can be applied to semiconductor structure 300. In some instances, the bias voltage can be less than or about 5,000 V, less than or about 4,500 V, less than or about 4,000 V, less than or about 3,500 V, less than or about 3,000 V, less than or about 2,500 V, less than or about 2,000 V, less than or about 1,500 V, less than or about 1,000 V, or less, however the clamping voltage can also be included in the range between any two of these values or within any smaller range encompassed by any of the stated ranges. The bias voltage can affect the critical dimension 320. For example, reducing the bias voltage can result in a smaller critical dimension 320.

[0049] During any of operations 204, 206, and / or 208 of method 200, a clamping voltage of a power supply may be applied to semiconductor structure 300. In some examples, the clamping voltage may be less than or about 5,000 V, less than or about 4,500 V, less than or about 4,000 V, less than or about 3,500 V, less than or about 3,000 V, less than or about 2,500 V, less than or about 2,000 V, less than or about 1,500 V, less than or about 1,000 V, or less, although the bias voltage may also be in a range between any two of these values or within any smaller range encompassed by any of the stated ranges.

[0050] Each of the operations of method 200 may be performed during a fixed temperature in an embodiment, although in some embodiments the temperature may be adjusted during different operations. For example, the substrate, pedestal, or chamber temperature during method 200 may be maintained at a temperature less than or about 100° C, less than or about 90° C, less than or about 80° C, and in some embodiments, the temperature may be maintained less than or about 70° C, less than or about 60° C, less than or about 50° C, less than or about 30° C, less than or about 20° C, less than or about 10° C, less than or about 0° C, less than or about -10° C, less than or about -20° C, less than or about -30° C, less than or about -40° C, less than or about -50° C, or less. The temperature may be in a range between 100° C and -50° C, or any combination of sub-ranges therein (e.g., 20° C to 40° C), or any value therebetween (e.g., -7° C and 31° C).

[0051] During method 200, the pressure within the processing chamber can be controlled. For example, when forming a local plasma and performing a removal operation, the pressure within the processing chamber can be maintained below or about 1 Torr. Additionally, in embodiments, the pressure within the processing chamber can be maintained below or about 1 Torr, below or about 500 mTorr, below or about 250 mTorr, below or about 200 mTorr, below or about 150 mTorr, below or about 100 mTorr, below or about 95 mTorr, below or about 90 mTorr, below or about 85 mTorr, below or about 80 mTorr, below or about 75 mTorr, below or about 705 mTorr, below or about 65 mTorr, below or about 60 mTorr, below or about 55 mTorr, below or about 50 mTorr, below or about 45 mTorr, below or about 40 mTorr, below or about 35 mTorr, below or about 30 mTorr, below or about 25 mTorr, below or about 20 mTorr, below or about 15 mTorr, below or about 10 mTorr, below or about 5 mTorr, below or about 4 mTorr, below or about 3 mTorr, below or about 2 mTorr, below or about 1 mTorr, or lower. The pressure can be in the range between 1 mTorr and 1 Torr, or any combination of sub-ranges therein (e.g., 5 mTorr to 100 mTorr), or any value therebetween (e.g., 650 mTorr and 8 mTorr). The pressure within the processing chamber can affect the ability to flow into the gap. For example, as the pressure increases, it becomes more difficult for the plasma effluent to penetrate the gap 320 to reach the hard mask 315. Thus, in some embodiments, the pressure can be maintained below or about 30 mTorr to allow the effluent to flow into the gap 320 and features 355 etched in the hard mask 315 on the organic material 310.

[0052] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of the various embodiments of the invention. However, certain embodiments may be practiced by those of ordinary skill in the art without some of these details and with additional details.

[0053] Having disclosed several embodiments, those of ordinary skill in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, several well-known processes and elements have not been described in order to avoid unnecessarily obscuring the invention. Accordingly, the foregoing description should not be construed as limiting the scope of the invention. Moreover, a method or process may be described as sequential or in steps, but it will be understood that the operations can be performed concurrently or in an order different from that listed.

[0054] Where numerical ranges are provided, unless the context clearly dictates otherwise, it is understood that each intermediate value between the upper and lower limits of the range, to the smallest unit of the lower limit's unit, is also expressly disclosed. Any narrower range between any stated value or unstated intermediate value in the stated range, as well as any other stated or intermediate value in the stated range, is also included. The upper and lower limits of those smaller ranges may be independently included or excluded within the range, and each range that includes any one of the limits, excludes any one of the limits, or includes both limits within the invention is also included, depending on any expressly excluded limits in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of the included limits are also included.

[0055] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural forms unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes plural such precursors, and reference to "the layer" includes reference to one or more layers and equivalents known to those of ordinary skill in the art, and so forth.

[0056] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and the subsequent claims, are intended to specify the presence of the stated feature, integer, component, or operation, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

[0057] 100: Processing chamber 101: Chamber volume 102: Substrate 105: Chamber body 110: Cover assembly 112: Side wall 113: Access port 114: Nozzle 115: Gasket 118: Bottom 121: Electrode 122: Electrostatic chuck ("ESC") 124: Matching circuit 125: RF power supply 126: Grounding 128: Isolator 129: Cooling substrate 130: Cover ring 135: Substrate support pedestal 136: Cathode pad 141: Matching circuit 142: Antenna power supply 145: Pumping port 148: Antenna 150: Power supply 160: Gas distribution plate 161,162,163,164: Process gas source 165: Controller 166: Valve 167: Gas line 200: Method 202,204,206,208,210: Operation 300: Semiconductor structure 302: Oxide material 304: Nitride material 306: Alternating material layer 308: Oxide cap 310: Mask 312: Gap 314: Feature 316: Depth 318: Critical dimension 320: Critical dimension 322: Critical dimension

[0058] Domestic deposit information (Please note in the order of deposit institution, date, number) None Foreign deposit information (Please note in the order of deposit country, institution, date, number) None

Claims

1. A semiconductor processing method comprising: forming a plurality of plasma effluents; contacting the plasma effluents with a carbon-containing hard mask and an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slits that allow the plasma effluents to enter the oxide cap; and etching one or more features partially through the oxide cap by means of the plasma effluents passing through the one or more slits of the carbon-containing hard mask to create a tapered profile of the one or more features, the one or more features being characterized by a critical dimension at the bottom of the one or more features, wherein the critical dimension is less than or about 80% of the width of the one or more slits.

2. The semiconductor processing method as described in claim 1, wherein the critical dimension is less than or about 70% of the width of the one or more slits.

3. The semiconductor processing method as claimed in claim 1, wherein the one or more features are characterized by a critical dimension of less than or about 50 nm.

4. The semiconductor processing method as claimed in claim 1, wherein the tapered profile of the one or more features is characterized by a tapered angle of less than or about 30 degrees.

5. The semiconductor processing method as claimed in claim 1, further comprising: etching one or more gaps in the carbon-containing hard mask to expose the oxide cap; and etching one or more recesses in the oxide cap through the one or more gaps, wherein the one or more features are subsequently formed within the one or more recesses.

6. The semiconductor processing method as claimed in claim 1, further comprising: using a master etching to etch the oxide cap and the plurality of alternating material layers such that the one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels.

7. The semiconductor processing method as claimed in claim 6, wherein the one or more channels define a first stack and a second stack, and wherein a second critical dimension between the first stack and the second stack is less than or about 130% of the critical dimension.

8. The semiconductor processing method as described in claim 7, wherein the second critical dimension is a maximum distance between the first stack and the second stack.

9. The semiconductor processing method as described in claim 8, wherein the second critical dimension is less than or about 65 nm.

10. The semiconductor processing method as claimed in claim 1, wherein the oxide cap has a thickness of less than or about 100 nm.

11. The semiconductor processing method as claimed in claim 1, wherein the one or more gaps are characterized by a width of less than or about 100 nm.

12. The semiconductor processing method as claimed in claim 1, wherein a carbon- and fluorine-containing precursor is used to form the plasma effluents.

13. The semiconductor processing method as described in claim 12, wherein the carbon and fluorine-containing precursor comprises CF4.

14. The semiconductor processing method as claimed in claim 1, wherein the plasma effluents are generated at a plasma power of about 5000 W or less.

15. The semiconductor processing method as claimed in claim 1, wherein a bias voltage of a power supply to the semiconductor processing chamber is about 5000 volts or less.

16. A semiconductor processing method comprising: forming a plurality of plasma effluents containing a carbon and a fluorine precursor; contacting the plasma effluents with a carbon-containing hard mask and an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slits that allow the plasma effluents to enter the oxide cap, wherein the one or more slits are characterized by a width of less than or about 120 nm; and etching one or more features partially through the oxide cap by means of the plasma effluents passing through the one or more slits of the hard mask to create a tapered profile of the one or more features, the one or more features being characterized by a critical dimension of less than or about 100 nm at the bottom of the one or more features.

17. The semiconductor processing method of claim 16, further comprising: forming the carbon-containing hard mask covering the oxide cap; etching the one or more gaps in the carbon-containing hard mask to expose the oxide cap; and partially etching the oxide cap to form the one or more features.

18. A semiconductor processing method comprising: forming a plurality of plasma effluents containing a carbon and a fluorine precursor; contacting the plasma effluents with a carbon-containing hard mask and an oxide cap in a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support in the processing region, wherein a plurality of alternating material layers cover the substrate, wherein the oxide cap covers the plurality of alternating material layers, and the carbon-containing hard mask covers the oxide cap, wherein the carbon-containing hard mask has one or more slits that allow the plasma effluents to enter the oxide cap; The plasma effluent is etched through one or more gaps in the hard mask to partially etch one or more features through the oxide cap to create a tapered profile of the one or more features, characterized by a key dimension at the bottom of the one or more features, wherein the tapered profile of the one or more features is characterized by a taper angle of less than or about 20 degrees; and a master etching is used to etch the oxide cap and the plurality of alternating material layers such that the one or more features extend through both the oxide cap and the plurality of alternating material layers to form one or more channels.

19. The semiconductor processing method as claimed in claim 18, wherein the one or more features are characterized by a critical dimension of a width of less than or about 90% of the one or more gaps.

20. The semiconductor processing method as claimed in claim 18, wherein the one or more channels define a first stack and a second stack, and wherein a second critical dimension between the first stack and the second stack is less than or about 100 nm.

Images