Semiconductor device structure and methods of forming the same

Abstract

A semiconductor device structure and a method for forming the same are described. In some embodiments, the structure includes a first region, a second region, and a boundary region disposed between the first region and the second region. The first region includes a gate electrode disposed above a semiconductor fin. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed above the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. A top surface of the second conductive layer and a top surface of the gate electrode may be substantially coplanar.

Description

Technical Field

[0001] None Prior Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid development. In most cases, the increase in integration density is caused by the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. However, this reduction also increases the complexity of the semiconductor manufacturing process. Therefore, achieving continuous advancement of semiconductor ICs and devices requires similar advancement of semiconductor manufacturing processes and technologies. Summary of the Invention

[0003] None Brief Description of the Drawings

[0004] Various aspects of the present disclosure can be best understood when reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. [] FIGS. 1A to 1C, FIGS. 2A to 2B, FIGS. 3A to 3B, FIGS. 4A to 4B, FIGS. 5A to 5B, and FIGS. 6A to 6B are various views of respective intermediate structures at intermediate stages in an exemplary process of forming a semiconductor device structure according to some embodiments. [] FIGS. 7A to 7B are various views of respective intermediate structures at an intermediate stage between FIGS. 6A and 6B in an exemplary process of forming a semiconductor device structure according to some embodiments. FIGS. 8 and 9 are cross-sectional views of intermediate structures at an intermediate stage in an exemplary process of forming a semiconductor device structure according to some embodiments. FIGS. 10A to 10B are various views of a metal-insulator-metal (MIM) structure of FIG. 9 according to some embodiments. [] FIGS. 11A to 11B are various views of a MIM structure of FIG. 9 according to an alternative embodiment. [] FIGS. 12A to 12B are various views of a MIM structure of FIG. 9 according to an alternative embodiment. [] FIG. 13A to FIG. 13C are cross-sectional side views of an intermediate structure of the MIM structure of FIGS. 12A to 12B according to some embodiments. [] FIG. 14A to FIG. 14C are various views of the MIM structure according to some embodiments. [] FIG. 15A to FIG. 15D, FIG. 16A to FIG. 16B, FIG. 17A to FIG. 17B, FIG. 18A to FIG. 18B, and FIG. 19A to FIG. 19B are various views of respective intermediate structures at intermediate stages in an example process of forming a semiconductor device structure including the MIM structure of FIGS. 14A to 14C according to some embodiments. [] FIG. 20A to FIG. 20B are top views of the MIM structure of FIGS. 11A to 11B or the MIM structure of FIGS. 19A to 19B according to alternative embodiments. [] FIG. 21A to FIG. 21C are cross-sectional views of an intermediate structure at an intermediate stage in an example process of forming a semiconductor device structure according to some embodiments. FIG. 22A to FIG. 22C are cross-sectional views of an intermediate structure at an intermediate stage in an example process of forming a semiconductor device structure according to some embodiments. FIG. 23A to FIG. 23B are various views of the MIM structure according to alternative embodiments. [] Embodiments

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and configurations to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "on top of", "on", "top", "upper", and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0007] Figures 1A to 22B illustrate a process for manufacturing a semiconductor device structure 40 according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the process shown in Figures 1A to 22B, and for additional embodiments of the method, some of the operations described below may be replaced or excluded. The order of the operations / processes is not restrictive and may be interchanged. []

[0008] Figures 1A, 1B, and 1C illustrate different views of an intermediate structure at stages in an exemplary process for forming a semiconductor device structure 40 according to some embodiments. Figures 1A and 1B are different cross-sectional views of the intermediate structure, and Figure 1C is a perspective view of the intermediate structure.

[0009] As shown in Figures 1A to 1C, the fin 74 is formed from a semiconductor substrate 70. The fin 74 is a semiconductor fin. Isolation regions 78 are disposed on the semiconductor substrate 70 and between adjacent fins 74. Each fin 74 projects above and between adjacent isolation regions 78. A sacrificial gate stack (or more generally, a sacrificial gate structure) is formed along the sidewalls of the fins 74 and above the top surfaces of the fins 74, each including a dielectric layer 80, a sacrificial gate layer 82, and a mask 84. Source / drain regions 52a-f are located in respective regions of the fins 74.

[0010] Figure 1C further illustrates reference cross-sections for other figures. Cross-section A-A is in a plane along the fin 74. Cross-section B-B is in a plane perpendicular to cross-section A-A and across source / drain regions 52a and 52d adjacent to the fins 74. For clarity, each figure refers to these reference cross-sections. Figures in Figures 1A to 6B ending with the label "A" illustrate cross-sectional views in various processing situations corresponding to cross-section A-A, while figures in Figures 1A to 6B ending with the label "B" illustrate cross-sectional views in various processing situations corresponding to cross-section B-B.

[0011] The semiconductor substrate 70 can be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, and it can be doped (e.g., doped with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate can include an elemental semiconductor that includes silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

[0012] The fin 74 can be formed from the semiconductor substrate 70, such as by etching trenches between the fins 74. An isolation region 78 can be formed in the trenches between the fins 74. The isolation region 78 can include or be an insulating material, such as an oxide (such as silicon oxide), a nitride, the like, or a combination thereof. The fins 74 protrude from between the adjacent isolation regions 78, whereby this can at least partially label the fins 74 as active regions on the semiconductor substrate 70. The fins 74 and the isolation region 78 can be formed by any acceptable process and can include any acceptable materials. In some examples, the fins 74 can include a heteroepitaxial structure (e.g., a material lattice mismatched with the semiconductor material of the semiconductor substrate 70) or other structures.

[0013] A sacrificial gate stack is formed over the fin 74 and extends laterally perpendicular to the fin 74. Each sacrificial gate stack includes a dielectric layer 80, a sacrificial gate layer 82, and a mask 84. The dielectric layer 80 can include or be silicon oxide, silicon nitride, the like, or a multilayer thereof. The sacrificial gate layer 82 can include or be silicon (e.g., polysilicon) or another material. The mask 84 can include or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof. Any acceptable process can be used to deposit and pattern the layer for the mask 84, the sacrificial gate layer 82, and the dielectric layer 80 into the sacrificial gate stack to form the mask 84, the sacrificial gate layer 82, and the dielectric layer 80 of each sacrificial gate stack.

[0014] FIGS. 2A and 2B illustrate the formation of a first gate spacer layer 86 along the sidewalls and top surface of the sacrificial gate stack and fin 74. The first gate spacer layer 86 is conformally deposited along the sidewalls and top surface of the fin 74 and the sacrificial gate stack (e.g., along the sidewalls of the dielectric layer 80, the sacrificial gate layer 82, and the mask 84 and on the top surface of the mask 84) and on the top surface of the isolation region 78. The first gate spacer layer 86 can be or include silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or another material. In some examples, an atomic layer deposition (ALD) process can be used to deposit the first gate spacer layer 86, but other deposition techniques can be used. In some embodiments, the first gate spacer layer 86 can be omitted.

[0015] FIGS. 3A and 3B illustrate the formation of a second gate spacer layer 88. The second gate spacer layer 88 is conformally deposited on the first gate spacer layer 86. The second gate spacer layer 88 is a dielectric layer including silicon, oxygen, nitrogen, and carbon. In some embodiments, the second gate spacer layer 88 can be or include silicon oxycarbonitride (SiOCN). The second gate spacer layer 88 can be deposited by an ALD process.

[0016] FIGS. 4A and 4B illustrate the formation of a gate spacer including respective portions of the first gate spacer layer 86 and the second gate spacer layer 88. A gate spacer (e.g., a bilayer gate spacer as illustrated) is formed along the sidewalls of the gate stack (e.g., the sidewalls of the dielectric layer 80, the sacrificial gate layer 82, and the mask 84) and over the fin 74. For example, depending on the height of the fin 74 over the isolation region 78, residual gate spacers can also remain along the sidewalls of the fin 74. The gate spacer can be formed by anisotropically etching the second gate spacer layer 88 and the first gate spacer layer 86. The etching process can include RIE, NBE, or another etching process. In other embodiments, the multilayer gate spacer can include additional and / or different layers and / or materials.

[0017] Figures 5A and 5B illustrate the formation of the source / drain regions 92. A recess is formed in the fin 74 on the opposite side of the sacrificial gate stack, and the source / drain regions 92 are formed in the recess. The recess can be achieved by an etching process. The etching process can be isotropic or anisotropic, or alternatively, can be selective with respect to one or more crystal planes of the semiconductor substrate 70. As shown in Figures 5A and 5B, an epitaxial source / drain region 92 can be formed in the recess. The epitaxial source / drain region 92 can comprise or can be silicon germanium, silicon carbide, silicon phosphorous, a group III-V compound semiconductor, a group II-VI compound semiconductor, or the like. The epitaxial source / drain region 92 can be formed in the recess by epitaxially growing a material in the recess, such as by metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. The epitaxial source / drain region 92 can extend beyond the sidewalls and the top surface (e.g., bulge) of the fin 74 and can have facets that can correspond to the crystal planes of the semiconductor substrate 70. In some examples, different materials are used for the epitaxial source / drain regions 92 for p-type devices and n-type devices. Appropriate masking during the recessing or epitaxial growth can allow different materials to be used in different devices. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are substantially the same. Additionally, depending on the context, either alone or jointly, the source / drain region can refer to the source or the drain.

[0018] As shown in Figures 6A and 6B, after the source / drain regions 92 are formed, a contact etch stop layer (CESL) 96 is conformally deposited on the surface of the epitaxial source / drain region 92, the sidewalls and the top surface of the multi-layer gate spacer, the top surface of the mask 84, and the top surface of the isolation region 78 by any acceptable process. Generally, an etch stop layer can provide a mechanism for terminating an etching process when forming, for example, a contact or a via. The etch stop layer can be formed of a dielectric material having a different etch selectivity from an adjacent layer or component. The CESL 96 can comprise silicon nitride, silicon carbonitride, the like, or a combination thereof.

[0019] A first interlayer dielectric (ILD) 100 can be formed over the CESL 96. The first ILD 100 can comprise or can be silicon dioxide, a low-k dielectric material such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiOxCy, spin-on glass, spin-on polymer, silicon carbide material, their compounds, their composites, the like, or combinations thereof. The first ILD 100 can be deposited by any acceptable process.

[0020] The first ILD 100 and the CESL 96 form a top surface coplanar with the top surface of the sacrificial gate layer 82. A planarization process such as chemical mechanical polishing (CMP) can be performed to make the top surfaces of the first ILD 100 and the CESL 96 flush with the top surface of the sacrificial gate layer 82. The CMP can also remove the mask 84 on the sacrificial gate layer 82 (and in some cases, remove the upper portion of the multi-gate spacer). Thus, the top surface of the sacrificial gate layer 82 is exposed via the first ILD 100 and the CESL 96, as shown in FIGS. 6A and 6B. In some embodiments, after the CMP process, the first ILD 100 can be recessed, and a dielectric material (not shown) can be formed over the first ILD 100. The dielectric material can be a nitride such as silicon nitride. Another planarization process can be performed such that the top surface of the dielectric material can be substantially coplanar with the top surface of the sacrificial gate layer 82. The dielectric material can protect the first ILD 100 during subsequent processes.

[0021] FIG. 7A to FIG. 7B are cross-sectional views of respective intermediate structures at an intermediate stage between FIG. 6A and FIG. 6B in an exemplary process of forming the semiconductor device structure 40 according to some embodiments. As shown in FIG. 7A, the semiconductor device structure 40 includes a first IP block 102-1 and a second IP block 102-2. An IP block is a reusable unit of a logic, cell, or IC layout design, which is the intellectual property of a party or a vendor. An IC designer can use these IP blocks as building blocks. The first IP block 102-1 is a reusable unit of a logic, cell, or IC layout design; the second IP block 102-2 is another reusable unit of a logic, cell, or IC layout design. In one example, the first IP block 102-1 is a static random access memory (SRAM) IP block, and the second IP block 102-2 is another SRAM IP block. The density of the gate structures (or sacrificial gate structures) in these SRAM IP blocks is relatively high. It should be understood that the example shown in FIG. 7A is illustrative and not restrictive, and in other embodiments, the semiconductor device structure 40 may include more than two IP blocks.

[0022] As shown in FIG. 7A, the boundary region 104 is located between the first IP block 102-1 and the second IP block 102-2 in the first horizontal direction (i.e., the X direction). In some embodiments, the fin 74 extends continuously from the first IP block 102-1 through the boundary region 104 and into the second IP block 102-2. In some embodiments, the continuous fin 74 can be patterned to form discrete fins 74 in the first IP block 102-1, the boundary region 104, and the second IP block 102-2. Whether the fins 74 are continuous or discrete, the fins 74 in the first IP block 102-1 and the second IP block 102-2 can be the same fins 74 as those in the boundary region 104 because the fins 74 in the first IP block 102-1, the second IP block 102-2, and the boundary region 104 are formed simultaneously. As shown in FIG. 7B (which is a top view of the semiconductor device structure 40 of FIG. 7A), the boundary region 104 has a width in the first horizontal direction (i.e., the X direction) and a length in the second horizontal direction (i.e., the Y direction). In one example, the width of the boundary region 104 is between 0.1 µm and 3.0 µm. Compared with the density of the gate structures in the IP block, the density of the gate structures (or dummy gate structures) in the boundary region 104 is relatively low. FIG. 7A illustrates that the density of the dummy gate layer 82 representing the dummy gate structure in the IP blocks 102-1, 102-2 is greater than the density of the dummy gate layer 82 in the boundary region 104. For clarity, the gate spacer layers 86, 88, the dielectric layer 80, the fins 74, and the semiconductor substrate 70 are omitted in FIG. 7A. In some embodiments, during the replacement gate (RPG) process, the CMP dishing effect can cause under-polishing defects in an integrated circuit (IC) having two or more IP blocks and the boundary region therebetween. For example, the metal gate replacing the dummy gate layer in the IP block adjacent to the boundary region can have a height substantially smaller than the height of the metal gate located at the center of the IP block.

[0023] It should be understood that the range from 0.1 µm to 3.0 µm is not arbitrarily selected. For boundary regions wider or longer than 3.0 µm, large dummy patterns (including large or spacious dummy gate layer patterns and large or spacious dummy fin patterns) have been adopted. It should be understood that the embodiments disclosed herein can replace the large dummy patterns in boundary regions wider or longer than 3.0 µm. For boundary regions narrower or shorter than 0.1 µm, since the boundary region is not large enough, the CMP dishing effect is not severe enough to cause problematic under-polishing effects.

[0024] FIG. 8 and FIG. 9 are cross-sectional views of intermediate structures in an intermediate stage of an exemplary process for forming a semiconductor device structure 40 according to some embodiments. As shown in FIG. 8, a mask layer (not shown) is formed in the first IP block 102-1 and the second IP block 102-2 to protect the materials in the first IP block 102-1 and the second IP block 102-2, and the sacrificial gate layer 82 exposed in the boundary region 104 is removed. The sacrificial gate layer 82 can be removed by an etching process selective to the gate layer 82, where the dielectric layer 80 serves as an etch stop layer. In some embodiments, one or more etching processes can then be performed to remove the dielectric layer 80 and the gate spacer layers 86, 88. The etching process can be, for example, RIE, NBE, wet etching, or another etching process. In some embodiments, the dielectric layer 80 is not removed. As shown in FIG. 8, after removing the sacrificial gate layer 82, the gate spacer layers 86, 88, and in some embodiments, the dielectric layer 80, an opening 106 is formed in the boundary region 104. After removing the sacrificial gate layer 82, the gate spacer layers 86, 88, and the dielectric layer 80, a portion of the fin 74 can be exposed.

[0025] As shown in FIG. 9, a metal-insulator-metal (MIM) structure 108 is formed in each opening 106. The MIM structure 108 can include one or more MIM capacitors. In some embodiments, as shown in FIG. 9, the MIM structure 108 includes a first conductive layer 110, a dielectric layer 112 disposed on the first conductive layer 110, and a second conductive layer 114 disposed on the dielectric layer 112. In some embodiments, the first conductive layer 110 and the second conductive layer 114 each include a metal or a metal nitride. For example, the first conductive layer 110 and the second conductive layer 114 each include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), platinum (Pt), or a combination thereof. In some embodiments, the first conductive layer 110 and the second conductive layer 114 include the same material. In some embodiments, the dielectric layer 112 includes a high-k dielectric material, such as zirconium oxide (ZrO2). Alternatively, the dielectric layer 112 can include one or more layers of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium silicate oxynitride (HfSiON), tantalum oxide (Ta2O5), hafnium oxide (HfO2), titanium oxide (TiO2), barium strontium titanate (BST), strontium titanate oxide (STO), or a combination thereof. The MIM structure 108 can be in contact with the exposed portion of the fin 74 (if the dielectric layer 80 is removed) or the dielectric layer 80.

[0026] In some embodiments, the MIM structure 108 can be formed by first forming a first conductive layer 110 in the opening 106. The first conductive layer 110 can be a conformal layer formed by a conformal process such as an ALD process. Next, a dielectric layer 112 is formed on the first conductive layer 110 in the opening 106, and the dielectric layer 112 can be a conformal layer formed by a conformal process. Next, a second conductive layer 114 is formed on the dielectric layer 112 to fill the opening 106. Portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 can be formed on a mask layer (not shown) formed in the IP blocks 102-1, 102-2, and a CMP process can be performed to remove the portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 formed on the mask layer located in the IP blocks 102-1, 102-2. The mask layer located in the IP blocks 102-1, 102-2 can also be removed by a CMP process, and the resulting structure is shown in FIG. 9.

[0027] The MIM structure 108 in the boundary region 104 reduces the CMP dishing effect because the MIM structure 108 includes different materials. In addition, the MIM structure 108 provides a MIM capacitor in the front-end-of-line (FEOL), which can save metal wiring to reduce the IR drop compared to a MIM capacitor in the back-end-of-line (BEOL). It should be understood that the example of the MIM structure 108 shown in FIG. 9 is illustrative and not restrictive, and the MIM structure 108 can have different configurations.

[0028] FIGS. 10A to 10B are various views of the MIM structure 108 of FIG. 9 according to some embodiments. FIG. 10A is a top view of the MIM structure 108, and FIG. 10B is a cross-sectional side view of the MIM structure 108. In some embodiments, the first conductive layer 110 is not a conformal layer. For example, the first conductive layer 110 can be formed in the opening 106 (FIG. 8) by any suitable process such as PVD, ECP, or CVD to fill the opening 106. Next, one or more openings are formed in the first conductive layer 110, and the dielectric layer 112 and the second conductive layer 114 are formed in the openings in the first conductive layer 110, as shown in FIGS. 10A and 10B. In some embodiments, the openings in the first conductive layer 110 extend through the first conductive layer 110 and separate the first conductive layer 110 into multiple discrete portions. In some embodiments, the dielectric layer 112 contacts a portion of the fin 74 or the dielectric layer 80. Next, a CMP process can be performed to remove portions of the first conductive layer 110, the dielectric layer 112, and the second conductive layer 114 formed on the mask layer located in the IP blocks 102-1, 102-2. The mask layer located in the IP blocks 102-1, 102-2 can also be removed by the CMP process, and the resulting structure is shown in FIG. 10B. Next, conductive contacts 116 are formed on the first conductive layer 110 and the second conductive layer 114, as shown in FIGS. 10A and 10B. The conductive contacts 116 comprise a conductive material such as a metal. In some embodiments, the conductive contacts 116 comprise tungsten, copper, aluminum, gold, silver, their alloys, the like, or a combination thereof. The conductive contacts 116 can be formed in the second ILD 130 (FIG. 22A), and the conductive contacts 116 can be formed simultaneously with the conductive contacts of the gate electrode 122 (FIG. 22A). []

[0029] In some embodiments, as shown in FIG. 10A, the length of the MIM structure 108 in the X direction is substantially small, such as less than about 90 nm, and the first conductive layer 110 and the second conductive layer 114 each have discrete portions. For example, the discrete portions of the first conductive layer 110 are aligned along the Y direction and separated by the discrete portions of the second conductive layer 114. Each discrete portion of the second conductive layer 114 is surrounded by the dielectric layer 112, as shown in FIG. 10A. In some embodiments, the length of the MIM structure 108 is determined by the length of the gate electrode layer (or metal gate). The gate electrode layer can have a length greater than about 90 nm, and the first conductive layer 110 can be a continuous layer surrounding the multiple discrete portions of the second conductive layer 114.

[0030] FIGS. 11A to 11B are various views of the MIM structure 108 of FIG. 9 according to an alternative embodiment. FIG. 11A is a top view of the MIM structure 108, and FIG. 11B is a cross-sectional side view of the MIM structure 108. As shown in FIG. 11A, the length of the MIM structure 108 is substantially greater than the length of the MIM structure 108 shown in FIG. 10A. In some embodiments, the length of the MIM structure 108 shown in FIG. 11A is greater than about 90 nm. With the larger length along the X direction, the opening formed in the first conductive layer 110 may not separate the first conductive layer 110 into discrete portions. In some embodiments, the first conductive layer 110 is a continuous layer having one or more openings filled with the dielectric layer 112 and the second conductive layer 114, as shown in FIG. 11A. In addition, in some embodiments, the opening in the first conductive layer 110 does not extend through the first conductive layer 110, and the dielectric layer 112 is formed on the first conductive layer 110, as shown in FIG. 11B. In some embodiments, the opening in the first conductive layer 110 extends through the first conductive layer, and the dielectric layer 112 is formed on a portion of the fin 74 or the dielectric layer 80. The first conductive layer 110, the dielectric layer 112, the second conductive layer 114, and the conductive contact 116 can be formed by the same process as the MIM structure 108 in FIGS. 10A and 10B. In some embodiments, as shown in FIG. 11B, the top surface of the first conductive layer 110 is substantially coplanar with the top surface of the second conductive layer 114.

[0031] As shown in FIG. 11B, the conductive contact 116 formed on the first conductive layer 110 does not contact the second conductive layer 114. Therefore, the process window for forming the conductive contact 116 on the first conductive layer 110 is substantially smaller. For example, the patterning process of forming an opening for the conductive contact 116 to be formed on the first conductive layer 110 in the second ILD 130 (FIG. 22A) cannot expose the second conductive layer 114. In some embodiments, in order to expand the process window for forming the conductive contact 116 on the first conductive layer 110, the MIM structure 108 is modified as shown in FIGS. 12A to 12B.

[0032] FIGS. 12A to 12B are various views of the MIM structure 108 of FIG. 9 according to an alternative embodiment. FIG. 12A is a top view of the MIM structure 108, and FIG. 12B is a cross-sectional side view of the MIM structure 108. As shown in FIG. 12B, the first conductive layer 110 is recessed from the level of the top surface of the second conductive layer 114, and a dielectric material 140 is formed on the first conductive layer 110 adjacent to the second conductive layer 114. Thus, as shown in FIGS. 12A and 12B, the vertical sides of the second conductive layer 114 are surrounded by the dielectric material 140, and the bottom of the second conductive layer 114 is disposed above the first conductive layer 110, with the dielectric layer 112 disposed therebetween. In some embodiments, the dielectric material 140 may include a dielectric material having an etching selectivity different from that of the material of the first ILD 100 (FIG. 6A). In some embodiments, a dielectric material is formed on the first ILD 100, and the dielectric material 140 may include the same material as the first ILD 100.

[0033] FIGS. 13A to 13C are cross-sectional side views of an intermediate structure of the MIM structure 108 of FIGS. 12A to 12B according to some embodiments. To form the MIM structure 108 of FIGS. 12A to 12B, the MIM structure 108 shown in FIGS. 11A to 11B may be the starting point, as shown in FIG. 13A. Next, as shown in FIG. 13B, the portions of the first conductive layer 110 disposed adjacent to the vertical sides of the second conductive layer 114 are recessed. In some embodiments, these portions are completely removed, leaving the first conductive layer 110 having a substantially constant thickness in the Z direction, as shown in FIG. 13B. In some embodiments, these portions are recessed, and the thickness of the edge portions of the first conductive layer 110 (the portions on which the second conductive layer 114 is not disposed) is substantially greater than the thickness of the central portion of the first conductive layer 110 (the portion on which the second conductive layer 114 is disposed). In some embodiments, these portions are completely removed by over-etching. Thus, the thickness of the edge portions of the first conductive layer 110 is substantially less than the thickness of the central portion of the first conductive layer 110. The process of removing / depressing the portions of the first conductive layer 110 disposed adjacent to the vertical sides of the second conductive layer 114 may be a selective etching process that substantially does not affect the sacrificial gate layer 82, the gate spacers 86, 88, the first ILD 100 (or the dielectric material formed on the first ILD 100), the CESL 96, the dielectric layer 112, and the second conductive layer 114. In some embodiments, a portion of the second conductive layer 114 may also be removed by a selective etching process, and the resulting top surface of the second conductive layer 114 may have a concave profile. []

[0034] Next, as shown in FIG. 13C, a dielectric material 140 is formed in the openings created by removing portions of the first conductive layer 110 / making these portions recessed. The dielectric material 140 can be formed by any suitable process. In some embodiments, the dielectric material 140 is formed by the same process as the first ILD 100. A planarization process such as a CMP process can be performed to remove the portions of the dielectric material 140 formed in the IP blocks 102-1, 102-2 and on the second conductive layer 114, as shown in FIG. 13C. The dielectric material 140 can have a top surface that is substantially coplanar with the top surface of the second conductive layer 114. After forming the second ILD 130 (FIG. 22A), openings are formed in the second ILD 130 and the dielectric material 140. In some embodiments, openings are also formed in the CESL 96 and the first ILD 100, the CESL 96 and the first ILD 100 are positioned adjacent to the dielectric material 140, and the side surface 110S of the first conductive layer 110 can be exposed in the openings. Compared with the openings for forming the conductive contacts 116 shown in FIG. 11B, the openings can be farther away from the second conductive layer 114. Next, conductive contacts 116 are formed in the openings, as shown in FIG. 12B. The conductive contacts 116 can contact a portion of the top surface of the first conductive layer 110 and the side surface 110S of the first conductive layer 110. Due to the presence of the dielectric material 140, the process window for forming the conductive contacts 116 is enlarged.

[0035] FIGS. 14A to 14C are various views of a MIM structure 208 according to some embodiments. FIG. 14A is a top view of the MIM structure 208, FIG. 14B is a cross-sectional side view of the MIM structure 208 of FIG. 14A taken along line C-C, and FIG. 14C is a cross-sectional side view of the MIM structure 208 of FIG. 14A taken along line D-D. As shown in FIGS. 14A to 14C, the MIM structure 208 includes more than one MIM capacitor. In some embodiments, the first MIM capacitor includes a first conductive layer 202 and a second conductive layer 210 separated by a dielectric layer 80, and the second MIM capacitor includes a second conductive layer 210 and a third conductive layer 214 separated by a dielectric layer 212. []

[0036] FIGS. 15A-15D, 16A-16B, 17A-17B, 18A-18B, and 19A-19B are various views of respective intermediate structures at an intermediate stage in an exemplary process of forming a semiconductor device structure 40 including the MIM structure 208 of FIGS. 14A-14C according to some embodiments. FIGS. 15A-15D are cross-sectional side views of the semiconductor device structure 40 of FIG. 1C taken along line B-B of the boundary region 104. As shown in FIG. 15A, the semiconductor device structure 40 is at a stage prior to forming the isolation region 78. The fins 74 are formed from the semiconductor substrate 70, and a dielectric material 204 is formed between adjacent fins 74. The dielectric material 204 may also be formed on the top surface of the fins 74, and a planarization process such as a CMP process may be performed to remove portions of the dielectric material 204 and expose the top surface of the fins 74. The dielectric material 204 may include the same material as the isolation region 78. Next, a mask layer (not shown) is formed in the IP blocks 102-1, 102-2 (FIG. 8) to protect the fins 74 and the dielectric material 204 formed in the first IP block 102-1 and the second IP block 102-2, and a portion of each fin 74 in the boundary region 104 is removed, as shown in FIG. 15B. The portion of the fin 74 may be removed by any suitable process such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that substantially does not affect the dielectric material 204. An opening 201 is formed over the remaining fins 74 in the boundary region 104. []

[0037] Next, as shown in FIG. 15C, a first conductive layer 202 is formed in the opening 201. The first conductive layer 202 may comprise the same material as the first conductive layer 110 and may be formed by the same process as the first conductive layer 110. The first conductive layer 202 may also be formed on the dielectric material 204 in the boundary region 104 and on the mask layer in the first IP block 102-1 and the second IP block 102-2. A planarization process such as a CMP process may be performed to remove portions of the first conductive layer 202 formed on the dielectric material 204 in the boundary region 104 and on the mask layer in the first IP block 102-1 and the second IP block 102-2. The CMP process may also remove the mask layer in the first IP block 102-1 and the second IP block 102-2. As shown in FIG. 15D, the dielectric material 204 is recessed to form the isolation region 78. In some embodiments, the semiconductor device structure 40 includes fins 74 extending over the isolation region 78 in the first IP block 102-1 and the second IP block 102-2 and a first conductive layer 202 extending over the isolation region 78 in the boundary region 104. In some embodiments, the isolation region 78 includes a top surface at or below the level of the top surface of the remaining fins 74 in the boundary region 104, as shown in FIG. 15D. []

[0038] Next, the semiconductor device structure 40 is processed, such as the processes described in FIGS. 2A to 6B. The resulting semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2 is shown in FIGS. 6A and 6B, and the resulting semiconductor device structure 40 in the boundary region 104 is shown in FIGS. 16A and 16B. As shown in FIGS. 16A and 16B, a dielectric layer 80 is formed on the first conductive layer 202, and a sacrificial gate layer 82 is formed on the dielectric layer 80. For clarity, the gate spacers 86, 88 are omitted in FIG. 16B. As shown in FIG. 16B, a CESL 96 and a first ILD 100 are formed over portions of the first conductive layer 202, and a planarization process is performed to expose the sacrificial gate layer 82.

[0039] As shown in FIGS. 17A and 17B, a mask layer (not shown) is formed in the first IP block 102-1 and the second IP block 102-2 to protect the materials in the first IP block 102-1 and the second IP block 102-2, and the exposed sacrificial gate layer 82 in the boundary region 104 is removed and replaced with a second conductive layer 210. In some embodiments, the gate spacer layers 86, 88 in the boundary region 104 are also removed. In the embodiments shown in FIGS. 17A and 17B, the dielectric layer 80 is not removed but is retained on the first conductive layer 202. The dielectric layer 80 serves as an insulator in the MIM capacitor of the MIM structure 208 (FIGS. 14A to 14C). The second conductive layer 210 may include the same material as the first conductive layer 110 and may be formed by the same process as the first conductive layer 110. The second conductive layer 210 may be formed in the opening 106 (FIG. 8). []

[0040] As shown in FIGS. 18A and 18B, an opening is formed in the second conductive layer 210, and a dielectric layer 212 and a third conductive layer 214 are formed in the opening. The dielectric layer 212 may include the same material as the dielectric layer 112 and may be formed by the same process as the dielectric layer 112. The third conductive layer 214 may include the same material as the second conductive layer 114 and may be formed by the same process as the second conductive layer 114. A portion of the second conductive layer 210, the dielectric layer 212, and the third conductive layer 214 may be formed on a mask layer (not shown) formed in the IP blocks 102-1, 102-2, and a CMP process may be performed to remove the portion of the second conductive layer 210, the dielectric layer 212, and the third conductive layer 214 formed on the mask layer located in the IP blocks 102-1, 102-2. The mask layer located in the IP blocks 102-1, 102-2 may also be removed by a CMP process. The resulting semiconductor device structure 40 may include the sacrificial gate layer 82 in the first IP block 102-1 and the second IP block 102-2, and the sacrificial gate layer 82 has a top surface substantially coplanar with the top surfaces of the second conductive layer 210 and the third conductive layer 214 located in the boundary region 104.

[0041] After replacing the sacrificial gate layers 82 in the first IP block 102-1 and the second IP block 102-2 with the use gate electrodes 122 (FIG. 22A) and forming the second ILD 130 (FIG. 22A), conductive contacts 116 are formed on the second conductive layer 210 and the third conductive layer 214, as shown in FIGS. 19A and 19B. The conductive contacts 116 in contact with the first conductive layer 202 can extend through the first ILD 100 and the CESL 96, as shown in FIG. 19B. In addition, the length of the first conductive layer 202 in the X direction is substantially greater than the length of the second conductive layer 210 to accommodate the conductive contacts 116.

[0042] FIGS. 20A to 20B are top views of the MIM structure 108 of FIGS. 11A to 11B or the MIM structure 208 of FIGS. 19A to 19B according to an alternative embodiment. As shown in FIGS. 20A to 20B, the conductive layers 114 / 214 can be arranged in any suitable pattern. In some embodiments, the conductive layers 114 / 214 and the dielectric layers 112 / 212 together have a width W and a length L, and the adjacent conductive layers 114 / 214 and the dielectric layers 112 / 212 are separated by a distance S in the Y direction. In some embodiments, the width W, the length L, and the distance S can be greater than about 0.144 µm. Thus, the CMP recess effect can be reduced. []

[0043] FIGS. 21A to 21C are cross-sectional views of an intermediate structure at an intermediate stage in an exemplary process for forming the semiconductor device structure 40 according to some embodiments. FIGS. 21A to 21B illustrate the semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2. For clarity, the gate spacers 86, 88 are omitted in FIG. 21C. As shown in FIGS. 21A to 21C, a mask layer (not shown) is formed on the MIM structure 108 / 208 in the boundary region 104, and the sacrificial gate layers 82 in the first IP block 102-1 and the second IP block 102-2 are removed. The sacrificial gate layers 82 can be removed by any suitable process. In some embodiments, the dielectric layer 80 disposed under the sacrificial gate layers 82 is also removed. After removing the sacrificial gate layers 82 and the dielectric layer 80, a replacement gate structure is formed in the groove from which the gate stack has been removed.

[0044] FIGS. 22A to 22C are cross-sectional views of intermediate structures in an intermediate stage of an exemplary process for forming a semiconductor device structure 40 according to some embodiments. FIGS. 22A to 22B illustrate the semiconductor device structure 40 in the first IP block 102-1 and the second IP block 102-2. For clarity, the gate spacers 86 and 88 are omitted in FIG. 22C. As shown in FIGS. 22A to 22C, each replacement gate structure includes one or more conformal layers 120 and a gate electrode 122. The one or more conformal layers 120 include a gate dielectric layer and may include one or more work function tuning layers. The gate dielectric layer may be conformally deposited in a recess from which the gate stack has been removed. The gate dielectric layer may be or include silicon oxide, silicon nitride, a high-k dielectric material, a multi-layer thereof, or other dielectric materials. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. Next, the gate electrode 122 is formed over the one or more conformal layers 120. The layer for the gate electrode 122 may fill the remaining recess from which the gate stack has been removed. The gate electrode 122 may include a conductive material, such as one or more layers of polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable materials, and / or any combination thereof.

[0045] In some embodiments, the gate electrode 122 includes a p-type gate electrode and an n-type gate electrode. For example, the gate electrode 122 formed in the first IP block 102-1 is an n-type gate electrode, and the gate electrode 122 formed in the second IP block 102-2 is a p-type gate electrode. The n-type and p-type gate electrodes 122 can be formed by first depositing a first type of gate electrode 122, such as an n-type or p-type, in both the first IP block 102-1 and the second IP block 102-2. Then, a planarization process, such as a CMP process, is performed to remove portions of the first type of gate electrode 122 formed on the first ILD 100 and in the boundary region 104. The mask layer formed in the boundary region 104 to protect the MIM structure 108 / 208 can also be removed by the CMP process. As described above, since the MIM structure 108 / 208 includes multiple materials, the CMP recess effect is reduced. Next, another mask layer is formed in the first IP block 102-1 and the boundary region 104 to protect the first type of gate electrode and the MIM structure 108 / 208. The first type of gate electrode 122 formed in the second IP block 102-2 is removed, and a second type of gate electrode opposite to the first type of gate electrode is formed in the second IP block 102-2. Then, another CMP process is performed to remove portions of the second type of gate electrode formed in the first IP block 102-1 and the boundary region 104, and the mask layer formed in the first IP block 102-1 and the boundary region 104 is also removed by the CMP process. The resulting semiconductor device structure 40 is shown in FIG. 22C. In some embodiments, the top surface of the gate electrode 122 and the top surface of the MIM structure 108 / 208 / 308 can be substantially coplanar, as shown in FIG. 22C. The top surface of the MIM structure 108 / 208 / 308 can include the top surface of the conductive layer 110 (FIGS. 10B and 11B), the top surface of the conductive layer 114 (FIGS. 10B, 11B, and 12B), the top surface of the dielectric material 140 (FIG. 12B), the top surface of the conductive layer 210 (FIG. 14B), and / or the top surface of the conductive layer 214 (FIG. 14B).

[0046] Next, as shown in FIGS. 22A and 22B, a second ILD 130 is formed over the replacement gate structure, the first ILD 100, and the MIM structure 108 / 208, and the conductive feature 134 is formed to pass through the second ILD 130, the first ILD 100, and the CESL 96 to reach the epitaxial source / drain region 92. Although not illustrated, in some examples, an etch stop layer (ESL) may be deposited over the first ILD 100 and the like, and the second ILD 130 may be deposited over the ESL. If implemented, the ESL may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof. The second ILD 130 may comprise or be silicon dioxide, a low-k dielectric material such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-on glass, spin-on polymer, silicon carbide material, compounds thereof, composite materials thereof, the like, or combinations thereof. The conductive feature 134 is formed to pass through the second ILD 130, the first ILD 100, and the CESL 96 to reach the epitaxial source / drain region 92. A silicide region 136 may be formed on an upper portion of the epitaxial source / drain region 92 by reacting the upper portion of the epitaxial source / drain region 92 with the conductive feature 134. The conductive contact 116 of the MIM structure 108 / 208 may be formed before, after, or simultaneously with the conductive feature 134. In some embodiments, the conductive contact 116 is formed after the conductive feature 134 is formed and simultaneously with a conductive feature (not shown) of the gate electrode 122. For clarity, the second ILD 130, the conductive feature 134, and the conductive contact 116 are omitted in FIG. 22C.

[0047] FIGS. 23A to 23B are various views of the MIM structure 308 according to an alternative embodiment. The semiconductor device structure 40 including the MIM structures 108 / 208 shown in the previous figures is FinFET-based. The MIM structures for reducing the CMP recess effect in the boundary region 104 can be applied to other types of devices, such as planar FETs, nanostructure FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. In some embodiments, planar FETs are formed in the first IP block 102-1 and the second IP block 102-2, and the MIM structure 308 is formed in the boundary region 104. As shown in FIGS. 23A to 23B, the MIM structure 308 is formed over the semiconductor substrate 302, which may include the same material as the semiconductor substrate 70. A first conductive layer 304 is formed in the semiconductor substrate 302. The first conductive layer 304 may include the same material as the first conductive layer 202 and may be formed by the same process as the first conductive layer 202. A mask layer may be formed in the first IP block 102-1 and the second IP block 102-2, and the mask layer may expose a portion of the semiconductor substrate 302 located in the boundary region 104. An opening is formed in the exposed portion of the semiconductor substrate 302, and the first conductive layer 304 is formed in the opening. []

[0048] Next, a dielectric layer 306 is formed on the first conductive layer 304. The dielectric layer 306 may include the same material as the dielectric layer 80 and may be formed by the same process as the dielectric layer 80. The dielectric layer 306 may also be formed in the first IP block 102-1 and the second IP block 102-2. The dielectric layer 306 may be formed by first forming a continuous layer in the first IP block 102-1, the second IP block 102-2, and the boundary region 104. Then, a patterning process is performed on the continuous layer to form the dielectric layer 306. A sacrificial gate layer (not shown) is formed on the dielectric layer 306 in the first IP block 102-1, the second IP block 102-2, and the boundary region 104. A gate spacer layer (not shown) may be formed on opposite sides of the sacrificial gate layer in the first IP block 102-1 and the second IP block 102-2. The gate spacer layer may include the same material as the gate spacer layers 86, 88 and may be formed by the same process as the gate spacer layers 86, 88. In some embodiments, no gate spacer layer is formed in the boundary region 104, which may be achieved by forming a mask layer in the boundary region 104 before forming the gate spacer layer. Still using the mask layer formed in the boundary region 104, source / drain regions (not shown) may be formed on opposite sides of the sacrificial gate layer in the first IP block 102-1 and the second IP block 102-2. After forming the source / drain regions, the mask layer in the boundary region 104 is removed, and a CESL and a first ILD are formed in the first IP block 102-1, the second IP block 102-2, and the boundary region 104. []

[0049] Next, a mask layer is formed in the first IP block 102-1 and the second IP block 102-2 to protect the sacrificial gate layer located therein, and the exposed sacrificial gate layer in the boundary region 104 is removed. A second conductive layer 310 is formed in the opening generated by removing the sacrificial gate layer. The second conductive layer 310 may include the same material as the second conductive layer 210 and may be formed by the same process as the second conductive layer 310. An opening is formed in the second conductive layer 310. A dielectric layer 312 and a third conductive layer 314 are formed in each opening in the second conductive layer 310. The dielectric layer 312 may include the same material as the dielectric layer 212 and may be formed by the same process as the dielectric layer 212. The third conductive layer 314 may include the same material as the third conductive layer 214 and may be formed by the same process as the third conductive layer 214. In some embodiments, the MIM structure 308 includes a first MIM capacitor having a first conductive layer 304, a dielectric layer 306, and a second conductive layer 310, and a second MIM capacitor having a second conductive layer 310, a dielectric layer 312, and a third conductive layer 314. After the MIM structure 308 is formed in the boundary region 104, a mask layer is formed in the boundary region 104, and processes are performed in the first IP block 102-1 and the second IP block 102-2, such as the processes described in FIGS. 21A to 21C and FIGS. 22A to 22C, to complete the planar FET. Then, a conductive contact 116 is formed in a second ILD (not shown), such as the second ILD 130 (FIG. 22A). []

[0050] In various embodiments, the present disclosure provides a semiconductor device structure and a method of forming the same. In some embodiments, the semiconductor device structure 40 includes a MIM structure 108 / 208 / 308 located in the boundary region 104. The MIM structure 108 / 208 / 308 may include one or more MIM capacitors. Some embodiments may achieve advantages. For example, by using the MIM structure 108 / 208 / 308 formed in the boundary region 104, the CMP depression effect is reduced when forming the gate electrode 122. In addition, compared with the MIM structure in the BEOL, the MIM structure 108 / 208 / 308 located in the FEOL can save metal wiring to reduce the IR drop.

[0051] An embodiment is a semiconductor device structure. The structure includes a first region, a second region, and a boundary region disposed between the first region and the second region. The first region includes a gate electrode disposed above a semiconductor fin. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed above the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. The top surface of the second conductive layer and the top surface of the gate electrode can be substantially coplanar.

[0052] Another embodiment is a semiconductor device structure. The structure includes a first region, a second region, and a boundary region disposed between the first region and the second region. The first region includes a gate electrode. The boundary region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. The top surface of the second conductive layer and the top surface of the first conductive layer can be substantially coplanar.

[0053] Another embodiment is a method. The method includes forming fins above a substrate, and the fins are disposed in a first region, a second region, and a boundary region, and the boundary region is disposed between the first region and the second region. The method further includes forming a first sacrificial gate layer above a first portion of the fins in the first region, forming a second sacrificial gate layer above a second portion of the fins in the second region, and forming a third sacrificial gate layer above a third portion of the fins in the boundary region. The method further includes removing the third sacrificial gate layer to create an opening; forming a metal-insulator-metal (MIM) structure in the opening; removing the first sacrificial gate layer and the second sacrificial gate layer to create openings in the first region and the second region; and depositing a gate electrode in the openings in the first region and the second region. The top surface of the gate electrode and the top surface of the MIM structure are substantially coplanar.

[0054] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0055] 40: Semiconductor device structure 52a~52f, 92: Source / drain region 70, 302: Semiconductor substrate 74: Fin 78: Isolation region 80, 112, 212, 306, 312: Dielectric layer 82: Gate layer 84: Mask 86: Gate spacer layer 88: Gate spacer layer 96: CESL 100: First ILD 102-1: IP block 102-2: IP block 104: Boundary region 106, 201: Opening 108, 208, 308: MIM structure 110, 202, 304: Conductive layer 110S: Side surface 114, 210, 310: Conductive layer 116: Conductive contact 120: Conformal layer 122: Gate electrode 130: Second ILD 134: Conductive feature 136: Silicide region 140, 204: Dielectric material 214, 314: Conductive layer A-A, B-B, C-C, D-D: Cross section L: Length S: Distance W: Width

[0056] Domestic deposit information (Please note in the order of deposit institution, date, and number) None Foreign deposit information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor device structure, comprising: A first region includes a gate electrode disposed above a semiconductor fin; Zone 1, Section 2; A boundary region is disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer disposed above the semiconductor fin; and a first dielectric layer in contact with the first conductive layer; A second conductive layer in contact with the first dielectric layer, wherein a top surface of the first conductive layer, a top surface of the second conductive layer, and a top surface of the gate electrode are all coplanar; and a third conductive layer disposed on the semiconductor fin and a second dielectric layer disposed on the third conductive layer, wherein the first conductive layer is in contact with the second dielectric layer.

2. The semiconductor device structure as claimed in claim 1, wherein the first conductive layer is disposed adjacent to a plurality of vertical sides of the second conductive layer, and the first dielectric layer is disposed between the first conductive layer and the vertical sides of the second conductive layer.

3. The semiconductor device structure as described in claim 1, wherein the first dielectric layer is in contact with the semiconductor fin.

4. The semiconductor device structure as claimed in claim 1, further comprising a dielectric material surrounding a plurality of vertical sides of the second conductive layer, wherein the dielectric material is disposed on the first conductive layer.

5. The semiconductor device structure as described in claim 4, wherein the first dielectric layer is in contact with the dielectric material.

6. The semiconductor device structure as claimed in claim 5, wherein a top surface of the dielectric material is coplanar with the top surface of the second conductive layer.

7. The semiconductor device structure as claimed in claim 1, wherein the second dielectric layer is disposed between the first conductive layer and the third conductive layer.

8. A semiconductor device structure, comprising: A first region, including a gate electrode disposed above a semiconductor fin; a second region; A boundary region is disposed between the first region and the second region, wherein the boundary region includes a metal-insulator-metal structure, and the metal-insulator-metal structure includes: a first conductive layer disposed above the semiconductor fin; and a first dielectric layer in contact with the first conductive layer; A second conductive layer in contact with the first dielectric layer, wherein a top surface of the gate electrode, a top surface of the second conductive layer, and a top surface of the first conductive layer are all coplanar; and a third conductive layer disposed on the semiconductor fin and a second dielectric layer disposed on the third conductive layer, wherein the first conductive layer is in contact with the second dielectric layer.

9. The semiconductor device structure as claimed in claim 8, wherein the second dielectric layer is disposed between the first conductive layer and the third conductive layer.

10. A method for forming a semiconductor device structure, comprising the following steps: forming a fin on a substrate, wherein the fin is disposed in a first region, a second region, and a boundary region, the boundary region being disposed between the first region and the second region; forming a first sacrificial gate layer on a first portion of the fin located in the first region, forming a second sacrificial gate layer on a second portion of the fin located in the second region, and forming a third sacrificial gate layer on a third portion of the fin located in the boundary region; removing the third sacrificial gate layer to create an opening; forming a metal-insulator-metal structure in the opening, the metal-insulator-metal structure comprising a first conductive layer, a first dielectric layer, and a second conductive layer, the first conductive layer being disposed on the fin, the first dielectric layer being in contact with the first conductive layer, and the second conductive layer being in contact with the first dielectric layer; Before forming the third sacrificial gate layer, the third portion of the fin is recessed and a third conductive layer is deposited on the recessed third portion of the fin, and a second dielectric layer is formed on the third conductive layer, wherein the first conductive layer is in contact with the second dielectric layer; the first sacrificial gate layer and the second sacrificial gate layer are removed to form a plurality of openings in the first region and the second region; and a plurality of gate electrodes are deposited in the openings in the first region and the second region, wherein a plurality of top surfaces of the gate electrodes are coplanar with a top surface of the first conductive layer and a top surface of the second conductive layer.

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