Level shifter

Abstract

This invention provides a level shifter disposed within a die. The level shifter includes a pull-up transistor, a first pull-down transistor, a second pull-down transistor, and a control circuit. A first terminal of the pull-up transistor receives a first power supply voltage higher than the die's base voltage. A first terminal of the first pull-down transistor receives a second power supply voltage lower than the base voltage. The second pull-down transistor is coupled between the first pull-down transistor and the pull-up transistor. A second terminal of the pull-up transistor is coupled to the output terminal of the level shifter. The input terminal of the control circuit is coupled to the input terminal of the level shifter. Different output terminals of the control circuit are respectively coupled to the control terminals of the pull-up transistor, the second pull-down transistor, and the first pull-down transistor.

Description

Technical Field

[0001] This invention relates to an integrated circuit (IC), and more particularly to a large voltage swing level shifter disposed in a die. Prior Technology

[0002] Level shifters are typically located within the die. When the lower limit of the voltage swing at the output of the level shifter is lower than the die's substrate voltage (VSUB), the junction (parasitic diode) between the die's P-type substrate and the level shifter's pull-down transistor is conductive, meaning the level shifter leaks current. Therefore, the existing die substrate voltage (VSUB) cannot be set to 0 volts. Summary of the Invention

[0003] The present invention provides a level shifter to provide a voltage swing output from a first power supply voltage (higher than the substrate voltage of the die) to a second power supply voltage (lower than the substrate voltage).

[0004] In one embodiment of the present invention, the aforementioned level shifter is disposed in a die. The level shifter includes a pull-up transistor, a first pull-down transistor, a second pull-down transistor, and a control circuit. A first terminal of the pull-up transistor is coupled to a first power supply voltage, wherein the first power supply voltage is higher than the substrate voltage of the die. A second terminal of the pull-up transistor is coupled to the output terminal of the level shifter. A first terminal of the first pull-down transistor is coupled to a second power supply voltage, wherein the second power supply voltage is lower than the substrate voltage of the die. A first terminal of the second pull-down transistor is coupled to a second terminal of the first pull-down transistor. A second terminal of the second pull-down transistor is coupled to the output terminal of the level shifter. An input terminal of the control circuit is coupled to the input terminal of the level shifter. A first output terminal of the control circuit is coupled to the control terminal of the pull-up transistor. A second output terminal of the control circuit is coupled to the control terminal of the second pull-down transistor. A third output terminal of the control circuit is coupled to the control terminal of the first pull-down transistor.

[0005] Based on the above, in some embodiments, the first pull-down transistor and the second pull-down transistor can be fully isolated metal-oxide-semiconductor (MOS) transistors. Therefore, the first and second pull-down transistors will not leak current to the die substrate. Furthermore, the first and second pull-down transistors are connected in series between the output of the level offset device and the second power supply voltage (lower than the die substrate voltage). Therefore, the voltage withstand capability (rated maximum source-drain voltage) of either the first or second pull-down transistor can be less than the voltage difference between the first and second power supply voltages.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of a level shifter disposed in a die according to an embodiment. Figure 2 is a schematic diagram of a circuit block of a level offset device according to an embodiment of the present invention. Figure 3 is a waveform diagram of the input and output terminals of a level offset device according to an embodiment of the present invention. Figure 4 is a schematic diagram of the operation of a transistor according to an embodiment of the present invention. Figure 5 is a partial circuit diagram of the control circuit according to an embodiment of the present invention. Figure 6 is a circuit block diagram of a level offset device according to another embodiment of the present invention. Figure 7 is a schematic diagram of the operation of a transistor according to another embodiment of the present invention. Implementation

[0008] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0009] Figure 1 is a circuit diagram illustrating a level shifter 100 disposed in a die according to one embodiment. The level shifter 100 includes a pull-up transistor P11, a pull-down transistor N11, a charge-sharing transistor N12, and a charge-sharing transistor N13. Transistors P11, N11, N12, and N13 are metal-oxide-semiconductor (MOS) transistors. For example, in one embodiment, transistor P11 is a P-channel MOS (PMOS) transistor, while transistors N11, N12, and N13 are N-channel MOS (NMOS) transistors. Charge-sharing transistors N12 and N13 are connected in series between ground voltage GND1 and the output terminal LVSH_OUT1. Charge-sharing transistors N12 and N13 are controlled by a control signal VG13. When charge-sharing transistors N12 and N13 are turned on, the voltage at the output terminal LVSH_OUT1 can be shared with the ground voltage GND1 (typically 0 volts).

[0010] The first terminal of pull-up transistor P11 is coupled to the power supply voltage VGH1 (e.g., 40 volts). The power supply voltage VGH1 is higher than the chip's substrate voltage (VSUB, typically 0 volts). The second terminal of pull-up transistor P11 is coupled to the output terminal LVSH_OUT1 of level offset 100. Pull-up transistor P11 is controlled by control signal VG11. When pull-up transistor P11 is turned on, the voltage at output terminal LVSH_OUT1 is pulled up to the power supply voltage VGH1. The first terminal of pull-down transistor N11 is coupled to the power supply voltage VGL1 (e.g., -20 volts). The power supply voltage VGL1 is lower than the chip's substrate voltage (0 volts). The second terminal of pull-down transistor N11 is coupled to the output terminal LVSH_OUT1 of level offset 100. Pull-down transistor N11 is controlled by control signal VG12. When the pull-down transistor N11 is turned on, the voltage at the output terminal LVSH_OUT1 will be pulled down to the power supply voltage VGL1.

[0011] Assume transistors P11, N11, N12, and N13 are laterally diffused MOS (LDMOS) transistors and are non-fully isolated high-voltage MOS transistors. The drain voltage swing of pull-down transistor N11 is between -20 and 40 volts. When the drain voltage of pull-down transistor N11 is lower than the die's base voltage (0 volts), the junction (parasitic diode) between the P-type base of the die and pull-down transistor N11 is conductive, meaning that pull-down transistor N11 leaks current. Under no circumstances should the parasitic diode between the P-type base and pull-down transistor N11 be conductive.

[0012] To address the leakage current issue between the pull-down transistor N11 and the die substrate, the die substrate voltage can be changed to a negative power supply voltage VGL1 (e.g., -20 volts). Because the die substrate voltage is not 0 volts, the adhesive layer between the die substrate and the package base plate must be changed to a non-conductive material (since the package base plate voltage is typically 0 volts). Generally, conductive materials have better thermal conductivity than non-conductive materials. If the adhesive layer between the die substrate and the package base plate is conductive, the die's heat can be easily conducted to the outside of the package through the adhesive layer and the package base plate.

[0013] To address the leakage current issue between the pull-down transistor N11 and the die substrate, a fully isolated LDMOS transistor could be used instead. However, fully isolated LDMOS transistors are unsuitable for high-slew rate level offset circuits because the output slew rate of the level offset circuit might exceed the transverse voltage withstand capability (rated maximum source-drain voltage) of the fully isolated LDMOS transistor. Generally, the transverse voltage withstand capability of a fully isolated LDMOS transistor is approximately 40 volts. If a fully isolated LDMOS transistor is simply used to implement the pull-down transistor N11, when the output of the level offset circuit 100 is 40 volts, the fully isolated LDMOS transistor (pull-down transistor N11) will withstand a transverse voltage of 60 volts and burn out.

[0014] Figure 2 is a circuit block diagram of a level shifter 200 according to an embodiment of the present invention. The level shifter 200 is disposed in a die. In some embodiments, the die may be a display driver integrated circuit, a touch driver integrated circuit, or other integrated circuits. The level shifter 200 shifts the voltage at the input terminal LVSH_IN2 to the voltage at the output terminal LVSH_OUT2. For example, the slew rate at the input terminal LVSH_IN2 may be 0 to 5 volts, while the slew rate at the output terminal LVSH_OUT2 may be -20 to 40 volts. The output terminal LVSH_OUT2 of the level shifter 200 can provide the shifted voltage to the load circuit. For example, in some embodiments, the load circuit may include a gate-on-array (GOA) circuit configured on a display panel. In other embodiments, the load circuit may include other circuitry.

[0015] Figure 2 shows a level shifter 200 including a pull-up transistor P21, a pull-down transistor N21, a pull-down transistor N22, a charge-sharing transistor N23, and a control circuit 210. The input of the control circuit 210 is coupled to the input LVSH_IN2 of the level shifter. The control terminals (e.g., gates) of transistors P21, N21, N22, and N23 are coupled to different outputs of the control circuit 210. The first output of the control circuit 210 outputs a control signal VGHS to control the control terminal of the pull-up transistor P21. The second output of the control circuit 210 outputs a control signal VGBS to control the control terminal of the pull-down transistor N22. The third output of the control circuit 210 outputs a control signal VGLS to control the control terminal of the pull-down transistor N21. The fourth output of the control circuit 210 outputs a control signal VGCS to control the control terminal of the charge-sharing transistor N23.

[0016] This embodiment does not limit the specific implementation of the control circuit 210. For example, the control circuit 210 may include logic circuit 211, driver 212, driver 213, driver 214, and driver 215. Drivers 212, 213, 214, and 215 may be output buffers or other driving circuits. Based on the voltage of the input terminal LVSH_IN2, logic circuit 211 may control transistors P21, N21, N22, and N23. For example, logic circuit 211 may generate a control signal VGHS through driver 212 to control the control terminal of pull-up transistor P21. The power supply terminal and reference terminal of driver 212 receive power supply voltage VGH2 and VHS_REG, respectively, where the level of power supply voltage VHS_REG is the level of power supply voltage VGH2 minus the differential voltage (e.g., 5 volts or other real number). Therefore, the swing of the control signal VGHS is between the power supply voltage VGH2 and the power supply voltage VHS_REG.

[0017] Logic circuit 211 can generate a control signal VGLS via driver 214 to the control terminal of pull-down transistor N21. The power supply terminal and reference terminal of driver 214 receive power supply voltages VLS_REG and VGL2, respectively, where the level of power supply voltage VLS_REG is the level of power supply voltage VGL2 plus a differential voltage (e.g., 5 volts or other real number). Therefore, the swing of control signal VGLS is between power supply voltage VLS_REG and power supply voltage VGL2. Logic circuit 211 can also generate a control signal VGBS via driver 213 to the control terminal of pull-down transistor N22. The power supply terminal and reference terminal of driver 213 receive node voltages VBOOT_REG and VBOOT, respectively, where node voltage VBOOT_REG is greater than node voltage VBOOT. For example, node voltage VBOOT_REG is node voltage VBOOT plus a differential voltage. Therefore, the swing of control signal VGBS is between node voltage VBOOT_REG and node voltage VBOOT. Logic circuit 211 can generate a control signal VGCS via driver 215 to the control terminal of charge-sharing transistor N23. The power supply terminal and reference terminal of driver 215 receive node voltages VBOOT_REG and VBOOT, respectively. Therefore, the swing of the control signal VGCS is between the node voltage VBOOT_REG and the node voltage VBOOT.

[0018] Transistors P21, N21, N22, and N23 are metal-oxide-semiconductor (MOS) transistors. For example, in one embodiment, transistor P21 is a P-channel MOS (PMOS) transistor, while transistors N21, N22, and N23 are N-channel MOS (NMOS) transistors. Depending on the design, transistors P21, N21, N22, and N23 may be laterally diffused MOS (LDMOS) transistors. Transistor P21 may be a non-fully isolated high-voltage MOS transistor. Transistors N21, N22, and N23 may be fully isolated high-voltage MOS transistors or fully isolated laterally diffused MOS (LDMOS) transistors.

[0019] The first terminal (e.g., the source) of pull-up transistor P21 is coupled to the power supply voltage VGH2, which is higher than the die's base voltage (VSUB, typically 0 volts). The level of power supply voltage VGH2 can be determined according to the actual design. For example (but not limited to), the level of power supply voltage VGH2 can be 40 volts or other fixed levels higher than the base voltage. The second terminal (e.g., the drain) of pull-up transistor P21 is coupled to the output terminal LVSH_OUT2 of level offset 200. The first terminal (e.g., the source) of pull-down transistor N21 is coupled to the power supply voltage VGL2, which is lower than the die's base voltage. The level of power supply voltage VGL2 can be determined according to the actual design. For example (but not limited to), the level of power supply voltage VGL2 can be -20 volts or other fixed levels lower than the base voltage.

[0020] The first terminal (e.g., source) of pull-down transistor N22 is coupled to the second terminal (e.g., drain) of pull-down transistor N21. The voltage between the first terminal of pull-down transistor N22 and the second terminal of pull-down transistor N21 is the node voltage VBOOT. The second terminal (e.g., drain) of pull-down transistor N22 is coupled to the output terminal LVSH_OUT2 of level offset 200. The first terminal (e.g., source) of charge-sharing transistor N23 is coupled to the first terminal of pull-down transistor N22 and the second terminal of pull-down transistor N21. The second terminal (e.g., drain) of charge-sharing transistor N23 is coupled to the charge-sharing voltage VCS2. The level of charge-sharing voltage VCS2 is between the supply voltage VGH2 and the supply voltage VGL2. The level of charge-sharing voltage VCS2 can be determined according to the actual design. For example (but not limited to), the level of charge-sharing voltage VCS2 can be 0 volts or other fixed levels.

[0021] Figure 3 is a waveform diagram of the input terminal LVSH_IN2 and the output terminal LVSH_OUT2 of the level offset device 200 according to an embodiment of the present invention. The horizontal axis of Figure 3 represents time. Figure 4 is a schematic diagram of the operation of transistors P21, N21, N22 and N23 according to an embodiment of the present invention. Referring to Figures 2, 3 and 4, in the transition phase P31, the input terminal LVSH_IN2 is at the original low level VL (e.g., 0 volts), so the control circuit 210 turns off the pull-up transistor P21 and the charge-sharing transistor N23, and turns on the pull-down transistors N21 and N22. At this time, the output voltage of the output terminal LVSH_OUT2 is pulled down to the level of the power supply voltage VGL2 (e.g., -20 volts), and the node voltage VBOOT is also pulled down to the level of the power supply voltage VGL2. In the transition phase P31, the transvoltage of the charge-sharing crystal N23 is VCS2-VGL2, for example 0-(-20)=20 volts.

[0022] In response to the input voltage at input terminal LVSH_IN2 transitioning from the original low level VL to the original high level VH (e.g., 5 volts), control circuit 210 turns on pull-down transistor N22 and turns off pull-up transistor P21, pull-down transistor N21, and charge-sharing transistor N23 during transition phase P32. At this time, the output voltage at output terminal LVSH_OUT2 and the node voltage VBOOT are maintained at the level of the power supply voltage VGL2. In transition phase P33 following transition phase P32, control circuit 210 turns on pull-down transistor N22 and charge-sharing transistor N23 and turns off pull-up transistor P21 and pull-down transistor N21. At this time, the output voltage at output terminal LVSH_OUT2 is pulled to the level of charge-sharing voltage VCS2 (e.g., 0 volts), and the node voltage VBOOT is also pulled down to the level of charge-sharing voltage VCS2. In transition phase P33, the voltage across pull-down transistor N21 is VCS2 - VGL2, for example, 0 - (-20) = 20 volts. In transition phase P34 following transition phase P33, control circuit 210 turns on charge-sharing transistor N23 and turns off pull-up transistors P21, N21, and N22. At this time, the output voltage of output terminal LVSH_OUT2 and node voltage VBOOT are maintained at the level of charge-sharing voltage VCS2. In transition phase P35 following transition phase P34, control circuit 210 turns on pull-up transistors P21 and charge-sharing transistor N23 and turns off pull-down transistors N21 and N22. At this time, the output voltage of output terminal LVSH_OUT2 is pulled up to the level of power supply voltage VGH2 (for example, 40 volts), while node voltage VBOOT is maintained at the level of charge-sharing voltage VCS2. In the transition phase P35, the voltage across the pull-down transistor N21 is VCS2-VGL2, for example 0-(-20)=20 volts, while the voltage across the pull-down transistor N22 is VGH2-VCS2, for example 40-0=40 volts.

[0023] In response to the input voltage at input terminal LVSH_IN2 transitioning from the original high level VH to the original low level VL, control circuit 210 turns on charge-sharing transistor N23 and turns off pull-up transistors P21, N21, and N22 in transition phase P36 after transition phase P35. At this time, the output voltage at output terminal LVSH_OUT2 is maintained at the level of power supply voltage VGH2 (e.g., 40 volts), while the node voltage VBOOT is maintained at the level of charge-sharing voltage VCS2. In transition phase P36, the voltage across pull-down transistor N21 is VCS2-VGL2, for example 0-(-20)=20 volts, while the voltage across pull-down transistor N22 is VGH2-VCS2, for example 40-0=40 volts. In transition phase P37 after transition phase P36, control circuit 210 turns on pull-down transistor N22 and charge-sharing transistor N23, and turns off pull-up transistor P21 and pull-down transistor N21. At this time, the output voltage of output terminal LVSH_OUT2 is pulled to the level of charge-sharing voltage VCS2 (e.g., 0 volts), while the node voltage VBOOT remains at the level of charge-sharing voltage VCS2. In transition phase P37, the voltage across pull-down transistor N21 is VCS2 - VGL2, for example, 0 - (-20) = 20 volts. In transition phase P38 after transition phase P37, control circuit 210 turns on pull-down transistor N22 and turns off pull-up transistor P21, pull-down transistor N21, and charge-sharing transistor N23. At this time, the output voltage of output terminal LVSH_OUT2 and node voltage VBOOT remain at the level of power supply voltage VGL2. In transition phase P39 following transition phase P38, control circuit 210 turns on pull-down transistors N21 and N22 and turns off pull-up transistors P21 and N23. At this time, the output voltage of output terminal LVSH_OUT2 and node voltage VBOOT are pulled down to the level of supply voltage VGL2 (e.g., -20 volts). In transition phase P39, the voltage across charge-sharing transistor N23 is VCS2 - VGL2, for example, 0 - (-20) = 20 volts.

[0024] As shown in Figure 4, the maximum voltage across pull-down transistor N21 is VCS2 - VGL2, for example, 0 - (-20) = 20 volts. The maximum voltage across pull-down transistor N22 is VGH2 - VCS2, for example, 40 - 0 = 40 volts. The maximum voltage across charge-sharing transistor N23 is VCS2 - VGL2, for example, 0 - (-20) = 20 volts. That is, assuming transistors N21, N22, and N23 are fully isolated lateral diffused MOS (LDMOS) transistors, and the voltage withstand capability (rated maximum source-drain voltage) of a fully isolated LDMOS transistor is approximately 40 volts, then the maximum voltage across transistors N21, N22, and N23 will not exceed the voltage withstand capability of the fully isolated LDMOS transistor. Therefore, the voltage difference between the power supply voltage VGH2 and the power supply voltage VGL2 (e.g., 40 - (-20) = 60 volts) can be greater than the transvoltage withstand capability of any one of the pull-down transistors N21, N22, and N23.

[0025] Figure 5 is a partial circuit diagram of the control circuit 210 according to an embodiment of the present invention. Referring to Figures 2 and 5, the control circuit 210 also includes a node voltage generation circuit 510 as shown in Figure 5. The node voltage generation circuit 510 is coupled to a first terminal of pull-down transistor N22 and a second terminal of pull-down transistor N21 to receive the node voltage VBOOT. The node voltage generation circuit 510 can generate a node voltage VBOOT_REG based on the node voltage VBOOT. The power supply terminal of the driver 520 (e.g., driver 213 or 215 shown in Figure 2) is coupled to the node voltage generation circuit 200 to receive the node voltage VBOOT_REG. The reference terminal of the driver 520 is coupled to a first terminal of pull-down transistor N22 and a second terminal of pull-down transistor N21 to receive the node voltage VBOOT.

[0026] In the embodiment shown in Figure 5, the node voltage generation circuit 510 includes a current source 511, a transistor 512, a transistor 513, a capacitor 514, a transistor 515, a transistor 516, and a current source 517. A first terminal of the current source 511 is coupled to a differential voltage, such as the original high level VH (e.g., 5 volts). A first terminal (e.g., drain) of the transistor 512 is coupled to a control terminal (e.g., gate) to a second terminal of the current source 511. A first terminal (e.g., drain) of the transistor 513 is coupled to a control terminal (e.g., gate) to the second terminal (e.g., source) of the transistor 512. The second terminal (e.g., source) of the transistor 513 is coupled to a first terminal of pull-down transistor N22 and a second terminal of pull-down transistor N21 to receive the node voltage VBOOT. A first terminal of the capacitor 514 is coupled to a first terminal of the transistor 512. A second terminal of the capacitor 514 is coupled to a second terminal of the transistor 513.

[0027] Transistor 515 has its first terminal (e.g., drain) coupled to a supply voltage VGH2 (e.g., 40 volts). Transistor 515's control terminal (e.g., gate) coupled to a differential voltage, such as the original high level VH (e.g., 5 volts). Transistor 516 has its first terminal (e.g., drain) coupled to the second terminal (e.g., source) of transistor 515. Transistor 516's control terminal (e.g., gate) coupled to the first terminal of transistor 512. Transistor 516's second terminal (e.g., source) coupled to the power supply terminal of driver 520 to provide the node voltage VBOOT_REG. Transistors 515 and 516 can be laterally diffused MOS (LDMOS) transistors. Current source 517 has its first terminal coupled to the second terminal of transistor 516. Current source 517 has its second terminal coupled to the first terminals of pull-down transistors N22 and N21 to receive the node voltage VBOOT.

[0028] In summary, pull-down transistors N21 and N22 can be fully isolated MOS transistors. Therefore, pull-down transistors N21 and N22 will not leak current to the die substrate. Because fully isolated MOS transistors do not leak current, the die substrate voltage can be set to 0 volts. Therefore, the adhesive layer between the die substrate and the package base plate can be made of a conductive material (because the voltage of the package base plate is generally 0 volts). It is conceivable that if the adhesive layer between the die substrate and the package base plate is a conductive material, the heat energy of the die can be easily conducted to the outside of the package through the adhesive layer and the package base plate. Furthermore, pull-down transistors N21 and N22 are connected in series between the output terminal LVSH_OUT2 of the level offset 200 and the power supply voltage VGL2, where the power supply voltage VGL2 is lower than the die substrate voltage (generally 0 volts). Therefore, the voltage withstand capability (rated maximum source-drain voltage) of either pull-down transistor N21 or N22 can be less than the voltage difference between the power supply voltage VGH2 and the power supply voltage VGL2.

[0029] Figure 6 is a circuit block diagram of a level shifter 600 according to another embodiment of the present invention. The level shifter 600 is disposed in a die. The level shifter 600, input terminal LVSH_IN6, output terminal LVSH_OUT6, load circuit, control circuit 610, power supply voltage VGH6, pull-up transistor P61, pull-down transistor N61, pull-down transistor N62 and power supply voltage VGL6 shown in Figure 6 can be deduced by referring to the relevant description of the level shifter 200, input terminal LVSH_IN2, output terminal LVSH_OUT2, load circuit, control circuit 210, power supply voltage VGH2, pull-up transistor P21, pull-down transistor N21, pull-down transistor N22 and power supply voltage VGL2 shown in Figure 2, and by analogy, so it will not be described again.

[0030] Unlike the level shifter 200 shown in Figure 2, the level shifter 600 shown in Figure 6 includes a charge-sharing diode D61. A first terminal (e.g., anode) of the charge-sharing diode D61 is coupled to a first terminal of a pull-down transistor N62 and a second terminal of the pull-down transistor N61 to receive the node voltage VBOOT. The second terminal (e.g., cathode) of the charge-sharing diode D61 is coupled to a charge-sharing voltage VCS6. The level of the charge-sharing voltage VCS6 is between the supply voltage VGH6 and the supply voltage VGL6. The level of the charge-sharing voltage VCS6 can be determined according to the actual design. For example (but not limited to), the level of the charge-sharing voltage VCS6 can be 0 volts or other fixed levels.

[0031] Figure 7 is a schematic diagram illustrating the operation of transistors P61, N61, and N62 according to another embodiment of the present invention. Referring to Figures 6 and 7, in the transition phase P71, the input terminal LVSH_IN6 is at its original low level VL (e.g., 0 volts). Therefore, the control circuit 610 cuts off the pull-up transistor P61 and turns on the pull-down transistors N61 and N62. At this time, the output voltage of the output terminal LVSH_OUT6 is pulled down to the level of the power supply voltage VGL6 (e.g., -20 volts), and the node voltage VBOOT is also pulled down to the level of the power supply voltage VGL6.

[0032] In response to the input voltage at the level offset terminal LVSH_IN6 of the level offset unit 600 transitioning from the original low level VL to the original high level VH (e.g., 5 volts), the control circuit 610 turns on the pull-down transistor N62 and turns off the pull-up transistors P61 and N61 in transition phase P72. In transition phase P73 following transition phase P72, the control circuit 610 turns off the pull-up transistors P61, N62, and N61. In transition phase P74 following transition phase P73, the control circuit 610 turns on the pull-up transistor P61 and turns off the pull-down transistors N61 and N62. At this time, the output voltage at the output terminal LVSH_OUT6 is pulled up to the level of the supply voltage VGH6 (e.g., 40 volts).

[0033] In response to the input voltage at the level offset terminal LVSH_IN6 of the level offset device 600 transitioning from the original high level VH to the original low level VL, the control circuit 610 cuts off the pull-up transistor P61, pull-down transistor N62, and pull-down transistor N61 in the transition stage P75 after transition stage P74. In the transition stage P76 after transition stage P75, the control circuit 610 turns on the pull-down transistor N62 and the charge-sharing diode D61, and cuts off the pull-up transistor P61 and pull-down transistor N61. At this time, the output voltage at the output terminal LVSH_OUT6 and the node voltage VBOOT are pulled to the level of the charge-sharing voltage VCS6. In the transition stage P77 after transition stage P76, the control circuit 610 turns on the pull-down transistor N61 and pull-down transistor N62, and cuts off the pull-up transistor P61. At this time, the output voltage of the output terminal LVSH_OUT6 and the node voltage VBOOT are pulled to the level of the power supply voltage VGL6.

[0034] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0035] 100, 200, 600: Level offset device 210, 610: Control circuit 211: Logic Circuits 212, 213, 214, 215, 520: Drivers 510: Node voltage generation circuit 511, 517: Current Source 512, 513, 515, 516: Transistors 514: Capacitor D61: Charge-sharing diode GND1: Grounding voltage LVSH_IN2, LVSH_IN6: Input terminals LVSH_OUT1, LVSH_OUT2, LVSH_OUT6: Output terminals N11, N21, N22, N61, N62: Pull-down transistors N12, N13, N23: Charge-sharing transistors P11, P21, P61: Pull-up transistors Pages 31-39, Pages 71-77: Transition Phase VBOOT, VBOOT_REG: Node voltage VCS2, VCS6: Charge sharing voltage VG11, VG12, VG13, VGBS, VGCS, VGHS, VGLS: Control signals VGH1, VGH2, VGH6, VGL1, VGL2, VGL6, VHS_REG, VLS_REG: Power supply voltage VH: Original High Level VL: Original Low Level

Claims

1. A level shifter disposed on a grain, the level shifter comprising: A pull-up crystal has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the pull-up crystal is coupled to a first power supply voltage, the first power supply voltage being higher than a base voltage of the crystal, and the second terminal of the pull-up crystal is coupled to an output terminal of a level shifter; a first pull-down crystal has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first pull-down crystal is coupled to a second power supply voltage, and the second power supply voltage being lower than the base voltage of the crystal; a second pull-down crystal has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second pull-down crystal is coupled to the second terminal of the first pull-down crystal, and the second terminal of the second pull-down crystal is coupled to the output terminal of the level shifter; The control circuit includes an input terminal, a first output terminal, a second output terminal, and a third output terminal, wherein the input terminal of the control circuit is coupled to an input terminal of the level offset device, the first output terminal of the control circuit is coupled to the control terminal of the pull-up crystal, the second output terminal of the control circuit is coupled to the control terminal of the second pull-down crystal, and the third output terminal of the control circuit is coupled to the control terminal of the first pull-down crystal.

2. The level shifter as claimed in claim 1, wherein the first pull-down transistor and the second pull-down transistor are fully isolated high voltage metal-oxide-semiconductor transistors.

3. The level offset device as claimed in claim 2, wherein the first pull-down transistor and the second pull-down transistor are fully isolated laterally diffused metal-oxide-semiconductor transistors.

4. The level shifter as claimed in claim 1, wherein the voltage difference between the first power supply voltage and the second power supply voltage is greater than the transvoltage withstand capability of either the first pull-down transistor or the second pull-down transistor.

5. The level shifter as described in claim 1, further comprising: A charge-sharing transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the charge-sharing transistor is coupled to the first terminal of a second pull-down transistor and the second terminal of the first pull-down transistor, the second terminal of the charge-sharing transistor is coupled to a charge-sharing voltage, and the control terminal of the charge-sharing transistor is coupled to a fourth output terminal of a control circuit.

6. The level offset device as claimed in claim 5, wherein the level of the charge-sharing voltage is between the first power supply voltage and the second power supply voltage.

7. The level shifter as described in claim 5, wherein, In response to an input voltage at the input terminal of the level offset device transitioning from an initial low level to an initial high level, the control circuit, in a first transition phase, turns on the second pull-down transistor and turns off the pull-up transistor, the first pull-down transistor, and the charge-sharing transistor; in a second transition phase following the first transition phase, the control circuit turns on the second pull-down transistor and the charge-sharing transistor and turns off the pull-up transistor and the first pull-down transistor; in a third transition phase following the second transition phase, the control circuit turns on the charge-sharing transistor and turns off the pull-up transistor, the first pull-down transistor, and the second pull-down transistor; and in a fourth transition phase following the third transition phase, the control circuit turns on the pull-up transistor and the charge-sharing transistor and turns off the first pull-down transistor and the second pull-down transistor. In response to an input voltage at the input terminal of the level offset device transitioning from the original high level to the original low level, the control circuit turns on the charge-sharing transistor and turns off the pull-up transistor, the first pull-down transistor, and the second pull-down transistor in a fifth transition phase; in a sixth transition phase following the fifth transition phase, the control circuit turns on the second pull-down transistor and the charge-sharing transistor and turns off the pull-up transistor and the first pull-down transistor; in a seventh transition phase following the sixth transition phase, the control circuit turns on the second pull-down transistor and turns off the pull-up transistor, the first pull-down transistor, and the charge-sharing transistor; and in an eighth transition phase following the seventh transition phase, the control circuit turns on the first pull-down transistor and the second pull-down transistor and turns off the pull-up transistor and the charge-sharing transistor.

8. The level shifter as claimed in claim 1, wherein the first output of the control circuit outputs a first control signal to control the control terminal of the pull-up crystal, the second output of the control circuit outputs a second control signal to control the control terminal of the second pull-down crystal, the third output of the control circuit outputs a third control signal to control the control terminal of the first pull-down crystal, the voltage between the first terminal of the second pull-down crystal and the second terminal of the first pull-down crystal is a first node voltage, a second node voltage is the first node voltage plus a differential voltage, and the swing of the second control signal is between the first node voltage and the second node voltage.

9. The level shifter as claimed in claim 8, wherein the control circuitry includes: A node voltage generating circuit is coupled to the first terminal and the second terminal of the second pull-down crystal to receive the first node voltage, wherein the node voltage generating circuit generates the second node voltage based on the first node voltage; and a driver has a power supply terminal, a reference terminal and an output terminal, wherein the power supply terminal of the driver is coupled to the node voltage generating circuit to receive the second node voltage, the reference terminal of the driver is coupled to the first terminal and the second terminal of the second pull-down crystal to receive the first node voltage, and the output terminal of the driver is coupled to the control terminal of the second pull-down crystal to provide the second control signal.

10. The level shifter as claimed in claim 9, wherein the node voltage generation circuit includes: A first current source having a first terminal and a second terminal, wherein the first terminal of the first current source is coupled to the differential voltage; A first transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal and the control terminal of the first transistor are coupled to the second terminal of the first current source; and a second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal and the control terminal of the second transistor are coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the first terminal and the second terminal of the first pull-down transistor to receive the first node voltage; and a third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the first power supply voltage, and the control terminal of the third transistor is coupled to the differential voltage; A fourth transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the third transistor, the control terminal of the fourth transistor is coupled to the first terminal of the first transistor, and the second terminal of the fourth transistor is coupled to the power supply terminal of the driver. And a second current source having a first terminal and a second terminal, wherein the first terminal of the second current source is coupled to the second terminal of the fourth transistor, and the second terminal of the second current source is coupled to the first terminal of the second pull-down transistor and the second terminal of the first pull-down transistor to receive the first node voltage.

11. The level shifter as claimed in claim 8, wherein a third power supply voltage is the first power supply voltage minus a differential voltage, and the swing of the first control signal is between the first power supply voltage and the third power supply voltage.

12. The level shifter as claimed in claim 8, wherein a fourth power supply voltage is the second power supply voltage plus a differential voltage, and the swing of the third control signal is between the fourth power supply voltage and the second power supply voltage.

13. The level shifter as described in claim 1, further comprising: A charge-sharing diode has a first terminal and a second terminal, wherein the first terminal of the charge-sharing diode is coupled to the first terminal of the second pull-down transistor and the second terminal of the first pull-down transistor, and the second terminal of the charge-sharing diode is coupled to a charge-sharing voltage.

14. The level offset device as claimed in claim 13, wherein the level of the charge-sharing voltage is between the first power supply voltage and the second power supply voltage.

15. The level shifter as described in claim 13, wherein, In response to an input voltage at the input terminal of the level offset device transitioning from an initial low level to an initial high level, the control circuit turns on the second pull-down transistor and turns off the pull-up transistor and the first pull-down transistor in a first transition phase; in a second transition phase following the first transition phase, the control circuit turns off the pull-up transistor, the second pull-down transistor, and the first pull-down transistor; and in a third transition phase following the second transition phase, the control circuit turns on the pull-up transistor and turns off the first pull-down transistor and the second pull-down transistor; and in response to When the input voltage at the input terminal of the level offset device changes from the original high level to the original low level, the control circuit turns off the pull-up transistor, the second pull-down transistor, and the first pull-down transistor in a fourth transition phase. In a fifth transition phase after the fourth transition phase, the control circuit turns on the second pull-down transistor and the charge-sharing diode and turns off the pull-up transistor and the first pull-down transistor. In a sixth transition phase after the fifth transition phase, the control circuit turns on the first pull-down transistor and the second pull-down transistor and turns off the pull-up transistor.

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