Semiconductor device and method of forming the same

Abstract

The method includes removing a plurality of first nanostructures from a plurality of nanostructures, wherein the nanostructures include a plurality of first nanostructures and a plurality of second nanostructures stacked in an alternating manner; performing a trimming process on the second nanostructures after removing the first nanostructures, wherein the trimming process increases the curvature of at least a first corner of the second nanostructures; forming a sacrificial material between the second nanostructures; and replacing the sacrificial material to form a gate stack.

Description

[Technical Field]

[0001] The present invention relates to a trimming process for reducing impurities on the surface of nanostructures, which can round off the corner areas of nanostructures. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to integrate more components into a given area. However, as the minimum structural dimensions decrease, additional problems arise that need to be addressed. [Summary of the Invention]

[0004] In some embodiments, the method of forming a semiconductor device includes removing a plurality of first nanostructures from a plurality of nanostructures, wherein the nanostructures include staggered stacked first nanostructures and a plurality of second nanostructures; performing a trimming process on the second nanostructures after removing the first nanostructures, wherein the trimming process increases the curvature of at least a first corner of the second nanostructures; forming a sacrificial material between the second nanostructures; and replacing the sacrificial material to form a gate stack.

[0005] In some embodiments, a method of forming a semiconductor device includes removing a plurality of first nanostructures from a plurality of nanostructures to define an opening between a plurality of second nanostructures of the nanostructures, wherein the first nanostructures and the second nanostructures are stacked perpendicularly, and wherein the step of removing the first nanostructures leaves a plurality of impurities on the surface of the second nanostructures in the opening; removing the impurities from the surface of the second nanostructures in the opening by a trimming process; forming a sacrificial material in the opening between the second nanostructures; and replacing the sacrificial material into a gate stack.

[0006] In some embodiments, the semiconductor device includes a first source / drain region and a second source / drain region; a plurality of nanostructures extending between the first source / drain region and the second source / drain region, wherein a first corner of a first nanostructure of the nanostructure has a first radius of 0.9 nm to 2 nm in a first cross-section; and a gate stack located on the nanostructures and covering the nanostructures.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify the present invention and not to limit it. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] In addition, spatial relative terms such as "below," "below," "lower," "above," "higher," or similar terms are used to describe the relationship between some elements or structures in the diagram and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0011] In various embodiments, the method of forming a nanostructured field-effect transistor includes forming a plurality of first nanostructures and a plurality of second nanostructures in an alternating stack. The second nanostructures are then replaced with a gate stack that may surround the first nanostructures. The step of replacing the second nanostructures may include removing the second nanostructures to define openings between the first nanostructures, depositing sacrificial material in the openings between the first nanostructures, and replacing the sacrificial material with the gate stack. Removing the second nanostructures may leave residues (such as impurities) on the surface of the first nanostructures, and various embodiments may include trimming the first nanostructures to remove impurities. This can improve the device performance of the final nanostructured field-effect transistor (e.g., increased carrier mobility, reduced channel resistance, or similar performance).

[0012] Trimming the first nanostructure can further round out the corner regions of the first nanostructure (e.g., by increasing its curvature). For example, the vertical and / or horizontal radii of the trimmed first nanostructure can be from 0.9 nm to 2 nm. It has been found that rounded corners (especially corners with radii falling within the above range) can increase the deposition allowance of the gate stack. In this way, the gate gap-filling effect between the first nanosheets can be improved, the gaps in the gate stack can be reduced, and the damage to the high-dielectric-constant gate dielectric layer (due to corona discharge over time) can be reduced.

[0013] The following embodiments are specifically illustrated using a grain containing a nanostructured field-effect transistor. However, various embodiments can be used for grains containing other types of transistors (such as stacked transistors or the like), which may replace or be combined with nanostructured transistors.

[0014] Figure 1 is a three-dimensional view of a nanostructured field-effect transistor (such as a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like) in some embodiments. Figure 1 has been simplified and / or specific structures omitted for ease of illustration. The nanostructured field-effect transistor includes a second nanostructure 54 (such as a nanosheet, nanowire, or the like) on a fin 66 on a substrate 50 (such as a semiconductor substrate), wherein the second nanostructure 54 serves as a channel region used by the nanostructured field-effect transistor. The second nanostructure 54 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. Shallow trench isolation regions 68 (also considered as shallow trench isolation structures) are located between adjacent fins 66, and the fins 66 may protrude above the shallow trench isolation regions 68 from between adjacent shallow trench isolation regions 68. Although the shallow trench isolation region 68 in the illustration and figures is separated from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate itself or a combination of a semiconductor substrate and a shallow trench isolation region. Furthermore, although the bottom of the fin 66 in the figures and the substrate 50 are a single continuous material, the bottom of the fin 66 and / or the substrate 50 may comprise a single material or multiple materials. In this illustration, the fin 66 may be considered as a portion extending between adjacent shallow trench isolation regions 68.

[0015] The gate dielectric layer 100 is located above the upper surface of the fin 66 and extends along the upper surface, sidewalls, and lower surface of the second nanostructure 54. The gate 102 is located on the gate dielectric layer 100. Epitaxial source / drain regions 92 are located on the fins 66 on both sides of the gate dielectric layer 100 and the gate 102. The epitaxial source / drain regions 92 can be considered as sources or drains individually or together, depending on their purpose.

[0016] Figure 1 also shows the reference cross-sections used in subsequent diagrams. Cross-section A-A' is along the longitudinal axis of the gate 102 and its direction is perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor, and its direction is the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nanostructured field-effect transistor. Subsequent diagrams will be based on these reference cross-sections for clarity.

[0017] Some embodiments described herein are illustrated using nanostructured field-effect transistors formed by a post-gate process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments may be used for planar devices (such as planar field-effect transistors) or finned field-effect transistors.

[0018] Figures 2 to 21C are cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Figures 2, 3, 4, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 15C, 15D, 15E, 16A, 16C, 17A, 18A, and 19A are cross-sectional views of section A-A' shown in Figure 1. Figures 5B, 6B, 6C, 7B, 8B, 9B, 10B, 10C, 10D, 11B, 12B, 13B, 14B, 15B, 15F, 16B, 16D, 17B, 18B, and 19B are cross-sectional views of section B-B' shown in Figure 1. Figures 7C, 11C, 11D, 17C, and 19C are sectional views of section C-C' shown in Figure 1.

[0019] In Figure 2, a substrate 50 may be provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer may be provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an n-type metal-oxide-semiconductor (e.g., an n-type nanostructured field-effect transistor), while the p-type region 50P can be used to form a p-type device such as a p-type metal-oxide-semiconductor (e.g., a p-type nanostructured field-effect transistor). The n-type region 50N and the p-type region 50P can be physically separated (e.g., separated by a separator 20), and any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) can be located between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. The process steps illustrated in the following figures can be performed in either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0021] As shown in FIG. 2, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes staggered first semiconductor layers 51A to 51C (which can be considered together as first semiconductor layer 51) and second semiconductor layers 53A to 53C (which can be considered together as second semiconductor layer 53). For illustrative purposes, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P, as detailed below. Nevertheless, in some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P. For example, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (such as silicon or another semiconductor material) and may be formed simultaneously.

[0022] In other embodiments, the first semiconductor layer 51 may be removed from the p-type region 50P and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructured field-effect transistor in the p-type region 50P. The second semiconductor layer 53 may be removed from the n-type region 50N and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructured field-effect transistor in the n-type region 50N. In other embodiments, the first semiconductor layer 51 may be removed from the n-type region 50N and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructured field-effect transistor in the n-type region 50N. The second semiconductor layer 53 may be removed from the p-type region 50P and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructured field-effect transistor in the p-type region 50P. In these embodiments, the channel region of the n-type region 50N and the channel region of the p-type region 50P may have different material compositions. The first semiconductor layer 51 and the second semiconductor layer 53 can be selectively removed from the n-type region 50N and the p-type region 50P by additional masking and etching steps. For example, the channel region of the n-type region 50N can be a silicon channel region, and the channel region of the p-type region 50P can be a silicon-germanium channel region.

[0023] The multilayer stack 64 shown in the figure contains three first semiconductor layers 51 and three second semiconductor layers 53, but it is for illustrative purposes only. In some embodiments, the multilayer stack 64 may contain any number of first semiconductor layers 51 and second semiconductor layers 53. The epitaxial growth process used for each layer of the multilayer stack 64 may be chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or a similar process.

[0024] In various embodiments, the first semiconductor layer 51 may be composed of a first semiconductor material such as silicon germanium or the like, while the second semiconductor layer 53 may be composed of a second semiconductor material such as silicon, silicon carbide, or the like. The first semiconductor material and the second semiconductor material may be materials with high etch selectivity relative to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby patterning the second semiconductor layer 53 to form the channel region of the nanostructured field-effect transistor.

[0025] As shown in some embodiments of FIG3, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, the method of forming nanostructures 55 and fins 66 in multilayer stack 64 and substrate 50, respectively, may be etching trenches 58 in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. Etching may be anisotropic. During the etching process, a hard mask 56 may be used to define the pattern of fins 66 and nanostructures 55. Hard mask 56 may include any suitable insulating material, such as oxides, nitrides, oxynitrides, carbonitrides, or the like. In some embodiments (not shown), hard mask 56 may be a multilayer structure. Acceptable processes such as thermal oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, or similar methods may be used to form hard mask 56 on nanostructure 55.

[0026] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, a sacrificial layer can be formed on a substrate and patterned using a photolithography process. A self-alignment process is then used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0027] The method of etching the multilayer stack 64 to form the nanostructure 55 may further define first nanostructures 52A to 52C (which can be regarded together as the first nanostructure 52) from the first semiconductor layer 51, and second nanostructures 54A to 54C (which can be regarded together as the second nanostructure 54) from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be regarded together as the nanostructure 55.

[0028] The fins 66 shown in FIG3 have substantially the same width and are for illustrative purposes only. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although the fins 66 and nanostructures 55 shown in FIG3 each have the same width, in other embodiments the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In these embodiments, the nanostructures 55 may each have different widths and be trapezoidal.

[0029] In Figure 4, a shallow trench isolation region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 may be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66 to fill the trench 58. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar methods, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In the embodiment described, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material illustrated is a single layer, some embodiments may use multilayer insulating materials. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructure 55. The filling material described above may then be formed on the liner.

[0030] Next, a removal process can be performed on the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back process, a combination of the above, or a similar process can be used. The planarization process exposes the nanostructure 55 so that the nanostructure 55 after the planarization process is completed is flush with the upper surface of the insulating material.

[0031] Next, the insulating material is recessed to form shallow trench isolation regions 68. The recessed insulating material causes the upper portion of the fin 66 to protrude from between adjacent shallow trench isolation regions 68. Furthermore, the upper surface of the shallow trench isolation region 68 can be a flat surface, a convex surface, a recessed surface (such as dishing), or a combination thereof, as illustrated. The upper surface of the shallow trench isolation region 68 can be made flat, convex, and / or recessed by suitable etching. An acceptable etching process can be used to recess the shallow trench isolation region 68, such as an etching process selective for the insulating material (where the etching rate of the insulating material is greater than the etching rate of the material between the fin 66 and the nanostructure 55). For example, an oxide removal method can be used, which may employ diluted hydrofluoric acid. A hard mask (not shown) can then be formed on the upper surface of the shallow trench isolation region 68 to cover it. The hard mask may be composed of nitrides or other materials that are etch-selective relative to the shallow trench isolation region 68 (e.g., etch-selective relative to the filler material of the shallow trench isolation region 68).

[0032] As shown in FIG. 4, suitable wells (not shown) can be formed in the fins 66 and / or nanostructures 55. In embodiments with different well morphologies, photoresist or other masks (not shown) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed on the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurities can be implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent the implantation of n-type impurities into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and their concentration in the implanted region can be from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. The photoresist can be removed after application, and the removal method can be an acceptable ashing process.

[0033] Before or after implanting the p-type region 50P, photoresist or other masks (not shown) may be formed on the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurities may be implanted in the n-type region 50N, and the photoresist may act as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like, and their concentration in the implanted region may be from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. The photoresist may be removed after implantation, and the removal method may be an acceptable ashing process.

[0034] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, in-situ doping can be performed during the growth of the epitaxial fin to omit implantation, but in-situ doping and implantation doping can be used in combination.

[0035] In Figures 5A and 5B, a dummy gate 76 is formed along the sidewalls of the nanostructure 55 and the fin 66, and is located on the nanostructure 55 and the fin 66. To form the dummy gate 76, a dummy dielectric layer is first formed on the fin 66 and / or the nanostructure 55. For example, the dummy dielectric layer may be silicon oxide, silicon nitride, a combination thereof, or the like, and its formation method may be deposition or thermal growth according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a masking layer is formed on the dummy gate layer. The dummy gate layer may be deposited on the dummy dielectric layer, and then the dummy gate layer may be planarized by methods such as chemical mechanical polishing. The masking layer may be deposited on the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, or metals. The deposition method for the dummy gate layer can be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other techniques used to deposit selected materials. The composition of the dummy gate layer can be other materials that exhibit high etch selectivity relative to the isolation region. For example, the masking layer may include silicon nitride, silicon oxynitride, or the like.

[0036] Subsequently, an acceptable photolithography and etching technique can be used to pattern the mask layer to form mask 78. The pattern of mask 78 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 76 and dummy gate dielectric layer 70, respectively. Dummy gate 76 covers individual channel regions of fin 66. The pattern of mask 78 can be used to physically separate adjacent dummy gates 76 from each other. The length direction of dummy gate 76 can also be substantially perpendicular to the length direction of individual fins 66. It is worth noting that the illustrated dummy gate dielectric layer 70 only covers fins 66 and nanostructure 55 and is for illustrative purposes only. In some embodiments, dummy gate dielectric layer 70 can be deposited to cover shallow trench isolation region 68, such that dummy gate dielectric layer 70 extends between dummy gate 76 and shallow trench isolation region 68. The method of patterning the dummy gate 76 and the dummy gate dielectric layer 70 can create any suitable sidewall profile. For example, the dummy gate 76 and the dummy gate dielectric layer 70 may have flat sidewalls (as shown in Figure 5B) or curved sidewalls (as shown in Figure 6C). Specifically, the bottom region of the dummy gate 76 and the dummy gate dielectric layer 70 may include rounded recessed sidewalls.

[0037] In Figures 6A and 6B, a gate spacer 81 is formed on the nanostructure 55 and the shallow trench isolation region 68, and on the exposed sidewalls of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric layer 70. The gate spacer 81 can be formed by conformally forming one or more dielectric materials, followed by etching. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, and can be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or similar methods. Other insulating materials formed using any acceptable process may be used. Any acceptable etching process such as dry etching, wet etching, similar processes, or combinations thereof may be performed to pattern the dielectric material. The etching may be anisotropic. The etched dielectric material has a portion remaining on the sidewalls of the dummy gate 76, thus forming the gate spacer 81. As detailed below, the etched dielectric material may also partially remain on the sidewalls of the fins 66 and / or nanostructures 55, thus forming fin spacers 83 (see Figure 7C). The etched fin spacers 83 and / or gate spacers 81 may have straight sidewalls (as shown) or curved sidewalls (not shown).

[0038] Although the gate spacer 81 shown in FIG. 6B is a single layer, the gate spacer 81 in other embodiments may be a multilayer structure. For example, the gate spacer 81 shown in FIG. 6C is a multilayer structure containing a first gate spacer 81A and a second gate spacer 81B located on the first gate spacer 81A. The first gate spacer 81A and the second gate spacer 81B may be formed by conformally forming at least two dielectric materials, followed by etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, nitrides, silicon oxynitride, silicon carbonitride, or the like, and their formation methods may be deposition processes such as chemical vapor deposition, atomic layer deposition, or similar processes. The first gate spacer 81A and the second gate spacer 81B may be composed of different materials, and they may have etching selectivity relative to each other. For example, the first gate spacer 81A may be composed of an oxide or similar compound, while the second gate spacer 81B may be composed of a nitride. Other combinations of insulating materials formed by any acceptable process may also be used. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. The etched dielectric material has an L-shaped portion retained on the sidewall of the dummy gate 76 (thus forming the first gate spacer 81A) and a portion retained on the L-shaped portion (thus forming the second gate spacer 81B).

[0039] Furthermore, the placement of lightly doped source / drain regions (not shown) can be performed. The placement of lightly doped source / drain regions can be performed before forming the gate spacer 81. In embodiments of different device types, similar to the placement used in the aforementioned well, a mask, such as photoresist, can be formed on the n-type region 50N, exposing the p-type region 50P. A suitable type (e.g., p-type) of impurity can be placed into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Afterwards, a mask, such as photoresist, can be formed on the p-type region 50P, exposing the n-type region 50N. A suitable type (e.g., n-type) of impurity can be placed into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration in the lightly doped source / drain regions can be from 10¹⁵ atoms / cm³ to 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0040] It is worth noting that the above describes a general process for forming spacers and lightly doped source / drain regions. Other processes and sequences may also be used. For example, fewer or more spacers may be used, different step sequences may be used, additional spacers may be formed and removed, and / or similar adjustments may be made. Furthermore, different structures and steps may be used to form n-type devices and p-type devices.

[0041] In some embodiments shown in Figures 7A to 7C, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region may be formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 into the substrate 50. As shown in Figure 7C, the upper surface of the shallow trench isolation region 68 may be flush with the lower surface of the first recess 86. In other embodiments, the fin 66 may be etched such that the lower surface of the first recess 86 is higher or lower than the upper surface of the shallow trench isolation region 68. The first recess 86 may be formed using anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar etching to etch the fin 66, the nanostructure 55, and the substrate 50. During the etching process that forms the first recess 86, the gate spacer 81, fin spacer 83, and mask 78 can mask portions of the fin 66, nanostructure 55, and substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. A time-controlled etching process can be used to stop etching the first recess 86 when it reaches the desired depth.

[0042] In Figures 8A to 9B, the first nanostructure 52 is replaced with a sacrificial material 72 (which can also be considered as a one-time oxide interlayer). As shown in Figures 8A and 8B, the method of replacing the first nanostructure 52 may include using a suitable etching process, such as an isotropic etching process, to etch and remove the first nanostructure 52 via the first recess 86. The etching process may be selective for the material of the first nanostructure 52 and may remove the first nanostructure 52 without significantly removing the second nanostructure 54 or the fin 66. In embodiments where the first nanostructure 52 comprises silicon germanium and the second nanostructure 54 comprises silicon or silicon carbide, a dry etching process using tetramethylammonium hydroxide, ammonium hydroxide, or the like may be used to remove the first nanostructure 52. The process of removing the first nanostructure 52 may leave residual impurities 88 on the surface of the second nanostructure 54 in the area where the first nanostructure 52 was removed (e.g., in the first recess 86). Impurities 88 may include elements of the first nanostructure 52 (such as germanium, when the first nanostructure 52 includes silicon germanium), and / or residues from the etching process used to remove the first nanostructure 52.

[0043] Subsequently, a sacrificial material layer 71 is deposited in the space formed by the first recess 86 and the removal of the first nanostructure 52. The deposition method of the sacrificial material layer 71 may be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or similar methods. The sacrificial material layer 71 may include an insulating material such as silicon oxide or the like, and its etch selectivity differs from that of the second nanostructure 54. In Figures 9A and 9B, the sacrificial material layer 71 may then be etched to form a sacrificial material 72. The etching may be isotropic or anisotropic. For example, the etching method of the sacrificial material layer may be a wet etching process using diluted hydrofluoric acid or the like as an etchant. In some embodiments, etching is performed until the sidewalls of the sacrificial material 72 are recessed compared to the sidewalls of the second nanostructure 54. Although the sidewalls of the sacrificial material 72 shown in Figure 9B are flat, these sidewalls may be recessed or protruding (see Figure 10C). Since impurity 88 is retained on the surface of the second nanostructure 54 deposited on the sacrificial material layer 71, impurity 88 can be located at the interface between the second nanostructure 54 and the sacrificial material 72.

[0044] Replacing the first nanostructure 52 with the sacrificial material 72 offers advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed to activate the dopants in the source / drain regions. When the material of the first nanostructure 52 (such as silicon-germanium) is exposed to high temperatures, germanium may mix with each other and increase the interface roughness between the first nanostructure 52 and the second nanostructure 54. These manufacturing defects can degrade the performance of the final transistor device. For example, when germanium diffuses into the second nanostructure 54, germanium residues may remain in the channel region of the final transistor device, negatively impacting the performance of the channel region. Replacing the first nanostructure 52 with an insulating material (such as the sacrificial material 72) before high-temperature processes (such as source / drain annealing) can reduce manufacturing defects and improve device performance (such as increasing drive current, reducing capacitance, and improving short-channel effects).

[0045] In Figures 10A and 10B, an inner spacer 90 is formed in a first recess 86 on the sidewall of the sacrificial material 72. The inner spacer 90 may be formed between the second nanostructures 54, and the impurity 88 may be located at the interface between the inner spacer 90 and the second nanostructure 54. The inner spacer 90 serves as an isolation structure between the subsequently formed source / drain region and the gate structure.

[0046] As detailed below, a source / drain region can be formed in the first recess 86, and the sacrificial material 72 can be replaced to form a corresponding gate structure. The inner spacer 90 can also be used to prevent subsequent etching processes (such as the etching process used to form the gate structure) from damaging the subsequently formed source / drain region.

[0047] The inner spacer 90 can be formed by depositing an inner spacer layer (not shown) on the structures shown in Figures 9A and 9B. The deposition method of the inner spacer layer can be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The inner spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material such as a low dielectric constant material with a dielectric constant lower than about 3.5 can be used. The inner spacer layer can then be anisotropically etched to form the inner spacer 90. The etching method of the inner spacer layer can be anisotropic etching processes such as reactive ion etching, neutral beam etching, or a similar process.

[0048] Although the outer sidewall of the inner spacer 90 in FIG. 10B is flush with the sidewall of the second nanostructure 54, the outer sidewall of the inner spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54 (see FIG. 10C). Furthermore, although the outer sidewall of the inner spacer 90 shown in FIG. 10B is straight, the outer sidewall of the inner spacer 90 may be recessed or protruding. For example, in the embodiment shown in FIG. 10C, the sidewall of the sacrificial material 72 is recessed, the outer sidewall of the inner spacer 90 is recessed, and the inner spacer 90 may be recessed from the sidewall of the second nanostructure 54. Other configurations are also possible. For example, in the embodiment shown in FIG. 10D, the sidewall of the sacrificial material 72 is recessed, the outer sidewall of the inner spacer 90 is straight, and the inner spacer 90 is flush with the sidewall of the second nanostructure 54.

[0049] In Figures 11A to 11D, epitaxial source / drain regions 92 are formed in a first recess 86. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the p-type region 50P, thereby improving performance. As shown in Figure 11B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that dummy gates 76 are each located between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while inner spacers 90 are used to provide a suitable lateral distance between the epitaxial source / drain regions 92 and the sacrificial material 72, so that the epitaxial source / drain regions 92 do not short-circuit outward to the gate subsequently formed by the final nanostructure field-effect transistor.

[0050] The method for forming the epitaxial source / drain region 92 in the n-type region 50N, such as an n-type metal-oxide-semiconductor region, may be to mask the p-type region 50P, such as a p-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the material comprising the epitaxial source / drain region 92 in the n-type region 50N may be subjected to tensile stress on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0051] The method for forming the epitaxial source / drain region 92 in the p-type region 50P, such as a p-type metal-oxide-semiconductor region, may be to mask the n-type region 50N, such as an n-type metal-oxide-semiconductor region. The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the material comprising the epitaxial source / drain region 92 in the p-type region 50P may be subjected to compressive stress on the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0052] Dopants can be implanted into the epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, which is similar to the process used to form the lightly doped source / drain region described above. Annealing can then be performed. The impurity concentration of the source / drain region can be between about 1 x 10¹⁹ atoms / cm³ and about 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities used in the source / drain region can be any of the aforementioned impurities. In some embodiments, in-situ doping can be performed during the growth of the epitaxial source / drain region 92.

[0053] The epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P results in the upper surface of the epitaxial source / drain regions 92 having crystal planes that laterally extend outward beyond the sidewalls of the nanostructure 55. In some embodiments, these crystal planes cause adjacent epitaxial source / drain regions of the same nanostructure field-effect transistor to merge, as shown in FIG11C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in FIG11D. In the embodiments shown in FIG11C and 11D, fin spacers 83 may be formed on the upper surface of the shallow trench isolation region 68 to block epitaxial growth. In some other embodiments, fin spacers 83 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 83 can be adjusted to remove spacer material and extend the epitaxial growth region to the surface of the shallow trench isolation region 68.

[0054] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, a third semiconductor material layer 92C, and a fourth semiconductor material layer 92D. The epitaxial source / drain region 92 may employ any number of semiconductor material layers.

[0055] The first semiconductor material layer 92A, the second semiconductor material layer 92B, the third semiconductor material layer 92C, and the fourth semiconductor material layer 92D may each be composed of different semiconductor materials and may each be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may be an undoped layer or a lightly doped layer, which avoids or reduces the diffusion of dopants from the upper epitaxial layer (especially the third semiconductor material layer 92C and the fourth semiconductor material layer 92D) into the lower substrate. In a specific example, the first semiconductor material layer 92A and the second semiconductor material layer 92B may be substantially germanium-free silicon layers, while the third semiconductor material layer 92C and the fourth semiconductor material layer 92D may be silicon-germanium layers. The second semiconductor material layer 92B may be a highly doped layer, which can increase the etching selectivity along the sidewalls of the second nanostructure 54 during subsequent oxide etching processes to reduce the risk of accidental etching. The oxide etching process can remove the sacrificial material 72, as shown in the following processes in Figures 14A and 14B. The second semiconductor material layer 92B may include a lateral portion 92B' derived from a doping process performed on an undoped or lightly doped first semiconductor material layer 92A. In embodiments where the epitaxial source / drain region 92 includes four semiconductor material layers, a first semiconductor material layer 92A may be deposited, a suitable dopant may be doped into the first semiconductor material layer 92A to form a second semiconductor material layer 92B and / or a second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, a third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B, and a fourth semiconductor material layer 92D may be deposited on the third semiconductor material layer 92C. Other source / drain configurations are also possible in other embodiments.

[0056] In Figures 12A and 12B, a first interlayer dielectric layer 96 is deposited on the structures shown in Figures 11A and 11B. The first interlayer dielectric layer 96 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer 94 is located between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, the mask 78, and the gate spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with an etch rate different from the etch rate of the material of the upper first interlayer dielectric layer 96.

[0057] After depositing the first interlayer dielectric layer 96, a planarization process such as chemical mechanical polishing can be performed to flush the upper surface of the first interlayer dielectric layer 96 with the upper surface of the dummy gate 76 (as shown) or the upper surface of the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and a portion of the gate spacer 81 along the sidewall of the mask 78. After the planarization process, the dummy gate 76, the gate spacer 81, and the upper surface of the first interlayer dielectric layer 96 can be flush (in process variables). In summary, the upper surface of the dummy gate 76 can be exposed from the first interlayer dielectric layer 96. In some embodiments, the mask 78 can be retained, and the planarization process flushes the upper surface of the first interlayer dielectric layer 96 with the upper surfaces of the mask 78 and the gate spacer 81.

[0058] In Figures 13A and 13B, the dummy gate 76 is removed by one or more etching steps to form the second recess 98. A portion of the dummy gate dielectric layer 70 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric layer 70 may be removed by an isotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases to selectively etch the dummy gate 76 at a rate greater than the rate at which the first interlayer dielectric layer 96 or the gate spacer 81 is etched. Each of the second recesses 98 exposes a portion of the nanostructure 55 and / or is located on a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanostructure field-effect transistor. The portion of the nanostructure 55 serving as a channel region may be located between adjacent pairs of epitaxial source / drain regions 92. During the removal step of etching the dummy gate 76, the dummy gate dielectric layer 70 may serve as an etching stop layer. After removing the dummy gate 76, the dummy gate dielectric layer 70 can be removed.

[0059] In Figures 14A and 14B, sacrificial material 72 is removed to extend the second recess 98. The removal of sacrificial material 72 can be an isotropic etching process such as wet etching or a similar process, using an etchant selective for the material of sacrificial material 72 to ensure that the second nanostructure 54 remains relatively unetched relative to sacrificial material 72. Sacrificial material 72 can be completely removed, or a residue of sacrificial material 72 can be left on the sidewalls of the inner spacers in the second recess 98 (see Figure 16D). Removing sacrificial material 72 exposes impurities 88 on the surface of the second nanostructure 54 in the second recess 98.

[0060] In some embodiments, the shallow trench isolation region 68 may be etched when the sacrificial material 72 is removed, but timing parameters such as time may be controlled during the removal of the sacrificial material 72 to reduce the total loss in the shallow trench isolation region 68. In other embodiments, the shallow trench isolation region 68 may include a hard mask (not shown) on its upper surface to protect the underlying shallow trench isolation region 68 from etching during patterning and removal of the sacrificial material 72. In these embodiments, the hard mask may include a nitride.

[0061] In Figures 15A to 15F, a trimming process is performed on the second nanostructure 54 to remove impurities 88 from exposed surfaces of the second nanostructure 54 (such as the surface of the second nanostructure 54 in the second recess 98). Removing impurities 88 can improve device performance in the final nanostructure field-effect transistor, such as increasing carrier mobility, reducing channel resistance, or similar performance. In some embodiments, the inner spacer 90 and / or residues from the sacrificial material 72 may mask specific areas of the second nanostructure 54 during the trimming process. In this way, a small portion of the impurities 88 may remain between the inner spacer 90 and the second nanostructure 54 (see Figures 15F and 16D). The area of ​​the retained impurities 88 is small, and device performance is not significantly degraded.

[0062] The finishing process can be a wet etching process. For example, the etchant solution in a wet etching process includes ammonia, hydrogen peroxide, or the like in water, which can be used to finish the second nanostructure 54. The wet etching process can take 60 to 400 seconds. It has been found that etching times less than 60 seconds may pose a risk of impurities 88 on the second nanostructure 54. Conversely, extending the etching time to more than 400 seconds may negatively affect the final size and / or profile of the second nanostructure 54. In one embodiment, the wet etching temperature is maintained between 30°C and 60°C. In some other embodiments, a narrower temperature range, such as 40°C to 50°C, may be used. It has been found that if the etching temperature is below 30°C, the etching rate becomes unexpectedly low. On the other hand, temperatures above 60°C present a challenge in maintaining a consistent temperature throughout the processing apparatus (e.g., the wafer). Temperature inconsistencies between the center and edges of the wafer may cause significant differences in the profile of the second nanostructure 54, negatively impacting the consistency and quality of the apparatus. These parameters can be adjusted according to the specific requirements of the trimming process, related materials, and the dimensions, profile, and consistency required for the second nanostructure 54.

[0063] The second nanostructure 54 and fin 66 after the trimming process may have trimmed contours. Trimmed contours can increase the curvature of the exposed corner regions of the second nanostructure 54 and / or fin 66. Increasing the curvature of the corner regions can increase the gap-filling tolerance of the subsequently formed gate stack (see Figures 16A to 16D), thereby reducing gaps in the gate stack and reducing damage to high-dielectric-constant dielectric layers (such as damage caused by corona discharge over time). The specific geometry of the corner regions of the second nanostructure 54 and fin 66 after the trimming process can vary depending on the specific corner positions of the second nanostructure 54 and fin 66. Generally, the etching deviation of the overall device is relatively minimized. For example, in some embodiments, the loading effect between sparse and dense patterned areas of the overall device can be relatively minimized.

[0064] Figures 15C, 15D, and 15E are detailed views of corner regions 200A, 200B, and 200C of the second nanostructure 54, respectively (see also Figure 15A). Corner regions 200A, 200B, and 200C are each cross-sectional views along section AA' (see Figure 1), extending along the longitudinal axis of the subsequently formed gate 102 (see Figures 16A to 16D) and perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructure field-effect transistor. Corner region 200A is the top corner of the second nanostructure 54C at the very top of the nanostructure stack along section AA. The horizontal radius R1 and vertical radius R2 of corner region 200A are each 1 nm to 4.5 nm. The horizontal radius R1 may or may not be equal to the vertical radius R2.

[0065] Corner region 200B is the remaining corner along section A-A', excluding the top corner of the topmost second nanostructure 54. For example, corner region 200B is the corner profile of the bottom corner of the top second nanostructure 54C and the top and bottom corners of the second nanostructures 54B and 54A along section A-A'. The horizontal radius R3 and vertical radius R4 of corner region 200B can each be from 0.9 nm to 2 nm. The horizontal radius R3 may or may not be equal to the vertical radius R4. It has been found that when the radius of corner region 200B falls within the above range, the gap-filling tolerance of the subsequently formed gate stack can be sufficiently increased to reduce gaps in the gate stack and reduce damage to the high-dielectric-constant dielectric layer. In some embodiments, corner region 200A may be rounded and have a greater curvature than corner region 200B because corner region 200A is exposed to additional processes (such as the process of removing the dummy gate 76 and the dummy gate dielectric layer 70). For example, the horizontal radius R1 and vertical radius R2 of corner area 200A can be greater than the horizontal radius R3 and vertical radius R4 of corner area 200B, respectively.

[0066] Corner region 200C is the corner of fin 66 along section A-A'. The horizontal radius R5 and vertical radius R6 of corner region 200C may each be from 0.9 nm to 3 nm. The horizontal radius R5 may or may not be equal to the vertical radius R6. In some embodiments, corner region 200A may be rounded and have a greater curvature than corner region 200C because corner region 200A is exposed to additional processes (such as the process of removing dummy gate 76 and dummy gate dielectric layer 70). For example, the horizontal radius R1 and vertical radius R2 of corner region 200A may be greater than the horizontal radius R5 and vertical radius R6 of corner region 200C, respectively. Furthermore, the horizontal radius R3 and vertical radius R4 of corner region 200B may or may not be equal to the horizontal radius R5 and vertical radius R6 of corner region 200C, respectively.

[0067] The contour and size variations of the second nanostructure 54 can also depend on the cross-section. Specifically, the inner spacer 90 and the epitaxial source / drain region 92 in cross-section B-B' can cover the corner region of the second nanostructure (see Figure 1). In this way, the curvature and roundness of the corner region in cross-section B-B' are less than those of the corner region in cross-section A-A'. For example, Figure 15F is a detailed view of corner region 200D (see Figure 15B). Corner region 200D is located in cross-section B-B', which is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructure field-effect transistor. The horizontal radius R7 and vertical radius R8 of corner region 200D are each 0.2 nm to 1.2 nm. The horizontal radius R7 may or may not be equal to the vertical radius R8. The rounding degree of corner region 200D can be less than that of corner regions 200A, 200B, and 200C. For example, the horizontal radius R7 and vertical radius R8 of corner region 200D can each be smaller than the individual horizontal radii R1, R3, and R5 and the individual vertical radii R2, R4, and R6 of corner regions 200A, 200B, and 200C, respectively. Furthermore, corner region 200D can be thinner than the trimmed area of ​​the second nanostructure 54. For example, the width W1 of the second nanostructure 54 in section A-A' is 5 nm to 100 nm, and the thickness T1 is 4 nm to 6.5 nm. However, in section B-B', the portion of the second nanostructure 54 covered by the inner spacer 90 can have a thickness T2, and the thickness T2 is greater than the thickness T1. The portion of the second nanostructure 54 exposed by the recess 98 has a thickness T1.

[0068] In Figures 16A to 16D, a gate dielectric layer 100 and a gate 102 are formed for gate replacement. The gate dielectric layer 100 is compliantly deposited in the second recess 98. The gate dielectric layer 100 may be formed on the upper surface and sidewalls of the substrate 50, and on the upper surface, sidewalls, and lower surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the upper surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the gate spacer 81, and the shallow trench isolation region 68.

[0069] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a dielectric material with a high dielectric constant. In these embodiments, the dielectric constant of the gate dielectric layer 100 is greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. The method of forming the gate dielectric layer 100 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0070] Gates 102 are deposited on gate dielectric layers 100 to fill the remaining portion of the second recess 98. Gates 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although the gates 102 shown in Figures 16A to 16D are single-layered, gates 102 may include any number of pad layers, any number of work function adjustment layers, and filler materials. Any combination of layers may be deposited in the n-type region 50N and the p-type region 50P as gates 102, and gates 102 are located between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50.

[0071] Gate dielectric layers 100 can be formed simultaneously in the n-type region 50N and the p-type region 50P, such that the gate dielectric layers 100 in each region are composed of the same material. Gates 102 can be formed simultaneously in the n-type region 50N and the p-type region 50P, such that the gates 102 in each region are composed of the same material. In some embodiments, the gate dielectric layers 100 in each region can be formed by separate processes, such that the gate dielectric layers 100 in each region can have different materials and / or different numbers of layers, and / or the gates 102 in each region can be formed by separate processes, such that the gates 102 in each region can have different materials and / or different numbers of layers. When using separate processes, various masking steps can be used to mask and expose suitable areas.

[0072] After filling the second recess 98, a planarization process such as chemical mechanical polishing can be performed to remove excess material from the gate dielectric layer 100 and gate 102 above the upper surface of the first interlayer dielectric layer 96. Therefore, the remaining material of gate 102 and gate dielectric layer 100 can form the substitution gate structure of the final nanostructure field-effect transistor. Gate 102 and gate dielectric layer 100 can be considered together as gate structure 100 / 102.

[0073] Figure 16C shows details of corner region 200C (see Figures 15A and 16A). As shown, the rounded corner of the second nanostructure 54 provides a V-shaped opening for depositing the gate dielectric layer 100 and the gate 102 between the second nanostructure 54. For example, the vertical distance between line segments 202 tangent to the corner of the second nanostructure 54 can increase in the direction away from the second nanostructure 54. This widens the process tolerance range for depositing the gate dielectric layer 100 and the gate 102 and improves the gap-filling effect. For example, it has been found that when the radius of corner region 200B is 0.9 nm to 2 nm, the coverage of the gate dielectric layer 100 and the gate 102 between the second nanostructures 54 can be improved and the gap can be reduced. The improved coverage helps to reduce damage to the high dielectric constant layer of the gate dielectric layer 100, which originates from the corona discharge of the gate 102.

[0074] Figure 16D shows details of corner region 200D (see Figure 16B), including epitaxial source / drain region 92, gate dielectric layer 100, gate 102, second nanostructure 54, and inner spacer 90. In some embodiments as shown in Figure 16D, residues of sacrificial material 72 may remain on the inner spacer 90, for example, between the inner spacer 90 and the gate dielectric layer 100 and the gate 102. For example, sacrificial material 72 may not be completely removed, and gate dielectric layer 100 may be formed on the retained sacrificial material 72. Since sacrificial material 72 is an insulating material such as silicon oxide, the retained residue does not significantly affect the electrical performance of the final device.

[0075] In Figures 17A to 17C, the gate structure (containing the gate dielectric layer 100 and the corresponding upper gate 102) is recessed to form a recess located directly above the gate structure and between portions of the opposing gate spacers 81. A gate mask 104 containing one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, may be filled into the recess, followed by a planarization process to remove excess dielectric material extending on the first interlayer dielectric layer 96. The subsequently formed gate contacts (such as contact 114 illustrated below with reference to Figures 18A to 18C) pass through the gate mask 104 to contact the upper surface of the recessed gate 102.

[0076] As shown in Figures 18A to 18C, a second interlayer dielectric layer 106 is deposited over the first interlayer dielectric layer 96 and the gate shield 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric layer 106 is composed of a dielectric material such as phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0077] In Figures 18A to 18C, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third recess 108, exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 may be formed using anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar processes. In some embodiments, the third recess 108 may be formed using a first etching process to etch through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96, a second etching process to etch through the gate mask 104, and then a third etching process to etch through the contact etch stop layer 94. A patterned mask, such as photoresist, may be formed and patterned on the second interlayer dielectric layer 106 to shield the second interlayer dielectric layer 106 from the first and second etching processes. In some embodiments, the etching process may be over-etched, so that the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same height or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although the third recess 108 shown in FIG. 18B exposes the epitaxial source / drain region 92 and gate structure in the same cross section, various embodiments may expose the epitaxial source / drain region 92 and gate structure in different cross sections, thereby reducing the risk of shorting the subsequently formed contacts.

[0078] After forming the third recess 108, a silicide region 110 may be formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing metal (not shown) on the exposed portion of the epitaxial source / drain region 92, which may react with the semiconductor material (such as silicon, silicon-germanium, or germanium) of the underlying epitaxial source / drain region 92 to form a silicide region or a germanide region. For example, the metal may be nickel, cobalt, titanium, tantalum, palladium, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. An annealing process is then performed to form the silicide region 110. The unreacted portion of the deposited metal is then removed, and the removal method may be an etching process. Although the silicate region 110 can be considered as a silicate region, it can also be a germanide region or a silica-germanide region (such as a region containing silicate and germanide). In one embodiment, the silicate region 110 includes titanium silicate and has a thickness between about 2 nm and about 10 nm.

[0079] Next, in Figures 19A to 19C, contacts 112 and 114 (which can also be considered as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive structure (such as the gate 102 and / or the silicate region 110 in the embodiments described). Contact 114 is electrically coupled to the gate 102 and can be considered as a gate contact, while contact 112 is electrically coupled to the silicate region 110 and can be considered as a source / drain contact 112. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes such as chemical mechanical polishing can be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0080] Figures 20A to 25C are cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Figures 20A, 21A, 22A, 22F, 22G, 22H, 23A, 24A, and 25A show cross-sectional views of section A-A' shown in Figure 1. Figures 20B, 21B, 22B, 22C, 22D, 22E, 23B, 24B, and 25B show cross-sectional views of section B-B' shown in Figure 1. Figure 25C shows cross-sectional views of section C-C' shown in Figure 1. Figures 20A and 20B are apparatuses for the same process stages shown in Figures 7A to 7C, and similar reference numerals are used to identify similar units formed by similar processes. Figures 20A and 20B are fabrication stages after the formation of the first recess 86, which exposes the sidewalls of the first nanostructure 52 and the second nanostructure 54. In Figures 20A and 20B, the first nanostructure 52 has not yet been replaced with any sacrificial material.

[0081] In Figures 21A and 21B, the first nanostructure 52 is removed to extend the first recess 86 between the second nanostructures 54. A suitable process can be used to remove the first nanostructure 52, as illustrated above with reference to Figures 8A and 8B. Removing the first nanostructure 52 results in impurities 88 remaining on the exposed surface of the second nanostructure 54. Specifically, the impurities may be located on the surface of the second nanostructure 54 within the first recess 86.

[0082] In Figures 22A to 22H, a trimming process is performed to remove impurities 88. Unlike the embodiments described above in Figures 2 to 19C, the process shown in the embodiments of Figures 20A to 25C trims the second nanostructure 54 before forming the sacrificial material 72, the inner spacer 90, and the epitaxial source / drain region 92. The trimming process can be performed using a wet etching process illustrated in Figures 15A to 15F. For example, the trimming process can be completed by a wet etching process using an etchant solution including ammonia, hydrogen peroxide, or the like in water. The wet etching process can take 60 seconds to 400 seconds. It has been found that etching times of less than 60 seconds pose a risk of impurities 88 on the second nanostructure 54. Conversely, extending the etching time to more than 400 seconds negatively impacts the final size and / or profile of the second nanostructure 54. In one embodiment, the wet etching temperature is maintained between 30°C and 60°C, or between 40°C and 50°C. It has been found that if the etching temperature is below 30°C, the etching rate becomes unexpectedly low. On the other hand, temperatures above 60°C present a challenge in maintaining a consistent temperature throughout the processing apparatus (e.g., the wafer). Removing impurities 88 can improve the device performance of the final nanostructured field-effect transistor, such as increasing carrier mobility, reducing channel resistance, or similar performance improvements.

[0083] After the trimming process, the second nanostructure 54 and the fin 66 may have trimmed profiles. The trimming process may increase the curvature of the exposed corner regions of the second nanostructure 54 and / or the fin 66. Increasing the curvature of the corner regions may increase the gap-filling tolerance of the subsequently formed gate stack (see Figures 25A to 25C), thereby reducing gaps in the gate stack and reducing damage to high-dielectric-constant dielectric layers (such as damage caused over time by corner discharge). The specific geometric changes of the corner regions of the second nanostructure 54 and the fin 66 after the trimming process may depend on the specific location of the corners of the second nanostructure 54 and the fin 66.

[0084] Figures 22C, 22D, and 22E are detailed views of corner regions 200A, 200B, and 200C, respectively (see also Figure 22A). Corner regions 200A, 200B, and 200C are each cross-sectional views along section AA' (see Figure 1), which extends along the longitudinal axis of the subsequently formed gate 102 (see Figures 25A to 25C) and is perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Corner region 200A is the top corner of the second nanostructure 54C at the very top of the nanostructure stack along section AA. Corner region 200A has a lower curvature due to the dummy gate 76 shielding it. For example, the horizontal radius R9 and vertical radius R10 of corner region 200A are each 0.2 nm to 1.2 nm. The horizontal radius R9 may or may not be equal to the vertical radius R10.

[0085] Corner region 200B is the remaining corner along section A-A', excluding the top corner of the topmost second nanostructure 54. For example, corner region 200B is the corner profile of the bottom corner of the top second nanostructure 54C and the top and bottom corners of the second nanostructures 54B and 54A along section A-A'. The horizontal radius R3 and vertical radius R4 of corner region 200B can each be from 0.9 nm to 2 nm. The horizontal radius R3 may or may not be equal to the vertical radius R4. In some embodiments, the horizontal radius R3 and vertical radius R4 of corner region 200B after additional processes (such as removing the dummy gate 76) can each be from 0.9 nm to 2 nm. It has been found that when the radius of corner region 200B falls within the above range, the gap-filling tolerance of the subsequently formed gate stack can be sufficiently increased to reduce gaps in the gate stack and reduce damage to the dielectric layer with high dielectric constant. In some embodiments, corner region 200B may be rounded and have a greater curvature than corner region 200A because the dummy gate 76 during the trimming process masks corner region 200A. For example, the horizontal radius R9 and vertical radius R10 of corner region 200A may be smaller than the horizontal radius R3 and vertical radius R4 of corner region 200B, respectively.

[0086] Corner region 200C is the corner of fin 66 along section A-A'. The horizontal radius R5 and vertical radius R6 of corner region 200C may each be from 0.9 nm to 3 nm. The horizontal radius R5 may or may not be equal to the vertical radius R6. In some embodiments, corner region 200C may be rounded and have a greater curvature than corner region 200A because the dummy gate 76 shields corner region 200A. For example, the horizontal radius R9 and vertical radius R10 of corner region 200A may be smaller than the horizontal radius R5 and vertical radius R6 of corner region 200C, respectively. Furthermore, the horizontal radius R3 and vertical radius R4 of corner region 200B may or may not be equal to the horizontal radius R5 and vertical radius R6 of corner region 200C, respectively.

[0087] The contour and size variations of the second nanostructure 54 can also depend on the cross-section. Due to the trimming process performed before the formation of the inner spacer 90 or the epitaxial source / drain region 92, the curvature of the corner regions in different cross-sections is generally more consistent than the curvature of the corner regions shown in the embodiments of Figures 2 to 19C. Specifically, the corner regions of the second nanostructure in cross-section BB' (see Figure 1) have not yet been formed with the inner spacer 90 and the epitaxial source / drain region 92. In this way, the curvature angle of the corner regions in cross-section B-B' can be similar to that of corner regions 200B and 200C in cross-section A-A'.

[0088] For example, Figures 22C, 22D, and 22E show details of corner regions 200D, 200E, and 200F, respectively (see also Figure 22B). Cross-sectional views of corner regions 200D, 200E, and 200F are taken along section BB' (see Figure 1), which is perpendicular to section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor. Corner region 200E is the top corner of the topmost second nanostructure 54 (such as second nanostructure 54C). Corner region 200D is the remaining corners along section B-B', excluding the top corner of the topmost second nanostructure 54. For example, corner region 200B is the corner outline of the bottom corner of the topmost second nanostructure 54C and the top and bottom corners of second nanostructures 54B and 54A along section B-B'. Corner region 200F is the corner of fin 66 along section B-B'. The horizontal radius R11 and vertical radius R12 of corner region 200D shown in Figure 22F are substantially similar to the horizontal radius R3 and vertical radius R4 of corner region 200B. For example, the horizontal radius R11 and vertical radius R12 can each be from 0.9 nm to 2 nm. As shown in Figure 22G, the horizontal radius R13 and vertical radius R14 of corner region 200E are substantially similar to the horizontal radius R9 and vertical radius R10 of corner region 200B. As shown in Figure 22H, the horizontal radius R15 and vertical radius R16 of corner region 200F are substantially similar to the horizontal radius R5 and vertical radius R6 of corner region 200C.

[0089] In Figures 23A and 23B, a sacrificial material 72 is formed between the second nanostructures 54. The method for forming the sacrificial material 72 can be similar to the process illustrated in Figures 8A to 9B. For example, the sacrificial material 72 can be formed by depositing a sacrificial material layer (such as an oxide or the like) followed by etching the sacrificial material layer. Since the second nanostructure 54 is trimmed before the sacrificial material 72 is formed, impurities 88 are not located at the interface between the sacrificial material 72 and the second nanostructure 54.

[0090] Next, in Figures 24A and 24B, inner spacers 90 are formed along the sidewalls of the sacrificial material 72 between the second nanostructures 54. The method for forming the inner spacers 90 can be similar to the process illustrated in Figures 8A to 9B. For example, the sacrificial material 72 can be formed by depositing a sacrificial material layer (such as an oxide or the like) and then etching the sacrificial material layer. Since the second nanostructure 54 is trimmed before the sacrificial material 72 is formed, the impurities 88 are not located at the interface between the sacrificial material 72 and the second nanostructure 54.

[0091] As shown in Figures 25A to 25C, this is an apparatus completed after performing an additional process similar to that shown in Figures 11A to 14B and Figures 16A to 19C, where similar reference numerals are used to indicate similar units formed by similar processes. In this embodiment, the corner profile of the second nanostructure 54 is as illustrated above with reference to Figures 22C to 22H. For example, the vertical and horizontal radii of the corner regions of the second nanostructure 54 along sections A-A' and B-B' are 0.9 nm to 2 nm. When the radius of the corner regions falls within the above range, the gap-filling effect of the gate deposition between the second nanostructures 54 can be improved, and damage to the high-dielectric-constant gate dielectric layer can be reduced.

[0092] Figure 26 shows a semiconductor package formed by bonding integrated circuit dies 302 and 304 (including integrated circuit dies 304A and 304B) in some embodiments. Integrated circuit dies 302 and 304 may each include active regions formed by different processes. For example, integrated circuit die 304A may include a nanostructured field-effect transistor device, which may be formed using the processes shown in Figures 2 to 19C, and may undergo a trimming process after removing the sacrificial material 72. Integrated circuit die 304B may include a nanostructured field-effect transistor device, which may be formed using the processes shown in Figures 20A to 25C, and may undergo a trimming process before forming the sacrificial material 72, the inner spacer 90, and the epitaxial source / drain region 92. Alternatively, integrated circuit die 302 may include a nanostructured field-effect transistor device, which may be formed without a trimming process and without forming the sacrificial material 72. For example, the method for forming the nanostructure field-effect transistor device in the integrated circuit die 302 can be to directly replace the first nanostructure 52 into a gate structure 100 / 102 without modifying the second nanostructure 54. In this way, due to the difference in device manufacturing process, the nanostructure profiles in the integrated circuit dies 302 and 304 can be different.

[0093] Integrated circuit chips 304 and 302 can be directly bonded together by methods such as metal-to-metal bonding and dielectric layer-to-dielectric bonding. For example, the contact pad 306 (e.g., a copper pad) of integrated circuit chip 302 can be directly bonded to the contact pad 308A (e.g., a copper pad) of integrated circuit chip 304A and the contact pad 308B (e.g., a copper pad) of integrated circuit chip 304B without any intermediate solder connectors. In addition, the insulating bonding layer 310 of integrated circuit chip 302 can be directly bonded to the insulating bonding layers 312A and 312B of integrated circuit chips 304A and 304B, respectively. For example, a method for bonding insulating bonding layers 310, 312A, and 312B may include planarizing each insulating bonding layer 310, 312A, and 312B, and then bonding the insulating bonding layers 310, 312A, and 312B together using direct oxide-to-oxide bonding without any intermediate adhesive layer. A molding compound 314 may then be deposited on the integrated circuit die 302 and around the integrated circuit dies 304A and 304B.

[0094] In various embodiments, the method of forming a nanostructured field-effect transistor involves interleaving a first nanostructure and a second nanostructure, followed by replacing the second nanostructure to form a gate stack surrounding the first nanostructure. This replacement process may retain impurities on the first nanostructure, and a trimming step is performed to remove these residues and improve device performance. The trimming step may also round the corners of the first nanostructure, typically defining the vertical and / or horizontal radii of the nanostructure corners as being between 0.9 nm and 2 nm. These rounded corners can increase the deposition allowance of the gate stack, improve the inter-nanometer filling effect, reduce gaps in the gate stack, and reduce damage to the high-dielectric-constant dielectric layer over time. Overall, these processes result in increased carrier mobility, reduced channel resistance, and reduced damage to the high-dielectric-constant dielectric layer of the nanostructured field-effect transistor.

[0095] In some embodiments, a method of forming a semiconductor device includes removing a plurality of first nanostructures from a plurality of nanostructures, the nanostructures including staggered stacked first nanostructures and a plurality of second nanostructures; performing a trimming process on the second nanostructures after removing the first nanostructures, wherein the trimming process increases the curvature of at least a first corner of the second nanostructure; forming a sacrificial material between the second nanostructures; and replacing the sacrificial material into a gate stack. The step of replacing the sacrificial material into a gate stack may optionally include removing the sacrificial material, and performing the trimming process after removing the sacrificial material. The method may further optionally include forming a plurality of inner spacers on the sidewalls of the sacrificial material between the second nanostructures, wherein the inner spacers shield a second corner of the second nanostructure during the trimming process. The first corner may optionally be located in a first cross-section, wherein the second corner is located in a second cross-section perpendicular to the first cross-section, and the curvature of the first corner after the trimming process is greater than the curvature of the second corner. The trimming process may optionally be performed before forming the sacrificial material between the second nanostructures. The trimming process may, as appropriate, further increase the curvature of a second corner of the second nanostructure, wherein the first corner is located in a first profile, and the second corner is located in a second profile, with the second profile perpendicular to the first profile. The trimming process may, as appropriate, include a wet etching process using an etching solution including ammonia or hydrogen peroxide. The trimming process may, as appropriate, include a wet etching process at a temperature of 30°C to 60°C. The trimming process may, as appropriate, include a wet etching process for a time of 60 seconds to 400 seconds.

[0096] In some embodiments, a method of forming a semiconductor device includes removing a plurality of first nanostructures from a plurality of nanostructures to define openings between a plurality of second nanostructures of the nanostructures, wherein the first nanostructures and second nanostructures are stacked perpendicularly, and wherein the step of removing the first nanostructures leaves a plurality of impurities on the surfaces of the second nanostructures in the openings; removing the impurities from the surfaces of the second nanostructures in the openings using a trimming process; forming a sacrificial material in the openings between the second nanostructures; and replacing the sacrificial material into a gate stack. The impurities may be located at the interface between the sacrificial material and the second nanostructures. The method may further include forming a plurality of inner spacers in the openings between the second nanostructures, wherein the impurities are located at the interface between the inner spacers and the second nanostructures. The inner spacers may be used to mask corner regions of the second nanostructures during the trimming process. The impurities may be removed before the formation of the sacrificial material. The trimming process may be used to etch the corner regions of the second nanostructures.

[0097] In some embodiments, the semiconductor device includes a first source / drain region and a second source / drain region; a plurality of nanostructures extending between the first source / drain region and the second source / drain region, wherein a first corner of a first nanostructure has a first radius of 0.9 nm to 2 nm in a first cross-section; and a gate stack located on and covering the nanostructures. The curvature of the top corner of the topmost nanostructure in the first cross-section may be greater than the curvature of the first corner of the first nanostructure, wherein the top corner is higher than the first corner. The curvature of a second corner of the first nanostructure in a second cross-section may be less than the curvature of the first corner of the first nanostructure in a second cross-section, wherein the first cross-section is along the longitudinal axis of the gate stack and the second cross-section is perpendicular to the first cross-section. The second radius of the second corner of the first nanostructure in the second cross-section may be 0.9 nm to 2 nm, wherein the first cross-section is along the longitudinal axis of the gate stack and the second cross-section is perpendicular to the first cross-section. The first thickness of the first nanostructure in the first cross-section may be greater than the second thickness of the first nanostructure in the second cross-section, wherein the first cross-section is along the longitudinal axis of the gate stack and the second cross-section is perpendicular to the first cross-section.

[0098] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a three-dimensional view of a nanostructured field-effect transistor in some embodiments. Figures 2, 3, 4, 5A, 5B, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 15D, 15E, 15F, 16A, 16B, 16C, 16D, 17A, 17B, 17C, 18A, 18B, 19A, 19B, and 19C are various diagrams of intermediate steps in manufacturing nanostructured field-effect transistors in some embodiments. Figures 20A, 20B, 21A, 21B, 22A, 22B, 22C, 22D, 22E, 22F, 22G, 22H, 23A, 23B, 24A, 24B, 25A, 25B, and 25C are various diagrams illustrating intermediate steps in fabricating nanostructured field-effect transistors in some embodiments. Figure 26 is a diagram illustrating semiconductor packaging in some embodiments.

Claims

1. A method for forming a semiconductor device, comprising: The process involves removing multiple first nanostructures from a fin, wherein the nanostructures include the first nanostructures and multiple second nanostructures stacked in an alternating manner; performing a trimming process on the second nanostructures and the fin after removing the first nanostructures, wherein the trimming process increases the curvature of at least a first corner of the second nanostructures and the curvature of a corner of the fin; forming a sacrificial material between the second nanostructures; and replacing the sacrificial material to form a gate stack.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the step of replacing the sacrificial material into the gate stack includes removing the sacrificial material and performing the trimming process after removing the sacrificial material.

3. The method of forming a semiconductor device as described in claim 2 further includes: Multiple inner spacers are formed on the sidewalls of the sacrificial material between the second nanostructures, wherein the inner spacers cover a second corner of the second nanostructures during the finishing process.

4. The method of forming a semiconductor device as claimed in claim 3, wherein the first corner is located in a first cross-section, wherein the second corner is located in a second cross-section, the second cross-section being perpendicular to the first cross-section, and the curvature of the first corner after the trimming process is greater than the curvature of the second corner.

5. A method for forming a semiconductor device, comprising: Multiple first nanostructures are removed from a plurality of nanostructures on a fin to define an opening between multiple second nanostructures of the nanostructures and between a bottommost nanostructure and the fin, wherein the first nanostructures and the second nanostructures are stacked perpendicularly, and wherein the step of removing the first nanostructures leaves multiple impurities on the surfaces of the second nanostructures and the fin in the opening; the impurities are removed from the surfaces of the second nanostructures and the fin in the opening by a trimming process to increase the curvature of the second nanostructures and the corner curvature of the fin; a sacrificial material is formed in the opening between the second nanostructures; and the sacrificial material is replaced to form a gate stack.

6. A method of forming a semiconductor device as claimed in claim 5, wherein the impurities are located at the interface between the sacrificial material and the second nanostructures.

7. The method of forming a semiconductor device as claimed in claim 6 further includes forming a plurality of inner spacers in the opening between the second nanostructures, wherein the impurities are located at the interface between the inner spacers and the second nanostructures.

8. A semiconductor device, comprising: A first source / drain region and a second source / drain region; Multiple nanostructures are stacked on a fin and extend between the first source / drain region and the second source / drain region, wherein a first corner of a first nanostructure has a first radius of 0.9 nm to 2 nm in a first cross-section, and the corner of the fin has a radius of 0.9 nm to 3 nm in the first cross-section; and a gate is stacked on the nanostructures and covers the nanostructures.

9. The semiconductor device as claimed in claim 8, wherein the curvature of a top corner of the topmost nanostructure of the nanostructures in the first cross-section is greater than the curvature of a first corner of the first nanostructure, wherein the top corner is higher than the first corner.

10. The semiconductor device of claim 8, wherein the curvature of a second corner of the first nanostructure in a second cross-section is less than the curvature of the first corner of the first nanostructure in a first cross-section, wherein the first cross-section is along the longitudinal axis of the gate stack and the second cross-section is perpendicular to the first cross-section.

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