Memory circuit and of operating the same

Abstract

A memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first precharge circuit coupled to at least one access line electrically connected to the memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second precharge circuit coupled to the at least one access line and configured to be in a second state during the standby mode.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The development of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices has led to an increased demand for memory devices. Memory devices are typically classified as volatile memory (VMI) or non-volatile memory (NDM). VMI can store data while powered on, but may lose the stored data once power is off. Unlike VMI, NDM retains data after power is off, but may be slower than VMI. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] The memory circuitry or device may include various components for accessing memory cells within a memory array. These components may include at least one of, for example, an address decoder, column and row selectors, a sense amplifier, a write driver, or control logic. The address decoder interprets memory addresses to select a specific column or row within the memory array. The column and row selector assists in addressing memory cells by directing selected column and row signals to the desired memory location, for example, for self-locating memory cell reads or writes. The sense amplifier amplifies signals retrieved during a read operation to assist in reading data from a memory cell. The write driver transfers data to be stored to the selected memory cell. The control logic manages the timing and sequence of memory operations to ensure accurate data retrieval and storage. Other components may be included as part of the memory device to operate together to provide the memory device with the characteristics or functions of accessing memory cells.

[0008] In various cases, integrated circuitry may include static random access memory (SRAM) circuitry to provide on-chip data storage. SRAM circuitry can be used to meet specific design requirements associated with the surrounding circuitry attached to the SRAM circuitry. One type of SRAM circuitry may provide a single port for reading or writing data stored in the SRAM circuitry. The address inputs of this type of circuitry are typically shared for both read and write access. Another common type of SRAM circuitry, called a dual-port SRAM circuitry, may include pseudo-dual-port (PDP) SRAM, which provides two ports for accessing data stored in the SRAM circuitry. A dual-port SRAM circuitry may include a first port for read access and a second port for write access. Read and write operations of a dual-port SRAM circuitry can be performed in separate clock cycles, such as read and write access operations being performed in one clock cycle. Each port of a dual-port SRAM circuitry is typically able to access data stored in the SRAM circuitry asynchronously and independently, thereby allowing dual-port SRAM circuitry to be incorporated into a range of different applications with different usage models.

[0009] When using dual-port SRAM circuits, bit line (BL) recovery time can be considered to ensure that read and write operations are performed correctly or as desired. For example, during the clock cycle used to access memory cells, bit lines (e.g., bit line BL) may discharge during (or while performing) a read operation, for example, to detect logic values ​​associated with memory cells. After discharging, the bit line may be in a low state (e.g., a low charge state). The discharged bit line may be recharged during the bit line recovery time (e.g., a recharge phase) so that a write operation can be performed after the read operation. Recharging the bit line can bring it to a high state (e.g., a high charge state). If the bit line charge is not restored to the required level (e.g., a predefined charge or voltage value) when a subsequent access operation (e.g., a write operation) is performed, one or more potential problems may be encountered, including data corruption, read interference, write failure, memory cell degradation, etc. Therefore, the bit line recovery time can be considered to delay subsequent access operations. For example, the write operation can be delayed after the read operation, and the clock cycles of the dual-port SRAM circuit can be extended to ensure the required bit line recovery.

[0010] For example, bit line recovery time can be predetermined or set during or after the manufacture of a memory device or semiconductor device. Bit line recovery time during read / write processes can affect or be a factor in PDP SRAM cycle time. However, bit line recovery time may be longer than expected due to the negative bias temperature instability (NBTI) effect. NBTI may involve the trapping of positive charges in the gate oxide of a transistor under the influence of negative bias voltage and high temperature. The trapped charge may alter the electrical characteristics of the transistor, causing a negative shift in the threshold voltage (e.g., voltage threshold offset (VTs)). Over time, the threshold voltage offset may become relatively large and affect the function and reliability of the circuit. For example, when NBTI occurs, the PMOS voltage threshold (VT) may increase according to the following formula:

[0011] For example, a precharge circuit can be constructed using multiple transistors, such as p-channel metal-oxide semiconductor (PMOS) transistors. Using PMOS transistors, the precharge circuit can be activated when the gate is in a low state (e.g., no voltage applied) and deactivated when the gate is in a high state (e.g., a predefined voltage applied). However, the effects of NBTI on the PMOS can be exacerbated when the gate of the PMOS transistor remains in a low state for an extended period. NBTI can occur when a device (e.g., a memory device) operates at relatively high or elevated temperatures, and a negative bias voltage is applied to the gate of the transistor, resulting in the trapping of positive charges in the gate oxide and a gradual increase in the transistor's voltage threshold (Vt) over time. This increase in the transistor's voltage threshold (VT) (e.g., sometimes referred to as threshold voltage offset) can lead to transistor degradation. For example, in a PMOS transistor, the threshold voltage is the gate voltage at which the transistor begins to conduct. When the gate of a PMOS transistor is held at a low voltage (e.g., zero volts) for an extended period, charge can accumulate at the gate oxide interface due to mechanisms such as trap charge or interface states. This charge accumulation can effectively increase the transistor's threshold voltage, and therefore (when the PMOS gate is held low for a long time), the transistor's threshold voltage may shift towards a relatively high voltage level, resulting in a relatively weak PMOS. A weak PMOS in the precharge circuitry prolongs the bit line recovery time in read / write processes, thereby reducing the PDP SRAM cycle time (e.g., a relatively long bit line recovery time results in a relatively long clock cycle).

[0012] The systems and methods of the technical solutions can provide various embodiments or configurations for memory devices to mitigate the cycle time degradation of PDP SRAM and other types of SRAM circuits due to the NBTI effect. In some configurations, the systems and methods can provide a plurality of precharge circuits for precharging one or more bit lines. For example, the systems and methods can provide a memory device or circuit including a first precharge circuit and a second precharge circuit. The precharge circuits can be implemented using PMOS transistors. The first precharge circuit can be activated during standby mode / state (e.g., when access operations are suspended or no read and write operations are performed) to precharge the bit lines. The second precharge circuit can be deactivated during standby mode.

[0013] In some cases, when the memory circuitry is in standby mode (or phase) for an extended period, the PMOS transistor associated with the first precharge circuit may have a relatively high NBTI effect, for example, when the gate of the PMOS transistor is low to initiate the precharge circuitry. For the second precharge circuitry, the gate of the PMOS associated with it may be high during standby mode, resulting in a relatively minimal or low NBTI effect (e.g., no cycle time effect). With this configuration, the second precharge circuitry can facilitate bit line recovery, thereby minimizing the time interval between the read / write process and the clock cycle duration. Although the read / write process is performed within the clock cycle of the access operation described herein, it should be noted that other types of operations, such as write-read processes, can be performed, and are not limited to read-write processes.

[0014] In some configurations, the system and method may provide a precharge circuit and an equalizer circuit to mitigate the NBTI effect on the cycle time degradation of PDP SRAM. For example, the memory device may include a precharge circuit and an equalizer circuit. The precharge circuit may be used to precharge bit lines during standby mode. The equalizer circuit may be deactivated during standby, wherein the gate of the transistor associated with the equalizer circuit is in a high state (e.g., a predefined voltage is applied). In this case, the PMOS transistor associated with the equalizer circuit may experience a relatively low or no NBTI effect during the extended standby phase of the memory array. Therefore, between read and write operations, the equalizer circuit may be activated by equalizing the voltage of the discharged bit lines (e.g., bit lines in a low state) to the voltage level of the charged bit lines (e.g., pulling the bit line voltage level to another bit line, such as a bit line bar (BLB) voltage level) to ensure minimum bit line recovery time.

[0015] The systems and methods of the technical solutions discussed herein can implement other configurations, not limited to those discussed herein, or add additional precharge circuits and / or equalizer circuits to perform features or operations that mitigate the degradation of PDP SRAM cycle time caused by the NBTI effect. It should be noted that although PMOS is used as an exemplary transistor in the precharge circuit, other types of transistors, not limited to PMOS, can be used as part of the memory circuits or devices described herein.

[0016] Figure 1 is a schematic diagram of a memory device 100 according to one embodiment. In some embodiments, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller 105 may write data to or read data from the memory array 120 via the word line WL and the bit line BL according to electrical signals. In other embodiments, the memory device 100 includes more, fewer, or different components than those shown in Figure 1.

[0017] The memory array 120 is a hardware component for storing data. In one embodiment, the memory array 120 is embodied as a semiconductor memory device. The memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 includes word lines WL0, WL1...WLJ extending in a first direction (e.g., the X direction) and bit lines BL0, BL1...BLK extending in a second direction (e.g., the Y direction). The word lines WL and bit lines BL may be conductive metal or conductive rails. In one embodiment, each memory cell 125 is coupled to and can be operated via the corresponding word line WL and the corresponding bit line BL according to voltage or current. In some embodiments, each bit line includes a bit line BL, BLB coupled to one or more memory cells 125 of a group of memory cells 125 disposed along the second direction (e.g., the Y direction). The bit lines BL, BLB may receive and / or provide differential signals. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is embodied as a static random access memory (SRAM) cell or other types of memory cell. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0018] The memory controller 105 is a hardware component for controlling the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line controller 112, a word line controller 114, and a timing controller 110. The bit line controller 112, word line controller 114, and timing controller 110 may be embodied as logic circuitry, analog circuitry, or a combination thereof. In one configuration, the word line controller 114 is circuitry that provides voltage or current via one or more word lines WL of the memory array 120, while the bit line controller 112 is circuitry that provides or senses voltage or current via one or more bit lines BL of the memory array 120. In one configuration, the timing controller 110 is circuitry that provides control signals or clock signals to synchronize the operation of the bit line controller 112 and the word line controller 114. In some embodiments, timing controller 110 embodies or includes a processor and a non-transitory computer-readable medium storing instructions that, when executed by the processor, cause the processor to perform one or more functions of timing controller 110 or memory controller 105 described herein. Bit line controller 112 may be coupled to bit line BL of memory array 120, while word line controller 114 may be coupled to word line WL of memory array 120. In some embodiments, memory controller 105 includes more, fewer, or different components than those shown in Figure 1.

[0019] In one example, timing controller 110 may generate control signals to coordinate the operation of bit line controller 112 and word line controller 114. In one method, for writing data to memory cell 125, timing controller 110 may cause word line controller 114 to apply voltage or current to memory cell 125 via word line WL coupled to memory cell 125, and cause bit line controller 112 to apply voltage or current corresponding to the data to be stored to memory cell 125 via bit line BL coupled to memory cell 125. In one method, for reading data from memory cell 125, timing controller 110 may cause word line controller 114 to apply voltage or current to memory cell 125 via word line WL coupled to memory cell 125, and cause bit line controller 112 to sense voltage or current corresponding to the data stored in memory cell 125 via bit line BL coupled to memory cell 125.

[0020] Figure 2 is a schematic diagram of an exemplary SRAM cell 125 according to one embodiment. SRAM cell 125 may be a PDP six-transistor (6T) SRAM for reading and writing in a single cycle. Although a PDP 6T SRAM is used as an example, other types of SRAM cells may be provided or utilized to perform the features, functions, or operations discussed herein. In some embodiments, SRAM cell 125 includes N-type transistors N1, N2, N3, N4 and P-type transistors P1, P2. N-type transistors N1, N2, N3, N4 may be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs) or N-type fin field-effect transistors (FinFETs). P-type transistors P1, P2 may be P-type MOSFETs or P-type FinFETs. These components may operate together to store bits. In other embodiments, SRAM cell 125 includes more, fewer, or different components than those shown in Figure 2.

[0021] In some configurations, N-type transistors N3 and N4 include gate electrodes coupled to word line WL. In some configurations, the drain electrode of N-type transistor N3 is coupled to bit line BL, and the source electrode of N-type transistor N3 is coupled to port Q. In some configurations, the drain electrode of N-type transistor N4 is coupled to bit line BLB, and the source electrode of N-type transistor N4 is coupled to port QB. In some configurations, N-type transistors N3 and N4 function as electrical switches. Depending on the voltage applied to word line WL, N-type transistors N3 and N4 can allow bit line BL to be electrically coupled or decoupled from port Q, and allow bit line BLB to be electrically coupled or decoupled from port QB. For example, based on the power supply voltage VDD (or 1 V) applied to the word line WL corresponding to the high state (or logic value "1"), N-type transistor N3 is enabled to electrically couple bit line BL to port Q, and N-type transistor N4 is enabled to electrically couple bit line BLB to port QB. As another example, based on the ground voltage VSS (or 0 V) ​​applied to the word line WL corresponding to the low state (or logic value "0"), N-type transistor N3 is disabled to electrically decouple bit line BL from port Q, and N-type transistor N4 is disabled to electrically decouple bit line BLB from port QB.

[0022] In some configurations, the N-type transistor N1 includes a source electrode coupled to a first power supply voltage rail coupled to a supply ground voltage VSS or 0 V, a gate electrode coupled to a gate electrode of the P-type transistor P1, and a drain electrode coupled to port Q. In some configurations, the P-type transistor P1 includes a source electrode coupled to a second power supply voltage rail coupled to a supply power voltage VDD, a gate electrode coupled to a gate electrode of the N-type transistor N1, and a drain electrode coupled to port Q. In some configurations, the N-type transistor N2 includes a source electrode coupled to a first power supply voltage rail coupled to a supply ground voltage VSS or 0 V, a gate electrode coupled to port Q, and a drain electrode coupled to port QB. In some configurations, the P-type transistor P2 includes a source electrode coupled to a second power supply voltage rail coupled to a supply power voltage VDD, a gate electrode coupled to port Q, and a drain electrode coupled to port QB. In these configurations, N-type transistor N1 and P-type transistor P1 operate as inverters, and N-type transistor N2 and P-type transistor P2 also operate as inverters, forming a cross-coupled inverter. In one configuration, the cross-coupled inverter senses and amplifies the voltage difference at ports Q and QB. During data writing, the cross-coupled inverter senses the voltage at ports Q and QB provided by N-type transistors N3 and N4 and amplifies the voltage difference at bit lines BL and BLB. For example, the cross-coupled inverter senses a voltage of 0.5 V at port Q and a voltage of 0.4 V at port QB, and amplifies the voltage difference at ports Q and QB via positive feedback (or regenerative feedback), making the voltage at port Q the supply voltage VDD (e.g., 1 V) and the voltage at port QB the ground voltage VSS (e.g., 0 V). The amplified voltages at ports Q and QB can then be read from bit lines BL and BLB via N-type transistors N3 and N4, respectively.

[0023] Figure 3 illustrates a schematic diagram 300 of a plurality of precharge circuits for the memory device 100 of Figure 1 according to various embodiments. Schematic diagram 300 of Figure 3 shows an example of using a plurality of precharge circuits to mitigate the NBTI effect on the cycle time degradation of memory cell 125 (e.g., PDP SRAM). Components or circuits of schematic diagram 300 may be part of memory device 100. As shown, schematic diagram 300 includes precharge circuits 302, 304, for example, sometimes referred to as first precharge circuit 302 and second precharge circuit 304. Precharge circuits 302, 304 are operatively and electrically coupled to bit lines (e.g., bit lines BL and BLB) to (pre)charge bit lines BL and BLB for accessing memory cell 125. In this case, first precharge circuit 302 may be labeled as a first printed circuit board (PCB) (e.g., PCB1), and second precharge circuit 304 may be labeled as a second PCB (e.g., PCB2). For the purpose of providing an example here, the precharge circuits 302, 304 can be described as charging bit line BL, although the precharge circuits 302, 304 can charge other bit lines, such as, but not limited to, bit line BLB or bit lines of other memory cells of the memory array 120 described in conjunction with Figure 1.

[0024] Each of the pre-charge circuits 302 and 304 may include a plurality of transistors 303A-303C and 305A-305C. Transistors 303A-303C may sometimes be referred to as transistor 303 or switch 303. Transistors 305A-305C may sometimes be referred to as transistor 305 or switch 305. Transistors 303 and 305 may be used as switches. Control lines are operatively coupled to the gates (e.g., gate electrodes) of transistors 303 and 305 for controlling or operating transistors 303 and 305. Operating transistors 303 and 305 may refer to starting or stopping transistors 303 and 305 by providing a voltage at the gate electrode or not providing a voltage to the gate electrode (e.g., holding the gate electrode at zero voltage). The control line can transmit control signals (e.g., labeled "Signal1" or "Signal2") to the gate electrodes of transistors 303 and 305.

[0025] Transistors 303 and 305 of the pre-charge circuits 302 and 304 may be PMOS transistors. Although transistors 303 and 305 are described herein as PMOS transistors, it should be noted that other types of transistors, such as NMOS, bipolar junction transistors (BJTs), and junction field-effect transistors (JFETs), may be implemented or used as part of at least one of the pre-charge circuits 302 and 304, and are not limited to PMOS transistors. Transistors 303A to 303C may be referred to as the first to third transistors of the first pre-charge circuit 302, respectively. Transistors 305A to 305C may be referred to as the fourth to sixth transistors of the second pre-charge circuit 304, respectively.

[0026] Each of transistors 303 and 305 may include a first source / drain (S / D) electrode, a second S / D electrode, and a gate electrode. The gate electrodes of transistors 303A to 303C may be electrically coupled to each other and connected to a first control line to receive a control signal (e.g., "Signal1"). The gate electrodes of transistors 305A to 305C may be electrically coupled to each other and connected to a second control line to receive a control signal (e.g., "Signal2").

[0027] The first S / D electrode of transistors 303A and 305A may be electrically coupled to bit line BL (e.g., the same bit line BL). Bit line BL may be referred to as the first bit line or the first access line. The second S / D electrode of transistors 303A and 305A may be electrically coupled to a power supply voltage or a voltage source (e.g., VDD). Furthermore, the second S / D electrodes of transistors 303A and 305A may be electrically coupled to each other. The first S / D electrode of transistors 303B and 305B may be electrically coupled to bit line BLB (e.g., the same bit line BLB). Bit line BLB may be referred to as the second bit line or the second access line. The second S / D electrode of transistors 303B and 305B may be electrically coupled to a power supply voltage or a voltage source (e.g., VDD). Furthermore, the second S / D electrodes of transistors 303B and 305B may be electrically coupled to each other.

[0028] The first S / D electrodes of transistors 303C and 305C can be electrically coupled to the second S / D electrodes of transistors 303A and 305A or to a power supply voltage, respectively. The second S / D electrodes of transistors 303C and 305C can be electrically coupled to the second S / D electrodes of transistors 303B and 305B or to a power supply voltage, respectively. For example, each of the pre-charge circuits 302 and 304 may include three transistors. Depending on the design and implementation of the pre-charge circuits 302 and 304, the pre-charge circuits 302 and 304 may include more or fewer transistors, and are not limited to three transistors.

[0029] To activate or enable transistors 303 and 305 (e.g., PMOS transistors), no voltage may be applied to or no signal may be sent to the gate electrodes of transistors 303 and 305. Furthermore, to deactivate or disable transistors 303 and 305, a predefined voltage (e.g., 1 V) may be applied to the gate electrodes of transistors 303 and 305. The predefined voltage may be applied to or not applied to the gate electrodes of transistors 303 and 305 via corresponding control lines. For example, memory controller 105 may send a first signal (e.g., "Signal1") for activating or deactivating the first precharge circuit 302 and a second signal (e.g., "Signal2") for activating or deactivating the second precharge circuit 304 via corresponding control lines (e.g., as shown in at least Figures 3 and 4). The control lines of the first precharge circuit 302 may transmit a first signal, including a high voltage level or a low voltage level, to the gate electrode of transistor 303 to operate transistor 303. The control line of the second precharge circuit 304 can transmit a second signal, including a high voltage level or a low voltage level, to the gate electrode of transistor 305 to operate transistor 305. The high voltage level can be a predefined voltage value, such as 1 V, 3 V, etc. The low voltage level can be a predefined voltage value, such as 0 V. For example, transistors 303 and 305 (e.g., PMOS transistors) can be started by applying a low voltage to the gate electrode, and transistors 303 and 305 can be stopped by applying a high voltage to the gate electrode.

[0030] Activating or deactivating transistors 303 and 305 may correspond to activating or deactivating the first precharge circuit 302 or the second precharge circuit 304, respectively. Activating precharge circuits 302 and 304 may sometimes be referred to as setting or using precharge circuits 302 and 304 to a low state or a first state. A low voltage level may signal precharge circuits 302 and 304 in a low state. After activating transistors 303A, 303B, 305A, and 305B, a conduction path may be established between the power supply voltage (e.g., VDD) and the corresponding bit line, thereby allowing current to flow to the corresponding line for charging. For example, activating transistor 303A or 305A allows bit line BL to be charged. In another example, activating transistor 303B or 305B allows bit line BLB to be charged.

[0031] Disabling pre-charge circuits 302 and 304 may sometimes be referred to as setting or using pre-charge circuits 302 and 304 in a high state or a second state. A high voltage level can signal pre-charge circuits 302 and 304 in a high state. After disabling transistors 303A, 303B, 305A, and 305B, the conduction path between the corresponding bit line and the power supply voltage will be broken, thereby suspending or preventing the (pre)charging of the bit line. After disabling pre-charge circuits 302 and 304, the corresponding bit line can be discharged. For example, disabling transistor 303A or 305A can suspend or disable the charging of bit line BL. In another example, disabling transistor 303B or 305B will suspend or disable the charging of bit line BLB.

[0032] Each of the precharge circuits 302 and 304 may include a corresponding equalizer. In some cases, the equalizer may be a circuit or other component for selectively coupling BL and BLB. For example, the equalizer is implemented as transistors 303C and 305C, as described in conjunction with Figure 3, although the equalizer may be implemented as one or more switches or one or more transistors. For example, the equalizer of the first precharge circuit 302 may correspond to transistor 303C. The equalizer of the second precharge circuit 304 may correspond to transistor 305C. Transistors 303C and 305C (e.g., equalizers) may be used to equalize the voltage between bit lines BL and BLB. Equalizing the voltage between bit lines BL and BLB may include or refer to adjusting the voltage level of one bit line to be the same as that of the other bit line, such as raising the voltage level of bit line BL to the voltage level of bit line BLB, as described in conjunction with at least Figure 4. Adjustment can be achieved by transferring charge between bit lines, such as by charging bit line BL by transferring charge from bit line BLB. In these cases, if one bit line has a higher voltage (e.g., representing logic "1"), charge can be transferred to the other bit line until the two bit lines reach the same voltage level or until the two bit lines reach the high state representing logic "1".

[0033] For the purpose of providing an example herein, activating at least one of the precharge circuits 302 and 304 may allow at least one of the transistors 303C and 305C to equalize the charge or voltage of bit lines BL and BLB to a high voltage level, respectively. In some implementations, the equalizer may be replaced by different components capable of performing the equalizer functions described herein. In various configurations, the equalizer may be controlled according to signals transmitted via control lines of the respective precharge circuits 302 and 304.

[0034] For example, in response to a first voltage (e.g., VDD or 1 V) applied to the gate electrode of transistor 303C via signal "Signal1", the equalizer can be activated / enabled to electrically couple bit line BL to bit line BLB. In another instance, in response to receiving a second voltage (e.g., VSS or 0 V) ​​or applying a second voltage to the gate electrode of transistor 303C (or lack thereof), the equalizer can be disabled to electrically decouple bit line BL from bit line BLB. A similar operation can be performed on the second precharge circuit 304 (e.g., with transistor 305C). In these cases, by coupling bit line BL and bit line BLB, the voltage between bit line BL and bit line BLB can be equalized to prevent potential functional errors, such as during read or write operations of memory device 100. In some configurations, such as those described in conjunction with Figure 4, the voltage between bit line BL and bit line BLB can be balanced to facilitate charging one bit line using charge from the other bit line, for example, by partially charging bit line BL by transferring or receiving charge through bit line BLB.

[0035] To perform a read or write operation, precharge circuits 302 and 304 can be disabled. Disabling precharge circuits 302 and 304 may include disabling transistors 303 and 305, respectively, to prevent precharging of bit lines BL and BLB. In these cases, signals "Signal1" and "Signal2" may include a second voltage (e.g., VSS or 0 V) ​​applied to the gate electrodes of transistors 303 and 305. The second voltage applied to the gate electrodes of transistors 303C and 305C may decouple the coupling between bit lines BL and BLB. The second voltage applied to the gate electrodes of transistors 303A, 303B, 305A, and 303B may disable current flow between the source and drain. Therefore, the precharge circuits 302 and 304 can terminate or pause the precharge of bit lines BL and BLB, so that read or write operations can be performed normally via bit lines BL and BLB, including but not limited to transmitting signals from memory cell 125 (or other memory cell) to circuits such as memory controller 105, or transmitting data signals to memory cell 125 (or other memory cell) for storage.

[0036] Before accessing memory cell 125 to perform read and write operations, at least one of precharge circuits 302 and 304 may be activated to precharge bit lines BL and BLB to the supply voltage. For example, and as described in conjunction with Figures 4 and 5, precharge circuit 302 may be activated before the access operation. The period (or clock cycle) during which the access operation is paused or not performed may be associated with the standby mode of memory array 120 or memory device 100. In some cases, memory array 120 may be in standby mode for a period of time, for example, by extending the duration for which the gate electrode of a transistor is in a low state (e.g., a first state or zero voltage applied). In these cases, the transistor (e.g., a PMOS transistor) may experience a relatively high NBTI effect, resulting in increased voltage threshold offset and reduced transistor performance. A transistor with degraded performance may be referred to as a weak transistor. Due to the presence of a weak transistor and the increased voltage threshold offset, the bit line recovery time may increase, thereby prolonging the duration between read and write operations (for read-write processes) and the clock cycle time for executing the read-write process. Therefore, for example, a second precharge circuit 304 may be implemented to reduce, minimize, or mitigate the impact of NBTI on the transistor 303 of the first precharge circuit 302.

[0037] In various configurations, during standby mode, when access operations are suspended (e.g., no read or write operations), the first precharge circuit 302 may be in a first state (e.g., low state), where no voltage is applied to the gate electrode of transistor 303. Furthermore, during standby mode, the second precharge circuit 304 may be in a second state (e.g., high state), where a predefined voltage is applied to the gate electrode of transistor 305. In this case, during standby mode, the first precharge circuit 302 is activated, while the second precharge circuit 304 is deactivated (or inactive). The first precharge circuit 302 may charge at least one of bit lines BL and BLB to the supply voltage (e.g., VDD) before accessing memory cells 125 during standby mode of memory array 120. The second precharge circuit 304 may not charge bit lines BL and BLB during standby mode, where the gate electrode of transistor 305 remains high, minimizing or eliminating the effect of NBTI on transistor 305.

[0038] During a read operation or write operation (e.g., access operation), the first precharge circuit 302 can be used in a high state (e.g., a second state) by applying a predefined voltage (e.g., a high voltage level) to the gate electrode of transistor 303. The first precharge circuit 302 can be disabled in the second state. The second precharge circuit 304 can remain in the second state during read and write operations. During a read operation or write operation, one of bit line BL or bit line BLB can be discharged to a lower state (e.g., a relatively low voltage level, representing logic "0"), while the other bit line can remain in a higher state (e.g., a relatively high voltage level, representing logic "1").

[0039] Between read and write operations, the first precharge circuit 302 and the second precharge circuit 304 can be configured from a second state or switched to a first state by applying a high voltage level to transistors 303 and 305. During the time interval between read and write operations, the first precharge circuit 302 and the second precharge circuit 304 can charge bit lines BL and BLB to the power supply voltage. If one or more transistors 303 of the first precharge circuit 302 are affected by NBTI, the second precharge circuit 304 can promote the charging of bit lines BL and BLB to minimize bit line recovery time and thus mitigate cycle time degradation.

[0040] After a read operation and a write operation, the memory array 120 may enter a standby mode until a subsequent access operation (e.g., the next clock cycle of executing a read / write process). For example, after a write operation is completed, the first precharge circuit 302 may be used in a first state to precharge bit lines BL and BLB, while the second precharge circuit 304 may remain in a second state. The operations discussed herein may be repeated or recurred for various access operations / processes. By using the second precharge circuit 304, which has a relatively low voltage threshold compared to the first precharge circuit 302 (because the transistor 305 remains high during standby mode), the NBTI effect of the first precharge circuit 302 can be minimized or mitigated.

[0041] In some embodiments, the first pre-charge circuit 302 and the second pre-charge circuit 304 may be connected in parallel. In these cases, the second S / D electrodes of transistors 305A and 305B may be electrically coupled to the second S / D electrodes of transistors 303A and 303B. Furthermore, the first S / D electrodes of transistors 305A and 305B may be electrically coupled to the first S / D electrodes of transistors 303A and 303B, which are respectively electrically coupled to bit lines BL and BLB.

[0042] Figure 4 illustrates a schematic diagram 400 of a precharge circuit 302 and an equalizer circuit 402 for a memory device 100 of Figure 1, according to various embodiments. In some implementations, the equalizer circuit 402 may be implemented in series with the first precharge circuit 302 (e.g., sometimes collectively referred to herein as precharge circuit 302) to minimize or mitigate the NBTI effect of the transistor 303. The equalizer circuit 402 may be used instead of the second precharge circuit 304. As shown, schematic diagram 400 includes at least a memory cell 125, a precharge circuit 302 (such as that described in conjunction with at least Figure 3), and an equalizer circuit 402. In this case, the precharge circuit 302 may be labeled PCB1, and the equalizer circuit 402 may be labeled PCB2.

[0043] The equalizer circuit 402 may include a transistor 403 serving as an equalizer. The transistor 403 may include a gate electrode, a first S / D electrode, and a second S / D electrode. The gate electrode may be electrically coupled to a control line to receive a signal (e.g., "Signal2"), similar to the signal of the second pre-charge circuit 304. The first S / D electrode of the transistor 403 may be electrically coupled to a power supply voltage (e.g., VDD), a second S / D electrode of transistor 303A, and / or a first S / D electrode of transistor 303C. The second S / D electrode of the transistor 403 may be electrically coupled to a power supply voltage, a second S / D electrode of transistor 303B, and / or a second S / D electrode of transistor 303C.

[0044] For example, when a high voltage level is applied to the gate electrode of transistor 403 via a corresponding control line, the equalizer circuit 402 can be deactivated, for example, by decoupling bit lines BL and BLB. When a low voltage level (e.g., zero voltage) is applied to the gate electrode of transistor 403, the equalizer circuit 402 can be activated, thereby equalizing the charge on bit lines BL and BLB. In various implementations, the equalizer circuit 402 can equalize bit lines BL and BLB by transferring charge from bit line BLB to bit line BL, for example, to mitigate or reduce the NBTI effect of degraded transistors, minimize bit line recovery time, and avoid erroneous read or write operations.

[0045] The operation of the precharge circuit 302 and the equalizer circuit 402 may be similar to the operation of the precharge circuits 302 and 304, as described in conjunction with at least Figure 3. For example, during standby mode, the precharge circuit 302 may be used in a first state (e.g., a low state) in which the gate electrode of the transistor 303 is in a low state (e.g., no voltage applied or a low voltage level). The precharge circuit 302 may be activated in the first state to charge bit lines BL and BLB to the supply voltage before accessing memory cell 125 to perform a read or write operation during standby mode. The equalizer circuit 402 may be in a second state (e.g., a high state) during standby mode by applying a high voltage (e.g., 1V) to the gate electrode of the transistor 403, similar to the second precharge circuit 304. In the second state, the equalizer circuit 402 may be deactivated.

[0046] During the clock cycle of accessing memory cell 125, for example, a read / write operation may be performed. During a read operation (e.g., a first access operation), the precharge circuit 302 may be set to or used in a high state to be disabled by applying a high voltage level to the gate electrode of transistor 303. The equalizer circuit 402 may be kept in a high state, for example, kept disabled. During a read operation, bit line BL may be discharged to a lower state (e.g., discharged to a low voltage level, representing logic "0"), while bit line BLB may be kept in a high state (e.g., a high voltage level, representing logic "1"). It should be noted that discharging bit line BL during a read operation is used as an example, and other bit lines (e.g., bit line BLB) may be discharged in a certain access operation (e.g., a read operation or a write operation), and is not limited to the read operation.

[0047] After a read operation, bit line BL discharges to a lower state. A predefined time period / duration can be used for bit line recovery, such as restoring the charge or voltage level of bit line BL. In some cases, the time period between a read operation and a write operation may be referred to as a predefined recovery time, time interval, or recharge time. During this time period, a precharge circuit 302 and an equalizer 402 can be activated by applying a low voltage (e.g., representing logic "0") to transistors 303 and 403. By activating the equalizer circuit 402, charge from bit line BLB (e.g., in a high state) can be transferred to bit line BL, thereby increasing or pulling up the low state of the bit line BL voltage to the bit line BLB voltage. The equalizer circuit 402 can operate together with the precharge circuit 302 to equalize and charge bit lines BL and BLB. For example, after a long standby mode, when no voltage is applied to the gate electrode of transistor 303, operating equalizer circuit 402 together with precharge circuit 302 can mitigate the potential NBTI effect of transistor 303 in precharge circuit 302.

[0048] A write operation (e.g., a second access operation) is performed after a predefined bit line recovery time. The precharge circuit 302 and the equalizer circuit 402 can be deactivated to perform the write operation, similar to a read operation. After the read / write process is complete, the precharge circuit 302 can be activated to precharge the bit lines BL and BLB before subsequent access operations.

[0049] In some embodiments, a plurality of precharge circuits 302, 304 may be implemented to precharge bit lines BL and BLB to improve the performance of memory device 100 by, for example, reducing the single clock cycle time and mitigating the NBTI effect of one of the precharge circuits 302, 304. In some other embodiments, precharge circuit 302 and equalizer circuit 402 may be implemented to precharge bit lines BL and BLB to improve the performance of memory device 100 while minimizing component area usage. An exemplary timing sequence for setting at least one of word line WL, bit lines BL and BLB, precharge circuit 302, precharge circuit 304, or equalizer 402 (but not limited to) to a first state or a second state may be described in conjunction with at least Figure 5.

[0050] Figure 5 illustrates an exemplary timing diagram 500 of components for operating at least one of the memory device 100 of Figures 1 to 4 according to various embodiments. Components of the memory device 100 may include or refer to at least one of word line WL, bit line BL, bit line BLB, first precharge circuit 302, second precharge circuit 304, equalizer circuit 402, etc. The timing diagram 500 of component operation may be described in conjunction with at least one of Figures 1 to 4 (but not limited to).

[0051] Timing diagram 500 shows lines 502-512, representing the states of certain components of memory device 100. For example, line 502 may represent the state of a clock cycle. Line 504 may represent the state of word line WL. Line 506 may represent the state of PCB1 (e.g., precharge circuit 302) or the voltage level applied to the gate electrode of transistor 303. Line 508 may represent the state of PCB2 (e.g., second precharge circuit 304 or equalizer circuit 402) or the voltage level applied to the gate electrode of transistor 305 or transistor 403. The second precharge circuit 304 may operate similarly to the equalizer circuit 402 to precharge bit line BL (or in some cases bit line BLB) and mitigate the NBTI effect. Line 510 may represent the state of bit line BL. Line 512 may represent the state of bit line BLB.

[0052] In various implementations, read and write operations (e.g., read-write processes) can be performed within one clock cycle, as shown by lines 502 and 504 in Figure 5. The word line WL can be high to perform read and write operations. For example, the word line controller 114 can apply voltage or current to the memory cell 125 via the word line WL coupled to the memory cell 125. By applying voltage or current via the word line WL, the word line WL can be high during access operations (e.g., applying a predefined voltage level).

[0053] As shown in lines 506 and 508, during standby mode / states where access operations are paused or terminated, PCB1 (e.g., the first precharge circuit 302) can be set to a low state (or a first state), while PCB2 (e.g., the second precharge circuit 304 or equalizer 402) can be set to a high state (or a second state). In standby mode, PCB1 can be activated to precharge bit lines BL and BLB, as shown in lines 510 and 512. To perform a read operation, PCB1 can be deactivated or set to a high state before the read operation is initiated or during a time instance. During a read operation, bit line BL can be discharged to a low state (or a low voltage level), as shown in line 510. Another bit line (e.g., bit line BLB) can remain in a high state (or a high voltage level). Although bit line BL is discharged in this example, it should be noted that in some cases, bit line BLB can be discharged while bit line BL remains in a high state.

[0054] After the read operation is completed, PCB1 and PCB2 can be set to a low state to enable their functions. For example, PCB1 can begin pre-charging bit lines BL and / or BLB. PCB2 can facilitate pre-charging of bit lines BL and / or BLB by charging bit lines BL and / or BLB to the supply voltage or by equalizing the voltage level of bit line BL to bit line BLB. By using PCB1 and PCB2, the NBTI effect can be minimized and cycle time degradation can be mitigated. As shown in Figure 5, bit line BL can be charged to a high state before starting a subsequent access operation (e.g., a write operation in this example).

[0055] After a predefined time length or period of bit line recovery, PCB1 and PCB2 can be set high to perform a write operation, thereby deactivating PCB1 and PCB2. PCB1 and PCB2 can be deactivated before initiating a write operation or at a time instance of the write operation (e.g., setting the word line WL high). After the write operation is completed, PCB1 can be set low to continue precharging the bit lines BL and BLB for subsequent access operations. PCB2 can be kept high, for example, deactivated until the next read / write process. Because transistor 305 or transistor 403 is kept at a high voltage level, the NBTI effect on transistor 305 or 402 (e.g., a PMOS transistor) may be small or nonexistent.

[0056] The various time lengths or periods described herein can be predefined, predetermined, or preset after the memory device 100 is manufactured. For example, the duration of each clock cycle can be predefined. The duration of a read or write operation, such as setting a word line to a high state or applying voltage or current to a word line to perform an access operation, can be predefined. The duration of PCB1 being in a high state can be predefined, and this duration can be associated with the duration of the corresponding access operation. The duration of PCB1 and PCB2 being in a low state (e.g., bit line recovery time) can be predefined. For example, the start and end times of at least one of an access operation, a high-state and low-state switching of PCB1 and / or PCB2, etc., can be predefined. In some implementations, for example, one or more time lengths or instances can be modified or set according to the specifications or configuration of the memory device 100.

[0057] In some embodiments, PCB2 (e.g., the second precharge circuit 304 or the equalizer circuit 402) or the transistors 305 or 403 associated with PCB2 may be provided with a relatively low voltage threshold (compared to PCB1). For example, lowering the voltage threshold of PCB2 may further minimize potential NBTI effects.

[0058] Figure 6 illustrates the flow of an exemplary method 600 for forming at least one of the memory devices (e.g., 100) of Figures 1 through 4 according to some embodiments. Method 600 can be performed to form any memory device or portion thereof herein. For example, method 600 can be performed to form any memory device or component thereof discussed with respect to Figures 1 through 4. For example, at least one operation of method 600 can be performed to form a memory device (e.g., 100). Therefore, the following discussion of method 600 may refer to some element symbols used in Figures 1 through 4 as non-limiting examples. Furthermore, method 600 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 600 of Figure 6, and only some other operations may be briefly described herein. Method 600 may be performed simultaneously and / or in any order other than that shown in Figure 6.

[0059] Method 600 may begin with operation 602: forming a memory array (e.g., 120) in a region of a substrate. The substrate may be a wafer, such as a silicon wafer, or a silicon-on-insulator (SOI) substrate. In some cases, the SOI substrate may include a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates may be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0060] The memory array includes a plurality of memory cells (e.g., 125). In some instances, each memory cell may be implemented as a six-transistor (6T) static random access memory (SRAM) cell (e.g., PDP 6T SRAM) consisting of six transistors (e.g., N1, N2, N3, N4, P1, and P2). However, it should be understood that the first to fourth memory cells may be implemented as other types of SRAM configurations besides 6T, such as an eight-transistor (8T) or ten-transistor (10T) configuration. In some instances, alternatively or additionally, memory cells may be implemented as other types of memory cells, such as dynamic random access memory (DRAM) cells, resistive random access memory (RRAM) cells, phase-change random access memory (PCRAM) cells, or magnetoresistive random access memory (MRAM) cells. In various embodiments, memory cells may be formed along the main surface (e.g., the front side) of the substrate. Depending on the fabrication of these memory cells (and corresponding memory arrays), the process may sometimes be referred to as front-end-of-line (FEOL) processing.

[0061] In some configurations, at least one word line (e.g., word line WL) may be coupled to at least one of the memory cells. During a read or write operation of the memory cell, the word line WL may be charged (e.g., a voltage or current may be applied) to a supply voltage or a predefined voltage level. For example, a voltage or current may be applied or supplied to the word line WL for a predefined time period or duration to perform a read or write operation. In various implementations, the memory cell (e.g., PDP SRAM) may be used to perform read and write operations within one clock cycle.

[0062] At operation 604, method 600 may include the step of forming a first precharge circuit (e.g., 302). The first precharge circuit may include a plurality of transistors, including a first transistor (e.g., 303A), a second transistor (e.g., 303B), and a third transistor (e.g., 303C). The first precharge circuit may include more or fewer transistors, not limited to three transistors. The transistors may be PMOS transistors, although other types of transistors may be implemented to perform the features or operations discussed herein. The transistors may operate or act as switches. For example, each transistor may be turned on or off by applying a predefined low voltage (e.g., setting the transistor to a low state) or a predefined high voltage (e.g., setting the transistor to a high state). For example, turning a transistor on or off the first precharge circuit may correspond to activating or deactivating the first precharge circuit. Activating the precharge circuit may initiate precharging of at least one access line.

[0063] Each transistor may include a first S / D electrode, a second S / D electrode, and a gate electrode. For example, the first S / D electrode of the first transistor may be electrically coupled to a first access line (e.g., bit line BL), and the second S / D electrode of the first transistor may be coupled to a power supply voltage and the first S / D electrode of the third transistor. In a further embodiment, the first S / D electrode of the second transistor may be electrically coupled to a second access line (e.g., bit line BLB), and the second S / D electrode of the second transistor may be coupled to a power supply voltage and the second S / D electrode of the third transistor. The first access line and the second access line may be electrically coupled to at least one of the memory cells (e.g., 125). The gate electrodes of the first to third transistors may be coupled to each other and to control lines (or a plurality of control lines) for transmitting signals (e.g., high voltage or low voltage).

[0064] By applying a high voltage at the gate electrode, a transistor (e.g., a PMOS transistor) can be turned off to suspend charging of the access line. By applying a low voltage at the gate electrode, a transistor can be turned on, thereby allowing at least one access line to be precharged to a supply voltage (e.g., a predefined voltage level). In these cases, the operation of the transistor (and the activation of the precharge circuit) can be based on or according to the voltage applied at the gate electrode (e.g., the gate voltage). Depending on the connections discussed herein, for example, a first precharge circuit can be electrically coupled to an access line electrically connected to a memory cell.

[0065] At operation 606, method 600 may include the step of forming a second precharge circuit (e.g., 304). The second precharge circuit may include components or features similar to those of the first precharge circuit. In some cases, the second precharge circuit may include components or features different from those of the first precharge circuit, such as additional or alternative components (e.g., transistors, switches, or functions). The second precharge circuit may be connected in parallel with the first precharge circuit, as described herein. For example, the second precharge circuit may include components and be structured similarly to the first precharge circuit, such as including three transistors and similar interconnects. It should be noted that the second precharge circuit may include different components or be structured differently from the first precharge circuit, and is not limited to the exemplary embodiments discussed herein.

[0066] For example, the second precharge circuit may include a fourth transistor (e.g., 305A), a fifth transistor (e.g., 305B), and a sixth transistor (e.g., 305C). Each transistor may include a first S / D electrode, a second S / D electrode, and a gate electrode. The first S / D electrode of the fourth transistor may be electrically coupled to a first access line, and the second S / D electrode of the fourth transistor may be coupled to a power supply voltage and the first S / D electrode of the sixth transistor. In a further embodiment, the first S / D electrode of the fifth transistor may be electrically coupled to a second access line, and the second S / D electrode of the fifth transistor may be coupled to a power supply voltage and the second S / D electrode of the sixth transistor. The gate electrodes of the fourth to sixth transistors may be coupled to each other and to control lines (or a plurality of control lines) for transmitting signals (e.g., high voltage or low voltage). The control lines associated with the fourth to sixth transistors are different from the control lines associated with the first to third transistors and are used to transmit separate signals (e.g., "Signal1" and "Signal2") to each precharge circuit.

[0067] In various implementations, the third transistor of the first precharge circuit and the sixth transistor of the second precharge circuit can be used as equalizers to electrically couple the first and second access lines. The equalizers can be used to equalize the charge on the access lines, for example, by adjusting the voltage level of one access line to be similar to the voltage level of the other access line.

[0068] In operation, the first precharge circuit may be in a first state during the standby mode of the memory array, while the second precharge circuit may be in a second state during the standby mode of the memory array. The standby mode may be associated with a period of time during which access operations are suspended or not performed, for example, no read or write operations. The first state may be referred to as a low state associated with applying a low voltage to the gate electrode of the transistor of the corresponding precharge circuit. The second state may be referred to as a high state associated with applying a high voltage to the gate electrode of the transistor of the corresponding precharge circuit. For PMOS transistors, the first state may instruct the active precharge circuit to charge at least one access line to the supply voltage (e.g., VDD). The second state may instruct the inactive precharge circuit to suspend charging of at least one access line. In these cases, during the standby mode, the first precharge circuit in the first state may be used to charge at least one access line to the supply voltage before accessing the memory cells. During the standby mode, the second precharge circuit in the second state may not charge at least one access line, for example, remaining in a deactivated state.

[0069] During a specific clock cycle, during or for performing read and / or write operations on the memory cells, at least one word line WL coupled to the memory cells may be charged to a supply voltage or a predefined voltage level. The word line WL may be charged to a high state (e.g., a high voltage or current level) during each predefined first time period (such as, in conjunction with at least Figure 5) during read and write operations (e.g., access operations). The time period during which the word line WL is high may be the same for both read and write operations. In some cases, the time period during which the word line WL is high may be different between read and write operations. The word line WL may be in a low state (e.g., a low voltage or current level) during standby mode or outside of access operations (e.g., between read and write operations). When access operations are paused, the word line WL may discharge from the high state to the low state.

[0070] In various configurations, the first precharge circuit may be in or configured to a second state to suspend charging of at least one access line during read and write operations of the memory cells. For example, when performing a read and / or write operation, the precharge circuit may be in an access mode / state (self-standby mode switching). The first precharge circuit may be in the second state during read and write operations for a predefined second time period associated with each predefined first time period. When the first precharge circuit is in the second state, the duration of the predefined second time period may be based on the duration of the predefined first time period of the read and write operations.

[0071] In some cases, the second time period may be relatively longer than the first time period, allowing the precharge circuit to switch to the second state (e.g., word line WL is charged to a high state) before or at the start of an access operation, or to switch to the first state (e.g., word line WL is discharged to a low state) after or at the end of an access operation. In other cases, the second time period may be the same as the first time period, such that the start and end times of the access operation (e.g., when word line WL is charged to a high state or discharged to a low state) are the same as when the precharge circuit switches to the second state to perform the access operation and switches to the first state to pause the access operation, respectively. Similar to the first precharge circuit, the second precharge circuit may remain in the second state during read and write operations.

[0072] During at least one access operation, such as during a read operation of the memory cells (as part of a read-write process), at least one access line may be discharged. At least one access line may be recharged or restored during a predefined time period between access operations (e.g., after a read operation and before a write operation). In this case, a first precharge circuit and a second precharge circuit may be in a first state for at least a portion of the predefined time period between the read and write operations to charge at least one access line. Setting the first and second precharge circuits to the first state activates the precharge circuit to charge at least one access line to the power supply voltage. Therefore, when the first and second precharge circuits are in the first state, at least one access line may be recharged after a read operation. The time period for recharging at least one access line (or the duration for which the precharge circuit is in the first state) may be predetermined / predefined.

[0073] After at least one access line is restored, a subsequent access operation (e.g., a write operation) can be performed. Similar to a read operation, a write operation can be performed by setting or disabling the precharge circuitry to a second state. In some implementations, for example, when the first and second precharge circuitries are in the second state or when switching from the first state to the second state, at least one character line WL can be charged to a power supply voltage or a predefined voltage level for the write operation in (simultaneous) time instances.

[0074] At operation 608, method 600 may include the step of forming an equalizer circuit (e.g., 402). For example, the equalizer circuit may be additionally or alternatively formed, implemented, or provided as a second precharge circuit. For example, herein, the equalizer circuit may be formed as an alternative to the second precharge circuit, such that the memory cells are coupled to both the (first) precharge circuit and the equalizer circuit.

[0075] The equalizer circuit may include a transistor (e.g., 403). The transistor of the equalizer circuit (e.g., sometimes referred to as the fourth transistor) may be a PMOS transistor. In this case, the fourth transistor may include a first S / D electrode coupled to a supply voltage (e.g., VDD), a first S / D electrode of the third transistor of the pre-charge circuit, and / or a second S / D electrode of the first transistor of the pre-charge circuit. The fourth transistor may include a second S / D electrode coupled to a supply voltage, a second S / D electrode of the third transistor of the pre-charge circuit, and / or a second S / D electrode of the second transistor of the pre-charge circuit. The fourth transistor may include a gate electrode coupled to a control line, which is different from the control line of the pre-charge circuit.

[0076] In some embodiments, the equalizer circuit may include more than one transistor of the same or different types, not limited to PMOS transistors. When powered on, the transistors of the equalizer circuit may couple a first access line (e.g., bit line BL) to a second access line (e.g., bit line BLB), for example, transferring charge from one access line to another, or pulling a relatively low voltage level of one access line to a relatively high voltage level of another. When powered off, the transistors of the equalizer circuit may decouple the first access line from the second access line.

[0077] The equalizer circuit may be activated or deactivated in a manner similar to the second precharge circuit, as described above. For example, a low voltage may be applied to the gate electrode of the transistor to activate the equalizer circuit. A high voltage may be applied to the gate electrode of the transistor to deactivate the equalizer circuit. In various implementations, the first precharge circuit may operate similarly to the equalizer circuit, for example, similar to the second precharge circuit.

[0078] In some configurations, the operation of the second precharge circuit can be similarly applied to the equalizer circuit. For example, during the standby mode of the memory array, when access operations are suspended or not performed, the precharge circuit coupled to the first and second access lines electrically connected to the memory cells can be in a low state, for example, activated to precharge the access lines. During standby mode, the equalizer circuit coupled to the first and second access lines can be in a high state, for example, deactivated.

[0079] A high state may indicate that the inactive precharge circuit suspends charging of the first and second access lines, or that the inactive equalizer circuit suspends equalizing charging of the first and second access lines. A low state may indicate that the active precharge circuit charges the first and second access lines to the power supply voltage, or that the active equalizer circuit equalizes the charge of the first and second access lines. In the low state during standby mode, the precharge circuit may (pre-)charge the first and second access lines to the power supply voltage before accessing the memory cells.

[0080] In a further embodiment, during operation, the precharge circuit may be in a high state to pause charging of at least one of the first access line or the second access line during read and / or write operations of the memory cells. The equalizer circuit may remain in a high state during read and write operations to pause equalizing the first charge of the first access line to the second charge of the second access line. The precharge circuit and the equalizer circuit may be in a low state for a predefined period of time between the read and write operations. For example, in the low state, the precharge circuit may charge the first and second access lines to the power supply voltage, and the equalizer circuit may equalize the first charge of the first access line to the second charge of the second access line, for example, by raising the voltage level of the first access line to the voltage level of the second access line.

[0081] In some configurations, when an access operation (such as a read operation) is performed, one access line may discharge while another access line can maintain its charge level. Therefore, when the equalizer circuit is activated, the access line with a relatively high charge level can transfer or charge another access line with a relatively low charge level. After the access operation is performed, the memory array can be in standby mode until a subsequent access operation.

[0082] In various implementations, the read and write operations of these memory cells can be performed within one clock cycle. In some implementations, the corresponding time period / duration of at least one of the read operation, write operation, high state of the precharge circuit (e.g., during an access operation), low state of the precharge circuit and equalizer circuit between read and write operations (e.g., during bit line recovery time), or time interval between read and write operations can be predefined / predetermined or configured, for example, according to the design of the memory device.

[0083] In some configurations, two or more pre-charge circuits may be formed for (pre)charging one or more access lines. In some configurations, one or more equalizer circuits may be formed for charging at least one access line. In some configurations, at least one pre-charge circuit (e.g., a second pre-charge circuit) may be connected to multiple pairs of access lines, such as to a third access line, a fourth access line associated with other memory cells, etc. In some embodiments, the equalizer circuit may couple at least one of the first or second access lines to at least one other access line, such as a third access line, a fourth access line, etc., so that the charge or voltage of at least one of the first or second access lines is equal to that of the other access line. In some configurations, the transistors discussed herein may include or may be other types of transistors, such as N-type transistors, etc., and are not limited to P-type transistors.

[0084] Figure 7 illustrates the flow of an exemplary method 700 for operating a memory device (e.g., 100) of at least one of Figures 1 through 4, according to some embodiments. Method 700 can be performed to operate any memory device or portion thereof herein. For example, method 700 can be performed to operate any memory device or component thereof discussed with respect to Figures 1 through 4. For example, at least one operation of method 700 can be performed to operate a memory device (e.g., 100). Therefore, the following discussion of method 700 may refer to some element symbols used in Figures 1 through 4 as non-limiting examples. Furthermore, method 700 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 700 of Figure 7, and only a few other operations may be briefly described herein. Method 700 may be performed simultaneously and / or in any order other than that shown in Figure 7. In some cases, one or more operations of method 700 may include or correspond to one or more operations of method 600 of at least Figure 6. In some cases, method 700 may include one or more operations described in conjunction with at least one of Figures 3 through 5 (but not limited to).

[0085] Method 700 may begin with operation 702: activating a first precharge circuit (e.g., 302) during a standby mode of the memory array (e.g., 120). Activating the first precharge circuit may refer to configuring or setting the precharge circuit in a first state. The first precharge circuit may be coupled to at least one access line (e.g., bit line BL or bit line BLB) electrically connected to a plurality of memory cells (e.g., 125) of the memory array. Setting the precharge circuit to a particular state may involve supplying a predefined voltage at the gate electrode or not supplying (or suspending) voltage to the gate electrode of a transistor (e.g., 303 or 305) associated with the precharge circuit.

[0086] For example, the first state may instruct an active precharge circuit to charge at least one access line to a supply voltage. To activate the first precharge circuit (or set the first precharge circuit to a first state), method 700 may include the step of pausing, for example, the supply of voltage at the gate electrode of a transistor (e.g., 303) associated with the first precharge circuit during a standby mode of the memory array. In this case, the transistor of the first precharge circuit may be a PMOS transistor, such that in the first state, the first precharge circuit can precharge at least one access line.

[0087] Method 700 may continue with operation 704: disabling the second precharge circuit (e.g., 304) during the standby mode of the memory array. Disabling the precharge circuit may refer to or involve configuring or setting the precharge circuit to a second state. The second state may indicate that the inactive precharge circuit suspends charging of at least one access line. For example, to disable the second precharge circuit (or set the second precharge circuit to the second state), method 700 may include the step of supplying a voltage at the gate electrode of a transistor (e.g., 305) associated with the second precharge circuit during the standby mode of the memory array. The transistor of the second precharge circuit may be a PMOS transistor. In this case, the transistor of the second precharge circuit may be deactivated, such that the second precharge circuit suspends charging of at least one access line during the standby mode of the memory array.

[0088] In various implementations, method 700 may set (e.g., enable or disable) at least one of a first or second precharge circuit during (or between) one or more access operations of the memory array. Access operations may include read operations and / or write operations. For example, during read and write operations of the memory array, method 700 may disable the first precharge circuit (or set the first precharge circuit to a second state) to suspend precharging of at least one access line. Similarly, method 700 may disable or maintain the deactivation of the second precharge circuit (e.g., set the second precharge circuit to a second state or maintain the second precharge circuit) such that at least one access line is not precharged during read and / or write operations. For example, the memory array may be in standby mode after performing read and write operations within a clock cycle until the next clock cycle.

[0089] During the time period between a read operation and a write operation (e.g., a standby mode between a read operation and a write operation), method 700 may include the following steps: activating a first precharge circuit and a second precharge circuit (e.g., setting the first precharge circuit and the second precharge circuit to a first state) to precharge at least one access line by pausing the supply voltage to the gate electrode of the transistor associated with the precharge circuit. Since the gate electrode of the transistor of the second precharge circuit is supplied with voltage before the second precharge circuit is activated, the potential NBTI impact (e.g., extended standby phase from the memory array) of using the first precharge circuit (e.g., in the absence of the second precharge circuit) can be minimized.

[0090] In some implementations, the memory device (e.g., 100) may include an equalizer circuit (e.g., 402) as a supplement to or alternative to the second precharge circuit. In this case, method 700 may include the step of setting the equalizer circuit to a first state or a second state based on the operation of the memory array (e.g., activating or deactivating the equalizer circuit, respectively). The operation of the equalizer circuit and the transistor (e.g., 403) associated with the equalizer circuit may be similar to the second precharge circuit. For example, during the standby mode of the memory array before or after read and write operations in a clock cycle, method 700 may include the step of setting the equalizer circuit to a second state (e.g., deactivating the equalizer circuit) by supplying a voltage to the gate electrode of a transistor (e.g., a PMOS transistor) of the equalizer circuit. During read and write operations, method 700 may include the step of setting or maintaining the equalizer circuit in the second state. During the time interval between read and write operations, method 700 may include the following steps: setting the equalizer circuit to a first state (e.g., activating the equalizer circuit) by pausing the supply of voltage to the gate electrode of the transistor of the equalizer circuit, thereby allowing the equalizer circuit to equalize the voltage between access lines (e.g., between bit line BL and bit line BLB), thereby minimizing the NBTI effect of the first precharge circuit during the extended standby phase of the memory array.

[0091] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first precharge circuit coupled to at least one access line electrically connected to the memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second precharge circuit coupled to at least one access line and configured to be in a second state during a standby mode.

[0092] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a precharge circuit coupled to a first access line and a second access line electrically connected to the memory cells and configured to be in a low state during a standby mode of the memory array. The memory circuit includes an equalizer circuit coupled to the first access line and the second access line and configured to be in a high state during a standby mode.

[0093] In another embodiment of this disclosure, a method for operating a memory device is disclosed. The method includes the steps of: activating a first pre-charge circuit during a standby mode of a memory array, the first pre-charge circuit being coupled to at least one access line electrically connected to a plurality of memory cells of the memory array, wherein activating the first pre-charge circuit charges the at least one access line to a power supply voltage. The method also includes the step of: deactivating a second pre-charge circuit during a standby mode of the memory array, the second pre-charge circuit being coupled to the at least one access line, wherein deactivating the second pre-charge circuit suspends charging of the at least one access line.

[0094] As used herein, the terms “about” and “approximately” generally refer to a given quantity value that may vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” may refer to a given quantity value that varies, for example, within 10-30% of that value (e.g., +10%, ±20%, or ±30% of the value).

[0095] As used herein, the terms “about” and “approximately” generally refer to a given quantity value that may vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” may refer to a given quantity value that varies, for example, within 10-30% of that value (e.g., +10%, ±20%, or ±30% of the value).

[0096] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be understood in conjunction with the accompanying drawings and the following detailed description. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 illustrates a block diagram of an exemplary memory device according to some embodiments. Figure 2 illustrates a schematic diagram of an exemplary static random access memory (SRAM) cell in the memory device of Figure 1 according to various embodiments. Figure 3 illustrates a schematic diagram of a plurality of precharge circuits for the memory device of Figure 1 according to various embodiments. Figure 4 illustrates a schematic diagram of a precharge circuit and an equalizer circuit for the memory device of Figure 1 according to various embodiments. Figure 5 illustrates an exemplary timing diagram of components for operating at least one of the memory devices of Figures 1 to 4 according to various embodiments. Figure 6 illustrates a flow chart of an exemplary method for forming at least one of the memory devices of Figures 1 to 4 according to some embodiments. Figure 7 illustrates a flow of an exemplary method for operating a memory device of at least one of Figures 1 through 4, according to some embodiments. [Biomaterial Storage]

[0098] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory circuit comprising: a memory array including a plurality of memory cells; a first precharge circuit coupled to at least one access line electrically connected to the memory cells and configured to be in a first state during a standby mode of the memory array; and a second precharge circuit coupled to the at least one access line and configured to be in a second state during the standby mode, wherein the first precharge circuit and the second precharge circuit are both in the same state during a period between a read operation and a write operation.

2. The memory circuit as claimed in claim 1, wherein the second state indicates that an inactive precharge circuit suspends charging of the at least one access line, and the first state indicates that an active precharge circuit charges the at least one access line to a power supply voltage, and wherein in the first state during the standby mode, the first precharge circuit is used to charge the at least one access line to the power supply voltage before accessing the memory cells.

3. The memory circuit as described in claim 1, wherein: The first precharge circuit is configured to be in the second state to suspend charging of at least one access line during the read operation and the write operation of the memory cells; and the second precharge circuit remains in the second state during the read operation and the write operation.

4. The memory circuitry as claimed in claim 1, further comprising: at least one word line coupled to the memory cells and configured to charge to a power supply voltage during a plurality of respective predefined first time periods during the read operation or the write operation of the memory cells, wherein the first precharge circuitry is in the second state to suspend charging of the at least one access line during the read operation and the write operation during a plurality of predefined second time periods associated with the respective predefined first time periods.

5. The memory circuit as described in claim 1, wherein: The at least one access line includes a first access line and a second access line; the first precharge circuit includes: a first transistor operatively coupled to the first access line, a second transistor operatively coupled to the second access line, and a third transistor operatively coupled to the first access line and the second access line, and for balancing multiple charges on the first access line and the second access line, wherein the respective gates of the first, second, and third transistors are operatively coupled; and the second precharge circuit includes: a fourth transistor operatively coupled to the first access line, a fifth transistor operatively coupled to the second access line, and a sixth transistor operatively coupled to the first access line and the second access line, and for balancing multiple charges on the first access line and the second access line, wherein the respective gates of the fourth, fifth, and sixth transistors are operatively coupled.

6. A memory circuit comprising: a memory array including a plurality of memory cells; a precharge circuit coupled to a first access line and a second access line electrically connected to the memory cells and configured to be in a low state during a standby mode of the memory array; and an equalizer circuit coupled to the first access line and the second access line and configured to be in a high state during the standby mode.

7. The memory circuit as claimed in claim 6, wherein the high state indicates that an inactive precharge circuit suspends charging of the first access line and the second access line or an inactive equalizer circuit suspends equalizing the multiple charges of the first access line and the second access line, and the low state indicates that an active precharge circuit charges the first access line and the second access line to a power supply voltage or an active equalizer circuit equalizes the multiple charges of the first access line and the second access line, and wherein in the low state during the standby mode, the precharge circuit is used to charge the first access line and the second access line to the power supply voltage before accessing the memory cells.

8. The memory circuitry as described in claim 6, wherein: The precharge circuit is configured to be in the high state to pause charging of at least one of the first access line or the second access line during a read operation and a write operation of the memory cells; the equalizer circuit remains in the high state during the read operation and the write operation to pause equalizing a first charge of the first access line to a second charge of the second access line; and the precharge circuit and the equalizer circuit are in the low state between the read operation and the write operation, wherein in the low state, the precharge circuit is configured to charge the first access line and the second access line to a power supply voltage, and the equalizer circuit is configured to equalize the first charge of the first access line to the second charge of the second access line.

9. A method of operating a memory circuit, comprising the steps of: during a standby mode of a memory array, activating a first precharge circuit coupled to at least one access line electrically connected to a plurality of memory cells of the memory array, wherein activating the first precharge circuit charges the at least one access line to a power supply voltage; and during the standby mode of the memory array, deactivating a second precharge circuit coupled to the at least one access line, wherein deactivating the second precharge circuit suspends charging of the at least one access line, wherein one or more of the memory cells correspond to a pseudo-dual-port static random access memory (PSRAM), wherein the PRAM is configured to perform a read operation and a write operation within one clock cycle.

10. The method as described in claim 9 further comprises the steps of: disabling the first precharge circuit during the read operation or the write operation of the memory array; and disabling the second precharge circuit during the read operation or the write operation of the memory array.

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