Analog to digital conversion device and analog to digital conversion method

Abstract

An analog-to-digital converter includes a first slope signal generator, a second slope signal generator, and a comparator. The first slope signal generator generates a first slope signal, which rises and falls within a voltage range at least with a first slope. The second slope signal generator generates a second slope signal, which rises and falls within a voltage range at least with a second slope, and the first and second slope signals have a phase difference. The comparator generates an output signal based on the first slope signal, the second slope signal, and an input signal.

Description

Technical Field

[0001] This case relates to analog-to-digital converters and analog-to-digital conversion methods, and in particular to analog-to-digital converters and analog-to-digital conversion methods that reduce operation cycles and thus increase operation frequency. Prior Technology

[0002] Analog-to-digital converters (ADCs) are commonly used in electronic devices to convert analog signals into digital signals that the device can process. A time-interleaved slope ADC is one type of ADC. However, due to the limitations of its operating conditions, the operating frequency of a time-interleaved slope ADC is restricted. Summary of the Invention

[0003] In view of the shortcomings of prior art, one of the objectives of this application is (but not limited to) to provide an analog-to-digital conversion device and an analog-to-digital conversion method to improve the shortcomings of prior art.

[0004] In some embodiments, the analog-to-digital converter includes a first slope signal generator, a second slope signal generator, and a comparator. The first slope signal generator generates a first slope signal, which rises and falls within a voltage range at least with a first slope. The second slope signal generator generates a second slope signal, which rises and falls within a voltage range at least with a second slope, and the first and second slope signals have a phase difference. The comparator generates an output signal based on the first slope signal, the second slope signal, and an input signal.

[0005] In some embodiments, the analog-to-digital conversion method includes: generating a first slope signal by a first slope signal generator, wherein the first slope signal rises and falls back and forth in a voltage range with at least a first slope; generating a second slope signal by a second slope signal generator, wherein the second slope signal rises and falls back and forth in a voltage range with at least a second slope, wherein there is a phase difference between the first slope signal and the second slope signal; and generating an output signal by a comparator based on the first slope signal, the second slope signal, and an input signal.

[0006] The technical means embodied in the embodiments of this invention can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion device and analog-to-digital conversion method of this invention can reduce the operation cycle and thus increase the operation frequency.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic diagram of an analog-to-digital converter according to some embodiments of this invention; Figure 2 is a flowchart illustrating an analog digit conversion method based on some embodiments of this case; Figure 3 is a timing diagram of an analog-to-digital converter based on some embodiments of this invention; and Figure 4 is a timing diagram of an analog-to-digital converter based on some embodiments of this case. Implementation

[0009] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0010] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0011] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and distinguish individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various diagrams will be assigned the same reference numerals.

[0012] To address the limitation of operating frequency in prior art time-interleaved slope analog-to-digital converters (ADCs), this invention proposes an analog-to-digital conversion device and an analog-to-digital conversion method, detailed below.

[0013] Figure 1 is a schematic diagram of an analog-to-digital converter 100 according to some embodiments of this invention. As shown, the analog-to-digital converter 100 includes a first slope signal generator 110, a second slope signal generator 120, a comparator 130, a capacitor Cs3, flip-flops DFF1 and DFF1X, and a digital logic processor 140.

[0014] In some embodiments, the analog-to-digital converter 100 may be, but is not limited to, a time-interlaced slope analog-to-digital converter, the operation of which is described below. The analog-to-digital converter 100 may sample the input signal using capacitor Cs3, and then comparator 130 compares the sampled signal with the first slope signal Vslope1 and the second slope signal Vslope2 generated by the first slope signal generator 110 and the second slope signal generator 120. Before comparator 130 generates a comparison result, the counter value Dcnt[3:0] continues to count until comparator 130 generates a comparison result. When the positive terminal of comparator 130 is greater than the negative terminal, the output signal cmpN generated by comparator 130 changes from negative to positive. The rising edge of the output signal cmpN changing from negative to positive will trigger the flip-flop (such as flip-flop DFF1, DFF1X). The flip-flop will store the current result of the count (such as Dcnt[3:0], Dcntx[3:0]) and send it to the digital logic processor 140. After processing by the digital logic processor 140, the data signal D1[3:0] is generated. As described above, the analog-to-digital converter 100 completes one conversion process.

[0015] To illustrate how the analog-to-digital converter 100 of this invention reduces the operating cycle and thus increases the operating frequency, please refer to Figures 2 and 3. Figure 2 is a flowchart illustrating an analog-to-digital conversion method 200 according to some embodiments of this invention. Figure 3 is a timing diagram illustrating an analog-to-digital converter 100 according to some embodiments of this invention.

[0016] Please refer to step 210 in Figure 2, where a first slope signal is generated by a first slope signal generator, wherein the first slope signal rises and falls back and forth in the voltage range with at least one first slope. For example, referring to Figures 1 and 3, the first slope signal generator 110 generates a first slope signal Vslope1, which rises with one slope and falls with another slope in the voltage range Vr to complete one round of rise and fall, and the first slope signal Vslope1 rises and falls back and forth in the voltage range Vr repeatedly.

[0017] Referring to step 220 in Figure 2, a second slope signal is generated by a second slope signal generator. This second slope signal rises and falls back and forth within a voltage range at least with a second slope, and there is a phase difference between the first slope signal and the second slope signal. For example, referring to Figures 1 and 3, the second slope signal generator 120 generates a second slope signal Vslope2. This second slope signal Vslope2 rises with one slope and falls with another slope within a voltage range Vr, completing one round trip. The second slope signal Vslope2 repeatedly rises and falls back and forth within the voltage range Vr. There is a phase difference between the first slope signal Vslope1 and the second slope signal Vslope2. In some embodiments, the phase difference between the first slope signal Vslope1 and the second slope signal Vslope2 can be 180 degrees. In some embodiments, the first slope when the first slope signal Vslope1 rises can be the same as the second slope when the second slope signal Vslope2 rises. However, this case is not limited to this. The phase difference between the first slope signal Vslope1 and the second slope signal Vslope2 can be any other suitable phase difference. The first slope can also be different from the second slope. The first slope and the second slope can be set according to actual needs.

[0018] Please refer to step 230 in Figure 2, where the comparator generates an output signal based on the first slope signal, the second slope signal, and the input signal. For example, referring to Figures 1 and 3, taking the input signal Vi,1 as an example, the comparator 130 generates output signals cmp1 and com1X based on the first slope signal Vslope1, the second slope signal Vslope2, and the input signal Vi,1.

[0019] In detail, referring to period T1, at point P1, comparator 130 generates an output signal com1X based on the second slope signal Vslope2 and the input signal Vi,1. At this time, the digital output will output the counting result of Dcntx[3:0]. As shown in the figure, point P1 is located in the first half of period T1. Referring to period T2, at point P3, comparator 130 generates an output signal com1 based on the first slope signal Vslope1 and the input signal Vi,1. At this time, the digital output will output the counting result of Dcnt[3:0]. As shown in the figure, point P3 is located in the first half of period T2. Referring to period T3, at point P4, comparator 130 generates an output signal com1X based on the second slope signal Vslope2 and the input signal Vi,1. At this time, the digital output will output the counting result of Dcntx[3:0]. As shown in the figure, point P4 is located in the first half of period T3.

[0020] Therefore, compared to using only a single slope signal, the analog-to-digital converter 100 of this invention uses two slope signals (such as the first slope signal Vslope1 and the second slope signal Vslope2), which enables the comparator 130 to generate a comparison result in the first half of the cycle, thereby enabling the digital logic processor 140 to generate a data signal in the first half of the cycle. For example, the points P1, P3, and P4 mentioned above are all clearly located in the first half of the cycles T1, T2, and T3. Therefore, the operating timing of the analog-to-digital converter 100 of this invention can be further adjusted to the new timing shown in Figure 4. As shown in Figure 4, taking the new timing 1' as an example, the period T / 2 of the new timing of the analog-to-digital converter 100 of this invention is half the period T of the old timing. Therefore, the operating frequency of the analog-to-digital converter 100 of this invention is increased by two times.

[0021] Furthermore, referring to period T3 in Figure 3, at point P4, comparator 130 generates output signal com1X based on the second slope signal Vslope2 and input signal Vi,1. At this time, the digital output will output the counting result of Dcntx[3:0]. As can be seen from the figure, after the analog-to-digital converter 100 of this case adds the second slope signal Vslope2, the point P4 where the output signal is generated is located before the time point Phol, and the time point Phol is located at half of the maintenance period (Thold / 2). In addition, if the analog-to-digital converter 100 of this case only uses the first slope signal Vslope1, then the point P5 where the output signal is generated is located after the time point Phol. Thus, it can be proven that the conversion time of this case is shortened, less than half of the maintenance period (Thold / 2).

[0022] Therefore, compared to using only a single slope signal, the analog-to-digital converter 100 of this invention uses two slope signals (such as the first slope signal Vslope1 and the second slope signal Vslope2), which can shorten the conversion time of this invention to less than half of the holding period (Thold / 2). In other words, the operation latency of this invention is shortened to less than half of the holding period (Thold / 2).

[0023] The following sections will introduce some embodiments of this case one by one. However, this case is not limited to the embodiments described below. The embodiments described below are only used to introduce the technical concepts of this case so that this case can be easily understood.

[0024] In some embodiments, referring to FIG4, the voltage range Vr includes a low voltage level V1 and a high voltage level V2. A first slope signal Vslope1 rises from the low voltage level V1 to the high voltage level V2 within the voltage range Vr with a slope, and then falls from the high voltage level V2 to the low voltage level V1. In some embodiments, referring to FIG4, at least one first slope includes a first positive slope and a first negative slope. The first slope signal Vslope1 rises from the low voltage level V1 to the high voltage level V2 with a first positive slope during a first period A1, and then falls from the high voltage level V2 to the low voltage level V1 with a first negative slope during a second period A2.

[0025] In some embodiments, referring to FIG4, the second slope signal Vslope2 rises from a low voltage level V1 to a high voltage level V2 within the voltage range Vr with a slope, and then falls from the high voltage level V2 to the low voltage level V1. In some embodiments, referring to FIG4, at least one second slope includes a second positive slope and a second negative slope. The second slope signal Vslope2 rises from the low voltage level V1 to the high voltage level V2 with a second positive slope during a third period A3, and then falls from the high voltage level V2 to the low voltage level V1 with a second negative slope during a fourth period A4.

[0026] In some embodiments, as shown in Figure 4, the first period A1 and the third period A3 partially overlap, the second period A2 and the third period A3 partially overlap, and the second period A2 and the fourth period A4 do not overlap. However, this embodiment is not limited thereto, and the first period A1 to the fourth period A4 can be set according to actual needs.

[0027] In some embodiments, referring to FIG1, the first slope signal generator 110 includes a first output terminal Out1, a first switch SW1, and a second switch SW2. The first switch SW1 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the first switch SW1 is used to receive the current source current I. The second terminal (as shown below) of the first switch SW1 is coupled to the first output terminal Out1. The second switch SW2 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the second switch SW2 is coupled to the first output terminal Out1. The second terminal (as shown below) of the second switch SW2 is used to receive the voltage level V1 shown in FIG4. The first switch SW1 and the second switch SW2 output a first slope signal Vslope1 according to the first control signal Scon1 and the first reset signal Sre1. For example, when the first control signal Scon1 is at a high level, the first slope signal Vslope1 is gradually charged from the low voltage level V1 shown in FIG4 to the high voltage level V2. When the first reset signal Sre1 is at a high level, the first slope signal Vslope1 is reset to a low voltage level V1.

[0028] In some embodiments, referring to FIG1, the second slope signal generator 120 includes a second output terminal Out2, a third switch SW3, and a fourth switch SW4. The third switch SW3 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the third switch SW3 is used to receive the current source current I. The second terminal (as shown below) of the third switch SW3 is coupled to the second output terminal Out2. The fourth switch SW4 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the fourth switch SW4 is coupled to the second output terminal Out2. The second terminal (as shown below) of the fourth switch SW4 is used to receive the low voltage level V1 shown in FIG4. The third switch SW3 and the fourth switch SW4 output a second slope signal Vslope2 according to the second control signal Scon2 and the second reset signal Sre2. For example, when the second control signal Scon2 is at a high level, the second slope signal Vslope2 is gradually charged from the low voltage level V1 shown in FIG4 to the high voltage level V2. When the second reset signal Sre2 is at a high level, the second slope signal Vslope2 is reset to a low voltage level V1.

[0029] In some embodiments, the analog-to-digital converter 100 of this invention may employ a rising slope or a falling slope. In some embodiments, the phases of the first control signal Scon1 and the first reset signal Sre1 are not necessarily the same. Furthermore, the phases of the second control signal Scon2 and the second reset signal Sre2 are not necessarily the same. In some embodiments, the phase of the first control signal Scon1 is different from the phase of the second control signal Scon2, and the phase of the first reset signal Sre1 is different from the phase of the second reset signal Sre2. In some embodiments, the first control signal Scon1 and the first reset signal Sre1 may be a pair, the second control signal Scon2 and the second reset signal Sre2 may be a pair, and the phases of the first control signal Scon1 and the first reset signal Sre1 may be different from the phases of the second control signal Scon2 and the second reset signal Sre2. In some embodiments, referring to FIG1, the capacitor Cs3 of this invention is not limited to two; other suitable numbers may be used depending on actual needs.

[0030] It should be noted that this application is not limited to the embodiments shown in Figures 1 to 4, which are merely illustrative representations of one implementation method to facilitate understanding of the technology. The scope of this patent application shall be determined by the scope of the invention application. Modifications and refinements made by those skilled in the art to the embodiments of this application without departing from the spirit of this application still fall within the scope of the invention application.

[0031] In summary, the technical means embodied in the embodiments of this invention can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion device and analog-to-digital conversion method of this invention can reduce the operation cycle and thus increase the operation frequency.

[0032] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0033] 100: Analog-to-digital converter 110: First slope signal generator 120: Second slope signal generator 130: Comparator 140: Digital Logic Processor 200: Method 210~230: Steps A1~A4: Period Cs3: Capacitor cmp1, cmp2, ​​cmpN: Output signals cmp1X, cmp2X, cmpNX: Output signals DFF1, DFF1X: Flip-Flipper D1[3:0]: Data signal D1~DN: Data signals Dout: Data signal Dcnt[3:0], Dcntx[3:0]: Count values Out1: First output terminal Out2: Second output terminal P1~P6: Points Phol: Time Point SW1: First switch SW2: Second switch SW3: Third switch SW4: Fourth Switch Scon1: First control signal Scon2: Second control signal Sre1: First reset signal Sre2: Second reset signal T1~T3: Period T: Period Vslope1: First slope signal Vslope2: Second slope signal Vi,1, Vi,2, Vi,N, Vi,p, Vi,n: input signal VDD: Power supply voltage I: Current source current V1, V2: Voltage levels Vr: Voltage range

Claims

1. An analog-to-digital converter, comprising: a first slope signal generator for generating a first slope signal, wherein the first slope signal rises and falls back and forth within a voltage range at least a first slope; a second slope signal generator for generating a second slope signal, wherein the second slope signal rises and falls back and forth within the voltage range at least a second slope, wherein the first slope signal and the second slope signal have a phase difference, wherein the phase difference between the first slope signal and the second slope signal includes 180 degrees; and a comparator for generating an output signal based on the first slope signal, the second slope signal, and an input signal.

2. The analog-to-digital converter as claimed in claim 1, wherein the voltage range includes a low voltage level and a high voltage level, wherein the first slope signal is raised from the low voltage level to the high voltage level in the voltage range with the at least one first slope, and then lowered from the high voltage level to the low voltage level.

3. The analog-to-digital converter as claimed in claim 2, wherein the at least one first slope includes a first positive slope and a first negative slope, wherein the first slope signal is boosted from the low voltage level to the high voltage level with the first positive slope in a first period, and then falls from the high voltage level to the low voltage level with the first negative slope in a second period.

4. The analog-to-digital converter as claimed in claim 3, wherein the second slope signal is boosted from the low voltage level to the high voltage level in the voltage range by the at least one second slope, and then drops from the high voltage level to the low voltage level.

5. The analog-to-digital converter as claimed in claim 4, wherein the at least one second slope includes a second positive slope and a second negative slope, wherein the second slope signal is boosted from the low voltage level to the high voltage level with the second positive slope in a third period, and then falls from the high voltage level to the low voltage level with the second negative slope in a fourth period.

6. The analog-to-digital converter as claimed in claim 5, wherein the first period partially overlaps with the third period, the second period partially overlaps with the third period, and the second period does not overlap with the fourth period.

7. The analog-to-digital converter as claimed in claim 2, wherein the first slope signal generator comprises: a first output terminal; a first switch comprising: a first terminal for receiving a current source current; and a second terminal coupled to the first output terminal; and a second switch comprising: a first terminal coupled to the first output terminal; and a second terminal for receiving the low voltage level; wherein the first switch and the second switch output the first slope signal according to a first control signal and a first reset signal.

8. The analog-to-digital converter as claimed in claim 7, wherein the second slope signal generator comprises: a second output terminal; a third switch comprising: a first terminal for receiving the current source current; and a second terminal coupled to the second output terminal; and a fourth switch comprising: a first terminal coupled to the second output terminal; and a second terminal for receiving the low voltage level; wherein the third switch and the fourth switch output the second slope signal according to a second control signal and a second reset signal.

9. An analog-to-digital conversion method, comprising: generating a first slope signal by a first slope signal generator, wherein the first slope signal rises and falls back and forth in a voltage range with at least a first slope; generating a second slope signal by a second slope signal generator, wherein the second slope signal rises and falls back and forth in the voltage range with at least a second slope, wherein the first slope signal and the second slope signal have a phase difference, wherein the phase difference between the first slope signal and the second slope signal includes 180 degrees; and generating an output signal by a comparator based on the first slope signal, the second slope signal, and an input signal.

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