Semiconductor devices and power conversion devices

Abstract

In a reverse-conducting IGBT, the sudden back phenomenon when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode is turned on are suppressed. The semiconductor device is configured to include an IGBT region (105), a diode region (106), and an IGBT / diode boundary region (210) when viewed from above. A low-concentration p-type anode layer (211) is provided in the IGBT / diode boundary region (210). The low-concentration p-type anode layer (211) is adjacent to a low-concentration n-type drift layer (214) and is formed near the surface opposite to the p-type collector layer (209). It is electrically connected to the surface metal electrode (208) and is doped with a lower concentration than the p-type base layer. It is formed at a deeper position than the side gate (204) and the trench (205) and covers the trench (205).

Description

Technical Field

[0001] This invention relates to a semiconductor device and a power conversion device. Prior Technology

[0002] Driven by the global trend towards achieving a carbon-neutral society, the power semiconductor market has steadily grown at an average annual growth rate of 9.8%. In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate both an IGBT (Insulated Gate Bipolar Transistor) and a diode within the same chip, have been commercialized to achieve low loss and low cost. Reverse-conducting IGBTs reduce chip size by allowing the terminal areas of the IGBT and diode to be shared. Furthermore, since losses generated in the IGBT or diode area are dissipated as heat within the overall chip, they offer advantages such as reduced thermal resistance.

[0003] In order to reduce thermal resistance (temperature uniformity) and lower turn-on voltage, these reverse-conducting IGBTs have proposed various shapes such as dot type or stripe type as diode configurations.

[0004] For example, in Patent Document 1, the feature is that it includes an IGBT and a diode. The IGBT has a trench gate and an emitter layer formed on the surface side of the substrate, and a collector layer formed on the back side of the substrate. The diode has a trench gate and an anode layer formed on the surface side of the substrate, and a cathode layer formed on the back side of the substrate. The trench gate of the diode portion is insulated from the trench gate of the IGBT portion. The trench gate of the IGBT portion includes multiple stripe portions, and the trench gate of the diode portion also includes multiple stripe portions. The trench gate of the diode portion is configured to have a gap with the trench gate of the IGBT portion in the extension direction. This gap is formed in a houndstooth shape when viewed from above. By adopting this structure, the distance between the trench gate of the IGBT and the trench gate of the diode can be shortened, or a p-well layer can be provided between the trench gate of the IGBT and the trench gate of the diode, thereby ensuring sufficient withstand voltage while reducing the gate capacity. [Existing Technical Documents] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-41983 Summary of the Invention

[0006] [The problem that the invention aims to solve]

[0007] A reverse-conducting IGBT is formed by combining an IGBT and a diode on the same chip. When the IGBT region is turned on, electrons flow to the high-concentration n-type cathode layer (metal oxide semiconductor, MOS) in the diode region, while the forward bias voltage of the high-concentration p-type collector layer is restricted. Therefore, insufficient hole injection occurs, resulting in a snapback phenomenon.

[0008] Here, the mechanism of backflow in IGBT mode is explained. When the gate is opened under a positive bias in IGBT mode, electrons are supplied from the emitter. In FS-IGBTs (Field Stop IGBTs), these electrons need to cross the potential barrier consisting of a buffer layer and a p-type collector diffusion layer. On the other hand, in the case of RC-IGBTs, electrons can cross the adjacent n-type cathode diffusion layer. This mode is called MOS mode. Due to this characteristic, the rise on the low current side of RC-IGBTs is usually faster than that of FS-IGBTs. A portion of the electron current in MOS mode flows across the buffer layer. The lateral current component causes a voltage drop, which becomes maximum at the center of the p-type collector diffusion layer (the part farthest from the n-type diffusion layer). Hole injection begins from this part. As holes are injected and accumulate to the drift layer, the device becomes in a conductivity-modulated state, the resistance decreases, and the voltage drops. This results in backflow. Furthermore, when the diode is turned on, holes are injected from the P-body in the IGBT region into the low-concentration n-type drift layer, which raises the issue of increased recovery current.

[0009] Therefore, the objective of this invention is to provide a structure in a reverse-conducting IGBT that can suppress the backflow phenomenon when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode is turned on. [Methods for solving problems]

[0010] To address the aforementioned problem, the semiconductor device of the present invention is characterized in that, in top view, the semiconductor device includes an IGBT region, a diode region, and a boundary region between the IGBT region and the diode region. The IGBT region is provided with: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed near the surface of the first semiconductor layer; a first main electrode electrically connected to the second semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively disposed on the upper part of the third semiconductor layer; a second main electrode electrically connected to the third and fourth semiconductor layers; and a gate electrode disposed penetrating the fourth and third semiconductor layers and reaching... The inner wall of the trench of the first semiconductor layer, in the diode region, is provided with: a fifth semiconductor layer of a first conductivity type, formed near the surface of the first semiconductor layer and electrically connected to the first main electrode; a sixth semiconductor layer of a second conductivity type, adjacent to the first semiconductor layer and formed near the surface opposite to the fifth semiconductor layer; and a seventh semiconductor layer of a second conductivity type, selectively disposed on the upper part of the sixth semiconductor layer and electrically connected to the second main electrode. An eighth semiconductor layer is disposed in the boundary region, adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer, electrically connected to the second main electrode, of the second conductivity type and doped with a lower concentration than the third semiconductor layer, formed at a position deeper than the gate electrode and the trench and covering the trench.

[0011] That is, the power conversion device of the present invention includes: an AC terminal having the same number of phases as the AC output; a switch pin having the same number of phases as the AC output, connected between a pair of DC terminals, and connected in series with a parallel circuit of two switching elements and a diode of opposite polarity; and a gate circuit for controlling the switching elements. The power conversion device is characterized in that the switching elements are semiconductor devices as described in any one of the first to seventh inventions. Other components will be described in the embodiments of the invention. [The effects of the invention]

[0012] According to the present invention, in a reverse-conducting IGBT, the sudden back phenomenon when the IGBT is turned on and the hole injection from the IGBT region to the diode region when the diode is turned on can be suppressed. Simple Explanation of the Diagram

[0013] Figure 1 is a top view of the reverse-conducting IGBT chip of the first embodiment. Figure 2 is an AA cross-sectional view of the reverse-conducting IGBT chip. Figure 3 is a cross-sectional view of the reverse-conducting IGBT chip of the second embodiment. Figure 4 is a cross-sectional view of the reverse-conducting IGBT chip of the third embodiment. Figure 5 is a cross-sectional view of the reverse-conducting IGBT chip according to the fourth embodiment. Figure 6 is a cross-sectional view (AA) of the reverse-conducting IGBT wafer according to the fifth embodiment. Figure 7 is a cross-sectional view of the reverse-conducting IGBT chip according to the sixth embodiment. Figure 8 is a circuit diagram showing the general structure of the power conversion device. Implementation

[0014] The following describes in detail, with reference to the figures, the manner in which the present invention is carried out. Figure 1 is a top view of the reverse-conducting IGBT chip 100 according to the first embodiment. In the reverse-conducting IGBT wafer 100 of the semiconductor device according to the first embodiment of the present invention, a plurality of diode regions 106 surrounded by IGBT regions 105 are disposed. An emitter electrode 104 is formed on one surface of the IGBT region 105. Furthermore, a gate wiring 102 insulated from the emitter electrode 104 of the IGBT region 105 and surrounding the emitter electrode 104, and a gate electrode pad 103 connected to the gate wiring 102 are provided. The gate wiring 102 is connected to a plurality of side gates 204 described later. That is, the reverse-conducting IGBT wafer 100 is configured such that, when viewed from above, it includes the IGBT region 105, the diode region 106, and the boundary region between the IGBT region 105 and the diode region 106, namely the IGBT / diode boundary region 210.

[0015] Figure 2 is a cross-sectional view of the reverse-conducting IGBT chip 100. In the reverse-conducting IGBT wafer 100, trenches 205 are repeatedly formed at predetermined intervals in a direction orthogonal to the cross-section. An insulator is formed on the sidewall of the trench 205, and a side gate 204 of a conductor is formed along the sidewall. Furthermore, a field plate polysilicon 206 of a conductor is formed in the center of the trench 205, separated from the side gate 204 and the insulator.

[0016] IGBT Area The IGBT region 105 of the reverse-conducting IGBT chip 100 includes: a back metal electrode (first main electrode) 217 ​​serving as the collector electrode, a p-type collector layer (second semiconductor layer) 209, an n-type buffer layer 215, a low-concentration n-type drift layer (first semiconductor layer) 214, a p-type base layer (third semiconductor layer) 203, a high-concentration n-type emitter layer (fourth semiconductor layer) 201, a high-concentration p-type contact layer 202, a trench 205, a side gate 204, insulating films 232 and 233 within the trench 205, a field plate polysilicon 206 disposed between the gate electrodes within the trench 205, an interlayer insulating film 231, and an emitter contact (second main electrode) 207.

[0017] The IGBT region 105 is provided with: a low-concentration n-type drift layer 214 and an n-type buffer layer 215 serving as the first semiconductor layer; a p-type collector layer (second semiconductor layer) 209 formed near the surface on the back side of the first semiconductor layer; and a back metal electrode (first main electrode) 217 ​​electrically connected to the second semiconductor layer. The IGBT region 105 is further provided with: a p-type base layer (third semiconductor layer) 203 adjacent to the low-concentration n-type drift layer 214 and formed near the surface opposite to the p-type collector layer (second semiconductor layer) 209; a high-concentration n-type emitter layer (fourth semiconductor layer) 201 selectively disposed on the upper part of the p-type base layer 203; a surface metal electrode (second main electrode) 208 electrically connected to the third and fourth semiconductor layers; and a side gate electrode (gate electrode) 204 disposed on the inner wall of the trench 205 that penetrates the fourth and third semiconductor layers and reaches the first semiconductor layer.

[0018] Furthermore, the terms "n-type" and "p-type" refer to an n-type layer where electrons are the majority carriers and a p-type layer where holes are the majority carriers, respectively. "High concentration" or "low concentration" refers to a relatively high or low concentration of majority carriers (impurity concentration) in that layer. Furthermore, the first and second conductivity types described in the invention application correspond to n-type and p-type, respectively. If the first conductivity type is n-type, then the second conductivity type becomes p-type; if the first conductivity type is p-type, then the second conductivity type corresponds to n-type.

[0019] The IGBT region 105 of the reverse-conducting IGBT wafer 100 is formed as an n-channel IGBT. An n-type buffer layer 215, a p-type collector layer 209, and a back metal electrode 217 are deposited near the back surface of the low-concentration n-type drift layer 214. The back metal electrode 217 is electrically connected to the p-type collector layer 209.

[0020] A p-type base layer 203 is formed near the surface of the low-concentration n-type drift layer 214, adjacent to the low-concentration n-type drift layer 214. A high-concentration n-type emitter layer 201 is selectively disposed on the upper part of the p-type base layer 203. Therefore, the high-concentration n-type emitter layer 201 and the p-type base layer 203 are alternately arranged in the direction along the side of the trench 205. The emitter contact 207 is electrically connected to the p-type base layer 203 via the high-concentration p-type contact layer 202, and is also electrically connected to the high-concentration n-type emitter layer 201.

[0021] The insulating film 232 on the side of the trench 205 is in contact with the high-concentration n-type emitter layer 201 and the p-type base layer 203. The bottom surface of the trench 205 is deeper than the bottom surface of the high-concentration n-type emitter layer 201 and the p-type base layer 203, and reaches the low-concentration n-type drift layer 214. An insulating film 232, a side gate electrode 204 serving as a gate electrode, an interlayer insulating film 231, and a field plate polycrystalline silicon 206 are disposed on the inner side of the trench 205. The insulating film 232 is disposed on the side surface and the bottom surface of the trench 205. The side gate electrode 204 serving as a gate electrode is disposed on the insulating film 232 along the side surface of the trench 205. An insulating film 232 is disposed in the center of the bottom surface of the trench 205. The field plate polycrystalline silicon 206 is disposed on the insulating film 232. The polycrystalline silicon field plate 206 is positioned at a predetermined distance from the side gate 204, which serves as the gate electrode. The polycrystalline silicon field plate 206 is electrically connected to the surface metal electrode 208, which serves as the emitter electrode.

[0022] Inside the wide trench 205, the field plate polysilicon 206 is also formed to be wide. In contrast, the contact holes formed on the field plate polysilicon 206 are formed in the center of the field plate polysilicon 206, thus generating internal resistance within the field plate polysilicon 206.

[0023] The emitter electrode of the reverse-conducting IGBT wafer 100 is disposed along the sidewall of the trench 205 via an insulating film 232 on each surface of the high-concentration n-type emitter layer 201, the p-type base layer 203, and the low-concentration n-type drift layer 214. The side gate 204, serving as the gate electrode of the reverse-conducting IGBT wafer 100 in this embodiment, is disposed via the insulating film 232 of the trench 205 on the sidewall of a p-type base layer 203 in the IGBT region 105. Two side gates 204, i.e., a pair, are disposed opposite to each p-type base layer 203 and are arranged in a stripe pattern. Here, the gate structure can also be a trench gate or a planar structure.

[0024] A p-type collector layer 209 is formed on the opposite side of the surface structure of the IGBT region 105, and it is connected to the back metal electrode 217.

[0025] Additionally, a field plate polysilicon 206 is disposed between the gate electrodes inside the trench 205. The field plate polysilicon 206 is electrically connected to the surface metal electrode 208 via contacts. Similarly, the high-concentration n-type emitter layer 201, p-type base layer 203, and high-concentration p-type contact layer 202 are electrically connected to the surface metal electrode 208 by etching deeper emitter contacts 207 from the higher-concentration n-type emitter layer 201. By forming the emitter contacts 207 to a deeper level than the higher-concentration n-type emitter layer 201, the operation of the thyristor formed by the high-concentration n-type emitter layer 201, p-type base layer 203, low-concentration n-type drift layer 214, and p-type collector layer 209 can be suppressed, thereby suppressing damage caused by current concentration. Furthermore, the field plate polysilicon 206 is responsible for the planar structure and voltage stabilization of the IGBT region 105.

[0026] Diode Region Trenches 205 are formed at predetermined intervals near the surface of the low-concentration n-type drift layer 214 in diode region 106. A low-concentration p-type anode layer 211 and a high-concentration p-type anode layer 212 are deposited between the trenches 205. The surface metal electrode 208 functions as an anode electrode in diode region 106. The high-concentration p-type anode layer 212 is connected to the surface metal electrode 208 via anode contacts 213.

[0027] An n-type buffer layer 215, a high-concentration n-type cathode layer 216, and a back metal electrode 217 are deposited near the back surface of the low-concentration n-type drift layer 214 in diode region 106. The back metal electrode 217 is electrically connected to the high-concentration n-type cathode layer 216 and functions as a cathode electrode.

[0028] In diode region 106, similar to IGBT region 105, a side gate 204 is provided inside trench 205 and is electrically connected to surface metal electrode 208. The side gate 204 of diode region 106 is disposed on the sidewall of trench 205 adjacent to low-concentration p-type anode layer 211 and high-concentration p-type anode layer 212, and two side gates are arranged in a stripe pattern relative to a p-type base layer 203.

[0029] The diode region 106 is provided with: a high-concentration n-type cathode layer (fifth semiconductor layer) 216 formed near the back surface of the low-concentration n-type drift layer 214 and n-type buffer layer 215, which are the first semiconductor layer, and electrically connected to the back metal electrode (first main electrode) 217; a low-concentration p-type anode layer (sixth semiconductor layer) 211 adjacent to the first semiconductor layer and formed near the surface opposite to the high-concentration n-type cathode layer (fifth semiconductor layer) 216; and a high-concentration p-type anode layer (seventh semiconductor layer) 212 selectively disposed on the upper part of the low-concentration p-type anode layer (sixth semiconductor layer) 211 and electrically connected to the surface metal electrode (second main electrode) 208.

[0030] Boundary Area An IGBT / diode boundary region 210 is disposed at the boundary between IGBT region 105 and diode region 106. Trench 205 is formed at predetermined intervals near the surface of the low-concentration n-type drift layer 214 in the IGBT / diode boundary region 210. A low-concentration p-type anode layer 211, which is lower in concentration than and deeper than the p-type base layer 203 in IGBT region 105, is formed to cover all trench 205. The opposite side of the IGBT / diode boundary region 210 to the low-concentration p-type anode layer 211 is the back surface of the low-concentration n-type drift layer 214, in which an n-type buffer layer 215, a high-concentration n-type cathode layer 216, and a back metal electrode 217 are stacked.

[0031] In the IGBT / diode boundary region 210, similar to the IGBT region 105, a side gate 204 is provided inside the trench 205, and it is electrically connected to the surface metal electrode 208. The side gate 204 of the diode region 106 is disposed on the sidewall of the trench 205 adjacent to the low-concentration p-type anode layer 211 and the high-concentration p-type anode layer 212, and two side gates are arranged in a stripe pattern relative to a p-type base layer 203.

[0032] A low-concentration p-type anode layer (eighth semiconductor layer) 211 is provided in the IGBT / diode boundary region 210. The low-concentration p-type anode layer (eighth semiconductor layer) 211 is adjacent to the low-concentration n-type drift layer 214 and n-type buffer layer 215, which are the first semiconductor layers, and is formed near the surface opposite to the p-type collector layer (second semiconductor layer) 209. It is electrically connected to the surface metal electrode (second main electrode) 208 and is doped with a lower concentration than the p-type base layer (third semiconductor layer) 203. It is formed at a deeper position than the gate electrode and the trench 205 and covers the trench 205.

[0033] When the diode is turned on (conducting), holes are injected from the p-type base layer 203 of the IGBT region 105 into the low-concentration n-type drift layer 214, which may increase the recovery current. According to this structure, the recovery current of the diode region 106 can be mitigated by the IGBT / diode boundary region 210, thereby suppressing component damage caused by current concentration.

[0034] The low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 has a lower concentration than the p-type base layer 203 in the IGBT region 105, and the hole current from the IGBT / diode boundary region 210 is smaller than that from the IGBT region 105. Therefore, the current concentration suppression effect can be improved.

[0035] Furthermore, a low-concentration p-type anode layer 211 is formed to cover the trench 205. This also suppresses the avalanche current caused by electric field concentration at the corner of the trench 205. By suppressing the hole-electron current caused by electric field concentration, current concentration can be further suppressed.

[0036] Figure 3 is a cross-sectional view of the reverse-conducting IGBT chip 100 according to the second embodiment. The difference between the reverse-conducting IGBT wafer 100 of the second embodiment and the reverse-conducting IGBT wafer 100 of the first embodiment is that a low-concentration p-type anode layer 211 is formed as a covering trench 205 in both the diode region 106 and the IGBT / diode boundary region 210. The low-concentration p-type anode layer 211 of the second embodiment is lower in concentration and deeper than the p-type base layer 203 in the IGBT region 105. A high-concentration n-type cathode layer 216 is formed on the opposite side of the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 and on the opposite side of the anode layer in the diode region 106, and is connected to the back metal electrode 217.

[0037] That is, the low-concentration p-type anode layer (sixth semiconductor layer) 211 of diode region 106 and the low-concentration p-type anode layer (eighth semiconductor layer) 211 of IGBT / diode boundary region 210 are integrated to achieve a lower doping concentration than the p-type base layer (third semiconductor layer) 203 of IGBT region 105, and the structure is deeper than the p-type base layer (third semiconductor layer) 203.

[0038] According to this structure, the low-concentration p-type anode layer 211 of the diode region 106 is formed to cover the trench 205, and the corners of the trench 205 in the diode region 106 are also covered by the low-concentration p-type anode layer 211. This suppresses avalanche currents caused by electric field concentration at the corners of the trench 205, and further suppresses current concentration by suppressing hole-electron currents caused by electric field concentration. Furthermore, since the electric field concentration at the corners of the trench 205 is suppressed, the withstand voltage is improved.

[0039] Figure 4 is a cross-sectional view of the reverse-conducting IGBT chip 100 according to the third embodiment. The difference between the reverse-conducting IGBT chip 100 of the third embodiment and the reverse-conducting IGBT chip 100 of the first and second embodiments is that a p-type collector layer 209 is formed on the opposite side of the IGBT / diode boundary region 210 to the low-concentration p-type anode layer 211, and it is connected to the back metal electrode 217.

[0040] The p-type collector layer (second semiconductor layer) 209 of IGBT region 105 extends near the back surface of the low-concentration n-type drift layer (first semiconductor layer) 214 facing the low-concentration p-type anode layer (eighth semiconductor layer) 211 in IGBT / diode boundary region 210, and is electrically connected to the back metal electrode (first main electrode) 217.

[0041] The p-type collector layer (second semiconductor layer) 209 of IGBT region 105 extends near the surface of the low-concentration n-type drift layer (first semiconductor layer) 214 facing the low-concentration p-type anode layer (eighth semiconductor layer) 211 in IGBT / diode boundary region 210, and is electrically connected to the back metal electrode (first main electrode) 217.

[0042] According to this structure, when the IGBT is turned on (conducting), the MOS operation of the high-concentration n-type cathode layer 216 in the diode region 106 is suppressed, promoting the positive bias of the p-type collector layer 209 when the IGBT is turned on, thereby suppressing the back-current surge. Furthermore, when the diode is turned on (conducting), hole injection from the low-concentration p-type anode layer 211 in the IGBT / diode boundary region 210 and excessive hole injection from the p-type base layer 203 in the IGBT region 105 are suppressed, thereby reducing the recovery current.

[0043] Figure 5 is a cross-sectional view (AA) of the reverse-conducting IGBT chip 100 according to the fourth embodiment. The difference between the reverse-conducting IGBT wafer 100 of the fourth embodiment and the first to third embodiments is that, on the opposite side of the IGBT / diode boundary region 210, opposite to the low-concentration p-type anode layer 211, the low-concentration n-type cathode layer 216 of the higher-concentration n-type cathode layer 216 is connected to the back metal electrode 217. That is, in the IGBT / diode boundary region 210 of this embodiment, the n-type buffer layer 215 is connected to the back metal electrode 217.

[0044] The surface of the low-concentration n-type drift layer (first semiconductor layer) 214 facing the low-concentration p-type anode layer (sixth semiconductor layer) 211 in the IGBT / diode boundary region 210 is doped to a lower concentration than the high-concentration n-type cathode layer (fifth semiconductor layer) 216 in the diode region 106.

[0045] According to this structure, when the IGBT is turned on (conducting), the MOS operation of the high-concentration n-type cathode layer 216 of the diode is suppressed, promoting the positive bias of the p-type collector layer 209 when the IGBT is turned on, thereby suppressing the backflow. Furthermore, when the diode is turned on (conducting), hole injection from the low-concentration p-type anode layer 211 of the IGBT / diode boundary region 210 and excessive hole injection from the p-type base layer 203 of the IGBT region 105 are suppressed, thereby reducing the recovery current.

[0046] Furthermore, compared to the second embodiment, when the IGBT is turned off, the excess hole current from the low-concentration p-type anode layer 211 of the IGBT / diode boundary region 210 can be reduced, and the turn-off tolerance is improved.

[0047] Figure 6 is a cross-sectional view (AA) of the reverse-conducting IGBT chip 100 according to the fifth embodiment. The fifth embodiment of the reverse-conducting IGBT wafer 100 differs from the first to fourth embodiments in that, in the IGBT / diode boundary region 210, the p-type base layer 203 of the IGBT region 105 and the low-concentration p-type anode layer 211, which is lower in concentration and deeper than the p-type base layer 203, are separately configured. In the IGBT / diode boundary region 210, a high-concentration n-type cathode layer 216 is formed on the opposite side to the low-concentration p-type anode layer 211, and it is connected to the back metal electrode 217.

[0048] The low-concentration p-type anode layer (eighth semiconductor layer) 211 of the IGBT / diode boundary region 210 is separated from the p-type base layer (third semiconductor layer) 203 of the IGBT region 105 by a low-concentration n-type drift layer (first semiconductor layer) 214. The high-concentration n-type cathode layer (fifth semiconductor layer) 216 of the diode region 106 extends near the surface of the low-concentration n-type drift layer (first semiconductor layer) 214 facing the low-concentration p-type anode layer (eighth semiconductor layer) 211 in the IGBT / diode boundary region 210 and is electrically connected to the back metal electrode (first main electrode) 217.

[0049] According to this structure, the hole current injected from the p-type base layer 203 of the IGBT region 105 through the low-concentration p-type anode layer 211 of the IGBT / diode boundary region 210 is suppressed, thus reducing the recovery current.

[0050] Figure 7 is a cross-sectional view of the reverse-conducting IGBT chip 100 according to the sixth embodiment. The difference between the reverse-conducting IGBT wafer 100 of the sixth embodiment and the first to fifth embodiments is that, in both the diode region 106 and the IGBT / diode boundary region 210, the anode contact 213 and the emitter contact 207 of the IGBT region 105 are similarly formed deeper relative to the silicon upper surface. According to this structure, after forming the contact hole in the diode region 106, ion implantation is performed in a self-matching manner, thereby reducing the number of steps in forming the high-concentration p-type anode layer 212, thus enabling low-cost manufacturing. In the case of ion implantation in a self-matching manner, a high-concentration p-type anode layer 212 is also formed on the sidewall of the contact hole.

[0051] In the IGBT / diode boundary region 210, a high-concentration n-type surface layer 601 with a higher concentration than the anode layer is configured to suppress hole injection from the sidewall of the contact hole in the IGBT / diode boundary region 210.

[0052] According to this structure, the hole current in the IGBT / diode boundary region 210 is suppressed, thus suppressing component damage caused by current concentration.

[0053] Figure 8 is a circuit diagram showing the schematic structure of the power conversion device 500. Referring to FIG8, a sixth embodiment of applying the semiconductor device of the present invention to a power conversion device 500 will be described. FIG8 is a circuit diagram showing the structure of a power conversion device 500 employing the semiconductor device according to the first embodiment. FIG8 shows an example of the circuit structure of the power conversion device 500 of this embodiment, the connection relationship of the DC power supply, and the three-phase AC motor (AC load).

[0054] In the power conversion device 500 of this embodiment, the semiconductor devices of the first embodiment are used as power switching elements 501 to 506. Power switching elements 501 to 506 are elements formed by combining an IGBT and a diode in the reverse-conducting IGBT wafer 100 of the first embodiment.

[0055] As shown in Figure 8, the power conversion device 500 of this embodiment includes: a pair of DC terminals, namely P terminal 531 and N terminal 532; and AC terminals, namely U terminal 533, V terminal 534 and W terminal 535, which have the same number of phases as the AC output. Additionally, the configuration includes a series connection of a pair of power switching elements 501 and 502, with the U terminal 533 connected to the series connection point serving as an output switch pin. Furthermore, it includes a series connection of power switching elements 503 and 504, having the same structure as described above, with the V terminal 534 connected to the series connection point serving as an output switch pin. Finally, it includes a series connection of power switching elements 505 and 506, having the same structure as described above, with the W terminal 535 connected to the series connection point serving as an output switch pin.

[0056] The three-phase switch pins of the power switching elements 501 to 506 are connected between the DC terminals P terminal 531 and N terminal 532, and are supplied with DC power from a DC power source (not shown). The three-phase AC terminals of the power conversion device 500, namely U terminal 533, V terminal 534, and W terminal 535, are connected as a three-phase AC power source to a three-phase AC motor (not shown).

[0057] The input terminals of the gates of the power switching elements 501 to 506, which are equipped with reverse-conducting IGBTs, are connected to gate circuits 511 to 516, respectively. Power switching elements 501 to 506 are controlled by gate circuits 511 to 516. Furthermore, gate circuits 511 to 516 are controlled by a unified control circuit (not shown).

[0058] By using gate circuits 511 to 516 to comprehensively and appropriately control power switching elements 501 to 506, the DC power of DC power supply Vcc is converted into three-phase AC power and output from U terminal 533, V terminal 534 and W terminal 535.

[0059] By applying the semiconductor devices described in the first to sixth embodiments to the power conversion device 500, the terminal regions of the IGBT and diode can be shared, thereby reducing costs. Furthermore, since the losses generated in the IGBT region 105 or the diode region 106 are dissipated as heat in the overall wafer, the thermal resistance can be reduced.

[0060] [1] A semiconductor device, characterized in that, The semiconductor device is configured, when viewed from above, to include: an IGBT region (105), a diode region (106), and a boundary region between the IGBT region (105) and the diode region (106) (IGBT / diode boundary region 210). The IGBT region (105) is provided with: The first semiconductor layer of the first conductivity type (n) (low-concentration n-type drift layer 214, n-type buffer layer 215); A second semiconductor layer (p-type collector layer 209) of the second conductivity type (p) is formed near the surface of the first semiconductor layer; The first main electrode (back metal electrode 217) is electrically connected to the second semiconductor layer; The third semiconductor layer (p-type base layer 203) of the second conductivity type (p) is adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer; A fourth semiconductor layer (high-concentration n-type emitter layer 201) of the first conductivity type (n) is selectively disposed on the upper part of the third semiconductor layer; The second main electrode (surface metal electrode 208) is electrically connected to the third semiconductor layer and the fourth semiconductor layer; and The gate electrode (side gate 204) is disposed on the inner wall of the trench that penetrates the fourth semiconductor layer and the third semiconductor layer and reaches the first semiconductor layer. The diode region (106) is provided with: A fifth semiconductor layer (high-concentration n-type cathode layer 216) of the first conductivity type (n) is formed near the surface of the first semiconductor layer and is electrically connected to the first main electrode (back metal electrode 217); A sixth semiconductor layer (low-concentration p-type anode layer 211) of the second conductivity type (p) is adjacent to the first semiconductor layer and is formed near the surface opposite to the fifth semiconductor layer; and A seventh semiconductor layer (high-concentration p-type anode layer 212) of the second conductivity type (p) is selectively disposed on the upper part of the sixth semiconductor layer and is electrically connected to the second main electrode (surface metal electrode 208). An eighth semiconductor layer (low-concentration p-type anode layer 211) is provided in the boundary region (IGBT / diode boundary region 210). The eighth semiconductor layer (low-concentration p-type anode layer 211) is adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer. It is electrically connected to the second main electrode (anode contact 213), is of the second conductivity type (p), and is doped with a lower concentration than the third semiconductor layer (p-type base layer 203). It is formed at a deeper location than the gate electrode and the trench (205) and covers the trench (205).

[0061] When the diode is turned on (conducted), holes are injected from the third semiconductor layer (p-type base layer 203) of the IGBT region (105) into the first semiconductor layer (low-concentration n-type drift layer 214), which may increase the recovery current. According to this structure, the recovery current of the diode region (106) can be mitigated by the boundary region (IGBT / diode boundary region 210), thereby suppressing component damage caused by current concentration.

[0062] The eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) has a lower concentration than the third semiconductor layer (p-type base layer 203) in the IGBT region (105), and the hole current in the boundary region (IGBT / diode boundary region 210) is smaller than that in the IGBT region (105). Therefore, the current concentration suppression effect can be improved.

[0063] Furthermore, the eighth semiconductor layer (low-concentration p-type anode layer 211) is formed to cover the trench (205). This also suppresses the avalanche current caused by electric field concentration at the corner of the trench (205), and by suppressing the hole-electron current caused by electric field concentration, current concentration can be further suppressed.

[0064] [2] (Second Embodiment) The semiconductor device as described in the first invention is characterized in that, The sixth semiconductor layer of the diode region (106) and the eighth semiconductor layer (low-concentration p-type anode layer 211) of the boundary region are integrated to have a lower doping concentration than the third semiconductor layer (p-type base layer 203) of the IGBT region and to have a deeper structure than the third semiconductor layer (p-type base layer 203).

[0065] According to this structure, the sixth semiconductor layer (low-concentration p-type anode layer 211) of the diode region (106) is formed to cover the trench (205), and the corners of the trench (205) of the diode region (106) are also formed to be covered by the sixth semiconductor layer (low-concentration p-type anode layer 211). This suppresses avalanche currents caused by electric field concentration at the corners of the trench (205), and further suppresses current concentration by suppressing hole-electron currents caused by electric field concentration. Furthermore, since the electric field concentration at the corners of the trench (205) is suppressed, the withstand voltage is improved.

[0066] [3] (Third implementation) The semiconductor device as described in the first invention is characterized in that, The second semiconductor layer (p-type collector layer 209) of the IGBT region (105) extends near the surface of the first semiconductor layer facing the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and is electrically connected to the first main electrode (back metal electrode 217).

[0067] According to this structure, when the IGBT is turned on (conducting), the MOS operation of electron flow to the fifth semiconductor layer (high-concentration n-type cathode layer 216) in the diode region (106) is suppressed, and the positive bias of the second semiconductor layer (p-type collector layer 209) when the IGBT is turned on is promoted, thereby suppressing the back-current surge. Furthermore, when the diode is turned on (conducting), hole injection from the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and excessive hole injection from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) are suppressed, thereby reducing the recovery current.

[0068] [4](Details of the first embodiment) The semiconductor device as described in the first invention is characterized in that, The fifth semiconductor layer (high-concentration n-type cathode layer 216) of the diode region (106) extends on the surface of the first semiconductor layer facing the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and is electrically connected to the first main electrode (back metal electrode 217).

[0069] [5] (Details of the fourth embodiment) The semiconductor device as described in the first invention is characterized in that, The surface of the first semiconductor layer in the boundary region (IGBT / diode boundary region 210) facing the eighth semiconductor layer (low-concentration p-type anode layer 211) is doped to a lower concentration than that of the fifth semiconductor layer (high-concentration n-type cathode layer 216) in the diode region (106).

[0070] According to this structure, when the IGBT is turned on (conducting), the MOS operation of electron flow to the fifth semiconductor layer (high-concentration n-type cathode layer 216) of the diode is suppressed, and the positive bias of the second semiconductor layer (p-type collector layer 209) when the IGBT is turned on is promoted, thereby suppressing the back-current surge. Furthermore, when the diode is turned on (conducting), hole injection from the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and excessive hole injection from the third semiconductor layer (p-type base layer 203) in the IGBT region (105) are suppressed, thereby reducing the recovery current.

[0071] [6] (Fifth implementation) The semiconductor device as described in the first invention is characterized in that, The eighth semiconductor layer (low-concentration p-type anode layer 211) of the boundary region (IGBT / diode boundary region 210) is separately disposed from the third semiconductor layer of the IGBT region (105) through the first semiconductor layer. The fifth semiconductor layer (high-concentration n-type cathode layer 216) of the diode region (106) extends near the surface of the first semiconductor layer facing the eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region (IGBT / diode boundary region 210) and is electrically connected to the first main electrode (back metal electrode 217).

[0072] According to this structure, the hole current injected from the third semiconductor layer (p-type base layer 203) of the IGBT region (105) through the eighth semiconductor layer (low-concentration p-type anode layer 211) of the boundary region (IGBT / diode boundary region 210) is suppressed, thus reducing the recovery current.

[0073] [7] The semiconductor device as described in the first invention is characterized in that, The third semiconductor layer (p-type base layer 203) of the IGBT region (105) is connected to the second main electrode via a trench structure. The sixth semiconductor layer (low-concentration p-type anode layer 211) of the diode region (106) is connected to the second main electrode (surface metal electrode 208) via a trench structure. The eighth semiconductor layer (low-concentration p-type anode layer 211) in the boundary region is connected to the second main electrode (surface metal electrode 208) via a trench structure. In the trench structure of the boundary region (IGBT / diode boundary region 210), a high-concentration n-type surface layer (601) with a higher concentration than the anode layer of the boundary region is in contact with the sidewall of the trench (205).

[0074] According to this structure, the hole current in the boundary region (IGBT / diode boundary region 210) is suppressed, thus suppressing component damage caused by current concentration.

[0075] [8] A power conversion device, comprising: The number of AC terminals is the same as the number of phases in the AC output. The number of switch pins is the same as the number of phases in the AC output, connected between a pair of DC terminals, and connected in series with a parallel circuit of two switching elements and a diode of opposite polarity; and The gate circuit controls the switching element. The power conversion device (500) is characterized in that the switching element is a semiconductor device as described in any one of the first to seventh inventions.

[0076] By applying the semiconductor devices involved in the first to seventh inventions to the power conversion device (500), the terminal regions of the IGBT and diode can be shared, thereby achieving cost reduction. Furthermore, since the losses generated in the IGBT region (105) or the diode region (106) are dissipated as heat in the overall wafer, the thermal resistance can be reduced.

[0077] (Modified Example) This invention is not limited to the described embodiments and includes various modifications. For example, the embodiments have been described in detail for ease of understanding of the invention, but are not necessarily limited to all the structures described. A part of the structure of one embodiment can be replaced with the structure of another embodiment, or the structure of another embodiment can be added to the structure of one embodiment. In addition, it is also possible to add, delete, or replace other structures in a part of the structure of each embodiment.

[0078] Some or all of the aforementioned structures, functions, processing units, processing methods, etc., can be implemented, for example, by hardware such as integrated circuits. In each embodiment, regarding control lines or information lines, only those deemed necessary for explanation are shown, and not all control lines or information lines on the product are necessarily shown. In fact, it can be assumed that almost all structures are interconnected.

[0079] As variations of the present invention, there are structures as shown in (a) to (b) below. (a) The gate structure is not limited to a side-gate structure, but can also be a trench gate or a planar structure. (b) The reverse-conducting IGBT is not limited to an n-channel type IGBT, but can also be a p-channel type IGBT. In this case, it can be achieved by interchangeding the n-type and p-type phases of the semiconductor.

[0080] 100: Reverse conduction IGBT chip 102: Gate wiring 103: Gate electrode pad 104: Emitter electrode 105: IGBT region 106: Diode Region 201: High-concentration n-type emitter layer (fourth semiconductor layer) 202: High-concentration p-type contact layer 203: p-type base layer (third semiconductor layer) 204: Side gate (gate electrode) 205: Trench 206: Polycrystalline silicon in a field plate 207: Emitter contact (second main electrode) 208: Surface metal electrode (second main electrode) 209: p-type collector layer (second semiconductor layer) 210: IGBT / Diode Boundary Region (Boundary Region) 211: Low-concentration p-type anode layer (sixth semiconductor layer, eighth semiconductor layer) 212: High-concentration p-type anode layer (seventh semiconductor layer) 213: Anode contact (second main electrode) 214: Low-concentration n-type drift layer (first semiconductor layer) 215: n-type buffer layer (first semiconductor layer) 216: High-concentration n-type cathode layer (fifth semiconductor layer) 217: Backside metal electrode (first main electrode) 231: Interlayer insulating film 232, 233: Insulating film 500: Power conversion device 501, 502, 503, 504, 504, 506: Power switching components 511~516: Gate circuit 531: P terminal 532: N-terminal 533:U terminal 534: V terminal 535:W terminal 601: High-concentration n-type surface layer

Claims

1. A semiconductor device, characterized in that, when viewed from above, the semiconductor device comprises: The system comprises an insulated-gate bipolar transistor (IGBT) region, a diode region, and a boundary region between the IGBT region and the diode region. The IGBT region includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed near the surface of the first semiconductor layer; a first main electrode electrically connected to the second semiconductor layer; a third semiconductor layer of a second conductivity type adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer; a fourth semiconductor layer of a first conductivity type selectively disposed on the upper part of the third semiconductor layer; a second main electrode electrically connected to both the third and fourth semiconductor layers; and a gate electrode disposed on the inner wall of a trench penetrating the fourth and third semiconductor layers and reaching the first semiconductor layer. The diode region includes: a fifth semiconductor layer of a first conductivity type formed near the surface of the first semiconductor layer and electrically connected to the first main electrode. A sixth semiconductor layer of the second conductivity type is adjacent to the first semiconductor layer and formed near the surface opposite to the fifth semiconductor layer; and a seventh semiconductor layer of the second conductivity type is selectively disposed on the upper part of the sixth semiconductor layer and electrically connected to the second main electrode. An eighth semiconductor layer is disposed in the boundary region. The eighth semiconductor layer is adjacent to the first semiconductor layer and formed near the surface opposite to the second semiconductor layer, electrically connected to the second main electrode, is of the second conductivity type and is doped with a lower concentration than the third semiconductor layer, and is formed at a position deeper than the gate electrode and the trench and covers the trench.

2. The semiconductor device of claim 1, wherein the sixth semiconductor layer of the diode region and the eighth semiconductor layer of the boundary region constitute a single and continuous layer, having a lower concentration of doping than the third semiconductor layer of the insulated-gate bipolar transistor region, and having a deeper structure than the third semiconductor layer.

3. The semiconductor device of claim 1, wherein the second semiconductor layer of the insulated-gate bipolar transistor region extends near the surface of the first semiconductor layer opposite to the eighth semiconductor layer in the boundary region and is electrically connected to the first main electrode.

4. The semiconductor device of claim 1, wherein the fifth semiconductor layer of the diode region extends on the surface of the first semiconductor layer facing the eighth semiconductor layer in the boundary region and is electrically connected to the first main electrode.

5. The semiconductor device of claim 1, wherein the surface of the first semiconductor layer facing the eighth semiconductor layer in the boundary region is doped to a lower concentration than that of the fifth semiconductor layer in the diode region.

6. The semiconductor device of claim 1, wherein the eighth semiconductor layer of the boundary region is disposed separately from the third semiconductor layer of the insulated-gate bipolar transistor region through the first semiconductor layer, and the fifth semiconductor layer of the diode region extends near the surface of the first semiconductor layer in the boundary region opposite to the eighth semiconductor layer and is electrically connected to the first main electrode.

7. The semiconductor device of claim 1, wherein the third semiconductor layer of the insulated-gate bipolar transistor region is connected to the second main electrode via a trench structure, the sixth semiconductor layer of the diode region is connected to the second main electrode via a trench structure, the eighth semiconductor layer of the boundary region is connected to the second main electrode via a trench structure, and in the trench structure of the boundary region, a high-concentration n-type surface layer with a higher concentration than the anode layer of the boundary region is in contact with the trench sidewall.

8. A power conversion device, comprising: The number of AC terminals is the same as the number of phases in the AC output. The power conversion device is characterized in that the switching elements are semiconductor devices as described in any one of claims 1 to 7. The switching pins are the same number as the phases of the AC output, connected between a pair of DC terminals, and connected in series with a parallel circuit of two switching elements and a diode of opposite polarity; and a gate circuit for controlling the switching elements.

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