Semiconductor structures and methods for fabricating the same

Abstract

A method is provided, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer being interleaved; forming a dummy gate structure on the stack; selectively removing the second semiconductor layer of the stack to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; performing a first etching process on the first dielectric material to form a dielectric interposer; performing a first cleaning process using a first cleaning chemical solution; performing a second etching process to laterally etch the dielectric interposer to form a second gap between the first semiconductor layers; and performing a second cleaning process using a second cleaning chemical solution, the second cleaning chemical solution being different from the first cleaning chemical solution.

Description

[Technical Field]

[0001] The present invention relates to a structure and a method of manufacturing the same, and particularly to a semiconductor structure and a method of manufacturing the same. [Previous Technology]

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnects per unit wafer area) typically increases while geometry (i.e., the smallest element (or line) that can be manufactured using a process) decreases. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs. This miniaturization also increases the complexity of IC manufacturing processes. Similar advancements in IC manufacturing processes are needed to achieve these progresses.

[0003] For example, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Gate-all-around (GAA) transistors are an example of multi-gate devices, where the gate structure extends around its channel region, providing access to the entire channel region. These GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, enabling significant miniaturization while maintaining gate control and mitigating SCEs. However, conventional methods for manufacturing GAA devices can encounter challenges, including epitaxial losses in the source / drain regions, variations in channel length, weak regions of the gate electrode, and gate work function shifts, especially as device size decreases. Therefore, while conventional GAA devices are generally sufficient for their intended purpose, they are not entirely satisfactory in every respect. [Summary of the Invention]

[0004] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and are interleaved in the stack; forming a dummy gate structure on the stack; forming gate spacers on the sidewalls of the dummy gate structure; etching the source / drain regions of the stack to form source / drain trenches; selectively removing the second semiconductor layer of the stack to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; and depositing a first dielectric material to fill the first gap. The first dielectric material is subjected to a first etching process to form a dielectric interposer between first semiconductor layers; a first cleaning process is performed using a first cleaning chemical solution; a second etching process is performed to laterally etch the dielectric interposer to form a second gap between the first semiconductor layers; a second cleaning process is performed using a second cleaning chemical solution; an inner spacer of a second dielectric material is formed in the second gap; and a third cleaning process is performed using a third cleaning chemical solution, wherein the first dielectric material and the second dielectric material have different compositions, and the first cleaning chemical solution, the second cleaning chemical solution, and the third cleaning chemical solution each include hydrofluoric acid and water.

[0005] Other embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and are interleaved in the stack; forming a dummy gate structure on the stack; forming gate spacers on the sidewalls of the dummy gate structure; etching the source / drain regions of the stack to form source / drain trenches; selectively removing the stacked second semiconductor layer in the source / drain trenches to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; performing a first etching process on the first dielectric material to form a dielectric interposer between the first semiconductor layers; performing a first cleaning process using a first cleaning chemical solution; performing a second etching process to laterally etch the dielectric interposer to form a second gap between the first semiconductor layers; and performing a second cleaning process using a second cleaning chemical solution, the second cleaning chemical solution being different from the first cleaning chemical solution.

[0006] Some embodiments of the present invention provide a semiconductor structure comprising: a substrate having a top surface; an active region on the substrate; an insulating structure surrounding the active region; a plurality of channels stacked perpendicularly to each other in the active region on the substrate; a first source / drain (S / D) component and a second source / drain component inserted into and connecting each of the channels; and a gate stack disposed on the channels and extending to surround each of the channels, wherein each of the channels includes an edge portion having a top surface at an angle α to the top surface of the substrate, and wherein the angle α is between 0.1 degrees and 10 degrees.

Implementation Method

[0008] The following provides many different embodiments or examples to achieve different features of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the following description mentions forming a first component on or above a second component, which may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, the embodiments disclosed may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0009] Spatially relative terms, such as "below," "below," "lower," "above," "higher," etc., may be used here to facilitate the description of the relationship between one or more components or features in the diagram and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] Furthermore, when terms such as "approximately" or "approximately" are used to describe numbers or ranges of numbers, the numerical values ​​intended to be covered are those that include the described numbers within a reasonable range, such as within + / - 10% of the described numbers, or other numerical values ​​understood by one of ordinary skill in the art. For example, the term "approximately 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0011] Multigate devices (e.g., fully wound gate (GAA) devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects. GAA devices can be significantly reduced while maintaining gate control and mitigating SCEs. However, conventional methods of fabricating GAA devices may encounter challenges, including poor epitaxial growth in the source / drain region, small margins for formation of gate dielectrics and electrodes in narrow channel–channel spaces, and channel deterioration associated with various etching residues and defects. As device size shrinks, these drawbacks become more serious.

[0012] This disclosure relates generally to IC and semiconductor devices and their formation methods. More specifically, the present disclosure relates to GAA devices. The GAA device includes any device whose gate structure or portion thereof is formed around all sides of the channel area (e.g., around a portion of the channel area). In some cases, the GAA device can also be referred to as a quad-gate device, where the channel region has four sides and the gate structure is formed on all four sides. The channel region of the GAA device may include one or more semiconductor layers, each of which may be one of many different shapes, such as wire (or nanowire), sheet (or nanosheet), rod (or nanorod), and / or other suitable shape. In some embodiments, the channel region of the GAA device may have vertically spaced multiple horizontal semiconductor layers (e.g., nanowires, nanosheets, or nanorods) (hereinafter collectively referred to as “nanochannels”) such that the GAA device is a stacked horizontal GAA device. The GAA devices provided in this disclosure may be complementary metal oxide semiconductor (CMOS) GAA devices, p-type metal oxide semiconductor (pMOS) GAA devices, n-type metal oxide semiconductor (nMOS) GAA devices, or complementary field effect transistors (CFETs) with vertically stacked nMOS and pMOS transistors. Furthermore, the GAA device may have one or more channel regions associated with a single continuous gate structure or multiple gate structures. The domain of belonging has other examples of semiconductor devices that can usually be perceived by a knowledgeable person to benefit from the present disclosure. For example, other types of metal-oxide semiconductor field effect transistors (MOSFETs), such as planar MOSFETs, FinFETs, other multi-gate FETs, could benefit from this disclosure. The GAA devices and fabrication methods presented in this disclosure exhibit desired characteristics, exemplified by: (1) processes using fictitious intermediaries or fictitious oxide intermediaries (DOIs), (2) various cleaning processes aimed at eliminating or reducing etching residues or defects, and (3) increasing channel size and improving channel profile.

[0013] In the illustrated embodiment, the IC device includes a device structure (or GAA device or workpiece) 100. The device structure 100 can be manufactured during the process of manufacturing the IC or a portion thereof, and can contain static random access memory (SRAM) and / or logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type field-effect transistors (pFETs), n-type FETs (nFETs), FinFETs, MOSFETs, CMOS, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0014] According to some embodiments of the present disclosure, Figures 1A to 1C are flowcharts of example methods for manufacturing the apparatus structure, and Figures 2A to 6A and 8A to 16A are top views of embodiments of the apparatus structure of the present disclosure constructed at various manufacturing stages. According to some embodiments of the present disclosure, Figures 2B to 6B and 8B to 16B, Figures 2C to 6C and 8C to 16C, and Figures 2D to 6D and 8D to 16D are cross-sectional views of embodiments of the apparatus structure of the present disclosure along lines A-A', B-B', and C-C' in Figures 2A to 6A and 8A to 16A, respectively. According to some embodiments of the present disclosure, Figures 7A to 7I are cross-sectional views of example methods for manufacturing the apparatus. According to some embodiments of the present disclosure, Figure 7J shows a table of cleaning chemical solutions.

[0015] Referring to step 810 of Figure 1A and Figures 2A to 2D, the device structure 100 includes a substrate 200. In some embodiments, the substrate 200 comprises a semiconductor material, such as bulk silicon (Si). Alternatively or additionally, the substrate 200 may also include another elemental semiconductor, such as crystalline germanium (Ge). The substrate 200 may also include compound semiconductors, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb) or combinations thereof. The substrate 200 may also include a semiconductor-on-insulator substrate, such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or germanium-on-insulator (GOI) substrates. A portion of the substrate 200 may be doped, for example, doped portion 205. The doped portion 205 can be doped with a p-type dopant, such as boron (B) or boron fluoride (BF3), or with an n-type dopant, such as phosphorus (P) or arsenic (As). The doped portion 205 can also be doped with a combination of p-type and n-type dopant (e.g., to form a p-type well and an adjacent n-type well). The doped portion 205 can be formed directly on the substrate 200 as a p-well structure, an n-well structure, a double-well structure, or a bump structure.

[0016] Referring to step 820 of Figure 1A and Figures 2A to 2D, the semiconductor layers 220A and 220B are stacked in an alternating or staggered manner on the substrate 200, extending perpendicularly (e.g., along the Z direction) from the substrate 200. For example, semiconductor layer 220B is disposed on the substrate 200, semiconductor layer 220A is disposed on semiconductor layer 220B, another semiconductor layer 220B is disposed on semiconductor layer 220A, and so on. In the depicted embodiment, there are three semiconductor layers 220A and three semiconductor layers 220B alternating with each other. However, any suitable number of layers can be in the stack. For example, there can be 2 to 10 semiconductor layers 220A alternating with 2 to 10 semiconductor layers 220B in the stack. For convenience, semiconductor layers 220A and 220B are also referred to as first semiconductor layer 220A and second semiconductor layer 220B, respectively. The material composition of semiconductor layers 220A and 220B is configured to give them etch selectivity in subsequent etching processes. For example, in some embodiments, semiconductor layer 220A comprises silicon germanium (SiGe), while semiconductor layer 220B comprises silicon (Si). In some other embodiments, semiconductor layer 220B comprises SiGe, while semiconductor layer 220A comprises Si. In the depicted embodiments, each semiconductor layer 220A has a substantially uniform thickness, depicted as a thickness of 300 in Figure 2B, while each semiconductor layer 220B has a substantially uniform thickness, depicted as a thickness of 310 in Figure 2B.

[0017] Referring to step 820 of Figure 1A and Figures 3A to 3D, the stack of semiconductor layers 220A and 220B is patterned into a plurality of fin structures, for example, patterned into fin structures (or fins) 130a and 130b. Each of fins 130a and 130b comprises a stack of semiconductor layers 220A and 220B arranged alternately to each other. Fins 130a and 130b each extend longitudinally (e.g., longitudinally) in a first direction (e.g., the Y direction) and are separated from each other (e.g., laterally) in a second direction (e.g., the X direction), as shown in Figures 3A and 3D. As shown in Figure 3A, each fin may have a lateral width along the X direction, depicted as a width of 350 in Figure 3A. It should be understood that the X and Y directions are horizontal directions perpendicular to each other, and the Z direction is a vertical direction orthogonal (or perpendicular) to the plane defined by the X and Y directions. The substrate 200 can have its top surface aligned parallel to the XY plane. In some embodiments, fins 130a and fins 130b have different widths.

[0018] Fins 130a and 130b can be patterned using any suitable method. For example, one or more lithography processes (including dual patterning or multiple patterning processes) can be used to pattern the fins. Generally, dual patterning or multiple patterning processes combine lithography with a self-aligned process to create, for example, a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrel can then be used as a mask to pattern the fins. Patterning can utilize a variety of etching processes, which may include dry etching and / or wet etching. The area where the fins are formed will be used to form the active device through subsequent processes and is therefore referred to as the active region. For example, fin 130a is formed in active region 202a, and fin 130b is formed in active region 202b. Fins 130a and 130b both protrude from the doped portion 205.

[0019] Device structure 100 includes an isolation component 203, which may be a shallow trench isolation (STI) component. In some examples, the isolation component 203 is formed by etching trenches in a substrate 200 between active regions and filling the trenches with one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. Any suitable method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-assisted CVD (PECVD), plasma-assisted ALD (PEALD), and / or combinations thereof, may be used to deposit the isolation component 203. The isolation component 203 may have a multilayer structure, such as a thermal oxide liner on the substrate 200 and a filler layer (e.g., silicon nitride or silicon oxide) on the thermal oxide liner. Alternatively, any other isolation formation technique may be used to form the isolation component 203. As shown in Figure 3D, fins 130a and 130b are located above the top surface 203a of the isolation member 203 (e.g., protruding beyond the isolation member 203) and above the top surface 200a of the substrate 200. In some embodiments, the fins 130a / 130b and the isolation member 203 are formed together in the same process, such as including a stack of patterned semiconductor layers 220A and 220B to form fins and trenches; filling the trenches with one or more dielectric materials; performing a chemical mechanical polishing (CMP) process; and etching back the isolation member 203 such that the isolation member 203 is recessed below the fins 130a and 130b.

[0020] Referring to step 830 of Figure 1A and Figures 4A to 4D, a dummy gate structure 210 is formed on a portion of each of fins 130a and 130b and on the isolation member 203 between fins 130a and 130b. The dummy gate structure 210 may be configured to extend longitudinally (e.g., longitudinally) parallel to each other, for example, each extending along the X direction, as shown in Figure 4A. In some embodiments, as shown in Figure 4D, the dummy gate structures each wrap around the top and side surfaces of each of fins 130a, 130b. The dummy gate structure 210 may include polysilicon. In some embodiments, the dummy gate structure 210 further includes one or more masking layers for patterning the dummy gate electrode layers. The dummy gate structure 210 may undergo a gate replacement process through subsequent processes to form a metal gate, such as a high-k (dielectric constant) metal gate, which will be discussed in more detail below. Some dummy gate structures 210 may also undergo a second gate replacement process to form a dielectric-based gate that electrically isolates the GAA device 100 from adjacent devices, as will be discussed in more detail below. The dummy gate structure 210 can be formed through processes including deposition, photolithography, and etching. Deposition processes may include CVD, ALD, PVD, other suitable methods, and / or combinations thereof.

[0021] Referring to step 840 of Figure 1A and Figures 5A to 5D, a gate spacer (or first spacer) 240 is formed on the sidewall of the dummy gate structure 210. The gate spacer 240 may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon carbide oxide (SiOC), silicon oxynitride (SiON), silicon oxynitride oxide (SiOCN), carbon-doped oxide, nitrogen-doped oxide, other suitable dielectric materials, or combinations thereof. The gate spacer 240 may include a single-layer or multi-layer structure. In some embodiments, each gate spacer 240 may have a thickness 241 of about 3 nm to about 10 nm (e.g., measured in the Y direction). Device performance may require thicknesses within a specified range, particularly for advanced technology nodes. In some embodiments, the gate spacer 240 may be formed by depositing a spacer layer (containing a dielectric material) on the dummy gate structure 210, followed by an anisotropic etching process to remove a portion of the spacer layer from the top surface of the dummy gate structure 210. After the etching process, a portion of the spacer layer on the sidewall surface of the dummy gate structure 210 is substantially retained and becomes the gate spacer 240. In some embodiments, the anisotropic etching process is a dry (e.g., plasma) etching process. Additionally or alternatively, the formation of the gate spacer 240 may also involve chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In the active region, the gate spacer 240 is formed on top of the semiconductor layer 220A. Therefore, the gate spacer 240 may also be interchangeably referred to as the top spacer 240. In some examples, one or more material layers (not shown) may also be formed between the dummy gate structure 210 and the corresponding top spacer 240. As an example, one or more material layers may include an interface layer and / or a high-k dielectric layer.

[0022] Referring to step 850 of Figure 1A and Figures 6A to 6D, portions of the fins 130a and 130b exposed by the dummy gate structure 210 and gate spacer 240 are at least partially etched (or removed) to form trenches 151 for subsequent epitaxial source and drain growth. The process for forming trenches 151 may include one or more lithography and etching steps, and any suitable method may be used, such as dry etching and / or wet etching. As an example, one or more of the plurality of lithography and etching steps for forming trenches 151 may include a first etching process having a first etch chemical and a second etching process having a second etch chemical different from the first etch chemical. The first etching process may be a master etching process that initially forms an opening in the stack of semiconductor layers 220A and 220B, while the second etching process may be an over-etching process that shapes the initially formed opening to produce the desired profile of trenches 151, such as trenches with vertical sidewalls. The first etching chemical may include hydrogen bromide (HBr) in combination with argon (Ar), helium (He), oxygen (O2), or combinations thereof. The second etching chemical may include hydrogen bromide (HBr) in combination with nitrogen, methane (CH4), or combinations thereof. The second etching process (e.g., an over-etching process) may be performed at high bias power (e.g., a bias power of about 200 watts to about 400 watts).

[0023] Method 800 proceeds to steps 860 to 874 of Figures 7A to 7I, which are related to the process steps applied to trench 151 and designed to reduce residue and enhance channel performance. For simplicity, only cross-sectional views of Figures 7A to 7I along line A-A' are shown. In detail, steps 860 to 874 begin with Figure 7A, which is similar to Figure 6B, although the number of semiconductor layers 220A and 220B may differ. As mentioned above, any suitable number of layers can be present in the stack.

[0024] Referring to step 860 of Figure 1B and Figure 7B, semiconductor layer 220B is removed through trench 151 via a selective etching process, thereby creating a first gap 602 between semiconductor layers 220A. The selective etching process can be any suitable process, such as wet etching or dry etching. In one embodiment, semiconductor layer 220A comprises Si and semiconductor layer 220B comprises SiGe. In such an embodiment, a Standard Clean 1 (SC-1) solution can be used to selectively etch the SiGe semiconductor layer 220B. For example, SiGe semiconductor layer 220B can be etched at a significantly faster rate than Si semiconductor layer 220A. Therefore, semiconductor layer 220B (e.g., the sides) is removed, while semiconductor layer 220A remains largely unchanged. The SC-1 solution contains ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). Optimal conditions can be achieved by further adjusting the etching temperature, dopant concentration, and other experimental parameters.

[0025] In another embodiment, semiconductor layer 220A comprises SiGe and semiconductor layer 220B comprises Si. In such an embodiment, a cryogenic deep reactive ion etching (DRIE) process can be used to selectively etch the Si semiconductor layer 220B. For example, the DRIE process can implement sulfur hexafluoride-oxygen (SF6-O2) plasma. Optimal conditions can be achieved by adjusting the etching temperature, the power of the inductively coupled plasma (ICP) power supply and / or the radio frequency (RF) power supply, the ratio between SF6 concentration and O2 concentration, the dopant (e.g., boron) concentration, and other experimental parameters. For example, at a temperature of approximately -80°C, the etching rate of the Si semiconductor layer 220B using SF6-O2 plasma (with approximately 6% O2) can exceed approximately 8 μm / min; while the SiGe semiconductor layer 220A is largely unaffected during this process.

[0026] Referring to step 862 of Figure 1B and Figure 7C, one or more dielectric materials 604 are deposited to fill the first gap 602. The dielectric material 604 is deposited on the sidewalls of the trench 151, the sidewalls of the gate spacer 240, and the top of the dummy gate structure 210. In some embodiments, the dielectric material 604 includes silicon oxide, silicon nitride, silicon oxynitride, any suitable dielectric material, or a combination thereof.

[0027] In some embodiments, the dielectric material 604 comprises silicon oxide. The silicon oxide dielectric material 604 can be formed by CVD, low-pressure chemical vapor deposition (LPCVD), ambient pressure chemical vapor deposition (APCVD), flow CVD (FCVD), thermal oxidation, other suitable methods, or combinations thereof. In some examples, silicon oxide is formed via CVD using precursors comprising silane (SiH4) and oxygen (O2), alternatively including PH3 or B2H6 as dopants. The deposition temperature ranges from 400°C to 500°C. In some examples, silicon oxide is formed via LPCVD using precursors comprising tetraethoxysilane (Si(OC2H5)4, TEOS) and oxygen (O2) at a deposition temperature of approximately 700°C, for example, between 650°C and 750°C. In some examples, silicon oxide is formed via PECVD using precursors including TEOS and ozone (O3) at deposition temperatures between 300°C and 350°C. In some examples, silicon oxide is formed via PECVD using precursors including SiH4 and N2O at deposition temperatures between 200°C and 450°C. In some examples, silicon oxide is formed via APCVD using precursors including TEOS and O3 at deposition temperatures between 350°C and 500°C. In some examples, silicon oxide is formed via thermal oxidation PECVD using precursors including SiH4 and N2O at deposition temperatures between 200°C and 450°C.

[0028] In the disclosed embodiments, the dielectric material 604 comprises silicon oxide and is formed through a process including CVD and FCVD. For example, CVD is applied to form a thin silicon oxide layer, and then FCVD is applied to form another silicon oxide to completely fill the first gap 602. In a further embodiment, the first deposition step includes forming a first silicon oxide layer via CVD using a precursor comprising silane (SiH4) and oxygen (O2) at a deposition temperature between 400°C and 500°C; and the second deposition step includes forming a second silicon oxide layer via FCVD, as specifically described below.

[0029] The FCVD process may include depositing silicon and nitrogen-containing films (e.g., silicon-nitrogen-hydrogen (Si-NH) films) from carbon-free silicon and nitrogen precursors and radical precursors. Because the silicon and nitrogen films are formed in a carbon-free environment, fewer pores are formed and less volume shrinkage occurs when the film is converted to hardened silicon oxide. The conversion of the silicon and nitrogen film to silicon oxide can be accomplished by heating the silicon and nitrogen film in an oxygen-containing environment. The oxygen-containing substances in this environment may include radical atomic oxygen (O), molecular oxygen (O2), ozone (O3), and / or vapor (H2O), as well as other oxygen-containing gases. The heating temperature, time, and pressure are sufficient to oxidize the silicon and nitrogen film to a silicon oxide film.

[0030] Referring to step 864 of Figure 1B and Figure 7D, an etching process (also referred to as a first etching process) is applied to the dielectric material 604 to remove portions of the dielectric material 604 deposited on the sidewalls of the trench 151 to form a dielectric interposer (or dummy oxide interposer) 606 in the first gap 602. The method includes anisotropic etching, such as electro-etching, which is generally performed in a vertical direction. In a further embodiment, plasma etching includes an etchant having a fluorine-containing gas, a chlorine-containing gas, other suitable gases, or combinations thereof.

[0031] Referring to step 866 of Figure 1B and Figure 7E, a first wet cleaning process 608 using a first cleaning chemical solution is applied to the workpiece 100 to remove any residues, such as metal residues after the first etching process in step 864. Due to the effective etching process, the metal residues remain on the etched surface. Furthermore, the existing cleaning process damages the dielectric interposer 606, resulting in defects such as voids on the dielectric interposer 606. Other problems may also exist. For example, the first semiconductor layer 220A, which ultimately serves as the channel for the GAA transistor, is further degraded, for example, by reducing the size of the portion exposed to the cleaning solution. The ends of the first semiconductor layer 220A are reduced to rounded corners and smaller in size by the cleaning solution, which further degrades the performance and critical voltage of the GAA device. Therefore, this disclosure has determined, through various experiments, the cleaning solutions, cleaning process conditions, and parameters to be implemented in this step and other subsequent steps described below.

[0032] In the disclosed embodiments, the first cleaning chemical solution comprises hydrofluoric acid (HF), water (H2O), and one or more pH adjusters. In some embodiments, the cleaning solution comprises hydrofluoric acid (HF) at a volume concentration (volume ratio: the ratio of the volume of the corresponding chemical to the total volume of the cleaning solution) of 0.02% to 20%, water (H2O) at a volume concentration of 60% to 99.8%, an alkaline pH adjuster, and an acidic pH adjuster. In some embodiments, the alkaline adjuster comprises ammonium hydroxide (NH4OH) at a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12. In some embodiments, the acidic adjuster comprises hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or combinations thereof at a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 1 and 6. In a further embodiment, when applied to workpiece 100, the cleaning solution comprises a temperature between 5°C and 80°C.

[0033] In one embodiment, the first cleaning solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an alkaline pH adjuster NH4OH with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12, and the solution temperature is between 5°C and 80°C. In another embodiment, the cleaning solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an acidic pH adjuster containing hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or a combination thereof, with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 1 and 6, and the solution temperature is between 5°C and 80°C.

[0034] The cleaning solution thus prepared exhibits high selectivity and effectiveness in cleaning the workpiece 100 without damaging the dielectric interposer 606 and the first semiconductor layer 220A, and leaves no metal residue. Furthermore, the cleaning solutions (e.g., second and third cleaning solutions, as described below) are further tailored to each cleaning step to achieve their respective effects.

[0035] Referring to step 868 of Figure 1B and Figure 7F, an etching process (also referred to as a second etching process) is applied to the dielectric interposer 606, by means of a selective etching process to laterally etch the dielectric interposer 606 through the exposed sidewall surfaces in the trench 151. The selective etching process can be any suitable etching process, such as a wet etching process or a dry etching process. The extent of etching of the dielectric interposer 606 (or the size of the removed portion) is determined by the process conditions (e.g., the duration of exposure of the dielectric interposer 606 to the etching chemicals). In the depicted embodiment, the duration is controlled such that the side of the dielectric interposer 606 located directly below the gate spacer 240 is completely removed, while the central portion of the dielectric interposer 606 remains substantially unchanged. In other words, the remaining portions of the dielectric interposer 606 each have sidewalls substantially aligned with the sidewalls of the dummy gate structure 210 (e.g., sidewalls in the XZ plane defined by the X and Z directions). As shown in Figure 7F, the selective etching process creates a trench (also referred to as a second gap) 610 that extends trench 151 into the region beneath semiconductor layer 220A and top spacer 240. Meanwhile, semiconductor layer 220A is only slightly affected during the selective etching process. The etching selectivity between the first semiconductor layer 220A and dielectric interposer 606 is made possible by the etchant and the etching process. For example, dielectric interposer 606 can be etched at a significantly faster rate than the first semiconductor layer 220A (e.g., about 5 to about 10 times faster). In some embodiments, the etching process is a wet etching using an HF solution as the etchant.

[0036] The steps in Figure 1B are described below with reference to Figures 7G to 7I. Figures 7G to 7I are cross-sectional views of the device structure 100, which is similar to but only partially shown in Figures 7A to 7F. For example, for simplicity, only a portion of the dashed box 612 in Figure 7F is shown.

[0037] Referring to step 870 of Figure 1B and Figure 7G, a second wet cleaning process 614 using a second cleaning chemical solution is applied to the workpiece 100 to remove any residues, such as metal residues after the second etching process of step 868, and to prepare the surface for subsequent processes. In the disclosed embodiments, the second cleaning chemical solution includes hydrofluoric acid (HF), water (H2O), and one or more pH adjusters. In some embodiments, the cleaning solution includes hydrofluoric acid (HF) at a volume concentration (volume ratio) of 0.02% to 20%, water (H2O) at a volume concentration of 60% to 99.8%, and one of an alkaline pH adjuster and an acidic pH adjuster. In some embodiments, the alkaline adjuster includes ammonium hydroxide (NH4OH) at a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12. In some embodiments, the acidity adjuster includes hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or combinations thereof, at a volume concentration of 0% to 20%, to adjust the pH of the cleaning solution to between 1 and 6. In a further embodiment, when applied to workpiece 100, the cleaning solution is at a temperature between 5°C and 80°C.

[0038] In one embodiment, the second cleaning chemical solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an alkaline pH adjuster NH4OH with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12, and the solution temperature is between 5°C and 80°C. In another embodiment, the cleaning solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an acidic pH adjuster containing hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or a combination thereof, with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 1 and 6, and the solution temperature is between 5°C and 80°C.

[0039] The cleaning solution thus prepared exhibits high selectivity and effectiveness in cleaning the workpiece 100 without damaging the dielectric interposer 606 and the first semiconductor layer 220A, and leaves no metal residue. Furthermore, the third cleaning solution (described below) is further modified to achieve its effectiveness. However, the cleaning process in step 870 and other subsequent cleaning processes can be modified to differ from the cleaning process in step 866, as will be described in further detail below.

[0040] After the second etching process in step 868 and the second cleaning process in step 870, a second gap 610 is formed between the first semiconductor layers 220A. Specifically, experimental data shows that the first semiconductor layer 220A has no loss or minimal loss at its edges, as shown in Figure 7G. The first semiconductor layer 220A maintains its contour without a rounding issue. Specifically, the first semiconductor layer 220A has a thickness T0 in its main portion and a thickness T1 at its edges. The difference ΔT = T0 - T1 is less than 2 nm. In other words, if there is loss, the loss ΔT is less than 2 nm. In some examples, the difference ΔT ranges from 0.1 nm to 1.5 nm. The top surface of the first semiconductor layer 220A is substantially coplanar with the XY plane. The edge portion of the first semiconductor layer 220A has a top surface at an angle α to the XY plane. In this embodiment, the angle α is less than 20 degrees. In some examples, the angle α ranges from 0.1 degrees to 20 degrees. In some examples, the angle α ranges from 0.1 degrees to 10 degrees.

[0041] In some embodiments, the sidewalls 616 of the recessed dielectric interposer 606 have concave surfaces as shown in Figure 7G. In this case, each gap 610 between adjacent first semiconductor layers 220A has a varying recess size along the Z direction from the lower first semiconductor layer 220A to the upper first semiconductor layer 220A. The maximum recess size is located at an intermediate level between the lower and upper first semiconductor layers 220A.

[0042] Referring to step 872 of Figure 1B and Figure 7H, dielectric material 250 is filled into the second gap 610. The method of forming dielectric material 250 includes deposition using a suitable deposition technique. Dielectric material 250 differs in composition from dielectric interposer 606 to achieve etch selectivity during subsequent processes, such as during channel release operations. In some embodiments, dielectric material 250 may be selected from SiON, SiOC, SiOCN, other suitable dielectric materials, or combinations thereof. In some embodiments, a suitable selection of dielectric material may be based on its dielectric constant. In one embodiment, dielectric material 250 may have a lower dielectric constant than the top spacer 240. In some other embodiments, dielectric material 250 may have a higher dielectric constant than the top spacer 240. This aspect of the dielectric material will be discussed further below. Deposition of the dielectric material can be by any suitable method, such as CVD, PVD, PECVD, MOCVD, ALD, PEALD, or combinations thereof.

[0043] Referring to step 874 of Figure 1B and Figure 7H, an etching process (also referred to as a third etching process) is applied to the dielectric material 250, such that the dielectric material 250 formed on the sidewalls of the trench 151 is removed by the third etching process. The third etching process includes anisotropic etching with generally perpendicular etching, such that portions of the dielectric material 250 deposited on the sidewalls and bottom surface of the trench 151 are removed. In the depicted embodiment, the third etching process is a self-aligned anisotropic dry etching process, such that the top spacer 240 serves as a masking element. Alternatively, different masking elements (e.g., photoresist) can be used. The third etching process removes the dielectric material 250 within the trench 151, but does not substantially affect the dielectric material 250 within the second gap 610. Therefore, the dielectric material 250 fills the second gap 610 as an inner spacer (or second spacer), also indicated by reference numeral 250. In other words, the inner spacer 250 is formed in the second gap 610 between the vertically adjacent (e.g., along the Z direction) sides of the first semiconductor layer 220A.

[0044] Referring to step 876 of Figure 1B and Figure 7I, a third wet cleaning process 618 using a third cleaning chemical solution is applied to the workpiece 100 to remove any residues, such as metal residues after the third etching process of step 872, and to prepare the surface for subsequent processes. In the disclosed embodiments, the third cleaning chemical solution includes hydrofluoric acid (HF), water (H2O), and one or more pH adjusters. In some embodiments, the cleaning solution includes hydrofluoric acid (HF) at a volume concentration (volume ratio) of 0.02% to 20%, water (H2O) at a volume concentration of 60% to 99.8%, and one of an alkaline pH adjuster and an acidic pH adjuster. In some embodiments, the alkaline adjuster includes ammonium hydroxide (NH4OH) at a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12. In some embodiments, the acidity adjuster includes hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or combinations thereof, at a volume concentration of 0% to 20%, to adjust the pH of the cleaning solution to between 1 and 6. In a further embodiment, when applied to workpiece 100, the cleaning solution is at a temperature between 5°C and 80°C.

[0045] In one embodiment, the third cleaning chemical solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an alkaline pH adjuster NH4OH with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 5 and 12, and the solution temperature is between 5°C and 80°C. In another embodiment, the cleaning solution comprises hydrofluoric acid (HF) with a volume concentration (volume ratio) of 0.02% to 20%; water (H2O) with a volume concentration of 60% to 99.8%; and an acidic pH adjuster containing hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), or a combination thereof, with a volume concentration of 0% to 20% to adjust the pH of the cleaning solution to between 1 and 6, and the solution temperature is between 5°C and 80°C.

[0046] The cleaning solution thus prepared exhibits high selectivity and effectiveness in cleaning the workpiece 100 without damaging the dielectric interposer 606 and the first semiconductor layer 220A, and leaves no metal residue. Furthermore, since each cleaning solution is applied to different surfaces and conditions, the cleaning solutions can be further tailored to each cleaning step to achieve their respective effects. However, the third cleaning process in step 876 can be modified to differ from the first cleaning process in step 866 and the second cleaning process in step 870, as will be described in further detail below.

[0047] According to various embodiments, Figure 7J provides a table of cleaning processes and corresponding cleaning chemical solutions. The cleaning processes and corresponding cleaning chemical solutions have different characteristics, and therefore different cleaning and removal selectivity suitable for different cleaning processes. The table in Figure 7J includes four embodiments of cleaning processes and corresponding cleaning chemical solutions. The first row shows various conditions, parameters, and characteristics of the cleaning processes and corresponding cleaning chemical solutions, including the HF concentration (%, volume ratio) in the cleaning solution, the pH value of the cleaning solution, the temperature of the cleaning solution, the removal selectivity between Al2O3 and SiO2, and the removal selectivity between SiN and SiO2. The removal selectivity between A and B is defined as the ratio of the removal rate of A to the removal rate of B. In various embodiments, the pH value and temperature of the cleaning chemical solution are adjusted differently to achieve significant variations in removal selectivity, as described in detail below.

[0048] In the first embodiment, the cleaning chemical solution comprises HF at a concentration of 0.02% to 1%; a pH value between 2.5 and 4.0; and a temperature between 20°C and 25°C. Therefore, the removal selectivity of the corresponding cleaning chemical solution for Al2O3 and SiO2 is between 7 and 10, and the removal selectivity for SiN and SiO2 is between 4 and 5.

[0049] In the second embodiment, the cleaning chemical solution includes HF at a concentration of 0.02% to 1%; a pH value between 1.5 and 2.5; and a temperature between 20°C and 25°C. Therefore, the removal selectivity of the corresponding cleaning chemical solution for Al2O3 and SiO2 is between 20 and 30, and the removal selectivity for SiN and SiO2 is between 0.5 and 1.5.

[0050] In the third embodiment, the cleaning chemical solution comprises HF at a concentration of 0.02% to 1%; a pH value between 0.5 and 1.5; and a temperature between 20°C and 25°C. Therefore, the removal selectivity of the corresponding cleaning chemical solution for Al2O3 and SiO2 is between 50 and 70, and the removal selectivity for SiN and SiO2 is between 1.5 and 2.

[0051] In the fourth embodiment, the cleaning chemical solution comprises HF at a concentration of 0.02% to 1%; a pH value between 0.5 and 1.5; and a temperature between 30°C and 70°C. Therefore, the removal selectivity of the corresponding cleaning chemical solution for Al2O3 and SiO2 is between 300 and 600, and the removal selectivity for SiN and SiO2 is between 2 and 3.

[0052] As can be seen from the fine-tuning formulation of the above-mentioned cleaning chemical solution, when the pH value of the cleaning chemical solution is adjusted from a higher pH value (e.g., 3) to a lower pH value (e.g., 1) using an acidic regulator, the removal selectivity between Al2O3 and SiO2 increases from below 10 to above 50, while the removal selectivity between SiN and SiO2 does not change monotonically; specifically, it decreases from 4 to 5 to 0.5 to 1.5, and then increases to 1.5 to 2. When the temperature increases from 20℃ and 25℃ to 30℃ and 70℃, the removal selectivity between Al2O3 and SiO2 significantly increases from below 70 to above 300, while the removal selectivity between SiN and SiO2 does not change much.

[0053] From the above data and experiments, it was found that temperature and pH value can be used to adjust the removal selectivity of various residues to adapt to various cleaning processes. The first, second, and third cleaning processes are performed after the first, second, and third etching processes. For example, the first etching process is a dry etching process to selectively remove silicon oxide; the second etching process is a wet etching process to selectively remove silicon oxide; and the third etching process is a dry etching process to selectively remove silicon nitride. Therefore, in order to better remove residues and minimize damage to the first semiconductor layer 220A and the dielectric interposer 606, in some embodiments, the first cleaning process uses the fourth formulation of the fourth embodiment in the table of Figure 7J; the second cleaning process uses the third formulation of the third embodiment in the table of Figure 7J; and the third cleaning process uses the first formulation of the first embodiment in the table of Figure 7J. In some embodiments, the first cleaning process uses the fourth formulation of the fourth embodiment in the table of Figure 7J; the second cleaning process uses the second formulation of the second embodiment in the table of Figure 7J; and the third cleaning process uses the first formulation of the first embodiment in the table of Figure 7J.

[0054] In some other embodiments, the first cleaning process and the second cleaning process respectively use a first cleaning chemical solution and a second cleaning chemical solution with different pH values, different temperatures, or different HF concentrations, or combinations thereof. For example, the first and second cleaning processes use first and second cleaning chemical solutions having first and second pH values, respectively, such that the second pH value is greater than the first pH value. In another example, the first and second cleaning processes use first and second cleaning chemical solutions having first and second temperatures, respectively, such that the second temperature is higher than the first temperature.

[0055] In one embodiment, the first cleaning solution comprises hydrofluoric acid (HF) at a volume concentration (volume ratio) of 0.02% to 0.5%; water (H2O) at a volume concentration of 94.5% to 99.88%; and an acidic pH adjuster, hydrogen chloride (HCl), at a volume concentration of 0.1% to 5.0%, to adjust the pH of the cleaning solution to 1 to 6, and the solution temperature to 25°C to 80°C. Therefore, the first semiconductor layer 220A exhibits significantly reduced losses. In the disclosed embodiment with this scheme, the channel sheet deviation T0-T1 of the topmost semiconductor layer 220A ranges from 0.1 nm to 1.5 nm; the channel sheet deviation T0-T1 of the remaining semiconductor layers 220A (excluding the topmost semiconductor layer) ranges from 0.1 nm to 1 nm; the channel sheet angle deviation α of the topmost semiconductor layer 220A ranges from 0.1 degrees to 20 degrees; and the channel sheet angle deviation α of the remaining semiconductor layers 220A (excluding the topmost semiconductor layer) ranges from 0.1 degrees to 15 degrees. The parameters T0, T1, and α are described in Figure 7G above.

[0056] The following steps are described with reference to the top views of Figures 8A to 16A constructed according to various embodiments and the cross-sectional views of Figures 8B to 16B, 8C to 16C and 8D to 16D.

[0057] Referring to step 890 of Figure 1C and Figures 8A to 8D, method 800 continues to form epitaxial source / drain components 208 in trench 151. In some embodiments, one source / drain component is a source electrode and the other source / drain component is a drain electrode. Semiconductor layer 220A extending from one source / drain component 208 to the other source / drain component 208 can form a channel of device structure 100. Various processes including growth processes can be used to grow the epitaxial source / drain components 208. In the depicted embodiments, the epitaxial source / drain component 208 has a top surface substantially aligned with the top surface of the topmost semiconductor layer 220A. However, in other embodiments, the epitaxial source / drain component 208 may alternatively have a top surface extending higher than the top surface of the topmost semiconductor layer 220A (e.g., along the Z direction). In the depicted embodiment, the epitaxial source / drain component 208 occupies the lower portion of trench 151 (e.g., the portion defined by inner spacer 250 and semiconductor layer 220A), leaving the upper portion of trench 151 (e.g., the portion defined by top spacer 240). In some embodiments, the epitaxial source / drain components 208 may be merged together, for example, along the X direction, to provide a greater lateral width than individual epitaxial components. In the depicted embodiment, as shown in Figure 8A, the epitaxial source / drain components 208 are not merged.

[0058] The epitaxial source / drain component 208 may include any suitable semiconductor material. For example, the epitaxial source / drain component 208 in an n-type GAA device may include Si, SiC, SiP, SiAs, SiPC, or combinations thereof; while the epitaxial source / drain component 208 in a p-type GAA device may include Si, SiGe, Ge, SiGeC, or combinations thereof. The source / drain component 208 may be doped in situ or out-of-situ. For example, an epitaxially grown Si source / drain component may be doped with carbon to form a silicon:carbon (Si:C) source / drain component, doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, or doped with both to form a silicon-carbon-phosphorus (SiCP) source / drain component; an epitaxially grown SiGe source / drain component may be doped with boron. One or more annealing processes may be performed to activate the dopants in the epitaxial source / drain component 208. Annealing processes may include rapid thermal annealing (RTA) and / or laser annealing processes.

[0059] The epitaxial source / drain component 208 is directly bonded to the continuous sidewall surface of the first semiconductor layer 220A. During epitaxial growth, semiconductor material grows from the exposed top surface 200a of the substrate 200 (e.g., the exposed top surface of the doped region 205) and from the exposed side surface of the semiconductor layer 220A. It should be noted that during the epitaxial growth process, semiconductor material does not grow from the surfaces of the inner spacer 250 and the top spacer 240.

[0060] Referring to step 900 of Figure 1C and Figures 9A to 9D, an interlayer dielectric (ILD) layer 214 is formed in the remaining space of trench 151 and on the epitaxial source / drain components 208, and also perpendicularly on the isolation component 203. The ILD layer 214 may also be formed along the Y direction between adjacent dummy gate structures 210 and along the X direction between source / drain components 208. The ILD layer 214 may include a dielectric material, such as a high-k material, a low-k material, or an extremely low-k material. For example, the ILD layer 214 may include SiO2, SiOC, SiON, or combinations thereof. The ILD layer 214 may include a single layer or multiple layers and may be formed using suitable techniques, such as CVD, FCVD, and / or spin coating. After the formation of the ILD layer 214, a CMP process may be performed to remove excess portions of the ILD layer 214, thereby planarizing the top surface of the ILD layer 214. In other functions, ILD layer 214 provides electrical isolation between various components of device structure 100.

[0061] Referring to step 910 of Figure 1C and Figures 10A to 10D, the dummy gate structure 210 is selectively removed using any suitable lithography and etching process. In some embodiments, the lithography process may include forming a photoresist layer (impedance), exposing the impedance to a pattern, performing a post-exposure baking process, and developing the impedance to form a mask element that exposes the area including the dummy gate structure 210. The dummy gate structure 210 is then selectively etched through the mask element. In some other embodiments, the top spacer 240 may be used as a mask element or part thereof. For example, the dummy gate structure 210 may include polysilicon, the top spacer 240 and the inner spacer 250 may include dielectric materials, and the semiconductor layer 220A includes a semiconductor material. Therefore, etching selectivity can be achieved by selecting suitable etching chemicals, allowing the dummy gate structure 210 to be removed with minimal impact on the components of the device structure 100. The removal of the dummy gate structure 210 creates a gate trench 153. Gate trench 153 exposes the top and side surfaces of the first semiconductor layer 220A and the dielectric interposer 606, as shown in Figure 10D. In other words, the first semiconductor layer 220A and the dielectric interposer 606 are exposed on at least two side surfaces in gate trench 153. Additionally, gate trench 153 also exposes the top surface of the isolation member 203.

[0062] Referring to step 920 of Figure 1C and Figures 11A to 11D, the dielectric interposer 606 is further selectively removed through the gate trench 153, thereby releasing the first semiconductor layer 220A as a channel, for example using a wet or dry etching process. The etching chemicals are selected such that the dielectric interposer 606 has a sufficiently different etch rate compared to the inner spacer 250 and the first semiconductor layer 220A. Therefore, the first semiconductor layer 220A and the inner spacer 250 remain substantially unchanged. This selective etching process may include one or more etching steps. The etching process may be similar to the etching process of step 868. For example, the etching process includes a wet etching step using an HF solution to selectively remove the dielectric interposer 606.

[0063] As shown in Figures 11A to 11D, in this embodiment, the removal of the dielectric interposer 606 forms a suspended semiconductor layer 220A and an opening 157 between vertically adjacent layers (e.g., in the Z direction), thereby exposing the top and bottom surfaces of the first semiconductor layer 220A. Each first semiconductor layer 220A is now circumferentially exposed in the XZ plane. Furthermore, portions of the doped region 205 located beneath the first semiconductor layer 220A are also exposed in the opening 157. However, in some other embodiments, the removal process removes only some, not all, of the second semiconductor layer 220B.

[0064] In the examples shown in Figures 10A to 10D and 11A to 11D, the gate trench 153 and the opening 157 perpendicularly adjacent to the gate trench 153 (e.g., along the Z direction) together form an opening with a vertical profile. In other words, the opening formed by the gate trench 153 and its corresponding opening 157 has vertical sidewalls. In some embodiments, such an opening with vertical sidewalls can be formed by multiple etching processes. For example, the etching chemistry of the etching process used to remove the dummy gate structure 210 and thereby form the gate trench 153 (e.g., in Figures 10A to 10D) may include hydrogen bromide (HBr) and may be combined with chlorine (Cl2), tetrafluoromethane (CF4), oxygen, or combinations thereof. Furthermore, the etching process for selectively removing the dielectric interposer 606 and thereby forming the opening 157 (e.g., in figures 11A to 11D) may have an initial etching chemical comprising hydrogen bromide (HBr) and may be combined with chlorine (Cl2), oxygen, or a combination thereof. This initial etching chemical is followed by a subsequent etching chemical comprising hydrogen bromide (HBr) and may be combined with tetrafluoromethane (CF4), oxygen, or a combination thereof, which causes a vertical profile of the opening formed together by the gate trench 153 and its corresponding opening 157. In an alternative embodiment, the initial etching chemical is followed by a subsequent wet etching chemical using an HF solution to selectively remove the dielectric interposer 606. However, as described further in detail below, in other embodiments, the opening formed together by the gate trench 153 and its corresponding opening 157 may have a tapered profile. Such a tapered profile can be achieved by omitting the aforementioned subsequent etching chemical, which comprises hydrogen bromide (HBr) and may be combined with tetrafluoromethane (CF4), oxygen, or a combination thereof. In such an example, the gate structure subsequently formed in the conical opening also has a conical profile.

[0065] Referring to steps 930 and 940 of Figure 1C, Figures 12A to 12D, and Figures 13A to 13D, a gate structure is formed. The gate structure includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. For example, the gate structure may include a polycrystalline silicon gate electrode on a SiON gate dielectric layer. As another example, the gate structure may include a metal gate electrode on a high-k dielectric layer. In some cases, a refractory metal layer may be inserted between the metal gate electrode (e.g., an aluminum gate electrode) and the high-k dielectric layer. As another example, the gate structure may include a silicate. In the depicted embodiments, each gate structure includes a gate dielectric layer 228 and a gate electrode, the gate electrode including one or more metal layers 230, 232, as shown in Figures 13A to 13D. The gate dielectric layer 228 is formed between the metal layers 230, 232 and the channel (semiconductor layer 220A).

[0066] In some embodiments, a gate dielectric layer 228 is compliantly formed on the device structure 100 (refer to Figures 12A to 12D). The gate dielectric layer 228 at least partially fills the gate trench 153. In some embodiments, a dielectric interface layer may be formed on the semiconductor layer 220A prior to the formation of the gate dielectric layer 228. The dielectric interface layer improves the adhesion between the semiconductor layer 220A and the gate dielectric layer 228. Such a dielectric interface layer is omitted in the examples described in this disclosure. Instead, in the illustrated embodiments, the gate dielectric layers 228 are formed around the exposed surfaces of each semiconductor layer 220A such that they surround each semiconductor layer 220A in 360 degrees. Furthermore, the gate dielectric layers 228 also directly contact the sidewalls of the inner spacer 250 and the sidewalls of the top spacer 240. The gate dielectric layer 228 may include a dielectric material having a dielectric constant greater than that of SiO2, which has a dielectric constant of approximately 3.9. For example, the gate dielectric layer 228 may comprise hafnium oxide (HfO2) having a dielectric constant of about 18 to about 40. As various other examples, the gate dielectric layer 228 may comprise ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, SrTiO, or combinations thereof. The gate dielectric layer 228 can be formed through any suitable process, such as CVD, PVD, ALD, or combinations thereof.

[0067] Referring to step 940 of Figure 1C and Figures 13A to 13D, metal layers 230 and 232 are formed on the gate dielectric layer 228 to fill the remaining space of the gate trench 153. The metal layers 230 and 232 may comprise any suitable material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbide nitride (TaCN), aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), or combinations thereof. In some embodiments, CMP is performed to expose the top surface of the ILD layer 214. The dielectric layer 228 and metal layer 230 together form the gate structure 270, while the dielectric layer 228 and metal layer 232 together form the gate structure 272. Each gate structure 270, 272 meshes with multiple nanochannels 220A.

[0068] The gate electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Ru, Co, or any suitable conductive material. In some embodiments, different metal materials are used for pFET and nFET devices having their respective work functions to improve device performance and reduce the threshold voltage. For example, gate structure 270 is the gate structure of a pFET device, and gate structure 272 is the gate structure of an nFET device.

[0069] The gate electrode may include various conductive materials, such as work function metal layers that differ for pFET and nFET devices, and a fill metal layer. In some embodiments, the gate electrode includes a capping layer, a barrier layer, a work function metal layer, and a fill metal layer. In further embodiments, the capping layer includes titanium nitride, tantalum nitride, or other suitable materials, formed by a suitable deposition technique (e.g., ALD). The barrier layer includes titanium nitride, tantalum nitride, or other suitable materials, formed by a suitable deposition technique (e.g., ALD). In various embodiments, the fill metal layer includes aluminum, tungsten, copper, or other suitable metals. The fill metal layer is deposited by a suitable technique, such as PVD, electroplating, or a combination thereof.

[0070] The work function metal layer comprises a conductive layer of a metal or metal alloy having a suitable work function, thereby improving the device performance of the corresponding FET. The composition of the work function (WF) metal layer differs between pFET and nFET devices, and they are therefore referred to as p-type WF metal and n-type WF metal, respectively. Specifically, an n-type WF metal is a metal with a first work function, which lowers the threshold voltage of the associated nFET. The n-type WF metal has a work function close to or lower than the silicon conduction band level (Ec), making it easier for electrons to disengage. For example, an n-type WF metal has a work function of about 4.2 eV or less. A p-type WF metal is a metal with a second work function, which lowers the threshold voltage of the associated pFET. The p-type WF metal has a work function close to or higher than the silicon valence band level (Ev), exhibiting a stronger electron bonding energy with the atomic nucleus. For example, a p-type work function metal has a WF of about 5.2 eV or higher. In some embodiments, the n-type WF metal comprises tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or combinations thereof. In other embodiments, the n-metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or combinations thereof. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or combinations thereof. The work function metal is deposited using a suitable technique, such as PVD. The n-type or p-type WF metal may include various metal substrate films as a stack to optimize device performance and process compatibility.

[0071] In some embodiments, the gate top hard mask layer 260 may be selectively formed on the gate structures 270, 272. For example, referring to Figures 14A to 14D, the metal layers 230, 232 may be selectively etched such that the top surfaces of the metal layers 230, 232 extend below the top surface of the ILD layer 214. Subsequently, as shown in Figures 15A to 15D, the gate top hard mask layer 260 is formed on the device structure 100 to cover the gate structures 270, 272 (specifically, the metal layers 230, 232), the ILD layer 214, and fill the space created by the etching process. CMP may be performed to planarize the top surface of the gate top hard mask layer 260. In some embodiments, as shown in Figures 16A to 16D, CMP exposes the top surface of the ILD layer 214, the top surface of the top spacer 240, and the top surface of the gate dielectric layer 228. The gate-top hard mask layer 260 may include a dielectric material such as SiO2, SiOC, SiON, SiOCN, nitride-based dielectrics, metal oxide dielectrics, HfO2, Ta2O5, TiO2, ZrO2, Al2O3, Y2O3, or combinations thereof. The gate-top hard mask layer 260 protects the gate structures 270, 272 during subsequent etching processes to form source / drain contact components and insulates the gate structures 270, 272. However, in some other embodiments (not shown), the etching of metal layers 230, 232 and / or the formation of the gate-top hard mask layer 260 are omitted. In some embodiments, gate structure 270 is the gate structure of a pFET device, and gate structure 272 is the gate structure of an nFET device.

[0072] As shown in Figure 7B, the channel (or first semiconductor layer) 220A maintains its contour without rounding issues. Specifically, the channel 220A has a thickness T0 in its main portion and a thickness T1 at its edges. The difference ΔT = T0 - T1 is less than 2 nm. In other words, if there is loss, the loss ΔT is less than 2 nm. In some examples, the difference ΔT ranges from 0.1 nm to 1.5 nm. The top surface of the first semiconductor layer 220A is substantially coplanar with the XY plane. The edge portion of the first semiconductor layer 220A has a top surface at an angle α to the XY plane. In this embodiment, the angle α is less than 20 degrees. In some examples, the angle α ranges from 0.1 degrees to 20 degrees. In some examples, the angle α ranges from 0.1 degrees to 10 degrees.

[0073] Method 800 may include additional process steps performed before, during, and / or after the various operations described above. For example, step 950 of method 800 in Figure 1C includes forming an interconnect structure to connect various FETs and other devices to an integrated circuit. The interconnect structure includes contacts, vias, and metal lines formed through a suitable process. In a copper interconnect structure, conductive components include copper and may also include a barrier layer. The copper interconnect structure is formed through a damascene process. The damascene process includes depositing an ILD layer; patterning the ILD layer to form trenches; depositing various materials (e.g., a barrier layer and copper); and performing a CMP process. The damascene process may be a single damascene process or a dual damascene process. Copper deposition may include PVD to form a seed layer and electroplating to form bulk copper on the copper seed layer. Other metals, such as ruthenium, cobalt, tungsten, or aluminum, may be used to form the interconnect structure. In some embodiments, silicon may be formed on the source and drain electrodes before filling the contact vias with conductive material to further reduce contact resistance. Silicides include silicon and metals such as titanium silicon, tantalum silicon, nickel silicon, or cobalt silicon. Silicides can be formed using a process called self-aligned silicide (or salicide). The process includes metal deposition, annealing to allow the metal to react with the silicon, and etching to remove unreacted metal. In some other embodiments, other metals, such as ruthenium or cobalt, can be used for contacts and / or through-holes.

[0074] This disclosure provides a semiconductor structure having a GAA structure and a method for manufacturing this semiconductor structure using designed clean chemicals and clean processes. While not intended to be limiting, the embodiments disclosed herein offer benefits to semiconductor processes and semiconductor devices. For example, the disclosed method reduces metal residue and damage to channels, thereby improving device performance.

[0075] In one example aspect, this disclosure provides a method of manufacturing a semiconductor structure, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and are interleaved with each other in the stack; forming a dummy gate structure on the stack; forming gate spacers on the sidewalls of the dummy gate structure; etching source / drain regions of the stack to form source / drain trenches; selectively removing the second semiconductor layer of the stack to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; and depositing a first dielectric material to fill the first gap. The dielectric material undergoes a first etching process to form a dielectric interlayer between first semiconductor layers; a first cleaning process is performed using a first cleaning chemical solution; a second etching process is performed to laterally etch the dielectric interlayer to form a second gap between the first semiconductor layers; a second cleaning process is performed using a second cleaning chemical solution; an inner spacer of the second dielectric material is formed in the second gap; and a third cleaning process is performed using a third cleaning chemical solution, wherein the first dielectric material and the second dielectric material have different compositions, and the first cleaning chemical solution, the second cleaning chemical solution, and the third cleaning chemical solution each include hydrofluoric acid and water.

[0076] In some embodiments, forming an inner spacer in the second gap further includes: depositing a second dielectric material to fill the second gap; and performing a third etching process on the second dielectric material.

[0077] In some embodiments, the first dielectric material includes silicon oxide, and the second dielectric material includes silicon nitride.

[0078] In some embodiments, the first cleaning chemical solution, the second cleaning chemical solution and the third cleaning chemical solution each further include a pH adjuster.

[0079] In some embodiments, the pH adjuster includes an alkaline pH adjuster having ammonium hydroxide (NH4OH).

[0080] In some embodiments, the pH adjuster includes an acidic pH adjuster having at least one of hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), and combinations thereof.

[0081] In some embodiments, the first cleaning chemical solution, the second cleaning chemical solution and the third cleaning chemical solution each comprise hydrofluoric acid (HF) with a volume concentration of 0.02% to 20% and water with a volume concentration of 60% to 99.8%.

[0082] In some embodiments, the first cleaning chemical solution includes hydrofluoric acid (HF) with a volume concentration of 0.02% to 0.5%; water (H2O) with a volume concentration of 94.5% to 99.88%; and an acidic pH adjuster including hydrogen chloride (HCl) with a volume concentration of 0.1% to 5.0%. The pH value of the first cleaning chemical solution is between 1 and 6, and the solution temperature is between 25°C and 80°C.

[0083] In some embodiments, the first cleaning chemical solution comprises hydrofluoric acid (HF) with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 30°C and 70°C; the second cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 20°C and 25°C; and the third cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 2.5 and 4.0, and a solution temperature between 20°C and 25°C.

[0084] In another example aspect, this disclosure provides a method of manufacturing a semiconductor structure, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and are interleaved with each other in the stack; forming a dummy gate structure on the stack; forming gate spacers on the sidewalls of the dummy gate structure; etching source / drain regions of the stack to form source / drain trenches; selectively removing the stacked second semiconductor layer in the source / drain trenches to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; performing a first etching process on the first dielectric material to form a dielectric interposer between the first semiconductor layers; performing a first cleaning process using a first cleaning chemical solution; performing a second etching process to laterally etch the dielectric interposer to form a second gap between the first semiconductor layers; and performing a second cleaning process using a second cleaning chemical solution, the second cleaning chemical solution being different from the first cleaning chemical solution.

[0085] In some other embodiments, the first cleaning chemical solution and the second cleaning chemical solution each include hydrofluoric acid with a volume concentration of 0.02% to 20%, water (H2O) with a volume concentration of 60% to 99.8%, and one of an alkaline pH adjuster and an acidic pH adjuster; and the first cleaning chemical solution includes a first solution temperature, and the second cleaning chemical solution includes a second solution temperature lower than the first solution temperature.

[0086] In some other embodiments, the first cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 30°C and 70°C; and the second cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 20°C and 25°C.

[0087] In some other embodiments, it further includes: depositing a second dielectric material to fill the second gap; performing a third etching process on the second dielectric material; and performing a third cleaning process using a third cleaning chemical solution, wherein the first dielectric material and the second dielectric material have different compositions, and wherein the third cleaning chemical solution includes hydrofluoric acid and water.

[0088] In some other embodiments, the first dielectric material comprises silicon oxide, and the second dielectric material comprises silicon nitride.

[0089] In some other embodiments, the third cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 2.5 and 4.0, and a solution temperature between 20°C and 25°C.

[0090] In some other embodiments, the first cleaning chemical solution and the second cleaning chemical solution each include hydrofluoric acid with a volume concentration of 0.02% to 20%, water with a volume concentration of 60% to 99.8%, and one of an alkaline pH adjuster and an acidic pH adjuster; and the second pH value of the second cleaning chemical solution is greater than the first pH value of the first cleaning chemical solution.

[0091] In some other embodiments, the first cleaning chemical solution includes a first solution temperature, and the second cleaning chemical solution includes a second solution temperature lower than the first solution temperature.

[0092] In some other embodiments, the temperature of the first solution is between 30°C and 70°C; and the temperature of the second solution is between 20°C and 25°C.

[0093] In another example aspect, this disclosure provides a method of manufacturing a semiconductor structure, comprising: forming a stack on a semiconductor substrate, the stack including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and are interleaved with each other in the stack; forming a dummy gate structure on the stack; forming gate spacers on the sidewalls of the dummy gate structure; etching source / drain regions of the stack to form source / drain trenches; selectively removing the second semiconductor layer of the stack to form a first gap between the first semiconductor layers; depositing a first dielectric material to fill the first gap; performing a first etching process on the first dielectric material to form a dielectric interposer between the first semiconductor layers; performing a first cleaning process using a first cleaning chemical solution having a first pH value; performing a second etching process to laterally etch the dielectric interposer to form a second gap between the first semiconductor layers; and performing a second cleaning process using a second cleaning chemical solution having a second pH value different from the first pH value, wherein the first cleaning chemical solution and the second cleaning chemical solution each include hydrofluoric acid (HF) and a pH adjuster.

[0094] In yet another example aspect, this disclosure provides a semiconductor structure comprising: a substrate having a top surface; an active region on the substrate; an insulating structure surrounding the active region; a plurality of channels stacked perpendicularly to each other in the active region on the substrate; a first source / drain (S / D) component and a second source / drain component inserted into and connecting each of the channels; and a gate stack disposed on the channels and extending to surround each of the channels, wherein each of the channels includes an edge portion having a top surface at an angle α to the top surface of the substrate, and wherein the angle α is between 0.1 degrees and 10 degrees.

[0095] In some other embodiments, each of the channels includes a main portion having a first thickness T1; an edge portion having a second thickness T2; and the difference between the first thickness T1 and the second thickness T2 is less than 2 nanometers.

[0096] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0007] The various aspects of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the units may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure. According to some embodiments of this disclosure, Figures 1A, 1B, and 1C are flowcharts of exemplary methods for manufacturing embodiments of the GAA device. According to some embodiments of this disclosure, Figures 2A to 6A and 8A to 16A are top views of embodiments of the GAA device of this disclosure constructed at various manufacturing stages. According to some embodiments of this disclosure, Figures 2B to 6B and 8B to 16B are cross-sectional views of embodiments of the GAA device of this disclosure along line A-A' in Figures 2A to 6A and 8A to 16A, respectively. According to some embodiments of this disclosure, Figures 2C to 6C and 8C to 16C are cross-sectional views of embodiments of the GAA device of this disclosure along line B-B' in Figures 2A to 6A and 8A to 16A, respectively. According to some embodiments of this disclosure, Figures 2D to 6D and 8D to 16D are cross-sectional views along line C-C' in Figures 2A to 6A and 8A to 16A, respectively, of embodiments of the GAA device of this disclosure. According to some embodiments of this disclosure, Figures 7A to 7I are cross-sectional views of example methods for manufacturing various embodiments of the GAA device. According to some embodiments of this disclosure, Figure 7J shows a table of cleaning chemical solutions.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A stack is formed on a semiconductor substrate, the stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and are interleaved in the stack; a dummy gate structure is formed on the stack; a gate spacer is formed on a plurality of sidewalls of the dummy gate structure; a plurality of source / drain regions of the stack are etched to form a plurality of source / drain trenches; the second semiconductor layers of the stack are selectively removed to form a plurality of first gaps between the first semiconductor layers; a first dielectric material is deposited to fill the first gaps; a first etching process is performed on the first dielectric material to form a plurality of dielectric interposers between the first semiconductor layers; a first cleaning process is performed using a first cleaning chemical solution; a second etching process is performed to laterally etch the dielectric interposers to form a plurality of second gaps between the first semiconductor layers; a second cleaning process is performed using a second cleaning chemical solution. A plurality of inner spacers of a second dielectric material are formed in the second gaps; and a third cleaning process is performed using a third cleaning chemical solution, wherein the composition of the first dielectric material and the second dielectric material is different, and the first cleaning chemical solution, the second cleaning chemical solution and the third cleaning chemical solution each include hydrofluoric acid and water.

2. The method of manufacturing a semiconductor structure as described in claim 1, wherein forming the inner spacers in the second gaps further comprises: Deposit the second dielectric material to fill the second gaps; And perform a third etching process on the second dielectric material.

3. The method of manufacturing a semiconductor structure as described in claim 1, wherein the first dielectric material comprises silicon oxide and the second dielectric material comprises silicon nitride.

4. The method of manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein the first cleaning chemical solution, the second cleaning chemical solution and the third cleaning chemical solution each further include a pH adjuster.

5. The method of manufacturing a semiconductor structure as described in claim 4, wherein the pH adjuster comprises an alkaline pH adjuster having ammonium hydroxide (NH4OH).

6. The method of manufacturing a semiconductor structure as described in claim 4, wherein the pH adjuster comprises an acidic pH adjuster having at least one of hydrogen chloride (HCl), phosphoric acid (H3PO4), sulfuric acid (H2SO4), and combinations thereof.

7. A method for manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein the first cleaning chemical solution, the second cleaning chemical solution, and the third cleaning chemical solution each comprise hydrofluoric acid (HF) at a volume concentration of 0.02% to 20% and water at a volume concentration of 60% to 99.8%.

8. A method for manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein the first cleaning chemical solution comprises hydrofluoric acid (HF) with a volume concentration of 0.02% to 0.5%; water (H2O) with a volume concentration of 94.5% to 99.88%; and an acidic pH adjuster comprising hydrogen chloride (HCl) with a volume concentration of 0.1% to 5.0%, the pH value of the first cleaning chemical solution being between 1 and 6, and the solution temperature being between 25°C and 80°C.

9. A method for manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein: The first cleaning chemical solution comprises hydrofluoric acid (HF) with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 30°C and 70°C; the second cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 0.5 and 1.5, and a solution temperature between 20°C and 25°C; and the third cleaning chemical solution comprises hydrofluoric acid with a volume concentration of 0.02% to 1%, a pH value between 2.5 and 4.0, and a solution temperature between 20°C and 25°C.

10. A method for manufacturing a semiconductor structure, comprising: A stack is formed on a semiconductor substrate, the stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and are interleaved in the stack; a dummy gate structure is formed on the stack; a gate spacer is formed on a plurality of sidewalls of the dummy gate structure; a plurality of source / drain regions of the stack are etched to form a plurality of source / drain trenches; the second semiconductor layers of the stack in the source / drain trenches are selectively removed to form a plurality of first gaps between the first semiconductor layers; a first dielectric material is deposited to fill the first gaps; a first etching process is performed on the first dielectric material to form a plurality of dielectric interposers between the first semiconductor layers; a first cleaning process is performed using a first cleaning chemical solution; Perform a second etching process to laterally etch the dielectric interposers to form a plurality of second gaps between the first semiconductor layers; and perform a second cleaning process using a second cleaning chemical solution, which is different from the first cleaning chemical solution.

11. A method for manufacturing a semiconductor structure as described in claim 10, wherein: The first cleaning chemical solution and the second cleaning chemical solution each comprise hydrofluoric acid with a volume concentration of 0.02% to 20%, water with a volume concentration of 60% to 99.8%, and one of an alkaline pH adjuster and an acidic pH adjuster; and a second pH value of the second cleaning chemical solution is greater than a first pH value of the first cleaning chemical solution.

12. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein the first cleaning chemical solution includes a first solution temperature, and the second cleaning chemical solution includes a second solution temperature lower than the first solution temperature.

13. A method for manufacturing a semiconductor structure as described in claim 12, wherein: The temperature of the first solution is between 30°C and 70°C; and the temperature of the second solution is between 20°C and 25°C.

14. A semiconductor structure comprising: A substrate having a top surface; An active region is located on the substrate; An insulating structure surrounds the active region; A plurality of channels are stacked perpendicularly to each other on the substrate in the active region; a first source / drain (S / D) component and a second source / drain component are inserted into and connected to each of the channels; and a gate stack is disposed on the channels and extends to surround each of the channels, wherein each of the channels includes an edge portion having a top surface at an angle α to the top surface of the substrate, and wherein the angle α is between 0.1 degrees and 10 degrees.

15. The semiconductor structure as described in claim 14, wherein: Each of these channels includes a main portion having a first thickness T0; an edge portion having a second thickness T1; and the difference between the first thickness T0 and the second thickness T1 is less than 2 nanometers.

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