Package structure

Abstract

The packaging structure disclosed herein includes a packaging substrate, a packaging element bonded to the packaging substrate and including a plurality of chips, a cover disposed above the packaging element and the packaging substrate, and a thermal interface material layer sandwiched between the packaging element and the cover. The cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the thermal interface material layer.

Description

[Technical Field]

[0001] This disclosure relates to a packaging structure, and more particularly to a packaging structure including a cover having a heat sink pattern extending to a thermal interface material layer. [Previous Technology]

[0002] In some three-dimensional integrated circuits (3DICs), device chips are bonded to a package substrate to form a package. The heat generated by the device chips during operation needs to be dissipated to prevent performance degradation or even physical damage. For heat dissipation, a metal cover can be bonded to the package substrate to hold the device chips. Device chips may warp due to temperature changes. Warping can stress the bond between the device and the metal cover. [Summary of the Invention]

[0003] This disclosure provides a packaging structure including a packaging substrate, a packaging element bonded to the packaging substrate and including a plurality of dies, a cover disposed above the packaging element and the packaging substrate, and a thermal interface material layer sandwiched between the packaging element and the cover. The cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the thermal interface material layer.

[0004] This disclosure provides a packaging structure including a packaging substrate and a packaging element. The packaging element includes an interposer layer bonded to the top surface of the packaging substrate and a plurality of dies bonded to the top surface of the interposer layer. The packaging structure includes a metal frame disposed on the packaging substrate and surrounding the interposer layer, a thermal interface material layer disposed on the packaging element, and a cover disposed above the packaging element, the metal frame, and the packaging substrate.

[0005] This disclosure provides a packaging structure including a packaging substrate, a packaging element bonded to the packaging substrate and including a plurality of dies, a metal frame disposed on the packaging substrate and surrounding the packaging element, a cover disposed above the packaging element, the packaging substrate and the metal frame, and a thermal interface material layer sandwiched between the packaging element and the cover. The cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the thermal interface material layer.

Implementation Method

[0007] The following disclosure provides many different embodiments or examples to implement different features of the embodiments disclosed herein. Reference numerals and / or letters may be repeated in the various examples described in this disclosure. These repetitions are for the purpose of brevity and clarity and do not in themselves represent any relationship between the various embodiments and / or configurations disclosed. In addition, specific examples of components and configurations are described below to simplify the description of the embodiments disclosed herein. Of course, these specific examples are merely illustrative and are not intended to limit the embodiments disclosed herein. For example, in the following description, it is mentioned that a first feature is formed on or above a second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, or it may include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetitions are for the purpose of brevity and clarity and do not in themselves represent any relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatial terms may be used herein. For example, terms such as "below," "under," "lower," "above," "higher," and similar terms are used to describe the relationship between one element or feature depicted in the diagram and another element(s). In addition to the orientation shown in the diagram, these spatial terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial terms used herein may be interpreted in the same way.

[0009] Furthermore, when terms such as "about" or "approximately" are used to describe numbers or ranges of numbers, these terms are intended to cover numbers that are within a reasonable range, taking into account variations during the manufacturing process, as understood by those skilled in the art to which this application pertains. For example, based on known manufacturing tolerances for manufacturing features having characteristics associated with this number, the number or range of numbers covers a reasonable range including said number, such as within + / -15% of said number. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, wherein the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to which this application pertains as + / -15%.

[0010] Semiconductor packaging technology was once considered merely a back-end process for connecting chips to external circuits. This is no longer the case. Computational workloads have grown so rapidly that packaging technology has become the forefront of innovation. Modern packaging integrates multiple chips or dies into a single semiconductor device. Depending on the stacking hierarchy, modern semiconductor packages can have 2.5D or 3D structures. In a 2.5D structure, at least two dies are coupled to a redistribution layer (RDL) structure or interposer that provides inter-chip communication. In a 2.5D structure, at least two dies are not stacked vertically, and the RDL structure or interposer is bonded to the package substrate. In a 3D structure, at least two dies are stacked together and interact through through silicon vias (TSVs). Depending on the process used, 2.5D and 3D structures can have integrated fan-out (InFO) structures or chip-on-wafer-on-substrate (CoWoS®) structures. To provide additional structural integration and improve heat dissipation, a metal cap can be attached to the package structure. Because the thermal expansion coefficient of the package substrate is much greater than that of the metal cap, the metal cap and package substrate may warp differently during heating cycles. This warping difference can stress the bonding interface between the package structure and the metal cap. For example, thermal interface material (TIM) may be present at the interface. When the bonding fails, the TIM may experience a loss of coverage, thereby interrupting heat dissipation and reducing thermal efficiency. This failure may be more likely to occur when the semiconductor package undergoes environmental testing (e.g., humidity sensitivity rating testing).

[0011] This disclosure provides a packaging structure that reduces or minimizes warpage differences between a metal cap and a packaging substrate. In some examples, the heat sink of the metal cap at the die boundary includes a broken protruding pattern. The broken protruding pattern provides greater flexibility to the metal cap. In some examples, a metal frame is formed on the packaging substrate to surround the die. The metal frame may include a plurality of guide pins that partially extend into the packaging substrate and provide greater rigidity to the packaging substrate. In some other examples, the packaging structure according to this disclosure includes a split protruding pattern and a metal frame to further control warpage differences between the metal cap and the packaging substrate.

[0012] Various embodiments of the present disclosure will now be described in more detail with reference to the figures. For this purpose, Figure 1 illustrates a flowchart of a method 1000 for forming an encapsulation structure on a work-in-progress (WIP) structure 200 (as shown in Figures 2 through 14) according to various embodiments of the present disclosure. Method 1000 is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in method 1000. Additional steps may be provided before, during, and after method 1000, and some steps may be replaced, deleted, or moved for other embodiments of this method. For brevity, not all steps are described in detail in this disclosure. Method 1000 is described below with reference to Figures 2 through 14, which are partial sectional and top views of the WIP structure 200 at different manufacturing stages according to various embodiments of method 1000. Since the WIP structure 200 will be manufactured as an encapsulation structure, the WIP structure 200 may be referred to as encapsulation structure 200 in this disclosure as needed by the context. To avoid confusion, the X, Y, and Z directions in Figures 2 through 14 and Figures 15 through 19 are perpendicular to each other. Throughout this disclosure, unless otherwise explicitly stated, the same reference numerals denote the same features.

[0013] Referring to Figures 1, 2, and 3, method 1000 includes block 1002, wherein a package element 300 is bonded to a front surface 202F of a package substrate 202. Figure 2 illustrates a top view of the package element 300 located above the package substrate 202. Figure 3 illustrates a cross-sectional view along section A-A' in Figure 2. In some embodiments, the package substrate 202 may include a printed circuit board (PCB) or the like, which may include glass fiber reinforced epoxy (FR-4), polytetrafluoroethylene (PTFE), and metal traces. Referring to Figure 3. For electrical coupling to the package element 300, the package substrate 202 may include a plurality of contact pads located above the front surface 202F. For electrical coupling to solder features on the back surface 202B, the package substrate 202 may also include a plurality of contact pads located on the back surface 202B. Package element 300 is a multi-die package (or multi-chip package) that may include more than one device die. A device die may also be referred to as a die or chip. In the embodiments shown in Figures 2 and 3, package element 300 includes multiple high bandwidth memory (HBM) dies 220 and multiple system-on-chip (SoC) dies 230. In some other embodiments, package element 300 may alternatively or additionally include logic dies or application-specific integrated circuit (ASIC) dies. In some cases, each SoC die 230 is connected to two HBM dies 220. In some embodiments shown in Figure 2, each HBM die 220 and SoC die 230 is bonded to an interposer layer 210 via a plurality of microbumps 212. The space between the interposer layer 210 and each HBM die 220 and SoC die 230 may be filled with a first underfill 214. The HBM die 220 and SoC die 230 are disposed side-by-side above the interposer layer 210. To provide structural integration and improve stress absorption, the upper edge of the package element 300 is surrounded by a molding compound 216. The space between the HBM die 220 and SoC die 230 may be filled with a first underfill 214. The molding compound 216 may also be referred to as the package layer 216. The package element 300 further includes a plurality of connection features 206 for connection to the package substrate 202. In some embodiments, the plurality of connection features 206 may include controlled collapse chip connection (C4) bumps or other solder bumps.As shown in Figure 3, the space between the package element 300 and the front surface 202F of the package substrate 202 can be filled with a second underfill 208. In some embodiments shown in Figure 2, the second underfill 208 may surround the sidewall of the interposer layer 210.

[0014] HBM is a computer memory interface typically used in conjunction with high-performance graphics accelerators, high-performance data centers, ASICs for artificial intelligence (AI) applications, packaged cache memory in central processing units (CPUs), or high-performance computing ICs. HBM dies 220 may include vertically stacked dynamic random access memory (DRAM) dies. In some cases, an HBM die may include 2 to 10 DRAM dies stacked together. Vertical stacking allows for higher bandwidth, lower power consumption, and smaller form factor. HBM has been accepted as an industry standard. To date, there have been three generations: HBM1, HBM2, and HBM3. The fourth generation (HBM4) will be released by the end of 2024. HBM dies 220 include HBM dies that conform to all current and future generations of HBM standards. The SoC die 230 may include a memory controller that connects the HBM die 220 to a graphics processing unit (GPU), a central processing unit (CPU), or a neural processing unit (NPU). The memory controller is typically built into the SoC die 230, which is why the SoC die 230 is referred to as a "system-on-a-chip."

[0015] Interposer 210 may include a semiconductor material or glass. In some embodiments, interposer 210 includes silicon (Si). In some alternative embodiments, interposer 210 includes silicon germanium (SiGe) or silicon carbon (SiC). Each of HBM die 220 and SoC die 230 may include a plurality of transistors, such as planar transistors, fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, nanowire transistors, nanosheet transistors, or other multi-gate transistors. First underfill 214 and second underfill 208 may include polymers or epoxy resins. Molding compound 216 may include a substrate and fillers embedded in the substrate. In some embodiments, the substrate of molding compound 216 may include polymers, resins, or epoxy resins, and the fillers may include spherical particles of silicon oxide (silicon dioxide) or aluminum oxide.

[0016] Referring to Figure 2, a top view of the package element 300 is provided. In some embodiments shown in Figure 2, the space between the HBM die 220 and the SoC die 230 may be filled with a first underfill 214, and the upper portion of the package element 300 may be surrounded by a molding compound 216. Each of the HBM die 220 and the SoC die 230 may have a flip-chip configuration, with the back side of its device substrate or carrier substrate exposed on the top surface of the package element 300. In some embodiments, the device substrate or carrier substrate may include silicon (Si). In this way, different materials may be exposed on the top surface of the package element 300. The molding compound 216 exposed on the top surface of the package element 300 may include a polymer, resin, epoxy resin, silicon oxide (silicon dioxide), aluminum oxide, or a combination thereof. The first underfill 214 exposed on the top surface of the package element 300 may include a polymer or epoxy resin. The package element 300 includes a die width (DW) along the X direction and a die length (DL) along the Y direction.

[0017] In block 1002, the packaged element 300 is placed above the packaged substrate 202 such that the connection feature 206 is perpendicularly aligned with the contact pad on the front surface 202F of the packaged substrate 202. A reflow process is performed such that the connection feature 206 electrically couples the interposer 210 of the packaged element 300 to the packaged substrate 202. After the reflow process, a liquid precursor of the second underfill 208 is allowed to fill the gap between the interposer 210 and the front surface 202F of the packaged substrate 202 through capillary action. The packaged substrate 202 and packaged element 300 shown in Figures 2 and 3 can be collectively referred to as work-in-process (WIP) structure 200. During the operation of the various blocks of method 1000, elements can be added to the WIP structure 200, and the resulting structure will continue to be referred to as WIP structure 200 in this disclosure.

[0018] Referring to Figures 1 and 4 through 7, method 1000 includes block 1004, wherein pin holes 402 are formed in a package substrate 202. In some embodiments, laser drilling may be used to form the pin holes 402. As shown in Figure 4, each pin hole 402 may extend to a depth D into the package substrate 202 having a thickness T. The thickness T of the package substrate 202 may be between about 0.2 mm and about 3.2 mm. In some embodiments, the ratio of depth D to thickness T may be between about 0.1 and about 0.9. This range is not meaningless. When the ratio is less than 0.1, the pin hole 402 is too shallow to provide mechanical anchoring for the metal frame to be mounted. When the ratio is greater than 0.9, the pin hole 402 may expose conductive features near the back surface 202B of the package substrate 202, thereby increasing the risk of electrical short circuits. It should be noted that none of the pin holes 402 expose any conductive features of the package substrate 202. Since the pin hole 402 will be used to insert a guide pin into a metal frame made of conductive material, exposure of conductive features in the pin hole 402 may lead to accidental electrical connections, which in turn may cause device malfunction.

[0019] Referring now to Figures 5 through 7, different pin hole patterns are illustrated. In the embodiment shown in Figure 5, a plurality of pin holes 402 are formed in the package substrate 202 to form a rectangular region surrounding the periphery of the package element 300. As shown in Figure 5, the plurality of pin holes 402 are equidistant from each other along the X and Y directions to surround the package element 300. In the embodiment shown in Figure 6, compared to the embodiment shown in Figure 5, additional corner pin holes (or diagonal pin holes) 402C are formed along the two diagonals of the rectangular shape of the package element 300. As shown in Figure 6, the corner pin holes 402C are closer to the edge of the package substrate 202 to provide mechanical rigidity to the package substrate 202. In the embodiment shown in Figure 7, compared to the embodiment shown in Figure 5, two additional edge-extending pin holes 402E are formed on each edge of the rectangle formed by the pin holes 402. As shown in Figure 7, the edge-extended pin hole 402E is closer to the edge of the package substrate 202, thereby providing mechanical rigidity to the package substrate 202. The pin hole pattern in Figure 5 does not include any corner pin holes 402C shown in Figure 6 or any edge-extended pin holes 402E shown in Figure 7. Although the pin hole pattern in Figure 5 may provide lower mechanical strength, omitting the corner pin holes 402C and edge-extended pin holes 402E allows for the insertion of other components (such as passive components, capacitors, or resistors) or conductive features.

[0020] Referring to Figures 1 and 8 through 11, method 1000 includes block 1006, in which a metal frame 404 is mounted on a package substrate 202 such that guide pins 406 on the metal frame 404 are inserted into pin holes 402. The guide pins 406 are integral parts of the metal frame 404 and extend from the bottom surface of the metal frame 404. In some embodiments, the metal frame 404 and the guide pins 406 are made of aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), or alloys of the aforementioned metals, and can be manufactured using casting or three-dimensional (3D) printing. At block 1006, the metal frame 404 is mounted on the package substrate 202 such that each guide pin 406 is vertically aligned and inserted into the pin hole 402. The insertion of the guide pins 406 into the pin holes 402 mechanically anchors the metal frame 404 to the package substrate 202. Because the coefficient of thermal expansion (CTE) of the metal frame 404 is less than that of the package substrate 202, this mechanical anchoring allows the metal frame 404 to increase the effective CTE of the package substrate 202. In other words, the metal frame 404 reduces the warpage of the package substrate 202 relative to the metal cover, which will be described below. As shown in Figures 8 through 11, the metal frame 404 can include different configurations to accommodate different pin hole configurations. Referring first to Figures 8 and 9, the metal frame 404 includes equally spaced guide pins 406. In Figure 9, when the metal frame 404 is mounted on the package substrate 202, each guide pin 406 is inserted into a pin hole 402. Figure 10 illustrates a first reinforcing metal frame 4042. The first reinforcing metal frame 4042 includes not only the guide pins 406 but also corner guide pins 406C for insertion into corner pin holes 402C shown in Figure 6. Figure 11 illustrates a second reinforcing metal frame 4044. The second reinforcing metal frame 4044 includes not only the guide pin 406 but also the edge extension pin 406E for insertion into the edge extension pin hole 402E shown in Figure 7. As shown in Figure 8, with the guide pin 406 inserted into the pin hole 402, the bottom surface of the metal frame 404 rests on the top surface of the package substrate 202. As shown in Figures 9 through 11, the metal frame 404, or the first reinforcing metal frame 4042 and the second reinforcing metal frame 4044, extends continuously around the package element 300. In some embodiments shown in Figure 8, the height H of the metal frame 404 is such that the top surface of the metal frame 404 is higher than the bottom surface of the interposer 210 but lower than the top surface of the thermal interface material (TIM) layer 410 to be deposited (described below). The metal frame 404 can be said to surround the interposer 210. In some embodiments shown in Figure 8, an adhesive 408 can be applied to the interface between the metal frame 404 and the package substrate 202.In some cases, adhesive 408 may include die attach film (DAF) gel, silicone resin, polyimide (PI), or epoxy resin. When using an adhesive, adhesive 408 may be located between the sidewall of guide pin 406 and the sidewall of pin hole 402.

[0021] Referring again to Figures 9 through 11. As shown in Figure 9, the metal frame 404 has a frame width Fw and is separated from the package element 300 by a spacing S. Each guide pin 406 is cylindrical and has a diameter d. In some embodiments, the frame width Fw is between about 0.03 times and about 0.1 times the smaller of the grain width DW and the grain length DL. The spacing S is about 0.05 times to 0.1 times the frame width Fw. The diameter d of the guide pin 406 is between about 0.3 times and 1 times the frame width Fw. Compared to the metal frame 404, the first reinforcing metal frame 4042 in Figure 10 further includes a diagonal extension forming an angle θ with the X direction. The angle θ may be between about 30º and about 60º, for example, between 40º and about 50º. The relationship between the frame width Fw, the diameter d, and the spacing S applies to the first reinforcing metal frame 4042. Compared to the metal frame 404, the second reinforcing metal frame 4044 in Figure 11 further includes an edge extension forming a zero-degree angle or a 90-degree angle with the X direction. The relationship between the frame width Fw, the diameter d, and the spacing S applies to the second reinforcing metal frame 4044.

[0022] Referring to Figures 1 and 12, method 1000 includes block 1008, in which a thermal interface material (TIM) layer 410 is deposited over packaged element 300. For the purposes of this disclosure, TIM refers to a material placed between an electronic device and a heat sink to improve heat dissipation of the electronic device. Since voids and gaps introduce air into the heat conduction path, and air has low thermal conductivity, one of the functions of TIM is to fill the gaps between the electronic device and the heat sink to reduce voids and gaps. To perform its gap-filling function well, the TIM or its precursor should have reasonable flowability or elasticity. In addition, the TIM should have sufficient thermal conductivity to facilitate heat conduction. Furthermore, the TIM needs to have good stress absorption properties to protect the electronic device and prevent delamination. According to this disclosure, in block 1008, the TIM layer 410 can be applied in gel or liquid form. In some embodiments, the TIM layer 410 may comprise a gallium alloy, zinc oxide (ZnO), or aluminum nitride (AlN). As shown in Figure 12, a dispensing system with a dispensing head 500 is used to deposit a TIM layer 410 over the packaged element 300, including the back side of the HBM die 220 and the SoC die 230. In some embodiments, the TIM layer 410 is disposed on a molding compound 216. In some embodiments, the thickness of the TIM layer 410 may be between about 25 µm and about 60 µm.

[0023] Referring to Figures 1 and 13, method 1000 includes block 1010, in which adhesive 412 is dispensed onto the top surface of encapsulation substrate 202. As described below, method 1000 attaches a metal cap 420 to encapsulation element 300 and encapsulation substrate 202. The metal cap 420 bonds to encapsulation element 300 through TIM layer 410 and to the top surface of encapsulation substrate 202 through adhesive 412. In block 1010, adhesive 412 is selectively deposited on mating regions on the top surface of encapsulation substrate 202. When the metal cap 420 is placed over encapsulation substrate 202, the lower edge of the cap wall of the metal cap 420 will engage with the adhesive 412 in the mating regions. In some embodiments, a dispensing system may be used for selective dispensing of adhesive 412. The dispensing system includes a dispensing head that dispenses or injects adhesive 412 in gel, liquid, or paste form. The stepper of the dispensing system can precisely move the dispensing head above the mating area. In some embodiments, the adhesive 412 may include a grain attachment film (DAF), silicone, polyimide (PI), or epoxy. Since the primary function of the adhesive 412 is bonding, rather than heat dissipation / conduction, the adhesive 412 does not include highly thermally conductive materials such as beryllium oxide, aluminum oxide, zinc oxide, aluminum nitride, hexagonal boron nitride, metals (i.e., silver, copper, tin, or indium), diamond, graphene, carbon nanotubes, or graphite. The mating area surrounds the metal frame 404, as does the adhesive 412.

[0024] Referring to Figures 1 and 13, method 1000 includes block 1012, in which a metal cap 420 is placed over the package element 300 and the package substrate 202 to bond the adhesive 412 and the TIM layer 410. In some embodiments, the metal cap 420 may be formed of a metal or alloy, such as aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), or alloys of the aforementioned metals. Exemplary alloys may include aluminum-copper alloys, iron-nickel alloys, or iron-nickel-cobalt alloys. The metal cap 420 has at least three functions. First, the metal cap 420 acts as a heat sink, dissipating heat from the package element 300 through the TIM layer 410. Second, the metal cap 420 provides structural rigidity to the package substrate 202 to prevent or reduce warpage. Third, the metal cap 420 creates a sealed environment to protect the package element 300. Referring to Figure 13, the metal cover 420 includes a cover top 420T and a cover wall 420W extending downward from the bottom surface of the cover top 420T. In block 1012, the metal cover 420 is placed above the package element 300 and the package substrate 202 such that the bottom edge of the cover wall 420W engages with the adhesive 412 on the package substrate 202, and the bottom surface of the cover top 420T presses against and engages with the TIM layer 410 on the package element 300.

[0025] According to this disclosure, the metal cover 420 also includes protruding patterns 430 extending downward from the bottom surface of the top cover 420T. These protruding patterns 430 have the same composition as the metal cover 420. In some embodiments, the metal cover 420 and the protruding patterns 430 may be manufactured using casting or 3D printing. As shown in Figure 13, when the metal cover 420 is mounted over the encapsulation element 300 and the encapsulation substrate 202, the protruding patterns 430 extend into the TIM layer 410. The protruding patterns 430 integrally form a heat sink to diffuse or distribute heat from the TIM layer 410 to the metal cover 420. In some embodiments shown in Figure 13, the protruding patterns 430 are split, such that the TIM layer 410 may extend between adjacent protruding patterns 430 to contact the bottom surface of the top cover 420T. Since the protruding patterns 430 are used to engage the TIM layer 410 for heat dissipation, the areas of the protruding patterns 430 overlap vertically with the areas of the TIM layer 410. In some embodiments, the protruding pattern 430 (i.e., the heat sink) defines a first rectangular region, while the package element 300 defines a second rectangular region. When the metal cover 420 is mounted over the package element 300 and the package substrate 202, the first rectangular region completely covers the second rectangular region. In some cases, the first rectangular region is about 5% to about 20% larger than the second rectangular region to ensure that the TIM layer 410 fully engages with the protruding pattern 430.

[0026] The protruding pattern 430 can be configured in different ways. Figures 15 to 19 illustrate a first configuration 430-1, a second configuration 430-2, a third configuration 430-3, a fourth configuration 430-4, and a fifth configuration 430-5. It should be understood that the first configuration 430-1, the second configuration 430-2, the third configuration 430-3, the fourth configuration 430-4, and the fifth configuration 430-5 are different implementations of the protruding pattern 430. Referring first to Figure 15, the first configuration 430-1 includes an array of island patterns 440 surrounded by corner patterns 450 and edge patterns 460. Each island pattern 440 is rectangular in the top view. Each corner pattern 450 is L-shaped in the top view. Overall, the first configuration 430-1 has a width W along the X direction and a length L along the Y direction. To ensure complete bonding with the TIM layer 410, the width W is greater than the grain width DW, and the length L is greater than the grain length DL. In some cases, the width W is about 2.5% to about 10% larger than the grain width DW, and the length L is about 2.5% to about 10% larger than the grain length DL. In some embodiments, the island pattern 440, corner pattern 450, and edge pattern 460 are separated by a gap gx along the X direction and by a gap gy along the Y direction. Each gap gx is between about 0.05W and about 0.1W, and each gap gy is between about 0.05L and about 0.1L. The first configuration 430-1 represents a uniformly split and distributed protruding pattern 430.

[0027] Referring now to Figure 16. The second configuration 430-2 does not have the array of island-shaped patterns 440 separated from each other as in the first configuration 430-1 of Figure 15, but instead includes a large pattern 442. The large pattern 442 is surrounded by corner patterns 450 and edge patterns 460. The large pattern 442 is rectangular in top view. The large pattern 442 provides greater structural rigidity to the metal cover 420. Compared to the first configuration 430-1, the large pattern 442 in the second configuration 430-2 reduces the flexibility of the metal cover 420. Overall, the second configuration 430-2 has a width W along the X direction and a length L along the Y direction. To ensure complete bonding with the TIM layer 410, the width W is greater than the grain width DW, and the length L is greater than the grain length DL. In some cases, the width W is about 2.5% to about 10% larger than the grain width DW, and the length L is about 2.5% to about 10% larger than the grain length DL.

[0028] Referring then to Figure 17. The third configuration 430-3 includes a cross-shaped pattern 444, instead of the array of island patterns 440 spaced apart from each other as in the first configuration 430-1 of Figure 15. In the illustrated embodiment, the cross-shaped pattern 444 and the four island patterns 440 together form a rectangular region surrounded by corner patterns 450 and edge patterns 460. The cross-shaped pattern 444 provides greater structural rigidity to the metal cover 420 in both the X and Y directions. Compared to the first configuration 430-1, the cross-shaped pattern 444 in the third configuration 430-3 reduces the flexibility of the metal cover 420. Overall, the third configuration 430-3 has a width W in the X direction and a length L in the Y direction. To ensure complete bonding with the TIM layer 410, the width W is greater than the grain width DW, and the length L is greater than the grain length DL. In some cases, the width W is about 2.5% to about 10% larger than the grain width DW, and the length L is about 2.5% to about 10% larger than the grain length DL.

[0029] Referring to Figure 18. The fourth configuration 430-4 includes a continuous peripheral pattern 462 surrounding the island pattern 440, instead of the split corner pattern 450 and edge pattern 460 as in the first configuration 430-1 of Figure 15. The continuous peripheral pattern 462 forms a closed loop and can act as a dam to confine the TIM layer 410 when the metal cover 420 is installed. The peripheral pattern 462 helps ensure that the fourth configuration 430-4 fully engages the TIM layer 410. Overall, the fourth configuration 430-4 has a width W in the X direction and a length L in the Y direction. To ensure full engagement with the TIM layer 410, the width W is greater than the grain width DW, and the length L is greater than the grain length DL. In some cases, the width W is about 2.5% to about 10% larger than the grain width DW, and the length L is about 2.5% to about 10% larger than the grain length DL.

[0030] Referring to Figure 19. In the fifth configuration 430-5, at least two island patterns 440 are merged to form a larger island pattern, rather than including completely split island patterns 440 as in the first configuration 430-1 of Figure 15. The island patterns are formed in this location such that when the metal cover 420 is installed, the island patterns vertically overlap local hot spots to facilitate better heat dissipation. The island patterns and the remaining island patterns 440 form a rectangular area surrounded by split corner patterns 450 and edge patterns 460. In the illustrated embodiment, the fifth configuration 430-5 includes a first island pattern 446 and a second island pattern 448. The first island pattern 446 is equivalent to two island patterns 440 merged together. The second island pattern 448 is equivalent to three island patterns 440 merged together. Overall, the fifth configuration 430-5 has a width W along the X direction and a length L along the Y direction. To ensure complete bonding with the TIM layer 410, the width W is greater than the grain width DW, and the length L is greater than the grain length DL. In some cases, the width W is about 2.5% to about 10% larger than the grain width DW, and the length L is about 2.5% to about 10% larger than the grain length DL.

[0031] Referring to Figures 1 and 14, method 1000 includes block 1014, in which adhesive 412 and TIM layer 410 are cured. In some embodiments, adhesive 412, TIM layer 410, and adhesive for bonding metal frame 404 are thermosetting. In these embodiments, the WIP structure 200 shown in Figure 14 may undergo an annealing process 10 to cure adhesive 412, TIM layer 410, and adhesive for bonding metal frame 404. In some embodiments, annealing process 10 may include a curing temperature between about 100°C and about 200°C and a curing time between about 1 hour and about 2 hours.

[0032] This disclosure provides numerous embodiments. In some embodiments, this disclosure provides a packaging structure. The packaging structure includes a packaging substrate, a packaging element bonded to the packaging substrate and including a plurality of dies, a cover disposed above the packaging element and the packaging substrate, and a thermal interface material (TIM) layer sandwiched between the packaging element and the cover. The cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the thermal interface material layer.

[0033] In some embodiments, the packaging element further includes an intermediary layer bonded to the packaging substrate, and a plurality of dies are bonded to the intermediary layer.

[0034] In some embodiments, the plurality of dies include high bandwidth memory (HBM) dies and system-on-a-chip (SoC) dies.

[0035] In some embodiments, the package element includes a first rectangular region, a plurality of heat sink patterns define a second rectangular region, and the second rectangular region vertically overlaps the first rectangular region.

[0036] In some embodiments, the cover and the plurality of heat sink patterns include aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co) or alloys of the aforementioned metals.

[0037] In some embodiments, the TIM layer comprises a gallium alloy, aluminum nitride, or zinc oxide.

[0038] In some embodiments, the packaging structure further includes a metal frame disposed above the packaging substrate and extending continuously around the packaging element.

[0039] In some embodiments, the metal frame includes a plurality of guide pins extending into the package substrate.

[0040] In some embodiments, the metal frame is covered by a cover.

[0041] In some embodiments, the metal frame includes aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), or alloys thereof.

[0042] In other embodiments, this disclosure provides a packaging structure. The packaging structure includes a packaging substrate and a packaging element. The packaging element includes an interposer layer bonded to a top surface of the packaging substrate and a plurality of dies bonded to the top surface of the interposer layer. The packaging structure includes a metal frame disposed on the packaging substrate and surrounding the interposer layer, a thermal interface material (TIM) layer disposed on the packaging element, and a cover disposed above the packaging element, the metal frame, and the packaging substrate.

[0043] In some embodiments, the cover includes a cover top and cover walls extending downward along the periphery of the cover top. The bottom surface of the cover top is bonded to the TIM layer, and the cover walls surround the encapsulation element, the metal frame, and the TIM layer.

[0044] In some embodiments, the bottom surface of the cover wall is bonded to the encapsulation substrate through an adhesive.

[0045] In some embodiments, the metal frame includes a plurality of guide pins extending into the package substrate.

[0046] In some embodiments, the cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the TIM layer.

[0047] In some embodiments, the cover and the plurality of heat sink patterns include aluminum (Al), copper (Cu), iron (Fe), nickel (Ni), cobalt (Co) or alloys thereof.

[0048] In other embodiments, this disclosure provides a packaging structure. The packaging structure includes a packaging substrate, a packaging element bonded to the packaging substrate and including a plurality of dies, a metal frame disposed on the packaging substrate and surrounding the packaging element, a cover disposed above the packaging element, the packaging substrate and the metal frame, and a thermal interface material (TIM) layer sandwiched between the packaging element and the cover. The cover includes a plurality of heat sink patterns extending from the bottom surface of the cover to the TIM layer.

[0049] In some embodiments, the metal frame includes a plurality of guide pins extending into the packaging substrate.

[0050] In some embodiments, the packaging substrate includes a plurality of contact features, and the plurality of guide pins are insulated from the plurality of contact features.

[0051] In some embodiments, the TIM layer comprises a gallium alloy, aluminum nitride, or zinc oxide.

[0052] The features of many embodiments have been summarized above to enable those skilled in the art to better understand the various embodiments of this disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments of this disclosure without departing from the spirit and scope of the appended claims. [Simplified Explanation of the Diagram]

[0006] The concepts of the embodiments disclosed herein will be better understood by referring to the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings. Figure 1 illustrates a flowchart of a method for manufacturing a package structure according to various embodiments of the present disclosure. Figures 2 through 14 illustrate partial sectional or top views of a work-in-progress (WIP) structure performing the various steps of the method in Figure 1 according to various embodiments of the present disclosure. Figures 15 through 19 illustrate different configurations of protruding patterns according to various embodiments of the present disclosure.

Claims

1. A packaging structure, comprising: One packaging substrate; A packaged element is bonded to the packaged substrate and includes a plurality of dies; A cover is disposed above the package element and the package substrate; a thermal interface material layer is sandwiched between the package element and the cover; and a metal frame is disposed above the package substrate and extends continuously around the package element, wherein the cover includes a plurality of heat sink patterns that extend from a bottom surface of the cover into the thermal interface material layer.

2. The packaging structure of claim 1, wherein the packaging element further includes an intermediary layer bonded to the packaging substrate, and the dies are bonded to the intermediary layer.

3. The package structure as claimed in claim 1, wherein the package element includes a first rectangular region, the heat sink pattern defines a second rectangular region, and the second rectangular region vertically overlaps the first rectangular region.

4. The packaging structure as claimed in claim 1, wherein the cover and the heat sink patterns comprise aluminum, copper, iron, stainless steel, nickel, cobalt, or an alloy of aluminum, copper, iron, stainless steel, nickel, and cobalt.

5. The packaging structure as claimed in claim 1, wherein the thermal interface material layer comprises gallium alloy, aluminum nitride, or zinc oxide.

6. The packaging structure of claim 1, wherein the metal frame includes a plurality of guide pins extending into the packaging substrate.

7. The encapsulation structure as claimed in claim 1, wherein the metal frame is covered by the cover.

8. The packaging structure as claimed in claim 1, wherein the metal frame comprises aluminum, copper, iron, stainless steel, nickel, cobalt, or an alloy of aluminum, copper, iron, stainless steel, nickel, and cobalt.

9. A packaging structure, comprising: One packaging substrate; A package element includes: an interposer bonded to a top surface of the package substrate; and a plurality of dies bonded to a top surface of the interposer; a metal frame disposed on the package substrate, surrounding the interposer and extending continuously around the package element; a thermal interface material layer disposed on the package element; and a cover disposed above the package element, the metal frame, and the package substrate.

10. The encapsulation structure as claimed in claim 9, wherein the cover comprises: The top of the cover; and a cover wall extending downward along the periphery of the top of the cover, wherein a bottom surface of the top of the cover is joined to the thermal interface material layer, wherein the cover wall surrounds the encapsulation element, the metal frame and the thermal interface material layer.

11. A packaging structure, comprising: One packaging substrate; A packaged element, bonded to the packaged substrate and comprising a plurality of dies; A metal frame is disposed on the packaging substrate and extends continuously around the packaging element; a cover is disposed above the packaging element, the packaging substrate and the metal frame; and a thermal interface material layer is sandwiched between the packaging element and the cover, wherein the cover includes a plurality of heat sink patterns extending from a bottom surface of the cover to the thermal interface material layer.

12. The packaging structure of claim 11, wherein the metal frame includes a plurality of guide pins extending into the packaging substrate, the packaging substrate including a plurality of contact features, and the guide pins being insulated from the contact features.

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