Test device and test method thereof

Abstract

A testing apparatus and a testing method thereof are proposed. The testing apparatus includes multiple connecting lines, multiple first testing circuits, and multiple second testing circuits. The multiple first testing circuits generate multiple detection signals based on multiple first test data, and transmit the multiple detection signals to the multiple connecting lines respectively. The multiple second testing circuits receive the multiple detection signals through the multiple connecting lines, and compare the multiple second test data with the multiple detection signals to generate multiple test results.

Description

Technical Field

[0001] This invention relates to a connection testing technique, and more particularly to a testing apparatus and testing method thereof. Prior Technology

[0002] In modern packaging technology, chips typically communicate and transmit data through numerous interconnects. Generally, these interconnects consist of internal metal wires and bonding interfaces.

[0003] However, during the packaging process, the interface of the interconnects between wafers is susceptible to thermomechanical stress, leading to defects such as short circuits and open circuits. Short circuit defects in the interconnects can cause bridging faults. In such cases, the operational quality of the wafers will be affected by these defects.

[0004] Therefore, how to enable chips to effectively self-test or detect abnormal interconnects in inter-chip interconnects, thereby improving chip operation quality, will be an important issue for those skilled in the art. Summary of the Invention

[0005] The present invention provides a testing device and a testing method thereof, which can compare multiple test data and multiple detection signals through multiple test circuits to generate multiple test results, and detect abnormal interconnects in the interconnects between chips based on these test results, thereby improving the operating quality of the chips.

[0006] The testing apparatus of the present invention includes multiple connecting lines, multiple first testing circuits, and multiple second testing circuits. The multiple first testing circuits are respectively coupled to the multiple connecting lines, and generate multiple detection signals based on multiple first test data, and transmit the multiple detection signals to the multiple connecting lines respectively. The multiple second testing circuits are respectively coupled to the multiple connecting lines, and receive the multiple detection signals through the multiple connecting lines. The multiple second testing circuits compare the multiple second test data with the multiple detection signals to generate multiple test results. The multiple first testing circuits and the multiple second testing circuits are arranged in an N*M matrix, where N and M are positive integers.

[0007] The testing method of the testing device of the present invention includes: providing a plurality of connecting lines; providing a plurality of first testing circuits, and causing the plurality of first testing circuits to generate a plurality of detection signals according to a plurality of first test data, and causing the plurality of detection signals to be transmitted to the plurality of connecting lines respectively; and providing a plurality of second testing circuits, and causing the plurality of second testing circuits to receive the plurality of detection signals through the plurality of connecting lines, and causing the plurality of second testing circuits to compare the plurality of second test data with the plurality of detection signals to generate a plurality of test results, wherein the plurality of first testing circuits and the plurality of second testing circuits are arranged in an N*M matrix, where N and M are positive integers.

[0008] Based on the above, in the testing apparatus and method described in the embodiments of the present invention, the testing apparatus can, in a first testing mode or a second testing mode, determine which of the multiple connection lines is short-circuited to the ground voltage or power supply voltage of the wafer based on multiple test results. Furthermore, in a third testing mode, the testing apparatus can, based on multiple test results, determine which of the multiple connection lines has a fixed or bridging fault. By observing the test output results, it can be determined whether the connection line has a fixed 0 fault, a fixed 1 fault, a wired-AND bridging fault, or a wired-OR bridging fault. In this way, the testing apparatus of the present invention can effectively test abnormal connection lines in the inter-wafer interconnections, thereby improving the operational quality of the wafer. Simple Explanation of the Diagram

[0009] Figures 1A and 1B are schematic diagrams of the connection lines between a first wafer and a second wafer according to an embodiment of the present invention. Figure 2 is a schematic diagram of a test apparatus according to an embodiment of the present invention. Figure 3 is a circuit diagram of a test apparatus according to an embodiment of Figure 2 of the present invention. Figures 4A and 4B are schematic diagrams of the test device shown in Figure 3 of the present invention operating in the first test mode and the second test mode, respectively. Figure 5 is an operation flowchart illustrating the operation of the test device in a first test mode and a second test mode according to an embodiment of the present invention shown in Figures 4A to 4B. Figures 6A to 6D are schematic diagrams of the test apparatus shown in Figure 3 of the present invention operating in the column test phase of the third test mode. Figures 7A to 7D are schematic diagrams of the test apparatus shown in Figure 3 of the present invention operating in the line test phase of the third test mode. Figure 8 is an operation flowchart illustrating the operation of the test apparatus in the column test phase and row test phase of the third test mode according to an embodiment of Figures 6A to 6D and 7A to 7D of the present invention. Figure 9 is a circuit diagram of a test apparatus according to another embodiment of Figure 2 of the present invention. Figure 10 is a flowchart of a test method using a test apparatus according to an embodiment of the present invention. Implementation

[0010] Figures 1A and 1B are schematic diagrams of the connection lines between a first chip DIE1 and a second chip DIE2 according to an embodiment of the present invention. Referring to Figure 1A, in the embodiment of Figure 1A, the first chip DIE1 and the second chip DIE2 can be connected through connection lines and connection points in an interposer, and the interposer can be disposed on a substrate. Furthermore, in the embodiment of Figure 1B, the first chip DIE1 and the second chip DIE2 can also be applied to the testing of connection lines between layers of chips in a 3D IC. The first chip DIE1 can be, for example, a memory controller, and the second chip DIE2 can be, for example, a stacked memory, but the present invention is not limited thereto.

[0011] Specifically, the first chip DIE1 includes multiple test circuits TX11~TX1N (i.e., first test circuits) and multiple test circuits RX11~RX1N (i.e., second test circuits), and the second chip DIE2 includes multiple test circuits TX21~TX2N (i.e., first test circuits) and multiple test circuits RX21~RX2N (i.e., second test circuits). In this embodiment, test circuits TX11~TX1N and TX21~TX2N can serve as transmitters for the chip, and test circuits RX11~RX1N and RX21~RX2N can serve as receivers for the chip.

[0012] For example, the test circuits TX11~TX1N of the first chip DIE1 can be connected to multiple first connection points of the first chip DIE1, and the multiple test circuits RX21~RX2N of the second chip DIE2 can be connected to multiple second connection points of the second chip DIE2. Furthermore, the multiple first connection points of the first chip DIE1 and the multiple second connection points of the second chip DIE2 can be interconnected via multiple connection lines P11~PNM.

[0013] Similarly, the multiple test circuits TX21~TX2N of the second chip DIE2 can be connected to multiple first connection points of the second chip DIE2, and the multiple test circuits RX11~RX1N of the first chip DIE1 can be connected to multiple second connection points of the first chip DIE1. Furthermore, the multiple first connection points of the second chip DIE2 and the multiple second connection points of the first chip DIE1 can be interconnected via multiple connection lines.

[0014] In this way, the first chip DIE1 and the second chip DIE2 can test or detect abnormal interconnects in the inter-chip interconnects through the test circuits TX11~TX1N of the first chip DIE1 and the corresponding test circuits RX21~RX2N of the second chip DIE2, or / and through the test circuits TX21~TX2N of the second chip DIE2 and the corresponding RX11~RX1N of the first chip DIE1, thereby improving the operating quality of the chips.

[0015] Figure 2 is a schematic diagram of a test apparatus 100 according to an embodiment of the present invention. Referring simultaneously to Figures 1A to 2, the test apparatus 100 includes multiple connecting lines P11~PNM, a test circuit array AR1, a column test pattern generator 110, a row test pattern generator 120, and a controller 130. The test circuit array AR1 includes multiple test circuits TX11~TXNM (i.e., first test circuits).

[0016] It is worth mentioning that, in this embodiment, the test circuits TX11~TXNM, column test pattern generator 110, row test pattern generator 120, and controller 130 shown in FIG2 can be, for example, set in the first wafer DIE1 shown in FIG1A and FIG1B, so that these test circuits TX11~TXNM can be tested in the first wafer DIE1. Here, N and M can be positive integers.

[0017] These test circuits TX11~TXNM can be (but are not limited to) arranged in an N*M matrix and configured at the intersections of multiple column test lines RL1~RLN and row test lines CL1~CLM. These test circuits TX11~TXNM can be arranged into multiple test columns TR1~TRN and multiple test rows TC1~TCM. Each of these test circuits TX11~TXNM is coupled to multiple connection lines P11~PNM to perform relevant tests on the corresponding connection lines P11~PNM.

[0018] In this embodiment, the controller 130 is coupled to the column test pattern generator 110, the row test pattern generator 120, and the test circuit array AR1. The controller 130 can receive a start signal ST, a reset signal RST, and a clock signal CLK. The controller 130 can generate a control signal CSTX to the column test pattern generator 110 and the row test pattern generator 120 based on the start signal ST, the reset signal RST, and the clock signal CLK, and generate a mode selection signal MODE to the test circuit array AR1.

[0019] In this embodiment, the column test pattern generator 110 is coupled between the controller 130 and the column test lines RL1~RLN. The column test pattern generator 110 can generate multiple test data TRP1~TRPN to multiple test circuits TX11~TXNM according to the control signal CSTX.

[0020] In this embodiment, the line test pattern generator 120 is coupled between the controller 130 and the line test lines CL1~CLM. The line test pattern generator 120 can generate multiple test data TCP1~TCPM to multiple test circuits TX11~TXNM according to the control signal CSTX.

[0021] In another aspect, in the embodiment of FIG2, the test apparatus 100 further includes a test circuit array AR2, a column test pattern generator 210, a row test pattern generator 220, a controller 230, a shift register 240, and an address decoder 250. The test circuit array AR2 includes multiple test circuits RX11~RXNM (i.e., second test circuits).

[0022] It is worth mentioning that, in this embodiment, the test circuits RX11~RXNM, column test pattern generator 210, row test pattern generator 220, controller 230, shift register 240 and address decoder 250 shown in FIG2 can be, for example, set in the second chip DIE2 shown in FIG1A and FIG1B, so that these test circuits RX11~RXNM can be tested in the second chip DIE2.

[0023] These test circuits RX11~RXNM can be (but are not limited to) arranged in an N*M matrix and configured at the intersections of multiple column test lines RL1~RLN and row test lines CL1~CLM. These test circuits RX11~RXNM can be arranged into multiple test columns TR1~TRN and multiple test rows TC1~TCM. Each of these test circuits RX11~RXNM is coupled to multiple connection lines P11~PNM to perform relevant tests on the corresponding connection lines P11~PNM. These test circuits RX11~RXNM can be connected to test circuits TX11~TXNM through these connection lines P11~PNM.

[0024] In this embodiment, controller 230 is coupled to column test pattern generator 210, row test pattern generator 220, shift register 240, and address decoder 250. Controller 230 can receive start signal ST, reset signal RST, and clock signal CLK. Controller 230 can generate control signal CSRX to column test pattern generator 210, row test pattern generator 220, and address decoder 250 based on start signal ST, reset signal RST, and clock signal CLK.

[0025] In this embodiment, the column test pattern generator 210 is coupled between the controller 230 and the column test lines RL1~RLN. The column test pattern generator 210 can generate multiple test data TAP1~TAPN to multiple test circuits RX11~RXNM according to the control signal CSRX.

[0026] In this embodiment, the row test pattern generator 220 is coupled between the column test pattern generator 210 and the row test lines CL1~CLM. The row test pattern generator 220 can generate multiple test data TBP1~TBPM to multiple test circuits RX11~RXNM according to the control signal CSRX.

[0027] In this embodiment, the address decoder 250 is coupled to the row test pattern generator 220 and multiple test circuits RX11~RXNM. The address decoder 250 can generate multiple control signals Y1~YN to multiple test circuits RX11~RXNM according to the control signal CSRX, so as to control the test circuits on the corresponding test columns to generate test results C[0]~C[P] in sequence.

[0028] In this embodiment, the shift register 240 is coupled between multiple test circuits RX11~RXNM and the controller 230. The shift register 240 can receive the reset signal RST and the clock signal CLK, and according to the reset signal RST and the clock signal CLK, sequentially receive and transmit the test results C[0]~C[P] of the test circuits RX11~RXNM, and output the corresponding test result DOUT to the controller 230.

[0029] Regarding the operation of the test device 100, specifically, in the test device 100 shown in Figure 2, the test circuits TX11~TXNM can generate multiple detection signals DS11~DSNM respectively based on the test data TRP1~TRPN, the test data TCP1~TCPN and the mode selection signal MODE, and transmit these detection signals DS11~DSNM to the connection lines P11~PNM respectively.

[0030] For example, test circuit TX11 can receive mode selection signal MODE, test data TRP1, and test data TCP1. Based on the mode selection signal MODE and the test data TRP1 and TCP1, test circuit TX11 can generate detection signal DS11. Then, test circuit TX11 can transmit detection signal DS11 to the corresponding connection line P11, and through connection line P11, transmit detection signal DS11 to the corresponding test circuit RX11. The operation of the remaining test circuits TX12 to TXNM can be deduced similarly.

[0031] On the other hand, the test circuits RX11~RXNM can receive detection signals DS11~DSNM from the test circuits TX11~TXNM via connection lines P11~PNM respectively. Then, the test circuits RX11~RXNM can compare the test data TAP1~TAPN and the test data TBP1~TBPM with the detection signals DS11~DSNM to generate multiple test results C[0]~C[P] respectively.

[0032] For example, the test circuit RX11 can receive the detection signal DS11 via the corresponding connection line P11, and receive test data TAP1 and test data TBP1 from the column test line RL1 and the row test line CL1, respectively. Then, the test circuit RX11 can compare the detection signal DS11 with the test data TAP1 and TBP1 to generate the test result C[0]. The operation mode of the other test circuits RX12 to RXNM can be deduced by analogy.

[0033] On the other hand, the shift register 240 can sequentially output the test results C[0] to C[P] of the test circuits RX11 to RXNM according to the timing state of the clock signal CLK. In other words, since these test results C[0] to C[P] can respectively correspond to the operating states of multiple connection lines P11 to PNM (for example, test result C[0] can correspond to connection line P11, and test result C[P] can correspond to connection line PNM), the test device 100 can determine or detect which connection line among these connection lines P11 to PNM has an abnormal state from these test results C[0] to C[P], so that the back-end system or circuit can perform corresponding processing for the abnormal connection line.

[0034] Figure 3 is a circuit diagram of a test apparatus 300 according to an embodiment of Figure 2 of the present invention. Referring to Figures 2 and 3 simultaneously, in this embodiment, the test apparatus 300 includes multiple connecting lines P11~P44, a test circuit array AR1, a column test pattern generator 310, a row test pattern generator 320, and a controller 330. The test circuit array AR1 is arranged in a 4*4 matrix and includes multiple test circuits TX11~TX44 (i.e., first test circuits). The test circuit array AR1 has multiple test columns TR11~TR41 and multiple test rows TC11~TC41.

[0035] It is worth mentioning that the operating functions and coupling methods of the test circuits TX11~TX44, column test pattern generator 310, row test pattern generator 320, and controller 330 shown in Figure 3 are the same as or similar to those of the test circuits TX11~TXNM, column test pattern generator 110, row test pattern generator 120, and controller 130 shown in Figure 2. Therefore, the test circuits TX11~TX44, column test pattern generator 310, row test pattern generator 320, and controller 330 shown in Figure 3 can be deduced by referring to the relevant descriptions of the test circuits TX11~TXNM, column test pattern generator 110, row test pattern generator 120, and controller 130 mentioned in Figure 2, and will not be repeated here. In addition, in Figures 2 and 3, the same or similar components or parts can be identified by the same or similar reference numerals.

[0036] Referring to Figure 3, in this embodiment, each of the test circuits TX11 to TX44 in the test circuit array AR1 may include a logic gate LOC1 and a multiplexer MUX. In the embodiment of Figure 3, the logic gate LOC1 may be implemented by an inverse OR gate.

[0037] For ease of explanation, test circuit TX11 is used as an example here; the operation of other test circuits TX12~TX44 can be deduced similarly. For instance, test circuit TX11 includes a logic gate LOC1 and a multiplexer MUX. The first input of logic gate LOC1 receives test data TRP1, and the second input receives test data TCP1. The control terminal of the multiplexer MUX receives the mode selection signal MODE. The first input of the multiplexer MUX is coupled to the output of logic gate LOC1, the second input receives the reference signal FI, and the output is coupled to the corresponding connection line P11.

[0038] Furthermore, in the test circuit TX11 of the test device 300, the logic gate LOC1 can perform an inverse OR operation on the test data TRP1 and TCP1, and output the detection signal DS11 accordingly based on the operation result. Then, the multiplexer MUX can select the transmission of the detection signal DS11 to the corresponding connection line P11 according to the mode selection signal MODE.

[0039] In another aspect, in the embodiment of FIG3, the test apparatus 300 further includes a test circuit array AR2, a column test pattern generator 410, a row test pattern generator 420, a controller 430, a shift register 440, and an address decoder 450. The test circuit array AR2 includes multiple test circuits RX11~RX44 (i.e., second test circuits). The test circuit array AR2 has multiple test columns TR12~TR42 and multiple test rows TC12~TC42.

[0040] It is worth mentioning that the operation functions and coupling methods of the test circuits RX11~RX44, column test pattern generator 410, row test pattern generator 420, controller 430, shift register 440 and address decoder 450 shown in Figure 3 are the same as or similar to the operation functions and coupling methods of the test circuits RX11~RXNM, column test pattern generator 210, row test pattern generator 220, controller 230, shift register 240 and address decoder 250 shown in Figure 2. Therefore, the test circuits RX11~RX44, column test pattern generator 410, row test pattern generator 420, controller 430, shift register 440, and address decoder 450 shown in Figure 3 can be deduced by analogy to the relevant descriptions of the test circuits RX11~RXNM, column test pattern generator 210, row test pattern generator 220, controller 230, shift register 240, and address decoder 250 mentioned in Figure 2, and will not be repeated here. Furthermore, in Figures 2 and 3, the same or similar components or parts can be labeled with the same or similar reference numerals.

[0041] Referring to Figure 3, in this embodiment, each of the test circuits RX11 to RX44 in the test circuit array AR2 may include a logic gate LOC2, a comparator COM, and a buffer BUF. In the embodiment of Figure 3, the logic gate LOC2 may be implemented by an inverse NOR gate, and the comparator COM may be implemented by an inverse mutex (XNOR gate).

[0042] For ease of explanation, test circuit RX11 is used as an example here; the operation of other test circuits RX12 to RX44 can be deduced similarly. For instance, test circuit RX11 includes a logic gate LOC2, a comparator COM, and a buffer BUF. The first input of logic gate LOC2 receives test data TBP1, and the second input receives test data TAP1. The first input of comparator COM is coupled to the corresponding connection line P11, and receives the detection signal DS11 from test circuit TX11 via connection line P11. The second input of comparator COM is coupled to the output of logic gate LOC2. The input of buffer BUF is coupled to the output of comparator COM, and the output of buffer BUF is coupled to shift register 440.

[0043] Furthermore, in the test circuit RX11 of the test device 300, the logic gate LOC2 can perform an inverse OR (NOR) operation on the test data TAP1 and TBP1, and generate an output signal accordingly based on the operation result. Next, the comparator COM can perform an inverse mutual exclusion OR (XNOR) operation on the output signal and the detection signal DS11 to generate a test result C[0] to the buffer BUF. And the buffer BUF can provide the test result C[0] to the shift register 440 according to the control signal Y1.

[0044] On the other hand, in the embodiment of FIG3, the shift register 440 includes multiple D-type flip-flops and multiple multiplexers connected in series. Each D-type flip-flop can sequentially output the test results C[0]~C

[15] of the test circuits RX11~RX44 according to the clock signal CLK and the reset signal RST, and transmit the corresponding test result DOUT to the controller 430.

[0045] Figures 4A and 4B are schematic diagrams of the test device 300 shown in Figure 3 of the present invention operating in the first test mode and the second test mode, respectively. Figure 5 is an operation flowchart illustrating the operation of the test device 300 in the first test mode and the second test mode according to an embodiment of Figures 4A and 4B of the present invention.

[0046] It should be noted that the test apparatus 300 shown in Figures 4A and 4B is the same as or similar to the test apparatus 300 shown in Figure 3. Specifically, Figure 4A illustrates the scenario state of the test circuits TX11~TX44 and RX11~RX44 of the test apparatus 300 when they are operating in the first test mode, while Figure 4B illustrates the scenario state of the test circuits TX11~TX44 and RX11~RX44 of the test apparatus 300 when they are operating in the second test mode.

[0047] In this embodiment, under the first test mode, the test device 300 can determine which of the multiple connection lines P11 to P44 is short-circuited to the ground voltage in the chip based on multiple test results C[0] to C

[15] . Additionally, under the second test mode, the test device 300 can determine which of the multiple connection lines P11 to P44 is short-circuited to the power supply voltage in the chip based on multiple test results C[0] to C

[15] .

[0048] In addition, the testing device 300 can perform the operation of the first test mode according to steps S510 to S530 in FIG5, and the testing device 300 can perform the operation of the second test mode according to steps S610 to S630 in FIG5.

[0049] Please refer to Figures 4A and 5 simultaneously. In the embodiment of Figure 4A, each of the test data TRP1~TRP4, test data TCP1~TCP4, test data TAP1~TAP4, and test data TBP1~TBP4 may include multiple bits.

[0050] In detail, in step S510, when the column test sample generator 310 generates test data TRP1~TRP4 with a logic value of 0000 according to the control signal CSTX and the row test sample generator 320 generates test data TCP1~TCP4 with a logic value of 0000 according to the control signal CSTX, the test circuits TX11~TX44 of the test device 300 can operate in the first test mode.

[0051] In the first test mode, the logic gates LOC1 in these test circuits TX11~TX44 can generate multiple detection signals DS11~DS44 with a logic value of 1 based on the test data TRP1~TRP4 with a logic value of 0000 and the test data TCP1~TCP4 with a logic value of 0000, respectively. Furthermore, the multiplexers MUX in these test circuits TX11~TX44 can select and transmit the multiple detection signals DS11~DS44 with a logic value of 1 to the corresponding connection lines P11~P44 based on the mode selection signal MODE.

[0052] On the other hand, in step S520, when the column test sample generator 410 generates test data TAP1~TAP4 with logic value 1111 according to the control signal CSRX and the row test sample generator 420 generates test data TBP1~TBP4 with logic value 0000 according to the control signal CSRX, the test circuits RX11~RX44 of the test device 300 can operate in the first test mode.

[0053] In the first test mode, the comparators COM in these test circuits RX11~RX44 can receive multiple detection signals DS11~DS44 with a logic value of 1 through the corresponding connection lines P11~P44.

[0054] For ease of explanation, test circuit RX11 is used as an example here, and the operation of the other test circuits RX12 to RX44 can be deduced in the same way. For example, in this embodiment, the logic gate LOC2 of test circuit RX11 can generate an output signal with a logic value of 0 based on the test data TAP1 with a logic value of 1 and the test data TBP1 with a logic value of 0. Then, the comparator COM of test circuit RX11 can generate a test result C[0] with a logic value of 0 based on the output signal with a logic value of 0 and the detection signal DS11 with a logic value of 1.

[0055] It is worth mentioning that in step S530, when the test result C[0] of the test circuit RX11 is a logic value of 0, it means that the test circuit TX11 transmits the detection signal DS11 to the transmission path of the test circuit RX11 through the connection line P11, and the connection line P11 has not experienced an abnormal state so that the detection signal DS11 can be maintained as logic 1.

[0056] In this case, under the first test mode, the test device 300 can test or determine that the corresponding connection line P11 is operating in a normal connection state based on the test result C[0] with a logic value of 0.

[0057] In contrast, as shown in Figure 4A, if the test circuit TX13 transmits the detection signal DS13 to the test circuit RX13 via the connection line P13, and the connection line P13 is in an abnormal state (that is, the connection line P13 is short-circuited with the ground voltage in the chip), causing the logic value of the detection signal DS13 to change from the original logic value 1 to the logic value 0, the test circuit RX13 will generate a test result C with a logic value of 1 based on the detection signal DS13, the test data TAP3 and the test data TBP3[2].

[0058] In this case, the test device 300 can determine that the corresponding connection line P13 is operating in an abnormal connection state based on the test result C[2] with a logic value of 1 (step S530). In other words, in the first test mode, the test device 300 can test or determine that the corresponding connection line P13 is in a short circuit state with the ground voltage in the chip (i.e., a stuck-at-0 fault) based on the test result C[2] with a logic value of 1.

[0059] On the other hand, referring to both Figures 4B and 5, in the embodiment of Figure 4B, each of the test data TRP1~TRP4, test data TCP1~TCP4, test data TAP1~TAP4, and test data TBP1~TBP4 may include multiple bits.

[0060] In detail, in step S610, when the column test sample generator 310 generates test data TRP1~TRP4 with logic value 0000 according to the control signal CSTX and the row test sample generator 320 generates test data TCP1~TCP4 with logic value 1111 according to the control signal CSTX, the test circuits TX11~TX44 of the test device 300 can operate in the second test mode.

[0061] In the second test mode, the logic gates LOC1 in these test circuits TX11~TX44 can generate multiple detection signals DS11~DS44 with a logic value of 0, respectively, based on test data TRP1~TRP4 with a logic value of 0000 and test data TCP1~TCP4 with a logic value of 1111. Furthermore, the multiplexers MUX in these test circuits TX11~TX44 can select and transmit the multiple detection signals DS11~DS44 with a logic value of 0 to the corresponding connection lines P11~P44 based on the mode selection signal MODE.

[0062] On the other hand, in step S620, when the column test sample generator 410 generates test data TAP1~TAP4 with logic value 0000 according to the control signal CSRX and the row test sample generator 420 generates test data TBP1~TBP4 with logic value 0000 according to the control signal CSRX, the test circuits RX11~RX44 of the test device 300 can operate in the second test mode.

[0063] In the second test mode, the comparators COM in these test circuits RX11~RX44 can receive multiple detection signals DS11~DS44 with a logic value of 0 through the corresponding connection lines P11~P44.

[0064] For ease of explanation, test circuit RX11 is used as an example here, and the operation of the other test circuits RX12 to RX44 can be deduced in the same way. For example, in this embodiment, the logic gate LOC2 of test circuit RX11 can generate an output signal with a logic value of 1 based on the test data TAP1 with a logic value of 0 and the test data TBP1 with a logic value of 0. Then, the comparator COM of test circuit RX11 can generate a test result C[0] with a logic value of 0 based on the output signal with a logic value of 1 and the detection signal DS11 with a logic value of 0.

[0065] It is worth mentioning that in step S630, when the test result C[0] of the test circuit RX11 is a logic value of 0, it means that the test circuit TX11 transmits the detection signal DS11 to the transmission path of the test circuit RX11 through the connection line P11, and the connection line P11 has not experienced an abnormal state so that the detection signal DS11 can be maintained as logic 0.

[0066] In this case, under the second test mode, the test device 300 can test or determine that the corresponding connection line P11 is operating in a normal connection state based on the test result C[0] with a logic value of 0.

[0067] In contrast, as shown in Figure 4B, if the test circuit TX13 transmits the detection signal DS13 to the test circuit RX13 via the connection line P13, and the connection line P13 is in an abnormal state (that is, the connection line P13 is short-circuited with the power supply voltage in the chip), causing the logic value of the detection signal DS13 to change from the original logic value 0 to the logic value 1, the test circuit RX13 will generate a test result C with a logic value of 1 based on the detection signal DS13, the test data TAP3 and the test data TBP3[2].

[0068] In this case, the test device 300 can determine that the corresponding connection line P13 is operating in an abnormal connection state based on the test result C[2] with a logic value of 1 (step S630). In other words, in the second test mode, the test device 300 can test or determine that the corresponding connection line P13 is in a short circuit state with the power supply voltage in the chip (i.e., a stuck-at-1 fault) based on the test result C[2] with a logic value of 1.

[0069] Figures 6A to 6D are schematic diagrams of the test device 300 shown in Figure 3 of the present invention operating in the column test phase of the third test mode. Figures 7A to 7D are schematic diagrams of the test device 300 shown in Figure 3 of the present invention operating in the row test phase of the third test mode. Figure 8 is an operation flowchart illustrating the operation of the test device 300 in the column test phase and row test phase of the third test mode according to an embodiment of Figures 6A to 6D and Figures 7A to 7D of the present invention.

[0070] It should be noted that the test apparatus 300 shown in Figures 6A to 7D is the same as or similar to the test apparatus 300 shown in Figure 3. Figures 6A to 6D illustrate the state of test circuits TX11 to TX44 and RX11 to RX44 of the test apparatus 300 when operating in the column test phase of the third test mode, while Figures 7A to 7D illustrate the state of test circuits TX11 to TX44 and RX11 to RX44 of the test apparatus 300 when operating in the row test phase of the third test mode.

[0071] When operating in the third test mode, the test device 300 can determine which of the multiple connecting lines P11 to P44 has a fixed fault or a bridging fault based on multiple test results C[0] to C

[15] . In addition, the test device 300 can also determine the type of fault of the connecting line based on multiple test results C[0] to C

[15] , such as fixed 0 fault, fixed 1 fault, wired-AND bridging fault, or wired-OR bridging fault.

[0072] In addition, the test device 300 can perform the column test phase operation of the third test mode according to steps S810 to S830 in FIG8, and the test device 300 can perform the row test phase operation of the third test mode according to steps S840 to S860 in FIG8.

[0073] Specifically, in step S810, the column test pattern generator 310 of the test device 300 can sequentially generate test data TRP1~TRP4 with logic values ​​of 1100, 0011, 0101, and 1010 for multiple first test bytes according to the control signal CSTX. Furthermore, the row test pattern generator 320 of the test device 300 can generate test data TCP1~TCP4 with logic value of 0000 according to the control signal CSTX.

[0074] Next, in step S820, the column test pattern generator 410 of the test device 300 can sequentially generate test data TAP1~TAP4 with logic values ​​of 0011, 1100, 1010 and 0101 for a plurality of second test bytes according to the control signal CSRX. Furthermore, the row test pattern generator 420 of the test device 300 can generate test data TBP1~TBP4 with logic value 0000 according to the control signal CSRX.

[0075] Referring to Figure 6A, in the first sub-stage of the column test phase of the third test mode, the column test pattern generator 310 can generate the first byte (i.e., test data TRP1~TRP4) with a logic value of 1100 according to the control signal CSTX to the test circuits TX11~TX44, and the row test pattern generator 320 can generate the test data TCP1~TCP4 with a logic value of 0000 according to the control signal CSTX to the test circuits TX11~TX44.

[0076] Next, the logic gates LOC1 in these test circuits TX11~TX44 can generate multiple detection signals DS11~DS44 respectively based on the test data TRP1~TRP4 and test data TCP1~TCP4. Furthermore, the multiplexers MUX in these test circuits TX11~TX44 can select and transmit these detection signals DS11~DS44 to the corresponding connection lines P11~P44 based on the mode selection signal MODE.

[0077] In the first sub-stage of the column test phase in the third test mode, the test circuits TX11~TX24 on test columns TR11 and TR21 can generate detection signals DS11~DS24, which are logic 0, respectively. Furthermore, the test circuits TX31~TX44 on test columns TR31 and TR41 can generate detection signals DS31~DS44, which are logic 1, respectively.

[0078] On the other hand, in the first sub-stage of the column test phase of the third test mode, the column test pattern generator 410 can generate a second byte (i.e., test data TAP1~TAP4) with a logic value of 0011 according to the control signal CSRX to the test circuits RX11~RX44, and the row test pattern generator 420 can generate test data TBP1~TBP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0079] Next, as shown in Figure 6A, in this embodiment, it is assumed that the connection line P13 is affected by other connection lines, causing the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 to change from the original logic value 0 to the logic value 1. At this time, the test device 300 can determine that the corresponding connection line P13 has an abnormal state (that is, the connection line P13 has a bridging fault) based on the test result C[2] with a logic value of 1.

[0080] Referring to Figure 6B, in the second sub-stage of the column test phase of the third test mode, the column test pattern generator 310 can generate the first byte (i.e., test data TRP1~TRP4) with a logic value of 0011 according to the control signal CSTX and send it to the test circuits TX11~TX44. The row test pattern generator 320 can generate test data TCP1~TCP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0081] In this case, the test circuits TX11~TX24 on test columns TR11 and TR21 can generate detection signals DS11~DS24, which are logic 1 respectively. Furthermore, the test circuits TX31~TX44 on test columns TR31 and TR41 can generate detection signals DS31~DS44, which are logic 0 respectively.

[0082] On the other hand, in the second sub-stage of the column test phase of the third test mode, the column test pattern generator 410 can generate a second byte (i.e., test data TAP1~TAP4) with a logic value of 1100 according to the control signal CSRX to the test circuits RX11~RX44, and the row test pattern generator 420 can generate test data TBP1~TBP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0083] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 1 to the logic value 0. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 0[2].

[0084] It should be noted that, according to the embodiment in Figure 6A, the detection signal DS13 on connection line P13 is mainly interfered with by the detection signals DS31~DS44 with a logic value of 1 on the connection lines P31~P44 of test columns TR32 and TR42 (or TR31 and TR41), causing the detection signal DS13 on connection line P13 to change from logic 0 to logic 1. Furthermore, according to the embodiment in Figure 6B, the detection signal DS13 on connection line P13 is mainly interfered with by the detection signals DS31~DS44 with a logic value of 0 on the connection lines P31~P44 of test columns TR32 and TR42 (or TR31 and TR41), causing the detection signal DS13 on connection line P13 to change from logic 1 to logic 0.

[0085] Therefore, the test device 300 can determine, based on the adjustment of the first byte (or test data TRP1~TRP4) and the second byte (or test data TAP1~TAP4), and according to the change in the detection signal DS13 and the test result C[2], that the connection line P13 will be affected by a connection line P31~P44 on the test columns TR32, TR42 (or TR31, TR41) of the multiple test columns of the test device 300, and thus a bridging fault will occur (step S830).

[0086] Referring to Figure 6C, in the third sub-stage of the column test phase of the third test mode, the column test pattern generator 310 can generate the first byte (i.e., test data TRP1~TRP4) with a logic value of 0101 according to the control signal CSTX and send it to the test circuits TX11~TX44. The row test pattern generator 320 can generate test data TCP1~TCP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0087] In this case, the test circuits TX11~TX14 and T31~T34 on test columns TR11 and TR31 can generate detection signals DS11~DS14 and DS31~DS34, respectively, which are logic 1. Furthermore, the test circuits TX21~TX24 and TX41~TX44 on test columns TR21 and TR41 can generate detection signals DS21~DS24 and DS41~DS44, respectively, which are logic 0.

[0088] On the other hand, in the third sub-stage of the column test phase of the third test mode, the column test pattern generator 410 can generate a second byte (i.e., test data TAP1~TAP4) with a logic value of 1010 according to the control signal CSRX to the test circuits RX11~RX44, and the row test pattern generator 420 can generate test data TBP1~TBP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0089] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 1 to the logic value 0. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 0[2].

[0090] Referring to Figure 6D, in the fourth sub-stage of the column test phase of the third test mode, the column test pattern generator 310 can generate the first byte (i.e., test data TRP1~TRP4) with a logic value of 1010 according to the control signal CSTX and send it to the test circuits TX11~TX44. The row test pattern generator 320 can generate the test data TCP1~TCP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0091] In this case, the test circuits TX11~TX14 and T31~T34 on test columns TR11 and TR31 can generate detection signals DS11~DS14 and DS31~DS34, respectively, which are logic 0. Furthermore, the test circuits TX21~TX24 and TX41~TX44 on test columns TR21 and TR41 can generate detection signals DS21~DS24 and DS41~DS44, respectively, which are logic 1.

[0092] On the other hand, in the fourth sub-stage of the column test phase of the third test mode, the column test pattern generator 410 can generate a second byte (i.e., test data TAP1~TAP4) with a logic value of 0101 according to the control signal CSRX to the test circuits RX11~RX44, and the row test pattern generator 420 can generate test data TBP1~TBP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0093] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 0 to the logic value 1. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 1[2].

[0094] It should be noted that, according to the embodiment in Figure 6C, the detection signal DS13 on connection line P13 is mainly interfered with by the detection signals DS41~DS44 with a logic value of 0 on the connection lines P41~P44 of test column TR42 (or TR41), causing the detection signal DS13 on connection line P13 to change from logic 1 to logic 0. Furthermore, according to the embodiment in Figure 6D, the detection signal DS13 on connection line P13 is mainly interfered with by the detection signals DS41~DS44 with a logic value of 1 on the connection lines P41~P44 of test column TR42 (or TR41), causing the detection signal DS13 on connection line P13 to change from logic 0 to logic 1.

[0095] Therefore, the test device 300 can determine, based on the adjustment of the first byte (or test data TRP1~TRP4) and the second byte (or test data TAP1~TAP4), and according to the change in the detection signal DS13 and the test result C[2], that the connection line P13 will be bridged by a connection line P41~P44 on the test column TR42 (or TR41) of the multiple test columns of the test device 300 (step S830).

[0096] Therefore, based on the examples in Figures 6A to 6D above (steps S810 to S830), the test device 300 of this embodiment can determine that the corresponding connection line P13 is an abnormal connection line based on the test result C[2]. Furthermore, the test device 300 can determine, based on the change in the detection signal DS13 and the test result C[2], that the connection line P13 is experiencing a bridging fault due to a connection line P41 to P44 on the test column TR42 (or TR41) (step S830), and select the test column TR42 (or TR41) as the selected test column.

[0097] Please refer back to Figure 8. In step S840, the row test pattern generator 320 of the test device 300 can sequentially generate test data TCP1~TCP4 with logic values ​​of 0011, 1100, 0101, and 1010 for multiple first test bytes according to the control signal CSTX. Furthermore, the column test pattern generator 310 of the test device 300 can generate test data TRP1~TRP4 with logic value of 0000 according to the control signal CSTX.

[0098] Next, in step S850, the row test pattern generator 420 of the test device 300 can sequentially generate test data TBP1~TBP4 with logic values ​​of 1100, 0011, 1010 and 0101 for multiple second test bytes according to the control signal CSRX. Furthermore, the column test pattern generator 410 of the test device 300 can generate test data TAP1~TAP4 with logic value of 0000 according to the control signal CSRX.

[0099] Referring to Figure 7A, in the first sub-stage of the row test phase of the third test mode, the row test pattern generator 320 can generate the first bit byte (i.e., test data TCP1~TCP4) with a logic value of 0011 according to the control signal CSTX and send it to the test circuits TX11~TX44. The column test pattern generator 310 can generate test data TRP1~TRP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0100] Next, the logic gates LOC1 in these test circuits TX11~TX44 can generate multiple detection signals DS11~DS44 respectively based on the test data TRP1~TRP4 and test data TCP1~TCP4. Furthermore, the multiplexers MUX in these test circuits TX11~TX44 can select and transmit these detection signals DS11~DS44 to the corresponding connection lines P11~P44 based on the mode selection signal MODE.

[0101] In the first sub-stage of the row test phase in the third test mode, multiple test circuits on test rows TC11 and TC21 can generate multiple detection signals of logic 1. Furthermore, multiple test circuits on test rows TC31 and TC41 can generate multiple detection signals of logic 0.

[0102] On the other hand, in the first sub-stage of the row test phase of the third test mode, the row test pattern generator 420 can generate a second byte (i.e., test data TBP1~TBP4) with a logic value of 1100 to the test circuits RX11~RX44 according to the control signal CSRX, and the column test pattern generator 410 can generate test data TAP1~TAP4 with a logic value of 0000 to the test circuits RX11~RX44 according to the control signal CSRX.

[0103] Next, as shown in Figure 7A, in this embodiment, it is assumed that the connection line P13 is affected by other connection lines, causing the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 to change from the original logic value 0 to the logic value 1. At this time, the test device 300 can determine that the corresponding connection line P13 has an abnormal state (i.e., the connection line P13 has a bridging fault) based on the test result C[2] with a logic value of 1.

[0104] Referring to Figure 7B, in the second sub-stage of the row test phase of the third test mode, the row test pattern generator 320 can generate the first byte (i.e., test data TCP1~TCP4) with a logic value of 1100 according to the control signal CSTX to the test circuits TX11~TX44, and the column test pattern generator 310 can generate test data TRP1~TRP4 with a logic value of 0000 according to the control signal CSTX to the test circuits TX11~TX44.

[0105] In this case, the multiple test circuits on test rows TC11 and TC21 can each generate multiple detection signals of logic 0. Furthermore, the multiple test circuits on test rows TC31 and TC41 can each generate multiple detection signals of logic 1.

[0106] On the other hand, in the second sub-stage of the row test phase of the third test mode, the row test pattern generator 420 can generate a second byte (i.e., test data TBP1~TBP4) with a logic value of 0011 according to the control signal CSRX to the test circuits RX11~RX44, and the column test pattern generator 410 can generate test data TAP1~TAP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0107] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 1 to the logic value 0. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 0[2].

[0108] It should be noted that, according to the embodiment in Figure 7A, the detection signal DS13 on connection line P13 is mainly interfered with by multiple detection signals with a logic value of 1 on multiple connection lines of test lines TC12, TC22 (or TC11, TC21), causing the detection signal DS13 on connection line P13 to change from logic 0 to logic 1. Furthermore, according to the embodiment in Figure 7B, the detection signal DS13 on connection line P13 is mainly interfered with by multiple detection signals with a logic value of 0 on multiple connection lines of test lines TC12, TC22 (or TC11, TC21), causing the detection signal DS13 on connection line P13 to change from logic 1 to logic 0.

[0109] Therefore, the test device 300 can determine, based on the adjustment of the first byte (or test data TCP1~TCP4) and the second byte (or test data TBP1~TBP4), and according to the change in the detection signal DS13 and the test result C[2], that the connection line P13 will be affected by a bridging fault caused by one of the multiple connection lines on the test lines TC12, TC22 (or TC11, TC21) of the multiple test lines of the test device 300 (step S860).

[0110] Referring to Figure 7C, in the third sub-stage of the row test phase of the third test mode, the row test pattern generator 320 can generate the first byte (i.e., test data TCP1~TCP4) with a logic value of 0101 according to the control signal CSTX and send it to the test circuits TX11~TX44. The column test pattern generator 310 can generate test data TRP1~TRP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0111] In this case, the multiple test circuits on test rows TC11 and TC31 can each generate multiple detection signals as logic 1. Furthermore, the multiple test circuits on test rows TC21 and TC41 can each generate multiple detection signals as logic 0.

[0112] On the other hand, in the third sub-stage of the row test phase of the third test mode, the row test pattern generator 420 can generate a second byte (i.e., test data TBP1~TBP4) with a logic value of 1010 according to the control signal CSRX to the test circuits RX11~RX44, and the column test pattern generator 410 can generate test data TAP1~TAP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0113] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 1 to the logic value 0. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 0[2].

[0114] Referring to Figure 7D, in the fourth sub-stage of the row test phase of the third test mode, the row test pattern generator 320 can generate the first byte (i.e., test data TCP1~TCP4) with a logic value of 1010 according to the control signal CSTX and send it to the test circuits TX11~TX44. The column test pattern generator 310 can generate test data TRP1~TRP4 with a logic value of 0000 according to the control signal CSTX and send it to the test circuits TX11~TX44.

[0115] In this case, the multiple test circuits on test rows TC11 and TC31 can each generate multiple detection signals of logic 0. Furthermore, the multiple test circuits on test rows TC21 and TC41 can each generate multiple detection signals of logic 1.

[0116] On the other hand, in the fourth sub-stage of the row test phase of the third test mode, the row test pattern generator 420 can generate a second byte (i.e., test data TBP1~TBP4) with a logic value of 0101 according to the control signal CSRX to the test circuits RX11~RX44, and the column test pattern generator 410 can generate test data TAP1~TAP4 with a logic value of 0000 according to the control signal CSRX to the test circuits RX11~RX44.

[0117] Assuming that the connection line P13 is in an abnormal state, the logic value of the detection signal DS13 received by the test circuit RX13 from the connection line P13 changes from the original logic value 0 to the logic value 1. At this time, the test circuit RX13 can generate a test result C with a logic value of 1 based on the detection signal DS13 with a logic value of 1[2].

[0118] It should be noted that, as shown in the embodiment of Figure 7C, the detection signal DS13 on connection line P13 is mainly interfered with by multiple detection signals with a logic value of 0 on multiple connection lines of test line TC22 (or TC21), causing the detection signal DS13 on connection line P13 to change from logic 1 to logic 0. Furthermore, as shown in the embodiment of Figure 7D, the detection signal DS13 on connection line P13 is mainly interfered with by multiple detection signals with a logic value of 1 on multiple connection lines of test line TC22 (or TC21), causing the detection signal DS13 on connection line P13 to change from logic 0 to logic 1.

[0119] Therefore, the test device 300 can determine, based on the adjustment of the first byte (or test data TCP1~TCP4) and the second byte (or test data TBP1~TBP4), and according to the change in the detection signal DS13 and the test result C[2], that the connection line P13 will be affected by a bridging fault caused by one of the multiple connection lines on the test line TC22 (or TC21) of the multiple test lines of the test device 300 (step S860).

[0120] Therefore, based on the examples in Figures 7A to 7D above (steps S840 to S860), the test device 300 of this embodiment can determine that the corresponding connection line P13 is an abnormal connection line based on the test result C[2]. Furthermore, the test device 300 can determine, based on the change in the detection signal DS13 and the test result C[2], that the connection line P13 is experiencing a bridging fault due to one of the multiple connection lines on the test line TC22 (or TR21) (step S860), and select the test line TC22 (or TC21) as the selected test line.

[0121] According to the relevant descriptions in Figures 6A to 7D above, in step S870, the test device 300 can determine, based on the test result C[2] for logic 1, that the connection line causing the bridging fault of the corresponding connection line P13 is the connection line P42 located at the selected test line TR42 (or TR41) and the selected test line TC22 (or TC21).

[0122] In addition, referring back to Figure 3, in some other embodiments, the test apparatus 300 may, according to design requirements, have the test circuit array AR1 having multiple first test partitions and the test circuit array AR2 having multiple second test partitions. Thereby, the test apparatus 300 can test the connection lines in each test partition for abnormal states according to the relevant descriptions mentioned in Figures 1 to 8.

[0123] Figure 9 is a circuit diagram of a test apparatus according to another embodiment of Figure 2 of the present invention. Referring simultaneously to Figures 2, 3, and 9, in this embodiment, the test apparatus 900 includes multiple connecting lines P11~P46, multiple test circuits TX11~TX46, a column test pattern generator 810, a row test pattern generator 820, and a controller 830. These test circuits TX11~TX46 (i.e., the first test circuits) can be arranged in a 4*6 matrix.

[0124] It is worth mentioning that the operating functions and coupling methods of the test circuits TX11~TX46, column test pattern generator 810, row test pattern generator 820, and controller 830 shown in Figure 9 are the same as or similar to those of the test circuits TX11~TXNM, column test pattern generator 110, row test pattern generator 120, and controller 130 shown in Figure 2. Therefore, the test circuits TX11~TX46, column test pattern generator 810, row test pattern generator 820, and controller 830 shown in Figure 9 can be deduced by referring to the relevant descriptions of the test circuits TX11~TXNM, column test pattern generator 110, row test pattern generator 120, and controller 130 mentioned in Figure 2, and will not be repeated here. In addition, in Figures 2, 3, and 9, the same or similar components or parts can be identified by the same or similar reference numerals.

[0125] Unlike the embodiment in Figure 3, in the test apparatus 900 shown in Figure 9, each of the test circuits TX11 to TX46 may include a logic gate LOC3 and a multiplexer MUX. In the embodiment of Figure 9, the logic gate LOC3 may be implemented by an AND gate.

[0126] In another embodiment, in FIG9, the test apparatus 900 further includes multiple test circuits RX11~RX46 (i.e., second test circuits), a column test pattern generator 910, a row test pattern generator 920, a controller 930, a shift register 940, and an address decoder 950.

[0127] It is worth mentioning that the operation functions and coupling methods of the test circuits RX11~RX46, column test pattern generator 910, row test pattern generator 920, controller 930, shift register 940 and address decoder 950 shown in Figure 9 are the same as or similar to the operation functions and coupling methods of the test circuits RX11~RXNM, column test pattern generator 210, row test pattern generator 220, controller 230, shift register 240 and address decoder 250 shown in Figure 2. Therefore, the test circuits RX11~RX46, column test pattern generator 910, row test pattern generator 920, controller 930, shift register 940, and address decoder 950 shown in Figure 9 can be deduced by referring to the relevant descriptions of the test circuits RX11~RXNM, column test pattern generator 210, row test pattern generator 220, controller 230, shift register 240, and address decoder 250 mentioned in Figure 2, and will not be repeated here. Furthermore, in Figures 2, 3, and 9, the same or similar components or parts can be labeled with the same or similar reference numerals.

[0128] Unlike the embodiment in Figure 3, in the test apparatus 900 shown in Figure 9, each of the test circuits RX11 to RX46 may include a logic gate LOC4, a comparator COM, and a buffer BUF. In the embodiment of Figure 9, the logic gate LOC4 may be implemented by an AND gate, and the comparator COM may be implemented by an XNOR gate.

[0129] It is worth mentioning that the implementation of the test device 900 operating in the first test mode and the second test mode can be deduced by referring to the relevant descriptions of the test device 300 operating in the first test mode and the second test mode mentioned in Figures 3 to 5, so it will not be repeated here.

[0130] It should be noted that, in the embodiment shown in Figure 9, when the test device 900 operates in the column test phase of the third test mode, the column test pattern generator 810 of the test device 900 can sequentially generate test data TRP1~TRP4 with logic values ​​of 1100, 0011, 0101, and 1010 for multiple first test bytes according to the control signal CSTX. Furthermore, the row test pattern generator 820 of the test device 900 can generate test data TCP1~TCP6 with logic value of 111111 according to the control signal CSTX.

[0131] Furthermore, when the test apparatus 900 operates in the column test phase of the third test mode, the column test pattern generator 910 of the test apparatus 900 can sequentially generate test data TAP1~TAP4 with logic values ​​of 1100, 0011, 0101, and 1010 for multiple second test bytes according to the control signal CSRX. Additionally, the row test pattern generator 920 of the test apparatus 900 can generate test data TBP1~TBP6 with logic value 111111 according to the control signal CSRX.

[0132] On the other hand, when the test device 900 operates in the row test phase of the third test mode, the row test pattern generator 820 of the test device 900 can sequentially generate test data TCP1 to TCP6 with logic values ​​of 000011, 111100, 001100, 110011, 010101, and 101010 for multiple first test bytes according to the control signal CSTX. Furthermore, the column test pattern generator 810 of the test device 900 can generate test data TRP1 to TRP4 with a logic value of 111111 according to the control signal CSTX.

[0133] Furthermore, when the test apparatus 900 operates in the row test phase of the third test mode, the row test pattern generator 920 of the test apparatus 900 can sequentially generate test data TBP1 to TBP6 with logic values ​​of 000011, 111100, 001100, 110011, 010101, and 101010 for multiple second test bytes according to the control signal CSRX. Additionally, the column test pattern generator 910 of the test apparatus 900 can generate test data TAP1 to TBP4 with logic value 1111 according to the control signal CSRX.

[0134] The implementation of the test device 900 operating in the third test mode can be deduced by analogy with the relevant descriptions of the test device 300 operating in the third test mode mentioned in Figures 3, 6A to 8, and therefore will not be repeated here.

[0135] Figure 10 is a flowchart of a test method using a test apparatus according to an embodiment of the present invention. In step S1010, the test apparatus provides a plurality of connection lines. In step S1020, the test apparatus provides a plurality of first test circuits, and the plurality of first test circuits generate a plurality of detection signals based on a plurality of first test data, and transmit the plurality of detection signals to the plurality of connection lines respectively. In step S1030, the test apparatus provides a plurality of second test circuits, and the plurality of second test circuits receive the plurality of detection signals through the plurality of connection lines, and compare the plurality of second test data with the plurality of detection signals respectively to generate a plurality of test results.

[0136] The implementation details of the above steps have been explained in detail in the foregoing embodiments, and will not be repeated here.

[0137] In summary, in the testing apparatus and method described in the embodiments of the present invention, the testing apparatus can, in a first test mode or a second test mode, determine which of the multiple connection lines is short-circuited to the ground voltage or power supply voltage of the chip based on multiple test results. Furthermore, in a third test mode, the testing apparatus can, based on multiple test results, determine which of the multiple connection lines has a fixed or bridging fault, and further observe the test output results to determine whether the connection line has a fixed 0 fault, a fixed 1 fault, a wired-AND bridging fault, or a wired-OR bridging fault. In this way, the testing apparatus of the present invention can effectively test abnormal connection lines in the inter-chip interconnects, thereby improving the operational quality of the chip.

[0138] 100, 300, 900: Testing equipment 110, 210, 310, 410, 810, 910: Sample generators 120, 220, 320, 420, 820, 920: Line test sample generator 130, 230, 330, 430, 830, 930: Controller 240, 440, 940: Shift registers 250, 450, 950: Address decoder AR1, AR2: Test Circuit Array CLK: Clock signal CSTX, CSRX, Y1~YN: Control signals CL1~CLM: Line Test Line DS11~DSNM: Detection signal DIE1, DIE2: Chips C[0]~C[P]、DOUT: Test Results MODE: Mode selection signal P11~PNM: Connecting wires RST: Reset signal RL1~RLN: Test lines ST: Start Signal S510~S530, S610~S630, S810~S870, S1010~S1030: Steps TX11~TXNM, RX11~RXNM: Test Circuit TC1~TCM, TC11~TC41, TC12~TC42: Test lines TRP1~TRPN, TCP1~TCPM, TAP1~TAPN, TBP1~TBPM: Test Data TR1~TRN, TR11~TR41, TR12~TR42: Test columns

Claims

1. A testing apparatus, comprising: Multiple connecting lines; A plurality of first test circuits are respectively coupled to the connection lines. The first test circuits generate a plurality of detection signals based on a plurality of first test data and transmit the detection signals to the connection lines respectively. A plurality of second test circuits are respectively coupled to the connection lines and receive the detection signals by the connection lines. The second test circuits compare a plurality of second test data with the detection signals to generate a plurality of test results. Each of the second test circuits includes: a logic gate that receives the second test data and performs a logic operation on the second test data to generate an output signal. A comparator receives the output signal and each of the detection signals, and compares the output signal and each of the detection signals to generate each of the test results, wherein the first test circuits and the second test circuits are arranged in an N*M matrix, where N and M are positive integers.

2. The test apparatus as claimed in claim 1, wherein the first test circuits are configured as a first test circuit array and the second test circuits are configured as a second test circuit array, wherein the first test circuit array has a plurality of first test columns and a plurality of first test rows, and the second test circuit array has a plurality of second test columns and a plurality of second test rows.

3. The testing apparatus as described in claim 2, further comprising: A first column test pattern generator is coupled to the first test circuits to generate multiple first column test data from the first test data to the first test circuits according to a first control signal. A first row test pattern generator, coupled to the first test circuits, is used to generate a plurality of first row test data from the first test data to the first test circuits according to the first control signal; a second column test pattern generator, coupled to the second test circuits, is used to generate a plurality of second column test data from the second test data to the second test circuits according to a second control signal; and a second row test pattern generator, coupled to the second test circuits, is used to generate a plurality of second row test data from the second test data to the second test circuits according to the second control signal.

4. The testing apparatus as described in claim 1, further comprising: A shift register is coupled to the second test circuits and is used to sequentially output the test results according to a clock signal.

5. The test apparatus as claimed in claim 1, wherein each of the first test circuits comprises: A logic gate is used to receive the first test data and perform a logic operation on the first test data to generate each detection signal; And a multiplexer, coupled to the logic gate, for selecting the transmission of each detection signal to each connection line according to a mode selection signal.

6. The testing apparatus as claimed in claim 1, wherein in a first test mode or a second test mode, when each of the test results has a first logic value, it indicates that the connection line corresponding to each of the test results having the first logic value is operating in a normal connection state, and when each of the test results has a second logic value, it indicates that the connection line corresponding to each of the test results having the second logic value is operating in an abnormal connection state, wherein the first logic value is different from the second logic value.

7. The test apparatus as claimed in claim 6, wherein the abnormal connection state includes a short circuit between the connection line and a power supply voltage, or a short circuit between the connection line and a ground voltage.

8. The test apparatus as claimed in claim 3, wherein in a test phase of a third test mode, the first test data have a plurality of first test bytes and the second test data have a plurality of second test bytes, wherein the first test pattern generator sequentially generates the first test bytes to the first test circuits according to the first control signal, and the second test pattern generator sequentially generates the first test bytes to the second test circuits according to the second control signal.

9. The test apparatus as claimed in claim 8, wherein in a row test phase of the third test mode, the first row test data has a plurality of third test bytes and the second row test data has a plurality of fourth test bytes, wherein the first row test pattern generator sequentially generates the third test bytes to the first test circuits according to the first control signal, and the second row test pattern generator sequentially generates the fourth test bytes to the second test circuits according to the second control signal.

10. The test apparatus of claim 2, wherein the first test circuit array has a plurality of first test partitions and the second test circuit array has a plurality of second test partitions, and the second test circuits test, based on the test results, at least one of the second test partitions has a connection line operating in an abnormal connection state.

11. A testing method for a testing device, comprising: Multiple connection cables are provided; The system provides multiple first test circuits, which generate multiple detection signals based on multiple first test data, and transmit the detection signals to the connection lines respectively; it also provides multiple second test circuits, which receive the detection signals via the connection lines and compare the multiple second test data with the detection signals to generate multiple test results; a logic gate is provided, which receives the second test data and performs a logical operation on the second test data to generate an output signal; and a comparator is provided, which receives the output signal and each of the detection signals and compares the output signal and each of the detection signals to generate the test results, wherein the first test circuits and the second test circuits are arranged in an N*M matrix, where N and M are positive integers.

12. The test method as described in Request 11 further includes: Configure these first test circuits as a first test circuit array; Configure these second test circuits as a second test circuit array; The first test circuit array is configured to have multiple first test columns and multiple first test rows; and the second test circuit array is configured to have multiple second test columns and multiple second test rows.

13. The test method as described in Request 12 further includes: A first column test pattern generator is provided, and the first column test pattern generator generates multiple first column test data from the first test data to the first test circuits according to a first control signal; A first row test pattern generator is provided, and the first row test pattern generator generates a plurality of first row test data from the first test data to the first test circuits according to the first control signal; a second column test pattern generator is provided, and the second column test pattern generator generates a plurality of second column test data from the second test data to the second test circuits according to the second control signal; and a second row test pattern generator is provided, and the second row test pattern generator generates a plurality of second row test data from the second test data to the second test circuits according to the second control signal.

14. The test method as described in Request 11 further includes: A shift register is provided, and the shift register outputs the test results sequentially according to a clock signal.

15. The test method as claimed in claim 11, wherein the steps of providing the first test circuits, causing the first test circuits to generate the detection signals respectively based on the first test data, and causing the detection signals to be transmitted to the connection lines respectively include: A logic gate is provided, which receives the first test data and performs a logic operation on the first test data to generate each of the detection signals; and a multiplexer is provided, which selects to transmit each of the detection signals to each of the connection lines according to a mode selection signal.

16. The test method as described in claim 11, wherein in a first test mode or a second test mode, when each test result has a first logical value, it indicates that the connection line corresponding to each test result having the first logical value is operating in a normal connection state, and when each test result has a second logical value, it indicates that the connection line corresponding to each test result having the second logical value is operating in an abnormal connection state, wherein the first logical value is different from the second logical value.

17. The test method as described in claim 16, wherein the abnormal connection state includes a short circuit between the connection line and a power supply voltage, or a short circuit between the connection line and a ground voltage.

18. The test method as claimed in claim 13, wherein in a test phase of a third test mode, the first test data columns have a plurality of first test bytes and the second test data columns have a plurality of second test bytes, and the test method further includes: The first test sample generator sequentially generates the first test bytes to the first test circuits according to the first control signal; And cause the second column test pattern generator to sequentially generate the first test bytes to the second test circuits according to the second control signal.

19. The test method as described in claim 18, wherein in a row test phase of the third test mode, the first row test data has a plurality of third test bytes and the second row test data has a plurality of fourth test bytes, and the test method further includes: The first row test pattern generator sequentially generates the third test bytes to the first test circuits according to the first control signal; and the second row test pattern generator sequentially generates the fourth test bytes to the second test circuits according to the second control signal.

20. The test method as described in claim 12 further includes: The first test circuit array is configured to have multiple first test partitions and the second test circuit array is configured to have multiple second test partitions; and the second test circuits are configured to test, based on the test results, at least one of the second test partitions for a connection line operating in an abnormal connection state.

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