Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same. In some embodiments, the semiconductor device includes a first interconnect structure on a first semiconductor substrate, wherein the first interconnect structure includes a first conductive metal material and a ring structure. The ring structure may extend over or around the first conductive metal material. In some embodiments, the semiconductor device may further include a second conductive metal material and optionally include a third conductive metal material. The ring structure may partially surround solder material formed over the first conductive metal material.

Description

Prior Technology

[0001] The semiconductor industry continues to evolve due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, these improvements in integration density come primarily from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area (i.e., the occupied area).

[0002] Package components may include a dielectric module mounted on a package substrate or interposer. The dielectric module may include one or more semiconductor dies connected to the dielectric or substrate dielectric via interconnect structures (e.g., microbumps). In some cases, particularly with fine-pitch interconnect structures, solder sidewall wetting can cause solder to form bridging between adjacent interconnect structures. This can lead to unintended electrical connections or electrical short circuits. Therefore, it is necessary to mitigate solder sidewall wetting. Simple Explanation of the Diagram

[0003] The nature of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is an example vertical cross-sectional view of a substrate and passivation layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 2 is a vertical cross-sectional view of an example of a patterned passivation layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 3 is an example vertical cross-sectional view of a seed layer deposited above a passivation layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 4 is a vertical cross-sectional view of an example of a cavity formed in a passivation layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 5 is a vertical cross-sectional view of an example of forming an under-bump metallization layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 6 is a vertical cross-sectional view of an example of forming a seed layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 7 is an example vertical cross-sectional view of forming a photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 8 is an example vertical cross-sectional view of a patterned photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 9 is an example vertical cross-sectional view of an intermediate interconnect structure plated with conductive metal material according to various embodiments of the present disclosure. Figure 10 is a vertical cross-sectional view of an example of removing a photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 11 is an example vertical cross-sectional view of forming a photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 12 is an example vertical cross-sectional view of a patterned photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 13 is an example vertical cross-sectional view of an annular structure plated in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 14 is a vertical cross-sectional view of an example of removing a photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 15 is an example vertical cross-sectional view of a photoresist layer formed in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 16 is an example vertical cross-sectional view of a patterned photoresist layer in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 17 is an example vertical cross-sectional view of the deposition of solder material in an intermediate interconnect structure according to various embodiments of the present disclosure. Figure 18 is a vertical cross-sectional view of an example of removing a photoresist layer in an interconnect structure according to various embodiments of the present disclosure. Figures 19A to 19E are example vertical cross-sectional views of alternative embodiments of interconnect structures according to various embodiments of the present disclosure. Figures 20A to 20E are example vertical cross-sectional views of alternative embodiments of the annular structure according to various embodiments of the present disclosure. Figure 21 is a top view of examples of interconnect structures and ring structures according to various embodiments of the present disclosure. Figures 22A to 22C are example vertical cross-sectional views of interconnect structures having bottom bump structures and top bump structures according to various embodiments of the present disclosure. Figure 23 is a flowchart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure. Implementation

[0004] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0005] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," "upper," and similar spatial relative terms are used herein to describe the relationship between one element or feature and another element(s) shown in the figures. Besides the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference numerals is assumed to have the same material composition and a thickness within the same thickness range. Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the claims.

[0006] Microbumps are interconnect structures that connect semiconductor dies to various surfaces and substrates, such as silicon substrates, redistribution layers, chip-on-a-wafer, or other suitable substrates. Generally, interconnect structures such as microbumps can include bottom bumps and top bumps. Bottom bumps (e.g., on a surface or substrate) can be copper-based, copper / nickel / copper / solder-based, or copper / nickel / solder-based. Top bumps (e.g., on a semiconductor die) can be copper / nickel / copper / solder-based.

[0007] A mass reflow process can be used to bond top bumps to bottom bumps. After an initial interconnect structure (also known as a bump, bump structure, or bump interconnect structure) can be formed on a surface or substrate and semiconductor die, the interconnect structure can undergo a reflow process. The reflow process involves heating the semiconductor structure, including the interconnect structure, in a reflow oven to uniformly heat and melt the solder material contained in one of the top or bottom bumps. As the solder melts, the interconnect structure is shaped into spheres due to surface tension. The semiconductor structure is then gradually cooled to allow the solder reflowed into the interconnect structure to solidify.

[0008] When interconnects are closely spaced together (e.g., with fine pitch), sidewall wetting can lead to bump bridge defects between adjacent interconnects during reflow. During reflow, solder wettability may cause molten solder to flow between adjacent interconnects instead of between the corresponding top and bottom bumps. This can not only cause electrical short circuits between adjacent interconnects but also result in insufficient solder volume due to solder migration to adjacent interconnects, thus hindering adequate electrical connection between the corresponding top and bottom bumps. Bump bridge defects can cause reliability tests such as high-temperature storage (HTS) tests to fail. Therefore, interconnect structures may make it difficult to increase the spacing (e.g., interconnect spacing, center-to-center distance between interconnects), as increased spacing (e.g., dense areas of fine-pitch bumps) may exacerbate the likelihood of bump bridge defects.

[0009] Furthermore, during the reflow process, interconnect structures may experience bump tilting due to uneven heating, unbalanced surface tension, or misalignment. Bump tilting can lead to poor electrical connections in the interconnect structure between the substrate and the semiconductor die. Additionally, bump tilting can reduce the mechanical strength of the interconnect structure, resulting in overall mechanical failure of the semiconductor device. Therefore, bump tilting impairs the performance and reliability of semiconductor devices.

[0010] Various embodiments disclosed herein relate to a semiconductor device including a ring structure to prevent bump bridging and bump tilting. In some embodiments, the semiconductor device includes a first conductive metal material and a ring structure extending over the first conductive metal material. In some embodiments, the semiconductor device further includes a second conductive metal material, a third conductive metal material, and / or a fourth conductive metal material. Additionally, the semiconductor device may include solder material. In alternative embodiments, the semiconductor device includes a first conductive metal material and a ring structure surrounding the first conductive metal material. In some embodiments, the semiconductor device further includes a second conductive metal material and / or a third conductive metal material, and the ring structure also surrounds the second conductive metal material and / or the third conductive metal material. Additionally, the semiconductor device may include a solder portion. Surface mount inspection tools may include lasers, detectors, and signal analysis modules.

[0011] In an alternative embodiment, the method of forming a semiconductor device includes patterning a photoresist layer to form an interconnect structure cavity. A first conductive metal material is deposited within the interconnect structure cavity, and the photoresist layer is further patterned to form an annular cavity. An annular conductive metal material is deposited within the annular cavity, and the photoresist layer is removed.

[0012] The various embodiments disclosed herein offer various advantages and improvements. For example, the various embodiments disclosed herein may include a ring structure surrounding a portion of the solder. Therefore, the various embodiments disclosed herein can prevent bump bridging by ensuring that individual interconnect structures are electrically isolated from each other during the reflow process. By preventing bump bridging, the various embodiments improve the reliability testing of semiconductor devices, such as HTS testing. Additionally, the various embodiments disclosed herein prevent bump tilting by ensuring that the interconnect structures are formed perpendicular to the substrate or interposer during the reflow process. By preventing bump tilting, the various embodiments improve the mechanical strength of the interconnect structures to reduce mechanical failures, thereby improving the performance and reliability of the semiconductor device. The various embodiments disclosed herein can further improve the electrical connection between the substrate and the semiconductor die through the interconnect structures by improving the interconnect structures formed during the reflow process.

[0013] Figures 1 through 17 illustrate various intermediate structures for forming semiconductor devices with interconnect structures according to various embodiments. Figures 18 through 21C illustrate various embodiments of the interconnect structure. Figure 1 is a vertical cross-sectional view of substrate 102 and passivation layer 104. Substrate 102 may include any substrate capable of supporting packaged components. For example, substrate 102 may include a system on integrated substrate (SoIS), a printed circuit board (PCB), a redistribution layer (RDL), a silicon substrate, or a suitable alternative substrate.

[0014] The substrate 102 may include metal interconnects 140 (e.g., metal traces and metal vias) formed therein to facilitate electrical connections to electrical devices. The substrate may be a dielectric material, such as silicon dioxide, silicon nitride, aluminum oxide, or other suitable materials. The substrate 102 may also include substrate bonding pads 142 (e.g., package substrate contact pads). The bonding pads 142 may be made of a conductive metallic material, such as copper, silver, chromium, nickel, tin, tungsten, titanium, gold, copper alloys, or other suitable conductive metallic materials or alloys. The substrate bonding pads 142 can be used to provide electrical connections to semiconductor devices (e.g., semiconductor dies) mounted on the substrate 102.

[0015] The passivation layer 104 may be formed of a dielectric material, such as silicon dioxide, silicon nitride, aluminum oxide, or other suitable materials. The passivation layer 104 acts as a barrier to protect the substrate 102 and bonding pad 142 from corrosion or contamination (e.g., dust particles or chemicals). Additionally, the passivation layer 104 reduces the chemical reactivity of the surfaces of the substrate 102 and / or bonding pad 142, thus maintaining material integrity over time and reducing surface conditions and defects, thereby improving the performance of the packaged assembly. The passivation layer 104 may be formed by spin-coating and drying a suitable dielectric polymer material. The thickness of the passivation layer 104 may range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers.

[0016] Figure 2 is a vertical cross-sectional view of a patterned passivation layer 104 in an intermediate interconnect structure, and Figure 3 is a vertical cross-sectional view of a dielectric material 106 deposited above the passivation layer 104 in the intermediate interconnect structure. The passivation layer 104 can be patterned, for example, by applying and patterning a corresponding photoresist layer thereon and transferring the pattern from the photoresist layer to the passivation layer 104 through an etching process such as anisotropic etching. The photoresist layer can then be removed, for example, by ashing. The passivation layer 104 can be patterned to prepare the surface of the dielectric material 106. The dielectric material 106 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO), or other suitable organic or inorganic dielectric materials. The dielectric material 106 acts as a stress buffer, thus reducing thermal and mechanical stresses on the passivation layer 104 and the substrate 102, further preventing cracking and other damage. Additionally, the dielectric layer 106 serves as an extra protective barrier to prevent moisture, contaminants, and environmental factors from damaging the underlying substrate 102 and bonding pads 142. The dielectric layer 106 also provides electrical insulation and flexibility to accommodate expansion and contraction during temperature changes, and provides an adhesive layer between different layers in the package.

[0017] Figure 4 is a vertical cross-sectional view of a patterned passivation layer 104 and dielectric layer 106 in an intermediate interconnect structure to form a bump cavity 108. The bump cavity 108 exposes a substrate bonding pad 142 to allow subsequent interconnect structures to connect to the substrate bonding pad 142. The upper surface of the substrate bonding pad 142 is exposed through the bump cavity 108. The bump cavity 108 may have tapered sidewalls such that the diameter of the bump cavity 108 (in the XY plane) can decrease in the direction toward the substrate bonding pad 142.

[0018] Figure 5 is a vertical cross-sectional view of a conductive metal material deposited in the bump cavity 108 within an intermediate interconnect structure to form an under-bump metallization (UBM) structure 110. Prior to depositing the conductive metal material, the bump cavity 108 can be cleaned using a chemical mechanical polishing (CMP) process or other suitable process. The cleaning process removes oxides or other contaminants from the bump cavity 108. The UBM structure 110 can be formed from a conductive metal material, such as copper, nickel, titanium, or other suitable materials.

[0019] Conductive metallic material can be deposited into the bump cavity 108 using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic vapor deposition (AVD), or other suitable deposition methods. In some embodiments, the UBM structure 110 can be further patterned or cleaned to achieve a desired shape and smooth the top surface.

[0020] The UBM structure 110 provides electrical and mechanical connections to the substrate bonding pads 142 and the interconnect structure 140. For example, the UBM structure 110 ensures reliable signal transmission to the interconnect structure and supports the interconnect structure, thus enhancing the structural integrity of the package. The UBM structure 110 also acts as a barrier to prevent material diffusion that could degrade package performance. Overall, the UBM structure 110 enhances reliability by providing sufficient electrical and mechanical connections while maintaining package performance by preventing material diffusion.

[0021] Figure 6 is a vertical cross-sectional view of a seed layer 112 deposited above the dielectric layer 106 and the UBM structure 110 in an intermediate interconnect structure. The seed layer 112 can be deposited via PVD, AVD, CVD, or other suitable deposition methods. In some embodiments, the seed layer 112 is formed of copper, titanium, nickel, gold, other suitable metals, and combinations thereof. The seed layer 112 provides a conductive substrate for electroplating conductive metals. Additionally, the seed layer 112 ensures sufficient adhesion between the UBM structure 110 and the subsequently electroplated conductive metal material. Furthermore, the seed layer 112 provides barrier properties to prevent material diffusion.

[0022] Figure 7 is a vertical cross-sectional view of the photoresist layer 114 formed above the seed layer 112. The photoresist layer 114 is a photosensitive material used in photolithography processes to form geometric patterns on a surface. The photoresist layer 114 can be a positive photoresist layer, wherein when exposed to light, the photoresist layer 114 becomes soluble, allowing exposed areas to be washed away; or a negative photoresist layer, wherein when exposed to light, the photoresist layer 114 becomes insoluble, and unexposed areas are washed away. The photoresist layer 114 can be formed from a resin, a photosensitive compound, and a solvent, and optionally, a dye for visual inspection or an antioxidant for enhancing stability.

[0023] Figure 8 is a vertical cross-sectional view of the patterned and developed photoresist layer 114 in the intermediate interconnect structure. First, the photoresist layer 114 can be exposed to light of a specific wavelength (e.g., UV light between 100 nm and 400 nm) through a mask with a desired pattern. In this embodiment, as shown in Figure 8, the mask may include portions corresponding to bump cavities 116 within the photoresist layer 114. The chemical structure of the photoresist layer 114 can be altered in the areas exposed to the light beam. The structure can then be developed using a chemical solution that removes exposed or unexposed areas based on the type of photoresist material used. For example, a positive photoresist material will wash away exposed areas, while a negative photoresist material will wash away unexposed areas. The resulting structure includes bump cavities 116 in the photoresist layer 114 that expose the seed layer 112 previously formed over the UBM structure 110.

[0024] Figure 9 is a vertical cross-sectional view of the first conductive metal material 118 plated in the bump cavity 116 in the intermediate interconnect structure. First, a thin layer of conductive metal material 118 is deposited on the seed layer 112. The conductive metal material 118 can be copper, nickel, titanium, tungsten, gold, silver, or other suitable conductive metal materials. In some embodiments, the first conductive metal material 118 is selected based on its conductivity characteristics, thus creating a suitable electrical connection.

[0025] The initial thin layer provides a conductive surface for electroplating. The entire structure can then be immersed in an electrolyte bath containing high-texture material ions (e.g., copper ions or copper sulfate). An electric current can be applied, causing the high-texture material ions to migrate and deposit on the thin layer, forming a thicker high-texture material layer. After electroplating, the surface can be planarized by polishing using a chemical mechanical polishing process to remove excess ions and obtain a smooth, flat surface. The resulting structure includes a first conductive metallic material 118 formed within bump cavities 116.

[0026] Figure 10 is a vertical cross-sectional view of a first conductive metal material 118 remaining after a portion of the photoresist layer 114 and seed layer 112 have been removed or stripped from the intermediate interconnect structure. The photoresist layer 114 stripping process may include wet stripping, dry stripping, or a combination of methods. A wet stripping process may use a chemical solution of solvents and / or acids to dissolve and remove the photoresist layer 114. A dry stripping process may use a plasma, such as an oxygen plasma, containing ionized gases to decompose the photoresist layer 114. The plasma may react with the photoresist layer 114 to form volatile compounds that are subsequently removed. A combination of wet and dry stripping methods ensures complete removal by dissolving and decomposing the photoresist layer 114. Additionally, a portion of the seed layer 112 not located beneath the first conductive metal material 118 may be stripped. The resulting structure includes the first conductive metal material 118, with the photoresist layer 114 removed.

[0027] Figure 11 is a vertical cross-sectional view of a second photoresist layer 120 formed around a first conductive metal material 118 in an intermediate interconnect structure. Similarly, the second photoresist layer 120 is a photosensitive material used in photolithography processes to form geometric patterns on a surface. The second photoresist layer 120 can be a positive photoresist layer, wherein when exposed to light, the second photoresist layer 120 becomes soluble to allow exposed areas to be washed away; or a negative photoresist layer, wherein when exposed to light, the second photoresist layer 120 becomes insoluble, and unexposed areas are washed away. The second photoresist layer 120 can be formed from a resin, a photosensitive compound, and a solvent, and optionally a dye for visual inspection or an antioxidant for enhancing stability.

[0028] Figure 12 is a vertical cross-sectional view of patterning and developing the second photoresist layer 120 in the intermediate interconnect structure. The second photoresist layer 120 can be exposed to light of a specific wavelength (e.g., UV light between 100 nm and 400 nm) through a mask with a desired pattern. In this embodiment, as shown in Figure 12, the mask may include a portion above each of the first conductive metal materials 118 corresponding to annular cavities 122 within the second photoresist layer 120. The chemical structure of the second photoresist layer 120 can be altered in the regions exposed to the light beam. The second photoresist layer 120 can then be developed using a chemical solution that removes exposed or non-exposed areas based on the type of photoresist material used. For example, a positive photoresist material will wash away exposed areas, while a negative photoresist material will wash away non-exposed areas. The resulting structure includes annular cavities 122 in the second photoresist layer 120.

[0029] Figure 13 is a vertical cross-sectional view of annular conductive metal material plated in annular cavity 122 to form annular structure 124 in an intermediate interconnect structure. First, a thin layer of annular conductive metal material is deposited on a first conductive metal material 118. The annular conductive metal material can be copper, nickel, titanium, tungsten, gold, silver, or other suitable conductive metal materials. The initial thin layer provides a conductive surface for electroplating. The intermediate interconnect structure can then be immersed in an electrolyte bath containing a solution of high-structure material ions (e.g., copper ions or copper sulfate). An electric current can be applied, causing the high-structure material ions to migrate and deposit on the thin layer, forming a thicker high-structure material layer. After electroplating, the surface can be planarized by polishing using a chemical mechanical polishing process to remove excess ions and obtain a smooth, flat surface. The resulting structure includes annular structure 124 formed within annular cavity 122.

[0030] Figure 14 is a vertical cross-sectional view of the annular structure 124 extending above the first conductive metal material 118 after the second photoresist layer 120 has been removed or stripped from the intermediate interconnect structure. The removal process of the second photoresist layer 120 may include wet stripping, dry stripping, or a combination of methods. The resulting structure includes the annular structure 124 located above and extending from the first conductive metal material 118, and the removed second photoresist layer 120.

[0031] Figure 15 is a vertical cross-sectional view of a third photoresist layer 126 formed in the intermediate interconnect structure, surrounding the first conductive metal material 118 and the annular structure 124. The third photoresist layer 126 is a photosensitive material used in photolithography processes to form geometric patterns on a surface. The third photoresist layer 126 can be a positive or negative photoresist layer. The third photoresist layer 126 can be formed from a resin, a photosensitive compound, a solvent, and optionally a dye for visual inspection or an antioxidant to enhance stability.

[0032] Figure 16 is a vertical cross-sectional view of patterning and developing a third photoresist layer 126 in an intermediate interconnect structure. The third photoresist layer 126 can be exposed to light of a specific wavelength (e.g., UV light between 100 nm and 400 nm) through a mask with a desired pattern. The mask may include portions above each first conductive metal material 118 between annular structures 124 corresponding to solder cavities 128 within the third photoresist layer 126. The chemical structure of the third photoresist layer 126 can be altered in the areas exposed to the light beam. The structure can then be developed using a chemical solution that removes exposed or non-exposed areas based on the type of photoresist material used. The resulting structure includes solder cavities 128 above the first conductive metal material 118 and surrounded by annular structures 124 within the third photoresist layer 126.

[0033] Figure 17 is a vertical cross-sectional view of solder material 130 plated in solder cavity 128 in an intermediate interconnect structure. A thin layer of solder material is deposited on a first conductive metal material 118. The solder material can be lead-free (LF) or copper lead-free (Cu / LF). LF materials can reduce environmental impact by eliminating lead that may accumulate in soil, water, or organisms. As an example, solder materials may include alloys containing at least one of tin, silver, copper, indium, and / or other suitable metallic materials. The initial thin layer provides a conductive surface for electroplating. The intermediate interconnect structure can then be immersed in an electrolyte bath containing a solution of high-structure material ions (e.g., copper ions or copper sulfate). An electric current can be applied, causing the high-structure material ions to migrate and deposit on the thin layer, forming a thicker high-structure material layer. After electroplating, the surface can be planarized by polishing using a chemical mechanical polishing process to remove excess ions and obtain a smooth, flat surface. The resulting structure includes solder material 130 formed within solder cavity 128.

[0034] Figure 18 is a vertical cross-sectional view showing the interconnect structure 150 after the third photoresist layer 126 has been removed or stripped. The removal process for the third photoresist layer 126 may include wet stripping, dry stripping, or a combination of methods. The resulting structure includes a solder portion 130 located above the first conductive metal material 118 and surrounded by an annular structure 124 forming the interconnect structure 150. The annular structure 124 may have a thickness between about 1 μm and about 10 μm. Such dimensions provide sufficient barrier to retain solder during the reflow process while also maintaining the individual interconnect structures 150 so that the total area occupied by the interconnect structures 150 does not increase.

[0035] Figures 1 through 18 illustrate a first photoresist layer 114 (Figure 7), a second photoresist layer 120 (Figure 11), and a third photoresist layer 126 (Figure 15). Multiple photoresist layers further prevent solder wetting. However, alternative embodiments can omit the removal of various photoresist layers between formation steps and simply reapply and pattern existing photoresist layers. For example, the first photoresist layer 114 can be patterned to form a bump cavity 116, then the second photoresist layer 120 can be applied over the first photoresist layer 114 and an annular cavity 122 can be patterned, and then the third photoresist layer 126 can be formed over the second photoresist layer 120 and a solder cavity 128 can be patterned. Thus, photoresist layers can be formed over each other without removing them between cavity formation steps.

[0036] Figures 19A to 19E show vertical cross-sectional views of the alternative interconnect structure 150. The interconnect structure 150 can have a spacing dimension between approximately 1 micrometer and approximately 100 micrometers. The ring structure 124 shown in Figures 18 and 19A to 19E is particularly useful when the spacing between the interconnect structures 150 is small and positioning is more difficult during the photoresist process. It is composed of ring structures 124. In this case, the architecture of the ring structure 124 minimizes the amount of space utilized by the interconnect structure 150.

[0037] Figure 19A illustrates an alternative interconnect structure 150 including a second conductive metal material 132. The second conductive metal material 132 may be formed of copper, nickel, tungsten, titanium, silver, gold, or other suitable conductive metal materials. In an embodiment, the ring structure 124 and the second conductive metal material 132 may be formed of the same conductive metal material. As shown in Figure 19A, the second conductive metal material 132 may be located above the first conductive metal material 118. Solder bumps 130 may be located above the second conductive metal material 132 and surrounded by the ring structure 124.

[0038] The addition of a second conductive metal material 132 improves the anti-wetting capability of the interconnect structure 150 compared to using only the first conductive metal material 118. For example, the first conductive metal material 118 can be selected based on its conductivity, while the second conductive metal material 132 can be selected based on its anti-wetting properties. Therefore, by using two different conductive metal materials, a balance can be achieved between conductivity, wettability, and material cost.

[0039] For example, the first conductive metal material 118 can be formed from copper due to its electrical and mechanical properties. However, copper is easily wetted due to its surface properties. More specifically, copper is easily oxidized, thus forming a copper oxide layer on the easily wettable surface. Furthermore, copper has an affinity for water molecules, which further promotes wetting. Therefore, selecting a second conductive metal material 132, such as nickel, can prevent wetting. According to this example, nickel can act as a barrier layer to prevent copper from diffusing into the solder material 130. In addition, nickel is less prone to oxidation than copper, thus inhibiting solder flow and resulting in less wetting. Moreover, nickel has a higher surface energy than copper, thus promoting the adhesion and spreading of the solder material. Therefore, by selecting the first conductive metal material 118 based on its electrical properties and the second conductive metal material 132 based on its anti-wetting properties, a balance can be achieved between proper electrical connection and preventing wetting of the solder material 130.

[0040] Figure 19B illustrates an alternative interconnect structure 150 including a second conductive metal material 132 and a third conductive metal material 134. As shown in Figure 19B, the third conductive metal material 134 is located below the second conductive metal material 132, which is located below the first conductive metal material 118. In an embodiment, the first conductive metal material 118 and the third conductive metal material 134 may be formed of the same material, and the second conductive metal material 132 and the annular structure 124 may be formed of the same material. Solder bumps 130 may be located above the first conductive metal material 118 and surrounded by the annular structure 124. Similarly, the addition of the second conductive metal material 132 and the third conductive metal material 134 improves the anti-wetting capability of the interconnect structure 150 compared to using only the first conductive metal material 118 or using both the first and second conductive metal materials 118 and 132.

[0041] Figure 19C illustrates an alternative interconnect structure 150 including a fourth conductive metal material 136 located above the first conductive metal material 118. In an embodiment, the fourth conductive metal material 136 may be formed of the same conductive metal material as the first conductive metal material 118. As shown in Figure 19C, the fourth conductive metal material 136 is located above the first conductive metal material 118 and surrounded by a ring structure 124. Solder material 130 may be located above the fourth conductive metal material 136. Using the first conductive metal material 118 and the fourth conductive metal material 136 formed of the same material reduces the overall cost of the interconnect structure 150. Furthermore, having the fourth conductive metal material 136 surrounded by the ring structure 124 reduces the amount of solder material 130 used in the interconnect structure 150. Reducing the amount of solder material 130 alleviates bump bridging because less solder can be used to achieve bump bridging between interconnect structures.

[0042] Figure 19D illustrates an alternative interconnect structure 150 including a fourth conductive metal material 136 located above a second conductive metal material 132. The second conductive metal material 136 may be located above a first conductive metal material 118. In an embodiment, the second conductive metal material 132 is formed of the same material as the ring structure 124, and the fourth conductive metal material 136 is formed of the same conductive metal material as the first conductive metal material 118. As shown in Figure 19D, the fourth conductive metal material 136 may be surrounded by the ring structure 124. Solder material 130 may be located above the fourth conductive metal material 136. The addition of the second conductive metal material 132 improves the anti-wetting capability of the interconnect structure 150. Furthermore, having a fourth conductive metal material 136 surrounded by the ring structure 124 reduces the amount of solder material 130 used in the interconnect structure 150.

[0043] Figure 19E illustrates an alternative interconnect structure 150 including a fourth conductive metal material 136 located above a first conductive metal material 118. Furthermore, the first conductive metal material 118 may be located above a second conductive metal material 132, which in turn is located above a third conductive metal material 134. In an embodiment, the first conductive metal material 118, the third conductive metal material 134, and the fourth conductive metal material 136 may be formed of the same conductive metal material. Additionally, in an embodiment, the second conductive metal material 132 may be formed of the same material as the ring structure 124. As shown in Figure 19E, the fourth conductive metal material 136 may be located above the first conductive metal material 118 and surrounded by the ring structure 124. Solder material 130 may be located above the fourth conductive metal material 136. Compared to using only the first conductive metal material 118 or using both the first and second conductive metal materials 118 and 132, the addition of the second and third conductive metal materials 132 improves the anti-wetting capability of the interconnect structure 150. Furthermore, the fourth conductive metal material 136 surrounded by the ring structure 124 can reduce the amount of solder material 130 used in the interconnect structure 150.

[0044] Figures 20A to 20E show vertical cross-sectional views of the alternative interconnect structure 150 in the alternative ring structure 124. More specifically, the ring structure 124 shown in Figures 20A to 20E is attached to the seed layer 112 and completely surrounds the interconnect structure 150. In these embodiments, the ring structure 124 is particularly useful when the spacing between the interconnect structures 150 is large and therefore easier to position during the photoresist process. In this case, the ring structure 124 occupies more space in the final interconnect structure 150.

[0045] Figure 20A illustrates an alternative interconnect structure 150 including a first conductive metal material 118. Furthermore, a ring structure 124 extends over and surrounds the first conductive metal material 118. Solder bumps 130 may be located over the first conductive metal material 118 and surrounded by the ring structure 124. The use of the first conductive metal material 118 reduces the overall cost of forming the structure 150.

[0046] Figure 20B illustrates an alternative interconnect structure 150 including a second conductive metal material 132. The second conductive metal material 132 may be formed of copper, nickel, tungsten, titanium, silver, gold, or other suitable conductive metal materials. In an embodiment, the ring structure 124 and the second conductive metal material 132 may be formed of the same conductive metal material. As shown in Figure 20B, the second conductive metal material 132 may be located above the first conductive metal material 118. Solder bumps 130 may be located above the second conductive metal material 132. The ring structure 124 may be connected to the seed layer 112 and surround a portion of the first conductive metal material 118, the second conductive metal material 132, and the solder material 130. The addition of the second conductive metal material 132 improves the anti-wetting capability of the interconnect structure 150 compared to using only the first conductive metal material 118.

[0047] Figure 20C illustrates an alternative interconnect structure 150 including a second conductive metal material 132 and a third conductive metal material 134. As shown in Figure 20C, the third conductive metal material 134 is located below the second conductive metal material 132, which is located below the first conductive metal material 118. In an embodiment, the first conductive metal material 118 and the third conductive metal material 134 are formed of the same material, and the second conductive metal material 132 and the annular structure 124 are formed of the same material. Solder bumps 130 may be located above the first conductive metal material 118. The annular structure 124 may be connected to the seed layer 112 and surround a portion of the first conductive metal material 118, the second conductive metal material 132, and the solder material 130. Similarly, the addition of the second conductive metal material 132 and the third conductive metal material 134 improves the anti-wetting capability of the interconnect structure 150 compared to using only the first conductive metal material 118 or using both the first and second conductive metal materials 118 and 132.

[0048] Figure 20D illustrates an alternative interconnect structure 150 comprising a first conductive metal material 118. The top surface of the first conductive metal material 118 may be coplanar with the annular structure 124. In an embodiment, the annular structure 124 completely surrounds the first conductive metal material 118. Solder material 130 may be located above the first conductive metal material 118. The use of the first conductive metal material 118 reduces the overall cost of forming the interconnect structure 150. Furthermore, having the first conductive metal material 118 surrounded by the coplanar annular structure 124 reduces the amount of solder material 130 used in the interconnect structure 150.

[0049] Figure 20E illustrates an alternative interconnect structure 150 including a second conductive metal material 132 and a third conductive metal material 134. As shown in Figure 20E, the third conductive metal material 134 is located below the second conductive metal material 132, which is located below the first conductive metal material 118. In an embodiment, the first conductive metal material 118 and the third conductive metal material 134 are formed of the same material, and the second conductive metal material 132 and the annular structure 124 are formed of the same material. The top surface of the first conductive metal material 118 may be coplanar with the annular structure 124. Solder bumps 130 may be located above the first conductive metal material 118. The annular structure 124 may completely surround the first conductive metal material 118, the second conductive metal material 132, and the third conductive metal material 134. Similarly, compared to using only the first conductive metal material 118 or using both the first and second conductive metal materials 118 and 132, the addition of the second conductive metal material 132 and the third conductive metal material 134 improves the anti-wetting capability of the interconnect structure 150. Furthermore, the first conductive metal material 118, surrounded by a coplanar annular structure 124, reduces the amount of solder material 130 used in the interconnect structure 150.

[0050] Figure 21 shows a top view (first horizontal direction hd1 and first horizontal direction hd2) of the annular structure 124 surrounding the solder material 130. As shown, the annular structure 124 may be substantially circular and surround the solder material 130. In alternative embodiments, the annular structure 124 may have a square, elliptical, or other shape based on the shape of the interconnect structure 150. For example, the annular structure may also have an elliptical cross-sectional shape if the interconnect structure 150 has an elliptical cross-sectional shape. Because the annular structure 124 surrounds the solder material 130, the annular structure 124 contains the solder material 130 during the reflow process. Therefore, the annular structure 124 can mitigate bump bridging and bump tilt by including the solder material 130 in the reflow process.

[0051] Figures 22A to 22C show example cross-sectional views of a bottom bump 150 with an interconnect structure and a top interconnect structure 160 or top bump 160 with a second configuration. The bottom interconnect structure 170 or bottom bump 170 can be connected to a substrate 102 having a passivation layer 104, a dielectric layer 106, a UBM structure 110, and a seed layer 112. The top interconnect structure 160 can be connected to a semiconductor die 105 having a passivation layer 103, a dielectric layer 107, a UBM structure 111, and a seed layer 113. The top interconnect structure 160 may include a first conductive metal material 119, a second conductive metal material 133, and / or a third conductive metal material 135.

[0052] In some embodiments, as shown in FIG22A, the top interconnect structure 160 may have the same interconnect structure as the bottom interconnect structure 170. In alternative embodiments, as shown in FIGS22B and 22C, the top interconnect structure 160 may have a different interconnect structure than the bottom interconnect structure 170. In some embodiments, both the top interconnect structure 160 and the bottom interconnect structure 170 include ring structures 124 / 125. In alternative embodiments, only the top interconnect structure 160 or the bottom interconnect structure 170 includes either ring structure 125 or ring structure 124. The ring structures 124 / 125 partially surround the solder material 130, thereby preventing bump bridging and bump tilting. By preventing bump bridging and bump tilting, the ring structures 124 / 125 improve the reliability and performance of the package while maintaining proper electrical connection between the substrate 102 and the semiconductor die 105.

[0053] Although various embodiments are shown in Figures 22A to 22C, other interconnect structures as shown in Figures 19A to 19E and Figures 20A to 20E can be used for the top interconnect structure 160 and the bottom interconnect structure 170. Therefore, various combinations of interconnect structures are conceivable within the scope of this disclosure.

[0054] The following discussion now deals with methods and method behaviors. Although method steps are discussed in a specific order or shown in a flowchart in a specific order, a specific order is not required unless explicitly stated or required because a step depends on the completion of another step before its execution.

[0055] A flowchart of an example method 2300 for forming a semiconductor device according to an embodiment of the present disclosure is now shown with reference to the embodiments described in FIG23. In the embodiment, step 2202 includes forming an interconnect structure over a seed layer. Referring to FIG6, 18, 19A to 19C and 20A to 20E, in step 2302 of method 2300, an interconnect structure 150 may be formed over a seed layer 112. The seed layer 112 may be deposited over a dielectric layer 106 and a UBM structure 110. The seed layer 112 may be formed of copper and titanium.

[0056] Steps 2304 and 2306 describe the sub-step of forming the interconnect structure 150 over the seed layer 112. In embodiment method 2300, step 2304 may optionally include patterning the photoresist layer 114 to form a bump cavity 116. Referring to Figures 8 and 23, in step 2306 of method 2300, the bump cavity 116 may expose the seed layer 112 located over the UBM structure 110.

[0057] In the embodiment method, step 2306 includes depositing a first conductive metal material 118 within the bump cavity 116. Referring to Figures 9, 18, 19A to 19E, 20A to 20E and 23, in step 2306 of method 2300, the first conductive metal material 118 may be deposited over the seed layer 112 in the bump cavity 116. In some embodiments, the first conductive metal material 118 may be formed of copper, tungsten, titanium, silver, gold or other suitable conductive metal materials. Optionally, after depositing the first conductive metal material 118, the photoresist layer 114 may be removed or stripped.

[0058] In an alternative embodiment, a second conductive metal material 132, a third conductive metal material 134, and / or a fourth conductive metal material 136 may be plated in the bump cavity 116. In some embodiments, the second conductive metal material 134 is located below the first conductive metal material 118. In some embodiments, the third conductive metal material 136 is located below the second conductive metal material 134. In some embodiments, the fourth conductive metal material 136 is located above the first conductive metal material 118. In an embodiment, the first conductive metal material 118, the third conductive metal material 134, and the fourth conductive metal material 136 are formed of the same conductive metal material. In an embodiment, the second conductive metal material 132 is formed of the same material as the annular structure 124.

[0059] In the embodiment method, step 2308 includes forming a ring structure 124 on the interconnect structure. Steps 2310 and 2312 describe the sub-steps for forming the ring structure 124. In an embodiment, step 2310 includes patterning a photoresist layer to form a ring cavity 122. Referring to Figures 12 and 23, in step 2310 of method 2300, a second photoresist layer 120 may be patterned to form the ring cavity 122.

[0060] In the embodiment method, step 2312 includes depositing an annular conductive metal material in the annular cavity 122 to form an annular structure 124. Referring to Figures 13, 18, 19A to 19E, 20A to 20E and 23, in step 2312 of method 2300, an annular conductive metal material may be deposited within the annular cavity 122 to form the annular structure 124. In some embodiments, the annular structure 124 extends over a first conductive metal material 118. In some embodiments, the annular structure 124 is connected to a seed layer 112 and surrounds the first conductive metal material 118.

[0061] In the embodiment method, step 2314 includes plating solder material that is partially surrounded by an annular structure. Referring to Figures 14, 17, and 23, in step 2314 of method 2300, the plating solder material 130 is placed over the first conductive metal material 118.

[0062] Referring to all the accompanying drawings and various embodiments disclosed herein, a semiconductor device includes a first interconnect structure on a first semiconductor substrate, wherein the first interconnect structure includes a first conductive metal material 118; and an annular structure 124 extending over the first conductive metal material 118.

[0063] In some embodiments, the semiconductor device further includes a second conductive metal material 132 formed beneath the first conductive metal material 118, wherein the second conductive metal material 132 is formed of a material different from the first conductive metal material 118. In some embodiments, the semiconductor device further includes a third conductive metal material 134 formed beneath the second conductive metal material 132, wherein the third conductive metal material 134 is formed of a material different from the second conductive metal material 132. In some embodiments, the ring structure is formed of the same material as the second conductive metal material 132. In some embodiments, the semiconductor device further includes solder material 130 located above the first conductive metal material 118 and surrounded by the ring structure 124. In some embodiments, the semiconductor device further includes a second interconnect structure 170, wherein the solder material 130 is located between the first interconnect structure 160 and the second interconnect structure 170. In some embodiments, the semiconductor device further includes a fourth conductive metal material 136, wherein the ring structure 124 surrounds the fourth conductive metal material 136.

[0064] In an alternative embodiment, the semiconductor device includes a first conductive metal material 118 and a ring structure 124, wherein the ring structure surrounds the first conductive metal material 118.

[0065] In some embodiments, the semiconductor device further includes a second conductive metal material 132 formed beneath the first conductive metal material 118, and an annular structure 124 surrounding the second conductive metal material 132, wherein the second conductive metal material 132 is formed of a material different from the first conductive metal material 118. In some embodiments, the semiconductor device further includes a third conductive metal material 134 formed beneath the second conductive metal material 132, and an annular structure 124 surrounding the third conductive metal material 134, wherein the third conductive metal material 134 is formed of a material different from the second conductive metal material 132. In some embodiments, the annular structure is formed of the same material as the second conductive metal material 132. In some embodiments, the semiconductor device further includes solder material 130 located above the first conductive metal material 118 and surrounded by the annular structure 124. In some embodiments, the semiconductor device further includes a second interconnect structure 170, wherein the solder material 130 is located between the first interconnect structure 160 and the second interconnect structure 170. In some embodiments, the annular structure 124 surrounds the second conductive metal material 132 and the third conductive metal material 134.

[0066] In an alternative embodiment, the method 2200 for forming a semiconductor device includes forming microbumps 150 over a seed layer 112, forming an annular structure 124 on the bumps 150, and plating solder material 130 partially surrounded by the annular structure 124.

[0067] In some embodiments, forming the bump 150 above the seed layer 112 further includes a patterned photoresist layer 114 to form a bump cavity 116, and a first conductive metal material 118 is plated within the bump cavity 116. In some embodiments, method 2200 further includes plating a second conductive metal material 132 within the bump cavity 116, wherein the first conductive metal material 118 is plated above the second conductive metal material 132. In some embodiments, method 2200 further includes plating a third conductive metal material 134 within the bump cavity 116, wherein the second conductive metal material 132 is plated above the third conductive metal material 134. In some embodiments, forming the annular structure 124 further includes a patterned photoresist layer 120 to form an annular cavity 122, and an annular conductive metal material is plated within the annular cavity 122 to form the annular structure 124. In some embodiments, the annular cavity 122 is patterned to extend above the bump 150. In some embodiments, the annular cavity 122 is patterned to surround the bump 150. In some embodiments, the method further includes forming a second bump 160, wherein solder material 130 is located between bump 160 and second bump 170.

[0068] The various embodiments disclosed herein offer various advantages and improvements. For example, the various embodiments disclosed herein may include a ring-shaped structure surrounding a portion of the solder. Therefore, the various embodiments disclosed herein can prevent bump bridging by ensuring that individual microbumps remain separated during the reflow process. By preventing bump bridging, the various embodiments improve the reliability testing of semiconductor devices, such as HTS testing. Additionally, the various embodiments disclosed herein prevent bump tilting by ensuring that microbumps are formed perpendicular to the substrate or interposer during the reflow process. By preventing bump tilting, the various embodiments improve the mechanical strength of the microbumps to reduce mechanical failure, thereby improving the performance and reliability of the semiconductor device. The various embodiments disclosed herein can further improve the electrical connection between the substrate and the semiconductor die via bumps by improving the interconnect structure formed during the reflow process.

[0069] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0070] 102:Substrate 103, 104: Passivation layer 105: Semiconductor die 106, 107: Dielectric layer 108, 116: Bump cavity 110, 111: Metal structure under the bump 112, 113: Seed layers 114: Photoresist layer 118, 119: First conductive metallic material 120: Second photoresist layer 122: Annular cavity 124, 125: Ring structure 126: Third photoresist layer 128: Solder cavity 130: Solder materials 132, 133: Second conductive metallic material 134, 135: Third conductive metal material 136: Fourth Conductive Metal Material 140: Metal interconnect 142: Substrate bonding pad 150: Interconnection Structure 160: Top bump 170: Bottom bump 2300: Method 2302, 2304, 2306, 2308, 2310, 2312, 2314: Steps hd1: First horizontal direction hd2: Second horizontal direction

Claims

1. A semiconductor device, comprising: A first interconnect structure on a first semiconductor substrate, wherein the first interconnect structure includes a first conductive metal material and an annular structure extending above the first conductive metal material, and further includes a second conductive metal material formed beneath the first conductive metal material, wherein the first conductive metal material is formed of a material based on conductive properties, and the second conductive metal material is formed of a material based on anti-wetting properties.

2. The semiconductor device as claimed in claim 1, wherein the annular structure is formed of the same material as the second conductive metal material.

3. The semiconductor device of claim 1 further includes a third conductive metal material formed beneath the second conductive metal material, wherein the third conductive metal material is formed of a material based on conductive properties.

4. The semiconductor device of claim 1 further includes a solder material located above the first conductive metal material and surrounded by the annular structure.

5. The semiconductor device of claim 4, further comprising a second interconnect structure, wherein the solder material is located between the first interconnect structure and the second interconnect structure.

6. A semiconductor device, comprising: A first interconnect structure is formed over a first semiconductor substrate, wherein the first interconnect structure includes a first conductive metal material and a ring structure, wherein the ring structure surrounds a portion of the first conductive metal material, and further includes a second conductive metal material formed beneath the first conductive metal material, wherein the first conductive metal material is formed of a material based on conductive properties, and the second conductive metal material is formed of a material based on anti-wetting properties.

7. The semiconductor device of claim 6, wherein the annular structure is formed of the same material as the second conductive metal material.

8. The semiconductor device as claimed in claim 6, wherein the annular structure surrounds the second conductive metal material.

9. A method of forming a semiconductor device, comprising: Forming bumps above a seed layer, wherein forming the bumps above the seed layer further includes: patterning a photoresist layer above the seed layer to form a bump cavity; plating a first conductive metal material inside the bump cavity; and plating a second conductive metal material inside the bump cavity, wherein the first conductive metal material is plated over the second conductive metal material, the first conductive metal material being formed of a material based on conductive properties, and the second conductive metal material being formed of a material based on anti-wetting properties; forming an annular structure on the bump; and plating solder material partially surrounded by the annular structure.

10. The method of claim 9, further comprising forming a second bump, wherein the solder material is located between the bump and the second bump.

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