Circuit configuration device and method

Abstract

This case discloses a circuit configuration apparatus and method. The method is applicable to buck converter circuits and includes the following steps: evaluating an inductance range suitable for the buck converter circuit according to its design specifications; testing multiple efficiency curves corresponding to multiple inductance values ​​within the inductance range according to the design specifications and the inductance range; analyzing the efficiency curves to obtain one or more efficiency curve intersection points; and planning an inductance region configured on the buck converter circuit based on the inductance range and the efficiency curve intersection points. The inductance region includes one or more inductor groups. Each inductor group is formed by encapsulating multiple inductor elements connected in series. The circuit inductance formed by the inductance region varies with the state of the buck converter circuit.

Description

Technical Field

[0001] This invention relates to a circuit configuration device and method that can improve circuit efficiency. Prior Technology

[0002] With increasingly stringent energy regulations governing electronic products, energy conservation has become a crucial design principle. Current electronic products often switch between light and heavy load states depending on usage scenarios. However, current circuit designs can only improve energy consumption for a single state. Summary of the Invention

[0003] This invention provides a circuit configuration apparatus suitable for configuring a step-down circuit. The circuit configuration apparatus includes a storage device and a circuit configuration processor. The storage device stores the design specifications of the step-down circuit. The circuit configuration processor is coupled to the storage device and loads the design specifications to perform the following: evaluating an inductance range suitable for the step-down circuit according to the design specifications; testing multiple efficiency curves corresponding to multiple inductance values ​​within the inductance range according to the design specifications and the inductance range; analyzing the efficiency curves to obtain one or more efficiency curve intersection points; and planning an inductor region configured on the step-down circuit based on the inductance range and the efficiency curve intersection points. The inductor region includes one or more inductor groups. Each inductor group is formed by encapsulating multiple inductor elements connected in series. The circuit inductance formed by the inductor region varies with the state of the step-down circuit.

[0004] This application also provides a circuit configuration method applicable to buck converter circuits. The circuit configuration method includes the following steps: evaluating the inductance range suitable for the buck converter circuit according to its design specifications; testing multiple efficiency curves corresponding to multiple inductance values ​​within the inductance range, based on the design specifications and the inductance range; analyzing the efficiency curves to obtain one or more efficiency curve intersection points; and planning the inductance region configured on the buck converter circuit based on the inductance range and the efficiency curve intersection points. The inductance region includes one or more inductor groups. Each inductor group is formed by encapsulating multiple inductor elements connected in series. The circuit inductance formed by the inductance region varies with the state of the buck converter circuit.

[0005] Based on the above, the circuit configuration device and method of this case can ensure that the planned step-down circuit maintains a high efficiency value regardless of whether it is under light load or heavy load. In this way, the energy consumption of the circuit under both light and heavy loads can be reduced simultaneously, thereby significantly improving circuit efficiency.

[0006] To make the above-mentioned features and advantages of this case more apparent and understandable, specific embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0007] Figure 1 is a block diagram illustrating a circuit configuration device according to an embodiment of the present invention. Figure 2 is a block diagram of a storage device according to an embodiment of the present invention. Figure 3 is a circuit architecture diagram of a step-down circuit according to an embodiment of the present invention. Figure 4 is a flowchart illustrating a line configuration method according to an embodiment of the present invention. Figure 5 is an example of an efficiency curve plotted according to an embodiment of the present invention. Figure 6A is a schematic diagram illustrating the relationship between the current value flowing through the inductor region and the efficiency value and inductance, according to an embodiment of the present invention. Figure 6B is a schematic diagram illustrating the relationship between the current value flowing through the inductor region and the output voltage according to an embodiment of the present invention. Figures 7A and 7B are circuit architecture diagrams of a step-down circuit according to an embodiment of the present invention. Implementation

[0008] Referring to Figure 1, the line configuration device 100 in this embodiment is, for example, an electronic device such as a personal computer, smartphone, personal digital assistant (PDA), notebook computer, tablet computer, or server, including a storage device 110 and a line configuration processor 120.

[0009] Storage device 110 may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or similar components or combinations thereof. Storage device 110 is used to store computer programs executable by line configuration processor 120 and the data used therein.

[0010] In detail, as shown in Figure 2, the storage device 110 stores relevant information for configuring the step-down line 300, including the design specification 200 for the step-down line 300. The design specification 200 includes a compilation of design guidelines and rules for the step-down line 300. An example of the circuit architecture of the step-down line 300 can be found later.

[0011] Line configuration processor 120 is coupled to storage device 110. Line configuration processor 120 is, for example, a central processing unit, or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), or other similar or combined components. In this embodiment, line configuration processor 120 can load design specification 200 from storage device 110 to execute the line configuration method of this embodiment.

[0012] The line configuration device of this invention is applicable to configuring a step-down line 300 supplying power. As shown in FIG3, the step-down line 300 includes an input capacitor Cin, a first switch SW1, a second switch SW2, an inductor region 310, and an output capacitor Cout. The first end of the input capacitor Cin is coupled to the input terminal IN of the step-down line 300, and the second end of the input capacitor Cin is grounded. The first end of the first switch SW1 is coupled to the input terminal IN of the step-down line 300. The first end of the second switch SW2 is coupled to the second end of the first switch SW1, and the second end of the second switch SW2 is grounded. The inductor region 310 is coupled between the second end of the first switch SW1 and the output terminal OUT of the step-down line 300. The first end of the output capacitor Cout is coupled to the output terminal OUT of the step-down line 300, and the second end of the output capacitor Cout is grounded. The inductor region 310 includes one or more inductor groups (e.g., a first inductor group 312), each inductor group being formed by encapsulating multiple inductor elements (e.g., a first inductor element L1 and a second inductor element L2) connected in series. In this embodiment, the inductance values ​​of each inductor element within the inductor group are different. Therefore, the line inductance formed by the inductor region 310 will vary depending on the state of the step-down line 300. For example, as the current flowing through the inductor region 310 increases, some inductors with larger inductance values ​​within the inductor region 310 will gradually become resistive elements. Therefore, the line inductance under light load conditions with smaller current flowing through the inductor region 310 will be greater than the line inductance under heavy load conditions with larger current flowing through the inductor region 310.

[0013] The input terminal IN of the buck converter 300 can receive an input voltage Vin provided by a power adapter (e.g., an AC adapter, PD adapter, etc.) or a battery. The output terminal OUT of the buck converter 300 can transmit the output voltage Vout, for example via a voltage regulator, to a central processing unit (CPU), graphics processing unit (GPU), and various other system components on the motherboard. The first switch SW1 and the second switch SW2 can be implemented, for example, with an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET), but the invention is not limited thereto.

[0014] Please refer to Figures 1 to 4 simultaneously. The line configuration method of this embodiment can be applied to the line configuration device 100 in Figure 1. The steps are described below.

[0015] First, in step S400, the line configuration processor 120 evaluates the appropriate inductance range for the buck line 300 according to the design specification 200 of the buck line 300. For example, the appropriate inductance range for the buck line 300 is 0.15 to 0.36 microhenries.

[0016] Next, in step S402, the line configuration processor 120 tests and obtains a first efficiency curve C1 and a second efficiency curve C2 corresponding to the inductance values ​​within the inductance range, according to design specification 200 and the inductance range. For example, the first efficiency curve C1 and the second efficiency curve C2 conform to design specification 200 and correspond to the first inductance value Id1 (e.g., 0.36 microhenries) and the second inductance value Id2 (e.g., 0.15 microhenries) within the evaluated inductance range suitable for the buck circuit 300, respectively. Figure 5 shows an example of the curves of the first efficiency curve C1 and the second efficiency curve C2. The horizontal axis of Figure 5 represents the current value flowing through the inductor region 310, and the vertical axis represents the efficiency value. The first efficiency curve C1 is the curve obtained when the inductor region 310 is configured with the first inductance value Id1, and the second efficiency curve C2 is the curve obtained when the inductor region 310 is configured with the second inductance value Id2. In this embodiment, the efficiency value is the ratio of the inductor's output energy to its input energy.

[0017] Next, in step S404, the line configuration processor 120 analyzes the first efficiency curve C1 and the second efficiency curve C2 to obtain the intersection point P1 of the first efficiency curve C1 and the second efficiency curve C2 as shown in Figure 5. The current value Ith at the efficiency curve intersection point P1 is, for example, 10 amperes, which can be regarded as the optimal point for switching the line inductance.

[0018] Finally, in step S406, the line configuration processor 120 plans the inductance region 310 configured on the step-down line 300 based on the inductance range and efficiency curve intersection point P1 of the step-down line 300. In this embodiment, the planned inductance region 310 includes a first inductor group 312 formed by packaging a first inductor element L1 and a second inductor element L2 connected in series. The rated inductance value of the second inductor element L2 (e.g., 0.21 microhenries) is greater than the rated inductance value of the first inductor element L1 (e.g., 0.15 microhenries).

[0019] When the step-down line 300 is under light load, the current IL flowing through the inductor region 310 is less than the current value Ith at the intersection point P1 of the efficiency curves C1 and C2. The line inductance of the step-down line 300 is equivalent to the sum of the inductance of the first inductor element L1 and the second inductor element L2 in the first inductor group 312 (the line inductance is high inductance). That is, the line inductance at this time is approximately equivalent to the first inductance Id1 (e.g., 0.36 microhenries) corresponding to the first efficiency curve C1, which corresponds to the sum of the inductance of the first inductor element L1 and the second inductor element L2 in the first inductor group 312.

[0020] When the step-down circuit 300 is under heavy load, it means that the current IL flowing through the inductor region 310 is greater than the current value Ith at the intersection point P1 of the efficiency curves of the first efficiency curve C1 and the second efficiency curve C2. The second inductor element L2 in the first inductor group 312 then becomes a resistive element, and the line inductance of the step-down circuit 300 is equivalent to the inductance of the first inductor element L1 in the first inductor group 312. In other words, the line inductance at this time is approximately equivalent to the second inductance Id2 (e.g., 0.15 microhenries) corresponding to the second efficiency curve C2, which in turn corresponds to the inductance of the first inductor element L1 in the first inductor group 312.

[0021] The following example illustrates the technical effect of improving circuit efficiency in this case. In Figure 6A, the horizontal axis represents the current flowing through inductor region 310, the vertical axis corresponding to the first efficiency curve C1 and the second efficiency curve C2 represents the efficiency value on the left, and the vertical axis corresponding to the line inductance curve C3 of the step-down circuit 300 represents the inductance on the right. When the step-down circuit 300 is under light load, the current IL flowing through inductor region 310 is less than the current value Ith at the intersection point P1 of the first efficiency curve C1 and the second efficiency curve C2. The line inductance curve C3 remains at the first inductance value Id1, and the corresponding efficiency curve is the first efficiency curve C1.

[0022] When the step-down circuit 300 is under heavy load, the current IL flowing through the inductor region 310 is greater than the current value Ith at the intersection point P1 of the first efficiency curve C1 and the second efficiency curve C2. Since the second inductor L2 in the first inductor group 312 becomes a resistive element, the circuit inductance curve C3 drops and transforms into the second inductance curve Id2, and the corresponding efficiency curve becomes the second efficiency curve C2. Based on the above circuit configuration, regardless of whether the step-down circuit 300 is under light load or heavy load, the corresponding efficiency curve is the one with the higher efficiency value (represented by a solid line). In this way, both light load and heavy load energy consumption can be reduced simultaneously, thereby significantly improving circuit efficiency.

[0023] On the other hand, in Figure 6B, the horizontal axis represents the current flowing through the inductor region 310, and the vertical axis represents the output terminal OUT of the buck circuit 300, which represents the output voltage Vout. When the buck circuit 300 is under light load, the ripple waveform of the output voltage Vout is wider due to the larger inductance of the circuit. When the buck circuit 300 is under heavy load, the ripple waveform of the output voltage Vout is narrower due to the smaller inductance of the circuit.

[0024] In the foregoing embodiment, the first inductor group 312 included in the planned inductor region 310 is formed by encapsulating a first inductor element L1 and a second inductor element L2 in series, but the present invention is not limited thereto. Those skilled in the art can, according to their actual needs and with reference to the teachings of this embodiment, extrapolate the number of inductor elements in the inductor group to a greater extent based on the analysis results of more efficiency curves.

[0025] In other embodiments of the present invention, those skilled in the art can, according to their actual needs and with reference to the teachings of this embodiment, plan an inductor region comprising multiple inductor groups connected in series or in parallel. For example, in FIG7A, the buck circuit 700 includes an input capacitor Cin, a first switch SW1, a second switch SW2, an inductor region 710, and an output capacitor Cout. The inductor region 710 is coupled between the second terminal of the first switch SW1 and the output terminal OUT of the buck circuit 700, and includes a first inductor group 712 and a second inductor group 714. The first inductor group 712 and the second inductor group 714 are connected in series. When the buck circuit 700 is under light load, the line inductance of the buck circuit 700 is equivalent to the sum of the inductance of the first inductor element L1 in the first inductor group 712 and the second inductor element L2 in the second inductor group 714.

[0026] When the step-down circuit 700 is under heavy load, the second inductor L2 in the first inductor group 712 and the second inductor group 714 becomes a resistive element. At this time, the line inductance of the step-down circuit 700 is equivalent to the sum of the inductance of the first inductor L1 in the first inductor group 712 and the second inductor group 714.

[0027] In Figure 7B, the buck circuit 800 includes an input capacitor Cin, a first switch SW1, a second switch SW2, an inductor region 810, and an output capacitor Cout. The inductor region 810 is coupled between the second terminal of the first switch SW1 and the output terminal OUT of the buck circuit 800, and includes a first inductor group 812 and a second inductor group 814. The first inductor group 812 and the second inductor group 814 are connected in parallel. The inductance of the circuit formed by the inductor region 810 also changes with the state of the buck circuit 800. Therefore, both series and parallel inductor circuits can be widely applied by this invention.

[0028] In practical applications, although the appearance of the inductor region of the present invention is also that of a single-structure inductor (which can occupy a relatively small space), its internal structure is composed of two or more inductor elements with different characteristics, and has multiple inductance levels and multiple characteristics.

[0029] In summary, the circuit configuration device and method of the present invention enable the planned step-down circuit to achieve relatively high efficiency values ​​regardless of whether it is under light or heavy load conditions. This simultaneously reduces both light-load and heavy-load energy consumption, thereby significantly improving circuit efficiency and complying with energy regulations.

[0030] 100: Line configuration device 110: Storage device 120: Line Configuration Processor 200: Design Specifications 300, 700, 800: Step-down circuits 310, 710, 810: Inductor region 312, 712, 812: First inductor group 714, 814: Second inductor group C1: First efficiency curve C2: Second efficiency curve C3: Line inductance curve Cin: Input capacitance Cout: Output capacitor Id1: First inductance value Id2: Second inductance Ith: Current value at the intersection of the efficiency curves IN: Input terminal L1: First inductor element L2: Second inductor element OUT: Output terminal P1: Crossing point of efficiency curves SW1: First switch SW2: Second switch Vin: Input voltage Vout: Output voltage S400~S406: Steps

Claims

1. A line configuration device, suitable for configuring a step-down line, the line configuration device comprising: A storage device for storing a design specification of the step-down circuit; The system also includes a line configuration processor coupled to the storage device for loading the design specification to perform the following: evaluating an inductance range suitable for the buck circuit according to the design specification; testing multiple efficiency curves corresponding to multiple inductance values ​​within the inductance range according to the design specification and the inductance range; analyzing the efficiency curves to obtain one or more efficiency curve intersection points; and planning an inductance region configured on the buck circuit based on the inductance range and the one or more efficiency curve intersection points, wherein the inductance region includes one or more inductor groups, each of which is formed by encapsulating multiple inductor elements connected in series, and the line inductance formed by the inductance region varies with the state of the buck circuit.

2. The line configuration apparatus as described in claim 1, wherein the step-down line comprises: An input capacitor, the first end of which is coupled to an input terminal of the buck circuit, and the second end of which is grounded; a first switch, the first end of which is coupled to the input terminal of the buck circuit; a second switch, the first end of which is coupled to a second terminal of the first switch, and the second terminal of which is grounded; an inductor region, coupled between the second terminal of the first switch and an output terminal of the buck circuit; and an output capacitor, the first end of which is coupled to the output terminal of the buck circuit, and the second end of which is grounded.

3. The line configuration apparatus as claimed in claim 1, wherein each of the one or more inductor groups includes a first inductor element and a second inductor element, the second inductor element having a rated inductance value greater than that of the first inductor element.

4. The line configuration apparatus as claimed in claim 3, wherein the inductance region includes a first inductor group, and when the step-down line is in a light load state, the line inductance is equivalent to the sum of the inductance of the first inductor element in the first inductor group and the inductance of the second inductor element in the first inductor group.

5. The line configuration apparatus as claimed in claim 4, wherein when the step-down line is under heavy load, the second inductor in the first inductor group becomes a resistive element, and the line inductance is equivalent to the inductance of the first inductor in the first inductor group.

6. The line configuration apparatus as claimed in claim 5, wherein the efficiency curves include a first efficiency curve and a second efficiency curve, the first efficiency curve corresponding to the sum of the inductance of the first inductor element in the first inductor group and the inductance of the second inductor element in the first inductor group, the second efficiency curve corresponding to the inductance of the first inductor element in the first inductor group, wherein when the step-down line is in the light load state, it indicates that the current flowing through the inductor region is less than the current value at the intersection of the efficiency curves of the first efficiency curve and the second efficiency curve, and when the step-down line is in the heavy load state, it indicates that the current flowing through the inductor region is greater than the current value at the intersection of the efficiency curves of the first efficiency curve and the second efficiency curve.

7. The line configuration device as claimed in claim 3, wherein the inductance region includes a first inductor group and a second inductor group, the first inductor group and the second inductor group being connected in series, and when the step-down line is under a light load, the line inductance is equivalent to the sum of the inductance of the first inductor element in the first inductor group and the second inductor group and the inductance of the second inductor element in the first inductor group and the second inductor group.

8. The line configuration apparatus as claimed in claim 7, wherein when the step-down line is under heavy load, the second inductor element in the first inductor group and the second inductor group becomes a resistive element, and the line inductance is equivalent to the sum of the inductances of the first inductor element in the first inductor group and the second inductor group.

9. A circuit configuration method applicable to a step-down circuit, the circuit configuration method comprising the following steps: evaluating an inductance range suitable for the step-down circuit according to a design specification of the step-down circuit; testing multiple efficiency curves corresponding to multiple inductances within the inductance range according to the design specification and the inductance range; analyzing the efficiency curves to obtain one or more efficiency curve intersection points; and planning an inductance region configured on the step-down circuit according to the inductance range and the one or more efficiency curve intersection points, wherein... The inductor region includes one or more inductor groups, each of which is formed by encapsulating multiple inductor elements connected in series. The inductance of the line formed by the inductor region varies with the state of the step-down line.

10. The line configuration method as described in claim 9, wherein the step-down line comprises: An input capacitor, the first end of which is coupled to an input terminal of the buck circuit, and the second end of which is grounded; a first switch, the first end of which is coupled to the input terminal of the buck circuit; a second switch, the first end of which is coupled to a second terminal of the first switch, and the second terminal of which is grounded; an inductor region, coupled between the second terminal of the first switch and an output terminal of the buck circuit; and an output capacitor, the first end of which is coupled to the output terminal of the buck circuit, and the second end of which is grounded.

11. The line configuration method as claimed in claim 9, wherein each of the one or more inductor groups includes a first inductor element and a second inductor element, the second inductor element having a rated inductance value greater than that of the first inductor element.

12. The line configuration method as claimed in claim 11, wherein the inductance region includes a first inductor group, and when the step-down line is in a light load state, the line inductance is equivalent to the sum of the inductance of the first inductor element in the first inductor group and the inductance of the second inductor element in the first inductor group.

13. The line configuration method as claimed in claim 12, wherein when the step-down line is under heavy load, the second inductor in the first inductor group becomes a resistive element, and the line inductance is equivalent to the inductance of the first inductor in the first inductor group.

14. The line configuration method as described in claim 13, wherein the efficiency curves include a first efficiency curve and a second efficiency curve, the first efficiency curve corresponding to the sum of the inductance of the first inductor element in the first inductor group and the inductance of the second inductor element in the first inductor group, the second efficiency curve corresponding to the inductance of the first inductor element in the first inductor group, wherein when the step-down line is in the light load state, it indicates that the current flowing through the inductor region is less than the current value at the intersection of the efficiency curves of the first efficiency curve and the second efficiency curve, and when the step-down line is in the heavy load state, it indicates that the current flowing through the inductor region is greater than the current value at the intersection of the efficiency curves of the first efficiency curve and the second efficiency curve.

15. The line configuration method as claimed in claim 11, wherein the inductance region includes a first inductor group and a second inductor group, the first inductor group and the second inductor group being connected in series, and when the step-down line is under a light load, the line inductance is equivalent to the sum of the inductance of the first inductor element in the first inductor group and the second inductor group and the inductance of the second inductor element in the first inductor group and the second inductor group.

16. The line configuration method as claimed in claim 15, wherein when the step-down line is under heavy load, the second inductor element in the first inductor group and the second inductor group are converted into resistive elements, and the line inductance is equivalent to the sum of the inductances of the first inductor element in the first inductor group and the second inductor group.

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