Display device

Abstract

One embodiment of the present invention provides a display device comprising: a substrate having a display area for displaying an image and a peripheral area surrounding the display area; a plurality of display elements disposed in the display area, each comprising: a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode, emitting light upon application of voltage; a first partition wall disposed in the display area and between adjacent display elements; and a second partition wall disposed in the peripheral area and connected to the first partition wall. The first and second partition walls each comprise: a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion. Furthermore, the second partition wall has a plurality of elongated openings.

Description

Technical Field

[0001] The present invention relates to a display device. Prior Technology

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. For such display devices, technologies capable of improving yield and reliability are essential. Summary of the Invention

[0003] Generally speaking, according to an embodiment, the display device includes: a substrate having a display area for displaying an image and a peripheral area surrounding the display area; a plurality of display elements disposed in the display area, each comprising: a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode, emitting light upon application of voltage; a first partition wall disposed in the display area and between adjacent display elements; and a second partition wall disposed in the peripheral area and connected to the first partition wall. The first and second partition walls each include: a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion. Furthermore, the second partition wall has a plurality of elongated openings.

[0004] Depending on the implementation, a display device can be provided that can improve yield or increase reliability. Simple Explanation of the Diagram

[0005] Figure 1 is a diagram showing an example of the configuration of the display device in the first embodiment.

[0006] Figure 2 is a schematic top view showing an example of the layout of subpixels.

[0007] Figure 3 is a schematic cross-sectional view of the display device along line III-III in Figure 2.

[0008] Figure 4 is a schematic top view of a display device used to illustrate the structure of the surrounding area.

[0009] Figure 5 is a schematic cross-sectional view of a portion of the area surrounding the VV line in Figure 4.

[0010] Figure 6 is a schematic enlarged cross-sectional view of a portion of the partition wall located in the surrounding area.

[0011] Figure 7 is a schematic enlarged top view of region VII in Figure 4.

[0012] Figure 8 is a schematic enlarged top view of region VIII in Figure 4.

[0013] Figure 9A is a schematic cross-sectional view showing one example of the manufacturing process of a display device.

[0014] Figure 9B is a schematic cross-sectional view showing the process that continues from Figure 9A.

[0015] Figure 9C is a schematic cross-sectional view showing the process that continues from Figure 9B.

[0016] Figure 9D is a schematic cross-sectional view showing the process that continues in Figure 9C.

[0017] Figure 9E shows a schematic cross-sectional view of the process that continues in Figure 9D.

[0018] Figure 9F is a schematic cross-sectional view showing the process that continues in Figure 9E.

[0019] Figure 9G shows a schematic cross-sectional view of the process that continues in Figure 9F.

[0020] Figure 9H is a schematic cross-sectional view showing the process that continues in Figure 9G.

[0021] Figure 9I is a schematic cross-sectional view showing the process that continues in Figure 9H.

[0022] Figure 10 is a schematic top view of the surrounding area of ​​the comparative example.

[0023] Figure 11 is a schematic cross-sectional view of the surrounding area of ​​the comparative example described above.

[0024] Figure 12 is a schematic enlarged top view of the surrounding area of ​​the second embodiment.

[0025] Figure 13 is another schematic enlarged top view of the surrounding area of ​​the second embodiment. Implementation

[0026] Several implementation forms are described with reference to the diagrams.

[0027] The disclosure is ultimately just one example, and appropriate modifications that can be readily conceived by those skilled in the art to maintain the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the drawings may schematically show the width, thickness, shape, etc., of various parts compared to the actual form, but this is ultimately just one example and does not limit the interpretation of the invention. Also, in this specification and the drawings, sometimes the same reference numerals are used for constituent elements that perform the same or similar functions as the constituent elements described in the previously shown drawings, and repeated detailed descriptions are appropriately omitted.

[0028] Furthermore, in the diagram, the X-axis, Y-axis, and Z-axis, which are orthogonal to each other, are shown as needed for ease of understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane that includes the X-direction and the Y-direction. Also, observing various elements parallel to the Z-direction is called a top view.

[0029] The display devices in each embodiment are organic electroluminescent display devices with organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle machines, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0030] [First Implementation Form]

[0031] Figure 1 is a diagram showing an example of the configuration of a display device DSP according to a first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0032] In this embodiment, the shape of the substrate 10 and the display area DA viewed from above is rectangular. However, the shape of the substrate 10 and the display area DA viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an oval.

[0033] The display area DA has a plurality of pixels PX arranged in a matrix along the X and Y directions. Each pixel PX contains a plurality of sub-pixels SP that display different colors. In this embodiment, it is envisioned that pixel PX contains a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, pixel PX may contain sub-pixels SP of other colors such as white, either together with or in place of sub-pixels SP1, SP2, and SP3.

[0034] The display device DSP further includes a terminal section T disposed in the peripheral area SA. A flexible circuit board for supplying, for example, voltage or signals for driving the display device DSP is connected to the terminal section T.

[0035] The sub-pixel SP has: a pixel circuit 1, and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements made of, for example, thin-film transistors.

[0036] The display area DA is configured with: a plurality of scan lines G supplying scan signals to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines S supplying image signals to the pixel circuit 1 of each sub-pixel SP, and a plurality of power lines PL. In the example of Figure 1, the scan lines G and power lines PL extend along the X direction, and the signal lines S extend along the Y direction, but this is not limited to this example.

[0037] The gate electrode of pixel switch 2 is connected to scan line G. One of the source electrode and drain electrode of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source electrode and drain electrode is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0038] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may include more thin-film transistors and capacitors.

[0039] Figure 2 is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Figure 2, subpixels SP2 and SP3 are arranged along the X direction with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged along the Y direction.

[0040] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA is formed by: rows consisting of sub-pixels SP2 and SP3 arranged alternately along the Y direction, and rows consisting of a plurality of sub-pixels SP1 arranged repeatedly along the Y direction. These rows are arranged alternately along the X direction. Furthermore, the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0041] A rib layer 5 is configured in the display area DA. The rib layer 5 has pixel apertures AP51, AP52, and AP53 in sub-pixels SP1, SP2, and SP3, respectively. In the example of Figure 2, pixel aperture AP51 is larger than pixel aperture AP52, and pixel aperture AP52 is larger than pixel aperture AP53. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio.

[0042] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP51. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP52. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP53.

[0043] The portion of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel opening AP51 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel opening AP52 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel opening AP53 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include the cover layer described later. Rib layer 5 surrounds each of the display elements DE1, DE2, and DE3.

[0044] A conductive partition wall 6A (first partition wall) is disposed on the rib layer 5. The partition wall 6A overlaps the rib layer 5 in its entirety and has the same planar shape as the rib layer 5. That is, the partition wall 6A has pixel openings AP61, AP62, and AP63 in sub-pixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition wall 6A appear as a lattice structure when viewed from above, surrounding each of the sub-pixels SP1, SP2, and SP3. The partition wall 6A serves as a wiring to supply a common voltage to the upper electrodes UE1, UE2, and UE3.

[0045] Figure 3 is a schematic cross-sectional view of the display device DSP along line III-III in Figure 2. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by the circuit layer 11.

[0046] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by rib layer 5. Although not shown in the cross-section of FIG3, the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0047] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. Consequently, the two ends of the upper portion 62 protrude more than the sides of the lower portion 61. The shape of this partition wall 6A is described as overhanging.

[0048] In the example of Figure 3, the lower part 61 has: a bottom layer 63 disposed on the rib layer 5, and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Also, in the example of Figure 3, the two ends of the bottom layer 63 protrude from the side of the shaft layer 64.

[0049] Organic layer OR1 covers lower electrode LE1 via pixel opening AP51. Upper electrode UE1 covers organic layer OR1 and faces lower electrode LE1. Organic layer OR2 covers lower electrode LE2 via pixel opening AP52. Upper electrode UE2 covers organic layer OR2 and faces lower electrode LE2. Organic layer OR3 covers lower electrode LE3 via pixel opening AP53. Upper electrode UE3 covers organic layer OR3 and faces lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower part 61 of partition wall 6A.

[0050] Display element DE1 includes a cover layer CP1 disposed on the upper electrode UE1. Display element DE2 includes a cover layer CP2 disposed on the upper electrode UE2. Display element DE3 includes a cover layer CP3 disposed on the upper electrode UE3. Cover layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3.

[0051] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as stacked film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as stacked film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as stacked film FL3.

[0052] A portion of the laminated film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminated film FL1 surrounding the separator wall 6A (the portion constituting display element DE1). Similarly, a portion of the laminated film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminated film FL2 surrounding the separator wall 6A (the portion constituting display element DE2). Furthermore, a portion of the laminated film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminated film FL3 surrounding the separator wall 6A (the portion constituting display element DE3).

[0053] Sealing layers SE11, SE12, and SE13 are respectively disposed in sub-pixels SP1, SP2, and SP3. Sealing layer SE11 continuously covers the overlay layer CP1 and the partition wall 6A surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the overlay layer CP2 and the partition wall 6A surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the overlay layer CP3 and the partition wall 6A surrounding sub-pixel SP3.

[0054] In the example of Figure 3, the laminated film FL1 and sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP2 are separated from the laminated film FL2 and sealing layer SE12 on the partition wall 6A. Furthermore, the laminated film FL1 and sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP3 are separated from the laminated film FL3 and sealing layer SE13 on the partition wall 6A.

[0055] Sealing layers SE11, SE12, and SE13 (first sealing layer) are covered by resin layer RS1 (first resin layer). Resin layer RS1 is covered by sealing layer SE2 (second sealing layer). Sealing layer SE2 is covered by resin layer RS2 (second resin layer). Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the peripheral area SA.

[0056] A polarizing plate, touch panel, protective film, or protective glass can be further disposed on top of the resin layer RS2. This cover component can be attached to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0057] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride oxide (SiON). In one example, the rib layer 5 is formed of silicon nitride oxide, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0058] The lower electrodes LE1, LE2, and LE3 have: a reflective layer formed of, for example, silver, and a pair of conductive oxide layers respectively covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0059] The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 are equivalent to anodes, and the upper electrodes UE1, UE2, and UE3 are equivalent to cathodes.

[0060] Organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked along the Z direction. However, organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure containing a plurality of light-emitting layers.

[0061] The capping layers CP1, CP2, and CP3 have a laminated structure formed by, for example, a plurality of overlapping transparent layers. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. In addition, at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0062] The bottom layer 63 and the axial layer 64 of the partition wall 6A are formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. Furthermore, the axial layer 64 can be formed of an insulating material.

[0063] For example, the upper portion 62 of the partition wall 6A has a laminated structure consisting of a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. As the metallic material forming the lower layer, materials such as titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys can be used. As the conductive oxide forming the upper layer, materials such as ITO or IZO can be used. Alternatively, the upper portion 62 may have a single-layer structure of metallic material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0064] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the image signals of the signal line S via the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0065] Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emitting layer of organic layer OR1 emits light in the blue wavelength band. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the emitting layer of organic layer OR2 emits light in the green wavelength band. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the emitting layer of organic layer OR3 emits light in the red wavelength band.

[0066] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can emit light of the same color (e.g., white). In this case, the display device DSP can have a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Furthermore, the display device DSP can have a layer containing quantum dots that generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3 excited by the light emitted by the light-emitting layers.

[0067] Figure 4 is a schematic top view of the display device DSP used to illustrate the structure of the peripheral region SA. The display device DSP further includes a partition wall 6B (second partition wall) disposed in the peripheral region SA. The partition wall 6B is formed using the same process as the partition wall 6A shown in Figures 2 and 3, and has the same structure as the partition wall 6A. In Figure 4, dotted patterns are used to indicate the area corresponding to the partition wall 6B. The partition wall 6B surrounds the display area DA.

[0068] The partition wall 6B has ends E1a, E1b, E1c, and E1d (the first to fourth ends). End E1a is located between the display area DA and the terminal portion T, and extends parallel to the X direction. End E1b is located on the opposite side of end E1a across the display area DA, and extends parallel to the X direction. End E1c connects the left ends of ends E1a and E1b in the diagram, and extends parallel to the Y direction. End E1d connects the right ends of ends E1a and E1b in the diagram, and extends parallel to the Y direction.

[0069] The display device DSP has a dam structure DS configured in the surrounding area SA. In the example of Figure 4, the dam structure DS includes rectangular dam sections DM1 and DM2.

[0070] Embankment section DM1 surrounds partition wall 6B. Embankment section DM2 surrounds embankment section DM1. A portion of embankment sections DM1 and DM2 passes between terminal section T and partition wall 6B.

[0071] Furthermore, the shapes of the weir sections DM1 and DM2 are not limited to the example in Figure 4. Also, the number of weir sections in the weir structure DS can be one or more.

[0072] Figure 5 is a schematic cross-sectional view of a portion of the surrounding region SA along line VV in Figure 4. The cross-sectional configuration shown in this figure can also be applied to any location within the surrounding region SA.

[0073] The circuit layer 11 shown in Figure 3 includes: inorganic insulating layers 31, 32, and 33 formed of inorganic insulating material; an organic insulating layer 34 formed of organic insulating material; and metal layers 41, 42, and 43. Inorganic insulating layer 31 covers the upper surface of substrate 10. Metal layer 41 is disposed on inorganic insulating layer 31. Inorganic insulating layer 32 covers metal layer 41. Metal layer 42 is disposed on inorganic insulating layer 32. Inorganic insulating layer 33 covers metal layer 42. Organic insulating layer 34 covers inorganic insulating layer 33. Metal layer 43 is disposed on organic insulating layer 34 and is covered by organic insulating layer 12.

[0074] Both dam portions DM1 and DM2 protrude upwards from the substrate 10. In the example shown in Figure 5, dam portion DM1 is formed from organic insulating layers 12 and 34. Dam portion DM2 is also formed from organic insulating layers 12 and 34 in the same way. That is, in this embodiment, dam portions DM1 and DM2 are formed using the same material and the same process as organic insulating layers 12 and 34.

[0075] Circuit layer 11 includes a feed line PW to which a common voltage is applied. The feed line PW is connected to terminal portion T shown in FIG. 4. In the example of FIG. 5, the feed line PW includes a first wiring W1 formed by metal layer 42 and a second wiring W2 formed by metal layer 43. The first wiring W1 and the second wiring W2 are in contact at the contact portion CN0 located between the end E0 of organic insulating layer 12 and dam portion DM1.

[0076] Within the surrounding area SA, a conductive relay layer RL and a rib layer 5 are further configured to connect the partition wall 6B and the feed line PW. The relay layer RL is formed, for example, using the same material and the same process as the aforementioned lower electrodes LE1, LE2, and LE3.

[0077] The relay layer RL is located on the side of the embankment section DM1 closer to the display area DA (left side in the figure), and is covered by an organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the embankment sections DM1 and DM2. The end of the rib layer 5 is located on the outer side of the embankment section DM2.

[0078] The partition wall 6B is disposed on the rib layer 5. The rib layer 5 has an opening in the contact portion CN1 that overlaps with the organic insulating layer 12 when viewed from above. The partition wall 6B contacts the relay layer RL in the contact portion CN1.

[0079] The relay layer RL contacts the second wiring W2 of the feeder line PW in the contact part CN2. The contact part CN2 is located between the end E0 of the organic insulation layer 12 and the dam part DM1 when viewed from above.

[0080] The separator 6B is covered by a laminated film FL. The laminated film FL is covered by a sealing layer SE1. The laminated film FL is any one of the laminated films FL1, FL2, and FL3 shown in Figure 3. The sealing layer SE1 is any one of the sealing layers SE11, SE12, and SE13 shown in Figure 3.

[0081] In the example of Figure 5, the end E2 of the laminated membrane FL and the sealing layer SE1 is located between the end E1a of the partition wall 6B and the dam section DM1. The laminated membrane FL is divided at end E1a. The sealing layer SE1 continuously covers each divided portion of the laminated membrane FL1. By dividing the laminated membrane FL in this way, the path of water infiltration through the laminated membrane FL can be blocked.

[0082] Above the sealing layer SE1, resin layer RS1, sealing layer SE2, and resin layer RS2, as shown in Figure 3, are disposed. Resin layer RS1 covers sealing layer SE1 and rib layer 5. The ends E2 of the laminated film FL and sealing layer SE1 are covered by resin layer RS1. The dam section DM1 serves to block the resin layer RS1 before curing during the manufacturing of the display device DSP.

[0083] In the example of Figure 5, the end Er1 of the resin layer RS1 is located above the embankment DM1. However, the position of the end Er1 is not limited to this example.

[0084] Sealing layer SE2 covers the end Er1 of resin layer RS1. Sealing layer SE2 contacts rib layer 5 in the area further outward from end Er1 (right side in the figure). In the example of Figure 5, end Es of sealing layer SE2 is located above dam section DM2. Resin layer RS1 is surrounded by sealing layer SE1, rib layer 5, and sealing layer SE2. This inhibits moisture infiltration into resin layer RS1.

[0085] Resin layer RS2 covers sealing layer SE2. The dam section DM2 serves to block the resin layer RS2 before curing during the manufacturing of the display device DSP. In this embodiment, the end Er2 of resin layer RS2 is located between the end Er1 of resin layer RS1 and the end Es of sealing layer SE2. More specifically, end Er2 is located above the dam section DM2. Furthermore, the position of end Er2 is not limited to the example in Figure 5.

[0086] Figure 6 is a schematic enlarged cross-sectional view of a portion of partition wall 6B. Partition wall 6B includes a lower portion 61 and an upper portion 62, similar to those of partition wall 6A. Furthermore, the lower portion 61 of partition wall 6B includes a bottom layer 63 and an axial layer 64.

[0087] In this embodiment, the partition wall 6B has a plurality of openings APx. The upper portion 62 of the edge Ex of each opening APx protrudes from the side of the shaft layer 64. That is, the edge Ex, like the partition wall 6A shown in FIG. 3, is overhanging. The ends E1a, E1b, E1c, and E1d of the partition wall 6B shown in FIG. 4 are also overhanging.

[0088] The laminated film FL is divided at the edge Ex. The sealing layer SE1 continuously covers each part of the divided laminated film FL.

[0089] Next, focusing on regions VII and VIII enclosed by the chain frame in Figure 4, the planar shape and configuration of the opening APx will be explained.

[0090] Figure 7 is a schematic enlarged top view of region VII. Figure 8 is a schematic enlarged top view of region VIII. In these figures, the partition walls 6A and 6B, the embankment sections DM1 and DM2, the intermediate layer RL, and the contact section CN1 are shown; other elements are omitted.

[0091] In Figures 7 and 8, the portions of the dotted patterns correspond to partition walls 6A and 6B. Partition walls 6A and 6B are formed as a single unit. Partition wall 6A has the aforementioned plurality of pixel openings AP61, AP62, and AP63. Partition wall 6B has the aforementioned plurality of openings APx.

[0092] The opening APx has a long, narrow shape. Specifically, the opening APx has a shape with rounded corners, forming a rectangle that is long along the Y direction. In one example, the width of the opening APx in the Y direction is 2 to 3 times the width of the opening APx in the X direction. Furthermore, the shape of the opening APx is not limited to this example. For instance, the opening APx may have a long, narrow shape along the X direction.

[0093] In the examples of Figures 7 and 8, two openings APx arranged along the X direction are configured close together. Furthermore, the pairs of openings APx are arranged along both the X and Y directions. For example, the spacing between the pairs of openings APx in the X and Y directions is the same as the spacing between the pixels PX in the X and Y directions. With this configuration, the density of the openings of the partition walls 6A and 6B is uniformized in the display area DA and the peripheral area SA. In this way, during the manufacturing of the display device DSP, it is possible to suppress the uneven erosion in the XY plane when etching the base layer of the partition walls 6A and 6B.

[0094] The partition wall 6B further has a plurality of slots SL1 (first slots) reaching any one of the ends E1a, E1b, E1c, E1d. These slots SL1 have a width smaller than, for example, the width in the short side direction of the opening APx (the X direction in the examples of FIG7 and FIG8).

[0095] Each slot SL1 is connected to at least one opening APx. In the following description, the opening APx connected to the slot SL1 is referred to as opening APx1 (first opening). Also, an independent opening APx not connected to the slot SL1 is referred to as opening APx2 (second opening).

[0096] For example, the slot SL1 with an opening at end E1a in Figure 7 and the slot SL1 with an opening at end E1b in Figure 8 have: a main stem ST extending parallel to the Y direction, and two branches BR intersecting the main stem ST and extending along the X direction. Furthermore, the two ends of each branch BR are respectively connected to the long side of the opening APx1. That is, all of these slots SL1 are connected to the four openings APx1.

[0097] Furthermore, the slot SL1 at the opening of end E1c in Figure 7 and the slot SL1 at the opening of end E1d in Figure 8 extend along the X direction and are mostly connected to the long side of the four openings APx1. However, the slots SL1 at the corners of ends E1a and E1c, and at the corners of ends E1b and E1d in the slot SL1 at the opening of end E1c are connected to the long side of one opening APx1.

[0098] Furthermore, the relationship between slot SL1 and opening APx1 is not limited to the relationship illustrated here. For example, there may be slot SL1 connected to 2 openings APx1, slot SL1 connected to 3 openings APx1, or slot SL1 connected to 5 or more openings APx1.

[0099] Here, as shown in Figures 7 and 8, a first region A1 and a second region A2 of the partition wall 6B are defined. The first region A1 is the portion along the ends E1a, E1b, E1c, and E1d of the partition wall 6B, including a plurality of slots SL1 and a plurality of openings APx1 connected to these slots SL1. The second region A2 is the portion located between the first region A1 and the display area DA, including a plurality of openings APx2 not connected to the slots SL1. The second region A2 surrounds the display area DA.

[0100] The boundary between region A1 and region A2 is located, for example, within a distance D from the embankment DM1. Distance D can be determined within, for example, a range of 100 to 300 μm. In one example, distance D is 200 μm.

[0101] Region A2 overlaps with the relay layer RL shown in Figure 5 in a top view. The relay layer RL surrounds, for example, the display area DA. The contact portions CN1 between the partition wall 6B and the relay layer RL are distributed at various locations in Region A2. In the examples of Figures 7 and 8, the contact portions CN1 are provided at positions that do not overlap with the opening APx2 in each of the following locations: between end E1a and display area DA, between end E1b and display area DA, between end E1c and display area DA, and between end E1d and display area DA.

[0102] Next, an example of a manufacturing method for a display device DSP will be described. Figures 9A to 9I are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 9A to 9I, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0103] When forming the display device DSP, firstly, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10. Secondly, as shown in FIG9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0104] Subsequently, as shown in Figure 9B, a rib layer 5 is formed covering the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The rib layer 5 can be formed using, for example, CVD (Chemical Vapor Deposition).

[0105] Furthermore, as shown in Figure 9C, a partition wall 6A is formed on the rib layer 5. Specifically, firstly, a layer forming the base layer 63, the axial layer 64, and the upper layer 62 is formed, and these layers are patterned by etching. In addition, the partition wall 6B shown in Figures 4 to 8 is formed using the same process as the partition wall 6A.

[0106] After the partition walls 6A and 6B are formed, as shown in FIG9D, pixel openings AP51, AP52, and AP53 are formed in the rib layer 5 by dry etching. In addition, in addition to this process, the rib layer 5 is subjected to multiple dry etchings. For example, these dry etchings include etching for forming the opening of the contact portion CN1 in the peripheral region SA in the rib layer 5.

[0107] After forming the rib layer 5 and the partition walls 6A and 6B, the process for forming display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is envisioned that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0108] When forming the display element DE1, firstly, as shown in FIG9E, a multilayer film FL1 and a sealing layer SE11 are formed. The multilayer film FL1, as shown in FIG3, includes: an organic layer OR1 that contacts the lower electrode LE1 via a pixel opening AP51, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by vapor deposition. Furthermore, the sealing layer SE11 is formed by CVD.

[0109] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA, but also in the peripheral area SA. The laminated film FL1 is divided into multiple parts by the hanging partitions 6A and 6B. The sealing layer SE11 continuously covers each of the divided parts of the laminated film FL1 and the partitions 6A and 6B.

[0110] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as shown in FIG9F, a resist R is disposed on the sealing layer SE11. The resist R covers a portion of the sub-pixel SP1 and the surrounding partition wall 6A.

[0111] Subsequently, as shown in Figure 9G, the portions of the stacked film FL1 and the sealing layer SE11 exposed from the resist R are removed by etching with the resist R as a mask. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 remain, while the rest are removed. This forms the display element DE1 on the sub-pixel SP1. This etching may include wet etching and dry etching performed sequentially on the sealing layer SE11, the cover layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0112] Display element DE2 is formed in the same sequence as display element DE1. That is, when forming display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed on the entire display area DA and the peripheral area SA. As shown in Figure 3, the multilayer film FL2 includes: an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP52, an upper electrode UE2 covering the organic layer OR2, and a cover layer CP2 covering the upper electrode UE2.

[0113] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into multiple parts by hanging partitions 6A and 6B. The sealing layer SE12 continuously covers each of the divided parts of the laminated film FL2 and the partitions 6A and 6B. By patterning this laminated film FL2 and the sealing layer SE2, as shown in Figure 9H, the display element DE2 is formed on the sub-pixel SP2.

[0114] Display element DE3 is formed in the same sequence as display elements DE1 and DE2. That is, when forming display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed on the entire display area DA and the peripheral area SA. As shown in Figure 3, the multilayer film FL3 includes: an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP53, an upper electrode UE3 covering the organic layer OR3, and a cover layer CP3 covering the upper electrode UE3.

[0115] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into multiple parts by suspended partitions 6A and 6B. The sealing layer SE13 continuously covers each of the divided parts of the laminated film FL3 and the partitions 6A and 6B. By patterning this laminated film FL3 and the sealing layer SE13, as shown in Figure 9I, the display element DE3 is formed on the sub-pixel SP3.

[0116] After forming display elements DE1, DE2, and DE3, resin layer RS1, sealing layer SE2, and resin layer RS2 as shown in Figure 3 are formed in sequence.

[0117] The laminated film FL shown in Figures 5 and 6 is, for example, the laminated film FL1 formed first among laminated films FL1, FL2, and FL3. Similarly, the sealing layer SE1 is the sealing layer SE11 formed first among sealing layers SE11, SE12, and SE13. In this way, if the sealing layer SE11 formed first remains in the peripheral area SA, the peripheral area SA can be protected from etching damage during the formation of display elements DE2 and DE3.

[0118] As another example, the laminated film FL can be the last laminated film FL3 formed among laminated films FL1, FL2, and FL3. Similarly, the sealing layer SE1 can be the last sealing layer SE13 formed among sealing layers SE11, SE12, and SE13.

[0119] The laminated films FL1, FL2, and FL3 formed by vapor deposition sometimes have poor adhesion to the substrate. Therefore, during the manufacturing of the display device DSP, the laminated films FL1, FL2, and FL3, as well as the sealing layers SE11, SE12, and SE13 covering them, may peel off from the substrate.

[0120] The aforementioned delamination is prone to occur when laminated films FL1, FL2, and FL3 are continuously formed over a wide area. In the display area DA, the laminated films FL1, FL2, and FL3 are finely separated by the separator 6A. Therefore, the aforementioned delamination is suppressed.

[0121] Furthermore, in this embodiment, a partition wall 6B with a plurality of openings APx is disposed in the peripheral region SA. This allows the laminated films FL1, FL2, and FL3 to be finely segmented in the peripheral region SA, suppressing the aforementioned delamination.

[0122] Furthermore, based on the configuration shown in Figures 7 and 8, the effects described below can be obtained.

[0123] Figure 10 is a schematic top view of the peripheral region SA of a comparative example with this embodiment. Figure 11 is a schematic cross-sectional view of the peripheral region SA of the comparative example. As shown in Figure 10, in this comparative example, a plurality of openings APc, smaller than the openings APx shown in Figures 7 and 8, are provided on the partition wall 6B. These openings APc have a shape with rounded corners of a square. That is, the width of the opening APc in the X direction is the same as the width of the opening APc in the Y direction.

[0124] When a small opening APc is placed in the partition wall 6B, the resin layer RS1 before curing may be recessed at the unevenness of the sealing layer SE1 caused by the opening APc during the formation of the resin layer RS1. Figure 11 shows the state of the resin layer RS1 being recessed near the opening APc on the far left of the figure, and the state of curing in this condition.

[0125] The resin layer RS1 serves to planarize the substrate of the sealing layer SE2. If the resin layer RS1 is cured in a recessed state, the sealing layer SE2 on it may develop abnormal shape, forming a path for moisture to penetrate into the interior of the display device DSP.

[0126] In this embodiment, as shown in Figures 7 and 8, the opening APx has a long strip shape along the Y direction. In this case, if we assume, for example, that the widths of the opening APx and the opening APc in the X direction are the same, then the width of the opening APx in the Y direction is larger. Therefore, it is less likely to cause a depression in the resin layer RS1 due to the opening APx.

[0127] The resin layer RS1 is coated, for example, by inkjet printing. In this case, if the relative movement direction (coating direction) of the nozzle ejecting the resin layer RS1 relative to the substrate is aligned with the elongated direction of the opening APx, the depression of the resin layer RS1 caused by the opening APx is better suppressed. Therefore, in the case where the opening APx is elongated along the Y direction as shown in Figures 7 and 8, it is preferable that the coating direction is also parallel to the Y direction. As another example, the opening APx may have a shape that is elongated along the X direction, with the coating direction parallel to the X direction.

[0128] Because the resin layer RS1 thins near the ends E1a, E1b, E1c, and E1d, the aforementioned depressions are easily formed. To address this, in the examples of Figures 7 and 8, a plurality of slots SL1 are provided in the first region A1 along the ends E1a, E1b, E1c, and E1d of the partition wall 6B, and openings APx1 are connected to these slots SL1. With this configuration, the resin layer RS1 before curing easily fills the depressions in the sealing layer SE1 caused by the openings APx via the slots SL1. Therefore, the aforementioned depressions can be effectively suppressed.

[0129] For example, the resin layer RS1 tends to become thinner within a range of less than 100 μm, as shown in Figure 7. Furthermore, if the slot SL1 is formed near the display area DA, the resistance of the second region A2, which is responsible for feeding from the relay layer RL, may increase. Therefore, it is preferable to determine the distance D within the range of 100–300 μm as described above.

[0130] [Second Implementation]

[0131] The second embodiment will be described in detail. The configuration of the display device DSP, which is not mentioned in this embodiment, is the same as that in the first embodiment.

[0132] Figures 12 and 13 are schematic enlarged top views of the surrounding area SA of this embodiment. Furthermore, Figures 12 and 13 show the same area as Figures 7 and 8, respectively.

[0133] In this embodiment, the partition wall 6A formed in the display area DA is divided into a plurality of partitions SG by a plurality of slots SL2 (the second slot). Each slot SL2 extends along the Y direction. In the examples of Figures 12 and 13, each partition SG is composed of a row of pixels PX arranged along the Y direction. Not limited to this example, each partition SG may be composed of a plurality of rows of pixels PX.

[0134] Similar to the first embodiment, a plurality of slots SL1 are provided in the partition wall 6B. Hereinafter, the slot SL1 that reaches the end E1a as shown in FIG. 12 will be referred to as slot SL1a (third slot). Also, the slot SL1 that reaches the end E1b as shown in FIG. 13 will be referred to as slot SL1b (fourth slot).

[0135] As shown in Figure 12, each slot SL1a is disposed in the first region A1 and separated from slot SL2. On the other hand, as shown in Figure 13, a portion of a plurality of slots SL1b transversely cuts through the first region A1 and the second region A2 and connects to slot SL2 of the display region DA. The interconnected slots SL1b and slot SL2 constitute a continuous slot disposed in the conductive layer including the partition walls 6A and 6B.

[0136] In the examples of Figures 12 and 13, a relay layer RL and a contact portion CN1 are provided between the display area DA and the end E1a. On the other hand, no relay layer RL and contact portion CN1 are provided between the display area DA and the ends E1b, E1c, and E1d.

[0137] In electronic devices equipped with a display device DSP, an antenna for near-field communication (NFC) is sometimes disposed on the back side of the display device DSP. In this case, if, as in the first embodiment, a grid-like partition wall 6A is disposed on the display area DA, and the area is surrounded by a second region of partition wall 6B, then the conductive layer formed by partition walls 6A and 6B reduces the sensitivity of wireless communication via the aforementioned antenna.

[0138] Specifically, the magnetic field generated by the antenna induces eddy currents in the conductive layer. These eddy currents create a magnetic field that cancels out the direction of the magnetic field, causing signal strength attenuation. Consequently, in the case of wireless communication via the display device's DSP, communication sensitivity may decrease.

[0139] To address this, in this embodiment, the conductive layer is interrupted from end E1b via slots SL1b and SL2. This suppresses the generation of eddy currents and improves the sensitivity of short-range wireless communication. Furthermore, the display device DSP of this embodiment achieves the same effect as in the first embodiment.

[0140] Based on the display device and substrate described above as embodiments of the present invention, all display devices that can be appropriately designed, modified, and implemented by those skilled in the art, as long as they contain the essence of the present invention, are also within the scope of the present invention.

[0141] Within the scope of the present invention, various modifications can be conceived by those skilled in the art, and such modifications should also be understood to be within the scope of the present invention. For example, for the above embodiments, any appropriate addition, deletion, or design change of constituent elements, or addition, omission, or change of processes or conditions, as long as they possess the essence of the present invention, are also included within the scope of the present invention.

[0142] Furthermore, any other effects resulting from the embodiments described above, which are clear from the description in this specification or which can be reasonably conceived by those skilled in the art, should be understood as effects resulting from the present invention.

[0143] Cross-reference of related applications

[0144] This invention application claims priority based on Japanese Patent Application No. 2024-020336, filed on February 14, 2024, and incorporates all the contents described in that Japanese Patent Application.

[0145] 1: Pixel circuit 2: Pixel switch 3: Driving transistor 4: Capacitor 5: Rib layer 6A, 6B: Partition walls 10:Substrate 11: Circuit Layer 12: Organic insulating layer 31, 32, 33: Inorganic insulating layer 34: Organic insulating layer 41, 42, 43: Metallic layer 61: Lower part 62: Upper part 63: Bottom layer 64: Axis Layer A1: Area 1 A2: Area 2 AP51, AP52, AP53, AP61, AP62, AP63: Pixel aperture APc, APx, APx1, Apx2: Openings BR: Branches CN0, CN1, CN2: Contact parts CP1, CP2, CP3: Overlay layers D: Distance DA: Display area DE, DE1, DE2, DE3: Display elements DM1, DM2: Embankment section DS: Dam Structure DSP: Display device E0, E1a, E1b, E1c, E1d, E2, Er1, Er2, Es: Endpoints Ex: Edge FL, FL1, FL2, FL3: Stacked films G: Scan line III-III: Line LE1, LE2, LE3: Lower electrodes OR1, OR2, OR3: Organic layer PL: Power cord PW: Feeder cable PX: pixel R: Corrosion resist RL: Relay Layer RS1: Resin layer RS2: Resin layer S: Signal line SA: Surrounding Area SE1, SE2, SE11, SE12, SE13: Sealing layer SG: Partition SL1, SL1a, SL1b: slots SP, SP1, SP2, SP3: Subpixels ST: Cadre T: Terminal section UE1, UE2, UE3: Upper electrode VV: Line VII, VIII: Regions W1: Wiring 1 W2: Second wiring X, Y, Z: Axis / Direction

Claims

1. A display device comprising: a substrate having a display area for displaying an image and a peripheral area surrounding the display area; a plurality of display elements disposed in the display area, each comprising: a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode, emitting light upon application of a voltage; a first partition wall disposed in the display area and between adjacent display elements; and a second partition wall disposed in the peripheral area and connected to the first partition wall; wherein the first partition wall and the second partition wall comprise: a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion; the second partition wall having a plurality of openings in the shape of an elongated strip.

2. The display device as claimed in claim 1, wherein the aforementioned second partition wall surrounds the aforementioned display area.

3. The display device of claim 2, wherein the aforementioned second partition wall has a plurality of first slots reaching an end of the aforementioned second partition wall; and the aforementioned plurality of openings includes a plurality of first openings respectively connected to any one of the aforementioned plurality of first slots.

4. The display device of claim 3, wherein the aforementioned plurality of first slots are respectively connected to the long side of the aforementioned plurality of first openings.

5. The display device of claim 3, wherein the aforementioned plurality of openings further includes a plurality of mutually independent second openings not connected to the aforementioned plurality of first slots.

6. The display device of claim 5, wherein the aforementioned second partition wall has: a first region along the aforementioned end of the aforementioned second partition wall, and a second region located between the aforementioned first region and the aforementioned display area; and the aforementioned plurality of first openings and the aforementioned plurality of first slots are provided in the aforementioned first region; and the aforementioned plurality of second openings are provided in the aforementioned second region.

7. The display device of claim 6, further comprising: a terminal portion disposed in the aforementioned peripheral area; a feed line connected to the aforementioned terminal portion; and a relay layer connected to the aforementioned feed line and the aforementioned second partition wall; wherein the aforementioned relay layer is formed in the same layer as the aforementioned lower electrode using the same material as the aforementioned lower electrode.

8. The display device of claim 7, wherein the aforementioned relay layer and the aforementioned second partition wall are connected by a contact portion located in the aforementioned second region.

9. The display device of claim 8, wherein the aforementioned second region and the aforementioned relay layer surround the aforementioned display area.

10. The display device of claim 3, wherein the aforementioned first partition wall is divided into a plurality of partitions by a second slot located in the aforementioned display area.

11. The display device of claim 10, wherein the aforementioned second partition wall has: a first end and a second end located on the opposite side of the aforementioned first end across the aforementioned display area; and the aforementioned plurality of first slots includes: a third slot reaching the aforementioned first end and a fourth slot reaching the aforementioned second end; the aforementioned second slot is spaced apart from the aforementioned third slot and connected to the aforementioned fourth slot.

12. The display device of any one of claims 1 to 11 further includes a dam portion disposed in the aforementioned peripheral area, surrounding the aforementioned second partition wall.

13. The display device of claim 12 further includes a rib layer formed of an inorganic insulating material, located below the aforementioned first partition wall and the aforementioned second partition wall; and the aforementioned rib layer covers the aforementioned embankment portion.

14. The display device of claim 13, further comprising a first sealing layer covering a multilayer film comprising the aforementioned organic layer and the aforementioned upper electrode; and a portion thereof being disposed in the aforementioned peripheral region.

15. The display device of claim 14, wherein the aforementioned laminated film is interrupted by the edges of the aforementioned plurality of openings.

16. The display device of claim 14, wherein the ends of the aforementioned laminated film and the aforementioned first sealing layer are located between the end of the aforementioned second partition wall and the aforementioned embankment portion.

17. The display device of claim 16, wherein the aforementioned laminated film is interrupted by the aforementioned end portion of the aforementioned second partition wall.

18. The display device of claim 14, further comprising a first resin layer covering the aforementioned first sealing layer.

19. The display device of claim 18, further comprising a second sealing layer covering the aforementioned first resin layer; and the aforementioned second sealing layer contacting the aforementioned rib layer in a region further outward from the end of the aforementioned first resin layer.

20. The display device of claim 19, further comprising a second resin layer covering the aforementioned second sealing layer.

Images