Method of operating forming-free random-access memory (RRAM) devices

Abstract

This invention provides a method for manufacturing a non-formable resistive random access memory (RRAM) device. The method includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide, a top electrode, and an interface layer formed between the top electrode and the switching oxide layer. In some embodiments, the at least one transition metal oxide comprises at least one of HfOx or TaOy, wherein x ≥ 2.0 and y ≥ 2.5. The interface layer comprises at least one of Al₂O₃, MgO, Y₂O₃, or La₂O₃. The non-formable RRAM device can be switched to multi-level resistance without a formation process.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to a resistive random access memory (RRAM) device, and more particularly, to a non-formational RRAM device and methods of manufacturing and operating the non-formational RRAM device. Prior Art

[0002] RRAM devices are two-terminal passive devices with adjustable, nonvolatile resistance. By applying a suitable programming signal to the RRAM device, its resistance can be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS). RRAM devices can be used to form crossbar arrays, which can be used to implement in-memory computing applications, nonvolatile solid-state storage, image processing applications, neural networks, and more. Summary of the Invention

[0003] The following is a brief summary of the invention, intended to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention, nor is it intended to indicate any scope of a particular implementation of the invention or any scope of the claims. The sole purpose of this summary is to present some concepts of the invention in a simplified manner for the more detailed description that follows.

[0004] According to one or more aspects of the present invention, a method for manufacturing a non-formational resistive random access memory (RRAM) device is provided. The method includes forming an RRAM cell having a designed interface layer and annealing the RRAM cell.

[0005] In some embodiments, fabricating the RRAM cell includes: fabricating a switching oxide layer comprising at least one transition metal oxide on a bottom electrode; fabricating an interface layer comprising a material that is more chemically stable than the at least one transition metal oxide on the switching oxide layer; and fabricating a top electrode on the interface layer.

[0006] In some embodiments, the RRAM cell is annealed in a forming gas environment comprising N 2 and H 2 .

[0007] In some embodiments, the RRAM cell is annealed at an annealing temperature between 350° C. and 450° C.

[0008] In some embodiments, one or more interconnect layers are fabricated on the RRAM cell, wherein the RRAM cell is annealed together with the one or more interconnect layers.

[0009] In some embodiments, fabricating the one or more interconnect layers includes fabricating metal pads or metal vias of the one or more interconnect layers on the top electrode of the RRAM cell.

[0010] In some embodiments, the RRAM cell and the one or more interconnect layers are annealed in a plurality of annealing processes, wherein the RRAM cell and the one or more interconnect layers are annealed in a forming gas at a temperature between 350° C. and 450° C. in each of the plurality of annealing processes.

[0011] In some embodiments, the thickness of the interface layer is determined based on the device size of the RRAM cell and a thermal budget associated with annealing, wherein the interface layer can be configured to reduce diffusion and reaction between the top electrode and the switching oxide layer.

[0012] According to one or more aspects of the present invention, a non-formative resistive random access memory (RRAM) device is provided. The non-formative RRAM device includes: a bottom electrode; a switching oxide layer including at least one transition metal oxide; a top electrode; and an interfacial layer formed between the top electrode and the switching oxide layer. The interfacial layer includes a material that is more chemically stable than the at least one transition metal oxide. The non-formative RRAM device is configured to be switched to a plurality of resistances without requiring a formation process to generate conductive filaments in the switching oxide layer.

[0013] In some embodiments, the at least one transition metal oxide comprises at least one of HfO x or TaO y , wherein x ≤ 2.0, and y ≤ 2.5.

[0014] In some embodiments, the interface layer includes a layer of at least one of Al 2 O 3, MgO, Y 2 O 3, or La 2 O 3.

[0015] In some embodiments, the thickness of the interface layer is between 0.2 nm and 1 nm.

[0016] In some embodiments, the thickness of the interface layer is greater than 1 nm.

[0017] In some embodiments, the initial resistance of the RRAM device is between 1 kΩ and 1 MΩ.

[0018] According to one or more aspects of the present invention, a method for operating a non-formational RRAM device is provided. The method includes: performing a first read operation on a first non-formational RRAM device in an initial state to determine a first initial resistance of the first non-formational RRAM device; and performing a first reset operation on the first non-formational RRAM device to switch the first non-formational RRAM device from the first initial resistance to a first target resistance. The first target resistance is greater than the first initial resistance. The first read operation and the first reset operation are performed without pre-forming a conductive filament in the first non-formational RRAM device during a formation process.

[0019] In some embodiments, a first reset current passing through the first non-formation RRAM device during the first reset operation is no greater than 500 μA.

[0020] In some embodiments, the method of operating a non-formation RRAM device further includes performing a first set operation on the first non-formation RRAM device to switch the first non-formation RRAM device from the first target resistance to a second target resistance. In some embodiments, performing the first set operation includes applying a first set voltage to the first non-formation RRAM device, wherein the first set voltage is no greater than 1.0V.

[0021] In some embodiments, performing a first reset operation on the first non-formation-type RRAM device includes applying a first reset voltage to the first non-formation-type RRAM device, and the first set voltage and the first reset voltage have opposite polarities.

[0022] In some embodiments, the method of operating a non-formation RRAM device further includes: performing a second read operation on a second non-formation RRAM device to determine a second initial resistance of the second non-formation RRAM device; and performing a second set operation on the second non-formation RRAM device to switch the second non-formation RRAM device from the second initial resistance to a third target resistance, wherein the third target resistance is less than the second initial resistance. The second read operation and the second set operation are performed without pre-forming a conductive filament in the second non-formation RRAM device during formation.

[0023] In some embodiments, the method of operating a non-formational RRAM device further includes applying a second reset voltage to the second non-formational RRAM device to switch the second non-formational RRAM device from a third target resistance to a fourth target resistance. In some embodiments, performing the second set operation on the second non-formational RRAM device includes applying a second set voltage to the second non-formational RRAM device, wherein the second reset voltage and the second set voltage have opposite polarities.

[0024] In some embodiments, a second reset current flowing through the second non-formed RRAM device in response to the second reset voltage is no greater than 500 μA, and the second reset voltage is no greater than 1.0 V. Simple diagram description

[0025] The present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present invention. However, the accompanying drawings should not be used to limit the present invention to specific embodiments, but are only for explanation and understanding. FIG. 1A is a schematic diagram illustrating an example of a crossbar switch circuit according to some embodiments of the present invention. FIG. 1B is a schematic diagram illustrating an example of a cross-point device according to some embodiments of the present invention. 2A , 2B, and 2C illustrate cross-sectional views of conventional RRAM devices that require a formation process to operate. 2D , 2E and 2F illustrate current-voltage (IV) characteristics of the conventional RRAM device described in conjunction with FIG. 2A , 2B and 2C . FIG. 3 is a schematic diagram illustrating a cross-sectional view of an example of a non-formation-type RRAM device according to some embodiments of the present invention. 4 is a schematic diagram illustrating a cross-sectional view of a semiconductor device including an example of a non-formation-type RRAM device according to some embodiments of the present invention. 5A-5D are graphs illustrating IV characteristics of a first example of a non-formation-type RRAM device according to some embodiments of the present invention. 6A-6D are graphs illustrating IV characteristics of a second example of a non-formation-type RRAM device according to some embodiments of the present invention. 7A , 7B, and 7C are flow charts illustrating examples of processes for operating a non-formational RRAM device according to some embodiments of the present invention. FIG. 8 is a flow chart illustrating an example process for fabricating a non-formation-type RRAM device according to some embodiments of the present invention. 9A-9E include graphs illustrating IV characteristics of example RRAM devices having different device sizes and fabricated under the same annealing conditions. 9F-9J include graphs illustrating IV characteristics of example RRAM devices having the same device dimensions and fabricated under varying annealing conditions. 10 is an IV curve illustrating simulated behavior of an example non-formational RRAM device according to some embodiments of the present invention. 11 is a graph showing device read current characteristics over time for an example of a non-formed RRAM device according to some embodiments of the present invention. Implementation Method

[0026] Aspects of the present invention provide formationless resistive random access memory (RRAM) devices and methods for fabricating and operating formationless RRAM devices.

[0027] RRAM devices are two-terminal passive devices with programmable resistance. These devices may include a bottom electrode, a top electrode, and a switching oxide layer located between the bottom and top electrodes. The bottom electrode may include a non-reactive metal such as platinum (Pt) or palladium (Pd). The top electrode may include a reactive metal such as tantalum (Ta) or titanium (Ti). The switching oxide layer may include a transition metal oxide such as hafnium oxide (HfOx) or tantalum oxide (TaOx).

[0028] In its original state (i.e., before appropriate stimulation after fabrication), a conventional RRAM device behaves as an insulator. The conventional RRAM device can be converted to a conductive state through a formation process that includes applying a high formation voltage (e.g., 1.7V) to the conventional RRAM device. During the formation process, a conductive filament is formed in the conventional RRAM device. The RRAM device can then switch between two resistive states, such as a high resistance state (HRS) and a low resistance state (LRS), in response to an appropriate programming signal (e.g., a voltage or current signal). The switching event from the HRS to the RRAM device is called a set process. The switching event from the LRS to the RRAM device is called a reset process. In a crossbar switch array circuit including an RRAM array, the programming signal can be provided to a specific RRAM device via a selector, such as a transistor.

[0029] Because the formation process involves the initial breakdown of the metal oxide in the switching oxide layer, the formation of the initial conductive filaments during the formation process is abrupt and requires a high formation voltage (e.g., 1.7V). In some embodiments, the formation voltage can be higher than 2V to 3V to form RRAM devices with thicker switching oxide layers. Due to the difficulty in controlling the size of the conductive filaments formed during the formation process, the formation process often does not produce the desired device resistance. Conventional RRAM devices may require tuning during a subsequent reset process (also known as the "initial reset process") to achieve the desired device resistance. During the initial reset process, a high reset current is required to break the conductive filaments. Consequently, conventional RRAM devices operate at high currents (e.g., greater than 1mA), resulting in high power consumption and the need for relatively large transistors capable of supplying this high operating current. The formation process is also time-consuming. For example, forming a 256x256 RRAM array can take several minutes, making the process of forming a crossbar circuit containing multiple 256x256 RRAM arrays even more time-consuming. Furthermore, the formation of the initial conductive filaments during the formation process and the breaking of the initial conductive filaments during the initial reset process are both sudden, which may lead to performance variations between devices.

[0030] Therefore, the present invention provides a non-formational RRAM and methods for marking and operating the non-formational RRAM. Unlike conventional RRAMs that require a formation process to become conductive, the non-formational RRAM described herein is conductive in its initial state and can be operated without forming a conductive filament. The non-formational RRAM device can have a medium to low resistance in its initial state, which can be read to determine appropriate programming parameters for subsequent operations (e.g., set operations, reset operations, etc.).

[0031] In some embodiments, the non-forming RRAM device may include an RRAM cell. The RRAM cell includes a bottom electrode, a top electrode, a switching oxide layer formed between the bottom electrode and the top electrode, and an interfacial layer formed between the switching oxide layer and the top electrode. The switching oxide layer may include one or more transition metal oxides, such as hafnium oxide, tantalum oxide, etc. The interfacial layer may include one or more layers of a metal oxide that is more chemically stable than the transition metal oxide, such as aluminum oxide. The metal oxide in the interfacial layer does not react with the top electrode or the switching oxide. Therefore, the interfacial layer can control reaction and diffusion between the top electrode and the switching oxide layer. The interfacial layer may include one or more continuous or discontinuous aluminum oxide layers.

[0032] The RRAM cell can be annealed to achieve non-formative behavior. For example, the RRAM cell can be annealed in one or more annealing processes, each of which involves annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at an annealing temperature between 350 and 450°C for a suitable time (e.g., 15-30 minutes). The annealing can enhance diffusion and reaction between the top electrode and the switching oxide, while the interfacial layer can reduce diffusion and reaction between the top electrode and the switching oxide layer. The interfacial layer and the annealing conditions (e.g., temperature, annealing time, etc.) can be optimized based on the device dimensions (e.g., critical dimensions) of the RRAM device to achieve a desired initial resistance of the RRAM device.

[0033] The resistance of a non-formation RRAM device can be programmed to multiple levels without a formation process. For example, to program the non-formation RRAM device to a target resistance, a read operation can be performed on the non-formation RRAM device to determine the initial resistance of the non-formation RRAM device. In some embodiments where the initial resistance is greater than the target resistance, the non-formation RRAM device can be programmed to the target resistance by applying a set voltage (e.g., a voltage of 0.6V) to the non-formation RRAM device without previously performing a formation process. In some embodiments where the target resistance is greater than the initial resistance of the non-formation RRAM device, the non-formation RRAM device can be programmed to the target resistance by applying a reset voltage to the non-formation RRAM device. The reset current through the RRAM device may be less than 200 µA. The reset is performed without previously performing a formation process or an initial set process on the RRAM device. The set voltage and the reset voltage can be of opposite polarity (e.g., positive and negative). The non-formational RRAM device can switch between a high-resistance state and a low-resistance state in response to an ultra-low set voltage (e.g., a voltage less than 1 V) and a reset current (e.g., a reset peak current less than 200 µA).

[0034] Thus, the present invention provides a mechanism for fabricating and operating non-formational RRAM devices. By balancing material factors (e.g., interfacial layer thickness) and annealing factors (e.g., annealing conditions), the mechanism described herein provides a non-formational RRAM device with desirable characteristics, such as low-power switching, low device-to-device performance variation, ultra-low operating current and voltage, bipolar switching with a large Ion / Ioff ratio, and multi-level analog resistive switching. The non-formational RRAM device described herein can enhance the stability of crossbar arrays of RRAM devices and enable high-density storage and / or computing applications with low power consumption.

[0035] FIG1A is a schematic diagram illustrating an example crossbar circuit 100 according to some embodiments of the present invention. As shown, crossbar circuit 100 may include a plurality of interconnecting conductive lines for a crossbar array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n and column lines 113a, 113b, ..., 113j, ..., 113m. Crossbar circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect a row line and a column line. For example, crosspoint device 120ij may connect row line 111i and column line 113j. In some embodiments, crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), switches (not shown), and one or more suitable circuit components for implementing a crossbar-based device. The number of column lines 113a-m may be the same as or different from the number of row lines 111a-n.

[0036] The row lines 111 may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each row line 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

[0037] The column lines 113 may include a first column line 113a, a second column line 113b, ..., and an mth column line 113m. Each column line 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

[0038] Each cross-point device 120 may be and / or include any suitable device having adjustable resistance, such as a memristor, a phase-change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include an RRAM device as described in conjunction with FIG. 3-11 .

[0039] The crossbar circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 100. The input signal can flow through the crosspoint devices in the rows of the crossbar circuit 100. The conductance of the crosspoint devices can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductance, generating a current flowing through the crosspoint devices. According to Kirchhoff's law, the sum of the currents through the devices in each column generates an output current signal, which can be read from the column (e.g., the output of an ADC). Based on Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductance matrix of the crosspoint devices. Therefore, the input signal is weighted by the conductance of each crosspoint device according to Ohm's law. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computation (IMC).

[0040] FIG1B is a schematic diagram illustrating an example cross-point device 1200 according to some embodiments of the present invention. As shown, cross-point device 1200 may connect bit lines (BL) 1211, select lines (SEL) 1213, and word lines (WL) 1215. Bit lines 1211 and word lines 1215 may be column lines and row lines, respectively, as shown in FIG1A .

[0041] Cross-point device 1200 may include an RRAM device 1201 and a transistor 1203. A transistor is a three-terminal device, which may be labeled as a gate (G), a source (S), and a drain (D). Transistor 1203 may be connected in series with RRAM device 1201. As shown in FIG1B , the bottom electrode of RRAM device 1201 may be connected to the drain of transistor 1203. The top electrode of RRAM device 1201 may be connected to bit line 1211. The source of transistor 1203 may be connected to word line 1215. The gate of transistor 1203 may be connected to select line 1213. RRAM device 1201 may include one or more RRAM devices as described in conjunction with FIG2A-5M below. Cross-point device 1200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. Transistor 1203 may function as a selector and a current controller, which may set the current compliance of RRAM device 1201 during programming. The gate voltage of transistor 1203 can set the current compliance of cross-point device 1200 during programming, thereby controlling the conductance and analog behavior of cross-point device 1200. For example, when setting cross-point device 1200 from a high-impedance state to a low-impedance state, a set signal (e.g., a voltage signal, a current signal) can be provided via bit line (BL) 1211. Another voltage, also known as a select voltage or gate voltage, can be applied to the transistor gate via select line (SEL) 1213 to turn the gate on and set the current compliance, while word line (WL) 1215 can be grounded. When resetting cross-point device 1200 from a low-impedance state to a high-impedance state, a gate voltage can be applied to the gate of transistor 1203 via select line 1213 to turn the transistor gate on. Simultaneously, a reset signal can be sent to RRAM device 1201 via word line 1215, while bit line 1211 can be grounded.

[0042] 2A, 2B, and 2C are cross-sectional views of conventional RRAM devices requiring forming process operations. RRAM devices 200a, 200b, and 200c may correspond to RRAM devices in an initial state, a low resistance state, and a high resistance state, respectively.

[0043] As shown in FIG2A , RRAM device 200a may include a bottom electrode 210, a switching oxide layer 220, and a top electrode 230. Bottom electrode 210 may include a suitable material that is electronically conductive and non-reactive to the switching oxide, such as Pt, Pd, etc. Switching oxide layer 220 may include one or more transition metal oxides selected from binary, ternary, or higher-order oxides, such as TaOx, HfOx, TiOx, NbOx, ZrOx, etc. In some embodiments, the non-reactive metal in bottom electrode 210 has a higher chemical stability than the transition metal oxide in switching oxide layer 220. Top electrode 230 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in top electrode 230 may include Ta, Hf, Ti, etc.

[0044] The RRAM device 200a may have a high initial resistance (e.g., several giga-ohms or gΩ) and, therefore, may be considered an insulator in its initial state. The initial resistance of the RRAM device 200a can be changed, and the RRAM device 200a can be switched to a low-resistance state during a formation process. For example, a formation voltage can be applied to the RRAM device 200a. The application of the voltage to the RRAM device 200a can cause the metal material in the top electrode to absorb oxygen ions in the switching oxide layer 220, generating oxygen vacancies in the switching oxide layer. As a result, a conductive path (e.g., a conductive filament) rich in oxygen vacancies can be formed in the switching oxide layer 220. For example, as shown in FIG. 2B , a conductive filament 225a is formed in the switching oxide layer 220. As shown, the conductive filament 225a can be formed across the switching oxide layer 220 from the top electrode 230 to the bottom electrode 210. The RRAM device 200b can be reset to a high-resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 200b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, i.e., positive and negative signals, respectively. Application of the reset signal can induce oxygen ions to migrate back into the switching oxide layer 220 and recombine with one or more oxygen vacancies. For example, during the reset process, an interrupted conductive filament 225b, as shown in FIG2C , can be formed in the switching oxide layer 220. As shown, the conductive filament can be interrupted by an oxide gap between the interrupted conductive filament 225b and the bottom electrode 210. The lateral dimensions of the conductive filament 225b can be smaller than the lateral dimensions of the conductive filament 225a. The conductive filament 225b does not continuously connect the bottom electrode 210 and the top electrode 230. The RRAM devices 200b-c can be electrically switched between a high-resistance state and a low-resistance state by applying a suitable programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0045] Figures 2D, 2E, and 2F are characteristic graphs 200d, 200e, and 200f illustrating the current-voltage (IV) characteristics of the conventional RRAM device described in conjunction with Figures 2A-2C. Figure 2D is an IV curve 200d of the conventional RRAM device in its initial state. As shown, the initial resistance of the conventional device is approximately 1.3 GΩ at 0.2V. Therefore, the conventional RRAM device can be considered an insulator in its initial state. As shown in Figure 2E, a forming process can be performed by applying a forming voltage Vform to the RRAM device. The forming voltage can be approximately 1.7V. After the forming process, the RRAM device can be reset to a high-resistance state in a reset process (also referred to as an "initial reset process") by applying a reset voltage range 261. During the initial reset process, the reset peak current through the RRAM device is approximately 1 mA. As shown in Figure 2F, the RRAM device can be switched between a high-resistance state and a low-resistance state by applying a set voltage within a suitable voltage range 263 and a reset voltage within a voltage range 261, respectively. The set voltage shown can be approximately 0.7V. The reset peak current can be approximately 100 µA. Therefore, forming a conventional RRAM device requires applying a high formation voltage. The reset peak current during the initial reset process is high. Conventional RRAM devices operate at high operating currents. The resistance of conventional RRAM devices cannot be switched without a formation process.

[0046] FIG. 3 is a cross-sectional view illustrating an example of a non-formational RRAM cell 300 according to some embodiments of the present invention. The RRAM cell 300 is also referred to herein as an RRAM device.

[0047] As shown, the RRAM cell 300 may include a substrate 310, a bottom electrode 320, a switching oxide layer 330, an interface layer 340, and a top electrode 350. The interface layer 340 is fabricated between the top electrode 350 and the switching oxide layer 330.

[0048] Substrate 310 may include one or more layers of any suitable material that can be used as an RRAM device substrate, such as silicon (Si), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), etc. In some embodiments, substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc. In some embodiments, the substrate may include one or more individually controllable driver circuits (e.g., a circuit matrix). In some embodiments, the driver circuits may include one or more complementary metal oxide semiconductor (CMOS) drivers.

[0049] The bottom electrode 320 can be and / or include any suitable material that is electronically conductive and non-reactive to the switching oxide, such as platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0050] The switching oxide layer 330 may include one or more transition metal oxides selected from binary oxides, ternary oxides, and advanced oxides, such as TaOx, HfOx, TiOx, NbOx, ZrOx, etc., where x may be used to indicate that the oxide is oxygen-deficient compared to its full (or terminal) oxide, and the value of x may vary depending on the oxygen-to-metal atomic ratio in the stoichiometry of the full oxide, such as x≤2.0 for HfOx (where HfO2 is the full oxide) and x≤2.5 for TaOx (where Ta2O5 is the full oxide). As an example, the switching oxide layer 330 may include Ta2O5 and / or HfO2.

[0051] Top electrode 350 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in top electrode 350 may include Ta, Hf, Ti, TiN, TaN, etc. Top electrode 350 may be reactive to the switching oxide and have a suitable oxygen solubility to absorb some oxygen ions from switching oxide layer 330 and generate oxygen vacancies in switching oxide layer 330. In other words, the reactive metal material in top electrode 350 may have a suitable oxygen solubility and / or oxygen mobility. In some embodiments, top electrode 350 may not only generate oxygen vacancies in switching oxide layer 330 (e.g., by scavenging oxygen), but may also serve as an oxygen reservoir or oxygen source for switching oxide layer 330 during cell programming.

[0052] In one embodiment, the top electrode 350 may include one or more alloys. Each alloy may include two or more metal elements. Each of the alloys may include a binary alloy (e.g., an alloy including two metal elements), a ternary alloy (e.g., an alloy including three metal elements), a quaternary alloy (e.g., an alloy including four metal elements), a quinary alloy (e.g., an alloy including five metal elements), and / or a higher-order alloy (e.g., an alloy including six or more metal elements). In some embodiments, the top electrode 350 may include one or more alloys including a first metal element and one or more second metal elements. Each second metal element may have a lower or higher reactivity toward the transition metal oxide in the switching oxide layer than the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of W, Hf, Mo, Nb, Zr, and the like.

[0053] Interfacial layer 340 is in thermochemical equilibrium with top electrode 350 and switching oxide layer 330 and does not react with either of them. Therefore, interfacial layer 340 can reduce diffusion and reaction with top electrode 350 and switching oxide layer 330. Interfacial layer 340 can be and / or include a film of a material that is more chemically stable than the transition metal oxide in the switching oxide layer. As a result, the material does not react with the transition metal oxide in the switching oxide layer 330. For example, the transition metal oxide in the switching oxide layer can be and / or include HfOx and / or TaOy, where x ≤ 2.0 and y ≤ 2.5, and interfacial layer 340 can include one or more layers of Al2O3, MgO, Y2O3, La2O3, and the like. In some embodiments, interfacial layer 340 can include a continuous film (e.g., a film having a thickness greater than or equal to 1 nm) of a material that is more chemically stable than the transition metal oxide. In some embodiments, the interface layer 340 can be discontinuous (eg, a film having a thickness of 0.2 nm-0.6 nm).

[0054] The RRAM cell 300 may be annealed in one or more annealing processes to achieve the desired non-forming behavior. Each annealing process may involve annealing the RRAM device in a forming gas environment at a suitable temperature (e.g., 350-450°C) for a suitable time (e.g., 15-30 minutes). The forming gas may include a mixture of nitrogen (N2) and hydrogen (H2) in a suitable ratio (e.g., 95:5, 90:10, etc.). The thickness of the interface layer 340 may be determined based on the RRAM cell 300 (critical dimensions, device area, etc.) and annealing conditions. Smaller device sizes may require longer annealing times and / or thinner interface layers 340 to reduce the initial resistance of the non-forming RRAM.

[0055] Annealing can enhance diffusion and reaction between the top electrode 350 and the switching oxide layer 330, while the interfacial layer 340 can reduce diffusion and reaction between the top electrode 350 and the switching oxide layer 330. Given the device size of the RRAM cell 300, balancing and / or optimizing the interfacial layer 340 and the thermal budget associated with the annealing (e.g., annealing temperature, annealing time, etc.) can control the initial resistance of the RRAM cell 300 to within a desired target range and achieve desired device behavior, such as non-formational, low-power switching, and low device-to-device performance variation. As described in more detail in conjunction with Figures 9A-9J, the thickness of the interfacial layer 340 can be determined based on the device size and thermal budget of the RRAM cell 300. In some embodiments, the initial resistance of the non-formational RRAM cell 300 can be between approximately 1 kΩ and approximately 1 MΩ. In some embodiments, the initial resistance of the RRAM cell 300 can be between several hundred ohms and several thousand ohms (e.g., 500 Ω-5 kΩ).

[0056] In some embodiments, the RRAM device 300 can be fabricated during a CMOS process. The thermal budget for annealing the RRAM cell 300 can be determined based on the annealing conditions associated with the CMOS process. For example, as shown in FIG4 , the semiconductor device 400 can include a transistor 403 fabricated on a substrate 401. The transistor 403 can include a source 403 a, a gate 403 b, and a drain 403 c. An interconnect layer 410 can be fabricated on the transistor 403 and the substrate 401.

[0057] Each of the interconnect layers 410 can provide electrical connections between the transistor 403 and / or one or more other devices (e.g., one or more other transistors, the RRAM cell 300, one or more other RRAM devices, etc.). The interconnect layer 410 can include, for example, via layers (or via layers) 411, 412, 413, 414, and 415 and metal layers (or pad layers) 421, 423, 424, and 425. Each via layer can include one or more metal vias. Each metal via can include a suitable metal material, such as Al, Cu, W, etc. Each metal layer can include one or more metal pads and / or one or more metal lines. Each metal pad can include a suitable metal material, such as Al, Cu, W, etc. For example, the via layer 411 can include metal vias 411a, 411b, and 411c, which can be connected to the source 403a, gate 403b, and drain 403c of the transistor 403, respectively. In some embodiments, via layer 411 may include tungsten (W) vias and doped poly-Si (poly-Si) terminals, where the poly-Si terminals may directly contact the gate 403b, source 403a, and drain 403c of transistor 403. The tungsten vias may directly contact the poly-Si terminals. Other via layers and the metal layer above via layer 411 may be made of Cu, W, Al, etc. Metal layer 421 may include metal pads 421a, 421b, and 421c. Metal pads 421a, 421b, and 421c may be connected to metal vias 411a, 411b, and 411c, respectively. Metal layer 422 may include metal pads 422a, 422b, and 422c. Metal pads 422a, 422b, and 422c may be connected to metal vias 412a, 412b, and 412c, respectively. As shown, a pair of adjacent metal layers can be connected via a via layer fabricated between the adjacent metal layers.

[0058] Fabricating the interconnect layer 410 may include fabricating a dielectric material layer using a suitable deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, and the like. The dielectric layer may be patterned to create one or more vias. One or more suitable metal materials may be deposited in the vias and patterned to create one or more metal vias and / or metal pads. The metal vias and / or metal pads may then be annealed in a forming gas environment. In some embodiments, the via layer and the metal layer may be fabricated in a dual damascene fabrication process, where the metal vias and metal pads are fabricated during the same metal deposition and patterning process and annealed together.

[0059] For example, to fabricate first via layer 411, dielectric layer 451 may be fabricated on substrate 401 and transistor 403. Dielectric layer 451 may include any suitable dielectric material, such as silicon nitride (Si3N4), silicon dioxide (SiO2), etc. Dielectric layer 452 may be processed using any suitable deposition technique. For example, dielectric layer 451 may be patterned and filled by metal deposition to fabricate metal vias 411a, 411b, and 411c in dielectric layer 452.

[0060] The RRAM cell 300 can be fabricated during the fabrication process of the interconnect layer 410 and, therefore, can be referred to as a CMOS-compatible RRAM device. For example, the RRAM cell 300 can be fabricated on a metal pad or metal via of the top interconnect layer of the first interconnect layer 410a. One or more second interconnect layers 410b can then be fabricated on the RRAM cell 300 and the first interconnect layer 410a. More specifically, for example, a metal pad or metal via of the bottom interconnect layer of the second interconnect layer 410b can be fabricated on the RRAM cell 300 and can directly contact the RRAM cell.

[0061] Fabricating each second interconnect layer 410b may include annealing the second interconnect layer associated with the RRAM cell 300. In some embodiments, the via layer and the metal layer may be fabricated in a dual damascene fabrication process, where the metal via and metal pad are fabricated during the same metal deposition and patterning process and annealed together. The interface layer 340 may have a suitable thickness to achieve a desired forming gas anneal (FGA) resistance. For example, a relatively thick interface layer may be more resistant to FGA than a relatively thin interface layer. Thus, the thermal budget for annealing the RRAM cell 300 may be determined based on the location of the RRAM cell, the number of second interconnect layers to be fabricated on the RRAM cell, and / or the annealing conditions used to anneal the second interconnect layers. The thickness of the interface layer 340 may then be optimized based on the annealing conditions and the device dimensions of the RRAM cell 300.

[0062] Although certain interconnect layers (e.g., metal layers and via layers) are shown in FIG4 , this is for illustrative purposes only. The first interconnect layer 410 a and the second interconnect layer 410 b may include any suitable number of interconnect layers. For example, in some embodiments, the RRAM cell 300 may be fabricated on the metal layer 413. In some embodiments, the semiconductor device 400 and / or the interconnect layer 410 may be fabricated using techniques described in U.S. patent application Ser. No. 17 / 848,238, filed on June 23, 2022, which is incorporated herein by reference.

[0063] 5A-5D are graphs 500A, 500B, 500C, and 500D illustrating IV curves of a first example of a non-formational RRAM according to some embodiments of the present invention.

[0064] FIG5A shows an IV curve 500A of an RRAM device in its original state. The horizontal axis of IV curve 500A represents the read voltage applied to the RRAM device in its original state. The vertical axis of IV curve 500A represents the current through the RRAM device during the application of the read voltage. As shown in the figure, the initial resistance of the RRAM device is approximately 4.5 kΩ at 0.2 V.

[0065] As shown in FIG5B , a reset voltage within a voltage range 511 can be applied to the RRAM device to switch the RRAM device from an initial resistance to a target resistance (also referred to as a "first target resistance") greater than the initial resistance. The initial resistance of the RRAM device is reset without requiring the RRAM device to undergo a prior formation or initial setup process. For example, the resistance of the RRAM device can be reset to approximately 127 kΩ. As shown in FIG5B , the peak reset current through the RRAM device is less than 200 µA, significantly lower than the reset current required to reset a conventional RRAM device after formation.

[0066] After the reset process, the resistance of the RRAM device can be set to a second target resistance greater than the first target resistance. For example, as shown in FIG5C , during the set process, a set voltage within a voltage range 513 can be applied to the RRAM device. In some embodiments, the set voltage is approximately 0.6 V. The set voltage and the reset voltage have opposite polarities. In some embodiments, the resistance of the RRAM device after the set process is approximately 5.2 kΩ at 0.2 V.

[0067] As shown in FIG5D , the resistance of the RRAM device can be switched between a high-resistance state 521 and a low-resistance state 523 at a set voltage within a voltage range 513 or a reset voltage within a voltage range 511. The set voltage may be approximately 0.6 V. The reset peak current is approximately or less than 200 µA. In some embodiments, the reset peak current is approximately or less than 500 µA. As shown in FIG5A-5D , without a pre-forming process and an initial reset process, the RRAM device can be reset to a desired target resistance at a low initial reset peak current. The RRAM device switches at a low voltage and a large Ion / Ioff ratio, and operates at ultra-low current.

[0068] 6A-6D are graphs 600A, 600B, 600C, and 600D illustrating current-voltage curves (IV curves) of a second example of a non-formational RRAM according to some embodiments of the present invention.

[0069] FIG6A shows an IV curve 600A of an RRAM device in its initial state. The horizontal axis of IV curve 600A represents the read voltage applied to the RRAM device in its initial state. The vertical axis of IV curve 600A represents the current through the RRAM device during the application of the read voltage. The initial resistance of the RRAM device is approximately 19 kΩ at 0.2 V.

[0070] As shown in FIG6B , the RRAM device can be switched from its original state 621 to a low-resistance state 623 by applying a set voltage within a voltage range 611. For example, the set voltage can be approximately 0.6 V, which is significantly lower than the formation voltage required to electrically form a conventional RRAM device. After the set process, the resistance of the RRAM device is approximately 8 kΩ at 0.2 V.

[0071] After the set process, the RRAM device can be reset to a higher resistance by applying a reset voltage within a voltage range 613 to the RRAM device. The reset peak current can be less than 200 µA, which is significantly lower than the reset peak current required to reset a conventional device after formation. After reset, the resistance of the RRAM device can be approximately 100 kΩ.

[0072] As shown in Figures 6C and 6D, the RRAM device can be repeatedly turned on and off at a set voltage within a voltage range 611 or a reset voltage within a voltage range 613. For example, by applying a set voltage of 0.7V to the RRAM device, the resistance of the RRAM device can be set to approximately 5kΩ. In some embodiments, the set voltage can be approximately 1V or less. As another example, the resistance of the RRAM device can be reset to approximately 100kΩ at a reset peak current of approximately 200µA or less. As shown in Figures 6A-6D, the RRAM device can be reset to a desired target resistance at a set voltage that is significantly lower than the formation voltage required during formation, and can operate at low voltage and low current during subsequent switching events.

[0073] 7A is a flow chart 700a illustrating an example process for operating a non-formation RRAM device according to some embodiments of the present invention. The resistance of the non-formation RRAM device can be switched to one of multiple levels of resistance without a formation process.

[0074] At 710, a read operation can be performed to determine the initial resistance of the RRAM device. For example, one or more read voltages can be applied to the RRAM device in its initial state to determine the initial resistance of the RRAM device. The read voltage can be, for example, between 0.05 and 0.5 V. It should be noted that a read operation cannot be performed on a conventional RRAM without first performing a formation process because conventional RRAM is non-conductive in its initial state.

[0075] At 720, the initial resistance can be compared to the target resistance to determine whether the initial resistance is greater than the target resistance. The target resistance can be a desired resistance or a weight to which the RRAM device is programmed.

[0076] In some embodiments, the target resistance can be greater than the initial resistance of the RRAM device. In such embodiments, step 700a can proceed to 730, and a reset operation can be performed to program the RRAM device to the target resistance. For example, a reset voltage can be applied to the RRAM device. The reset current can be hundreds of microamperes (µA). Unlike the conventional RRAM device described in conjunction with Figures 2A-2F, the non-formation RRAM device can be programmed to the target resistance without a formation process and an initial reset process after the formation process.

[0077] In some embodiments, the initial resistance of the RRAM device can be greater than the target resistance. In such embodiments, step 700a can proceed to 735, and a set operation can be performed on the RRAM device to program the RRAM device to the target resistance. For example, a set voltage can be applied to the RRAM device. In some embodiments, the set voltage can be approximately 0.3-0.7V. In some embodiments, the set voltage can be approximately 0.5-1V. Thus, the non-formation RRAM device can be set to the target resistance without requiring a formation process that creates conductive filaments in the RRAM device.

[0078] 7B is a flow chart 700b illustrating an example process for operating a non-formation-type RRAM device (also referred to as a "first non-formation-type RRAM device") according to some embodiments of the present invention.

[0079] At 740, a first read operation may be performed on the first non-formed RRAM device in an initial state to determine a first initial resistance of the first non-formed RRAM device. The first initial resistance represents a resistance of the first non-formed RRAM device in an initial state before undergoing a formation process. Performing the first read operation on the first non-formed RRAM device in the initial state includes applying one or more read voltages (e.g., a voltage of approximately 0.2 V) to the first non-formed RRAM device.

[0080] At 750, a first reset operation can be performed to program the first non-formed RRAM device to a first target resistance greater than the first initial resistance. Performing the first reset operation can include applying a reset signal (e.g., a voltage signal, a current signal, etc.) to the first non-formed RRAM device. During the first reset operation, a reset peak current (also referred to as a "first reset current") through the first non-formed RRAM device can be approximately or less than 200 µA. In some embodiments, the first reset current can be approximately or less than 500 µA. The reset operation is performed without previously forming the first non-formed RRAM device during the formation process.

[0081] At 760, a first set operation may be performed on the first non-formation RRAM device to switch the first non-formation RRAM device from a first target resistance to a second target resistance. The first target resistance is greater than the second target resistance. Performing the first set operation may include applying a first set voltage to the first non-formation RRAM device. In some embodiments, the first set voltage is no greater than 0.7 V. In some embodiments, the first set voltage is no greater than 1 V.

[0082] 7C , a flow chart illustrates an example process 700 c for operating a non-formation-type RRAM device having a medium resistance (“second non-formation-type RRAM device”) in accordance with some embodiments of the present invention.

[0083] At 770, a second read operation may be performed on the second non-formed RRAM device in the initial state to determine an initial resistance of the second non-formed RRAM device ("second initial resistance"). The second initial resistance represents the resistance of the second non-formed RRAM device in an initial state before undergoing a formation process. Performing the second read operation on the second non-formed RRAM device includes applying one or more read voltages to the second non-formed RRAM device in the initial state.

[0084] At 780, a second set operation may be performed to switch the second RRAM device from the second initial resistance to a third target resistance. The second initial resistance is greater than the third target resistance. The second set operation may be performed without previously performing a formation process on the second non-formed RRAM device. Performing the second set operation may include applying a second set voltage to the second non-formed RRAM device. In some embodiments, the second set voltage is no greater than 0.7V.

[0085] At 790, a second reset operation may be performed to switch the second non-formed RRAM device from the third target resistance to a fourth target resistance. The fourth target resistance may be less than the third target resistance. The reset operation may be performed without previously performing a formation process on the second non-formed RRAM device.

[0086] FIG. 8 is a flow chart 800 illustrating an example process for fabricating a non-formational RRAM device according to some embodiments of the present invention.

[0087] At 810, an RRAM cell can be fabricated. The RRAM cell may include a bottom electrode, a switching oxide layer, a top electrode, and an interface layer fabricated between the switching oxide layer and the top electrode. The RRAM cell may be RRAM cell 300 of FIG. 3 . Specifically, at 811, a bottom electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of one or more inactive metals, such as Pt, Pd, Ir, etc., using physical vapor deposition (PVD), chemical vapor deposition, sputtering, atomic layer deposition (ALD), and / or any other suitable deposition technique. In some embodiments, fabricating the bottom electrode may involve depositing one or more layers of metal nitride, such as TiN or TaN. The bottom electrode may be and / or include bottom electrode 320, as described above in conjunction with FIG. 3 .

[0088] At 813, a switching oxide layer may be formed on the bottom electrode. The switching oxide layer may include one or more transition metal oxides. The transition metal oxides may include, for example, TaOx, HfOx, TiOx, NbOx, ZrOx, etc. The switching oxide layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0089] At 815, an interfacial layer may be formed on the switching oxide layer. Forming the interfacial layer may include depositing a material that is more chemically stable than the transition metal oxide in the switching oxide layer, such as Al2O3, MgO, Y2O3, La2O3, etc. In one embodiment, forming the interfacial layer may include depositing a continuous layer of Al2O3, MgO, Y2O3, La2O3, etc. In another embodiment, forming the interfacial layer may include depositing a layer of material having a suitable thickness (e.g., a thickness between about 0.2 nm and about 0.6 nm) to form a discontinuous film of Al2O3, MgO, Y2O3, La2O3, etc. The interfacial layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0090] At 817, a top electrode can be fabricated on the interface layer. Fabricating the top electrode can include depositing one or more suitable metal materials that are conductive and reactive with the switching oxide in the switching oxide layer, such as Ta, Hf, Ti, TiN, TaN, etc. The top electrode can include one or more alloys. The top electrode can be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0091] The RRAM cell may be annealed at 830. For example, the RRAM cell may be annealed in one or more annealing processes, each of which may include annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at a suitable annealing temperature (e.g., 350-450° C.) for a suitable time period (e.g., 15-30 minutes) for each annealing process.

[0092] In some embodiments, process 800 may further include 820, where one or more interconnect layers are fabricated on the top electrode. In such embodiments, the RRAM cell may be annealed along with the interconnect layers at 830. Fabricating each interconnect layer may include fabricating a dielectric material layer, such as Si3N4, SiO2, etc., using a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, etc. The dielectric layer may be patterned to create one or more vias. One or more suitable metal materials may be deposited in the vias and patterned to create one or more metal vias and / or metal pads.

[0093] 9A-9E are characteristic graphs illustrating IV characteristics of example RRAM devices having different device sizes and fabricated under the same annealing conditions.

[0094] IV curve characteristic graphs 911, 913, and 915 show IV characteristics of an RRAM device with a critical dimension of 0.18 µm. IV curve characteristic graphs 921, 923, and 925 show IV characteristics of an RRAM device with a critical dimension of 0.24 µm. IV curve characteristic graphs 931, 933, and 935 show IV characteristics of an RRAM device with a critical dimension of 0.28 µm. The RRAM devices corresponding to IV curve characteristic graphs 911, 921, and 931 do not include an interfacial layer. Each of the RRAM devices corresponding to IV curve characteristic graphs 913, 923, and 933 includes a thin interfacial layer (e.g., a layer of 0.2 nm–0.6 nm). In some embodiments, the thin interfacial layer can be and / or include a discontinuous layer. Each of the RRAM devices corresponding to IV curve characteristic graphs 915, 925, and 935 includes a thick interfacial layer (e.g., a layer of approximately or greater than 1 nm). As shown in FIG. 9A , the RRAM devices exhibit varying resistance. The RRAM devices corresponding to the IV curve characteristic graphs 921 , 931 , 913 , 923 , and 933 are non-formed RRAM devices, and their initial resistances are approximately 549Ω, 543Ω, 7.5kΩ, 465Ω, and 460Ω, respectively.

[0095] 9F-9J are graphs illustrating IV characteristics of example RRAM devices having the same device dimensions (eg, a critical dimension of 0.24 μm) fabricated under different annealing conditions.

[0096] The RRAM devices corresponding to the IV characteristic graphs 941, 943, and 945 were fabricated without annealing. The RRAM devices corresponding to the IV characteristic graphs 951, 953, and 955 were fabricated under short annealing conditions. The RRAM devices corresponding to the IV characteristic graphs 961, 963, and 965 were fabricated under long annealing conditions. Each of the RRAM devices corresponding to the IV characteristic graphs 941, 951, and 961 does not include an interfacial layer. Each of the RRAM devices corresponding to the IV characteristic graphs 943, 953, and 963 includes a thin interfacial layer (e.g., a layer of 0.2 nm to 0.6 nm). In some embodiments, the thin interfacial layer can be and / or include a discontinuous layer. Each of the RRAM devices corresponding to the IV characteristic graphs 945, 955, and 965 includes a thick interfacial layer (e.g., a layer of approximately or greater than 1 nm). The RRAM devices corresponding to the IV curves in graphs 951, 953, 961, and 963 are non-formed RRAM devices as described herein, and have initial resistances of approximately 549Ω, 460Ω, 389Ω, and 239Ω, respectively. Based on Figures 9A-9B , the annealing conditions and the thickness of the interfacial layer can be optimized to achieve a desired initial resistance, taking into account the device size.

[0097] FIG10 is a graph 1000 illustrating an IV curve of analog behavior of an example non-formational RRAM device according to some embodiments of the present invention. As shown, the non-formational RRAM device exhibits desirable analog behavior, i.e., by controlling current compliance, the device resistance can be tuned to multiple levels (or analog behavior) without a formation process, and the current is linearly proportional to the voltage (or linear behavior) at each resistance state.

[0098] FIG11 is a characteristic graph 1100 illustrating device read current characteristics over time for an example non-formed RRAM device according to some embodiments of the present invention. Graph 1100 illustrates device read current characteristics of an example RRAM device at 135°C. Graph 1100 may represent device retention test results for the ability of a non-formed RRAM device to maintain resistance levels over time. Graph 1100 may also represent the results of a read stability test, as the RRAM device is subjected to a constant read (with a read voltage of 0.2V) due to its ability to maintain resistance levels over time.

[0099] For simplicity of illustration, the methods of the present invention are depicted and described as a series of actions. However, the actions according to the present invention can occur in various orders and / or simultaneously, and in conjunction with other actions not presented and described herein. Furthermore, not all illustrated actions are required to implement the methods according to the disclosed subject matter. Furthermore, those skilled in the art will understand and appreciate that methods can alternatively be represented as a series of interrelated states via state diagrams or events.

[0100] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target dimension in some embodiments, within ±10% of a target dimension in some embodiments, within ±5% of a target dimension in some embodiments, within ±2% of a target dimension in some embodiments, within ±1% of a target dimension in some embodiments, and within ±0.1% of a target dimension in some embodiments. The terms "approximately" and "about" may include the target dimension. Unless otherwise specified or apparent from the context, all numerical values described herein are modified by the term "about."

[0101] As used herein, a range includes all values within that range. For example, a range of 1 to 10 can include any number, combination of numbers, subranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10, and fractions thereof.

[0102] The present invention has been described in detail above. However, it is apparent that the present invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form rather than in detail to highlight the present invention.

[0103] The terms "first", "second", "third", "fourth", etc. used in this article are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

[0104] As used herein, the words "example" or "exemplary" mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to present concepts in a concrete manner. Throughout this application, the term "or" is intended to be inclusive, not exclusive. That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to include any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied in any of these cases. Furthermore, as used in this application and the appended claims, "a" and "an" should generally be understood to mean "one or more," unless otherwise specified or clear from the context to be directed to the singular. Reference to "one embodiment" or "an embodiment" throughout this specification means that a particular feature, structure, or characteristic associated with that embodiment is included in at least one embodiment. Thus, the appearances of the phrases "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0105] As used herein, when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, there are no intervening elements or layers present.

[0106] Although additional changes and modifications to the present invention are undoubtedly obvious to those skilled in the art after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of the various embodiments are not intended to limit the scope of the patent application, which itself merely describes the technical features of the invention.

[0107] 100: Crossbar switch circuit 111a, 111b, 111i, 111n: lines 113a, 113b, 113j, 113m: alignment lines 120a, 120b, 120ij, 120z: cross-point devices 1200: Crosspoint device 1201:RRAM device 1203: Transistor 1211: bit line 1213: Line selection 1215: Word line G: Gate S: Source D: Drain 200a, 200b, 200c: RRAM devices 200d, 200e, 200f: Characteristic curve 210: bottom electrode 220: Switching oxide layer 225a: Conductive filament 225b: Interrupted conductive filaments 230: Top electrode 261, 263: Voltage range 300:RRAM devices 310: substrate 320: bottom electrode 330: Switching oxide layer 340: Interface layer 350: Top electrode 400:Semiconductor devices 401: substrate 403: Transistor 403a: Source 403b: Gate 403c: Drain 410: Interconnection layer 410a: First interconnection layer 410b: Second interconnection layer 411, 412, 414, 415: through-hole layer 411a, 411b, 411c: Metal through holes 412a, 412b, 412c: metal through holes 413:Metal through hole 421, 422, 423, 424, 425: Metal layer 421a, 421b, 421c: Metal pads 422a, 422b, 422c: metal pads 451: dielectric layer 500A, 500B, 500C, 500D: Curve Graph 511: Voltage range 513: Voltage range 521: High impedance state 523: low resistance state 600A, 600B, 600C, 600D: Curve Graph 611: Voltage range 613: Voltage range 621: Original state 623: low resistance state 700a: Flowchart 710, 720, 730, 735: Steps 700b: Flowchart 740, 750, 760: Steps 700c: Flowchart 770, 780, 790: Steps 800: Flowchart 810, 811, 813, 815, 817, 820, 830: Steps 911, 913, 915, 921, 923, 925, 931, 933, 935, 941, 943, 945, 951, 953, 955, 961, 963, 965: Characteristic curve diagram 1000: Graph 1100:Characteristic diagram

Claims

1. A method of operating the unformed RRAM device, comprising: Perform a first read operation on a first non-formable RRAM device in its initial state to determine a first initial resistance of the first non-formable RRAM device; A first reset operation is performed on the first non-formable RRAM device to switch the first non-formable RRAM device from a first initial resistance to a first target resistance, wherein the first target resistance is greater than the first initial resistance, and the first read operation and the first reset operation are performed without pre-forming conductive filaments in the first non-formable RRAM device during the formation process.

2. The method as described in claim 1, wherein the first reset current through the first non-formable RRAM device during the first reset operation is no greater than 500µA.

3. The method as described in claim 1, further comprising: Perform a first setting operation on the first non-formable RRAM device to switch the first non-formable RRAM device from the first target resistor to the second target resistor, wherein performing the first setting operation includes applying a first setting voltage to the first non-formable RRAM device, and the first setting voltage is not greater than 1.0V.

4. The method of claim 3, wherein performing a first reset operation on the first non-formable RRAM device includes applying a first reset voltage to the first non-formable RRAM device, and the first set voltage and the first reset voltage have opposite polarities.

5. The method as described in claim 1, further comprising: Perform a second read operation on the second non-formable RRAM device to determine the second initial resistance of the second non-formable RRAM device; A second setting operation is performed on the second non-formable RRAM device to switch the second non-formable RRAM device from a second initial resistance to a third target resistance, wherein the third target resistance is smaller than the second initial resistance, and the second read operation and the second setting operation are performed without pre-forming conductive filaments in the second non-formable RRAM device during the formation process.

6. The method as described in claim 5, further comprising: Applying a second reset voltage to the second non-formable RRAM device to switch the second non-formable RRAM device from a third target resistor to a fourth target resistor, wherein performing the second setting operation on the second non-formable RRAM device includes applying a second setting voltage to the second non-formable RRAM device, and the second reset voltage and the second setting voltage have opposite polarities.

7. The method of claim 6, wherein the second reset current through the second non-formable RRAM device in response to the second reset voltage is not greater than 500µA, and the second reset voltage is not greater than 1.0V.

Images