Semiconductor devices and semiconductor memory devices

Abstract

An embodiment provides a semiconductor device and a semiconductor memory device that can manufacture semiconductor devices with better quality. The semiconductor device of the embodiment includes: a plurality of gate electrodes extending along a first direction intersecting the vertical direction and spaced apart from each other in a second direction intersecting both the vertical and first directions; a plurality of bit electrodes extending above the gate electrodes along the second direction and spaced apart from each other in the first direction; and a plurality of oxide semiconductors, which, when viewed along the vertical direction, are arranged according to each region where the gate electrodes and bit electrodes intersect, extending along the vertical direction; and when viewed along the vertical direction, the gate electrodes in the first region are separated from the oxide semiconductors corresponding to the first region by a gate insulating film, and the bit electrodes in the first region are connected to the oxide semiconductors corresponding to the first region via upper electrodes; the cross-section of the oxide semiconductors perpendicular to the vertical direction has an elliptical shape.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a semiconductor memory device. Prior Technology

[0002] Semiconductor devices include those formed from oxide semiconductors. Summary of the Invention

[0003] The aim is to find a technology that can improve the quality of semiconductor devices by properly connecting an oxygen-containing semiconductor layer to an electrode.

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor memory device that can manufacture semiconductor devices of better quality.

[0005] The semiconductor device of the embodiment includes: a plurality of gate electrodes extending along a first direction intersecting the vertical direction and spaced apart from each other in a second direction intersecting the vertical direction and the first direction; a plurality of bit electrodes extending above the gate electrodes along the second direction and spaced apart from each other in the first direction; and a plurality of oxide semiconductors, which, when viewed along the vertical direction, are arranged according to each region where the gate electrodes and the bit electrodes intersect, and extend along the vertical direction; and when viewed along the vertical direction, the gate electrodes in the first region are separated by a gate insulating film and face the oxide semiconductor corresponding to the first region, and the bit electrodes in the first region are connected to the oxide semiconductor corresponding to the first region via an upper electrode; the cross section of the oxide semiconductor perpendicular to the vertical direction has an elliptical shape.

[0006] An embodiment of the semiconductor memory device includes: the aforementioned semiconductor device; a first capacitor electrode connected to the aforementioned oxide semiconductor via a lower electrode; a second capacitor electrode facing the aforementioned first capacitor electrode; and a dielectric film disposed between the aforementioned first capacitor electrode and the aforementioned second capacitor electrode. Simple Explanation of the Diagram

[0007] Figure 1 is a circuit diagram illustrating an example of the circuit configuration of the memory cell array in the first embodiment. Figure 2 is a cross-sectional schematic diagram illustrating the structural example of the semiconductor memory device of the first embodiment, and shows a cross-sectional view parallel to the ZX plane. Figure 3 shows a detailed cross-sectional view of the semiconductor device 30 as viewed from a section 70ZX parallel to the ZX plane and from a section 70ZX encompassing the oxide semiconductor layer 70. Figure 4 shows a detailed cross-sectional view of the semiconductor device 30 as viewed from a section 70YZ parallel to the YZ plane and encompassing the oxide semiconductor layer 70. Figure 5 is a cross-sectional view at the cut line VV shown in Figures 3 and 4. Figure 6 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 8 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 9 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 10 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 11 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 12 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 13 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 14 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 15 is a cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment, and is parallel to the ZX plane. Figure 16 is a cross-sectional view of the semiconductor device 30B at the cut line VV shown in Figures 3 and 4. Figure 17 is a cross-sectional view of the semiconductor device 30C at the cut line VV shown in Figures 3 and 4. Figure 18 shows a detailed cross-sectional view of the semiconductor device 30D as viewed from a cross-section 70ZX parallel to the ZX plane and encompassing the oxide semiconductor layer 70. Figure 19 shows a detailed cross-sectional view of the semiconductor device 30D as viewed from a cross-section 70YZ parallel to the YZ plane and encompassing the oxide semiconductor layer 70. Figure 20 is a cross-sectional view of the cut line XX-XX shown in Figures 18 and 19. Figure 21 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 22 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 23 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 24 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 25 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 26 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 27 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 28 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment, and is parallel to the ZX plane. Figure 29 is a cross-sectional view of the semiconductor device 30E at the cut line XX-XX shown in Figures 18 and 19. Figure 30 shows a cross-sectional view of the semiconductor device 30F at the cut line XX-XX shown in Figures 18 and 19. Implementation

[0008] The following description, with reference to the accompanying drawings, will focus on this embodiment. To facilitate understanding, identical symbols will be used for the same constituent elements in each drawing, and repetitive explanations will be omitted.

[0009] [First Implementation Form] The configuration of the semiconductor memory device according to the first embodiment will be described. In various diagrams, the X-axis, Y-axis, and Z-axis are sometimes shown. The X-axis, Y-axis, and Z-axis form a right-handed 3D orthogonal coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the opposite direction is sometimes referred to as the X-axis- direction; the same applies to the other axes. Additionally, the Z-axis+ direction and Z-axis- direction are sometimes referred to as "above" and "below," respectively. Furthermore, the planes orthogonal to the X-axis, Y-axis, or Z-axis are sometimes referred to as the YZ plane, ZX plane, or XY plane. Also, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms used to indicate relative positional relationships within the diagrams and are not necessarily terms indicating orientation based on the vertical direction.

[0010] Furthermore, unless otherwise specifically stated, the dimensions of the constituent elements shown in the drawings may differ from the actual dimensions for ease of understanding and explanation.

[0011] In this specification, "connection" includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0012] In this specification, "formed above" includes not only the case where it is formed in contact with the above, but also the case where it is formed above, except where otherwise specified. The same applies to the case of "formed below".

[0013] The semiconductor memory device 101 in the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) and has a memory cell array.

[0014] As shown in Figure 1, the memory cell array contains a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0015] In Figure 1, as an example of a plurality of character lines WL, character lines WLn, WLn+1, and WLn+2 are shown (where n is a positive integer). Also in Figure 1, as an example of a bit line BL, bit lines BLm, BLm+1, and BLm+2 are shown (where m is a positive integer). Furthermore, the number of plurality of memory cells MC is not limited to the number shown in Figure 1.

[0016] Multiple memory cells (MCs) can be arranged in a matrix to form a memory cell array. A memory cell (MC) includes a field-effect transistor (FET), i.e., a memory transistor (MTR), and a memory capacitor (MCP).

[0017] A series of memory cells MC are set along the column direction and connected to the character line WL (e.g., character line WLn) corresponding to their own column (e.g., column n). A series of memory cells MC are set along the row direction and connected to the bit line BL (e.g., bit line BLm+2) corresponding to their own row (e.g., row m+2).

[0018] In detail, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the column to which the memory cell MC belongs. The source or drain of the memory transistor MTR is connected to the bit line BL corresponding to the row to which the memory cell MC belongs.

[0019] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to either the source or the drain of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power supply line (not shown) that provides a specific potential.

[0020] The memory cell MC is configured such that data can be retained by using the current flowing through the corresponding bit line BL to store charge in the memory capacitor MCP through the switching of the memory transistor MTR based on the potential of the corresponding word line WL.

[0021] As shown in Figure 2, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35 and 63.

[0022] The capacitor 20 includes an insulating film 22 (an example of a "dielectric film"), a conductor 23, a capacitor electrode 24 (an example of a "first capacitor electrode"), and a capacitor electrode 25 (an example of a "second capacitor electrode").

[0023] The semiconductor device 30 includes a field-effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 disposed above the field-effect transistor 40, a lower electrode 32 disposed below the field-effect transistor 40, and a conductive layer 51 (an example of a "bit electrode").

[0024] The field-effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of a "gate electrode"), and an insulating layer 45. The field-effect transistor 40 is equivalent to the memory transistor MTR of a memory cell MC (see Figure 1).

[0025] An oxide semiconductor layer 70 is formed within the insulating layer 45, having an upper end 70a and a lower end 70b. The oxide semiconductor layer 70 is a columnar structure extending in the vertical direction. The oxide semiconductor layer 70 forms the channel for the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0026] The oxide semiconductor layer 70 is a semiconductor in which oxygen defects become donors. The oxide semiconductor layer 70 includes at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), iridium (Ir), ruthenium (Ru) and titanium (Ti), as well as oxygen.

[0027] In this embodiment, the oxide semiconductor layer 70 comprises indium, zinc, and gallium as metallic elements. Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely IGZO (InGaZnO). Alternatively, the oxide semiconductor layer 70 may be other types of oxide semiconductors.

[0028] The field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) that is substantially perpendicular to the surface of the semiconductor substrate 10.

[0029] The conductive layer 42 is separated from the gate insulating film 43 and faces the oxide semiconductor layer 70. Specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40, and the gate insulating film 43 surrounds the oxide semiconductor layer 70 between its upper end 70a and lower end 70b. The conductive layer 42 may contain, for example, tungsten (W).

[0030] The gate insulating film 43 comprises, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen. The gate insulating film 43 is formed in such a way that it covers the entire periphery of the oxide semiconductor layer 70.

[0031] An upper electrode 50 is formed above the oxide semiconductor layer 70 and connected to the upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0032] A metal oxide layer 50a is connected to the upper end 70a of the oxide semiconductor layer 70. In this embodiment, the metal oxide layer 50a is in contact with the upper end 70a of the oxide semiconductor layer 70. The metal oxide layer 50a contains an oxide conductive material. Specifically, the oxide conductive material is an oxide conductive material containing indium and tin as metal elements. More specifically, the oxide conductive material is indium-tin oxide (ITO).

[0033] A metal film 50c is disposed above the metal oxide layer 50a and contains tungsten. A barrier metal layer 50b is formed between the metal oxide layer 50a and the metal film 50c. The barrier metal layer 50b contains, for example, titanium and nitrogen. In this embodiment, the barrier metal layer 50b is formed of titanium nitride (TiN).

[0034] The conductive layer 51 is connected to the upper end 70a of the oxide semiconductor layer 70 via the upper electrode 50. The conductive layer 51 contains, for example, tungsten (W).

[0035] The lower electrode 32 is connected to the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 is formed of a metal oxide containing an oxide conductive material. Specifically, the lower electrode 32 contains, for example, indium and tin as metal elements. In this embodiment, the lower electrode 32 is formed of indium-tin oxide (ITO).

[0036] Furthermore, the lower electrode 32 and the metal oxide layer 50a are not limited to ITO, but may also be composed of at least one element including indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten and iron.

[0037] Circuit 11 constitutes a plurality of memory cells MC (capacitors 20) in the semiconductor memory device 101, a decoder for selecting specified memory cells MC in the field-effect transistor 40, a sense amplifier connected to bit line BL, and a temporary register composed of SRAM (Static Random Access Memory), and other peripheral circuits. Circuit 11 may include CMOS circuitry with P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs) formed by CMOS (Complementary Metal Oxide Semiconductor) processes.

[0038] The field-effect transistor of circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon substrate. Pch-FET and Nch-FET are so-called horizontal field-effect transistors. These horizontal field-effect transistors have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have channels in a region near the surface of the semiconductor substrate 10 for allowing carriers to flow along the X-axis or Y-axis direction, which is substantially parallel to the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 can have a conductivity type from P-type to N-type. For convenience, Figure 2 illustrates an example of the field-effect transistor of circuit 11.

[0039] Capacitor 20 is a memory capacitor MCP contained in the memory cell MC (see Figure 1). Although four capacitors 20 are shown in Figure 2, the number of capacitors 20 is not limited to four.

[0040] In this embodiment, capacitor 20 is disposed above semiconductor substrate 10. Capacitor electrode 24 of capacitor 20 is connected to oxide semiconductor layer 70 via conductor 21 and lower electrode 32. Capacitor electrode 25 faces capacitor electrode 24. Insulating film 22 is disposed between capacitor electrode 24 and capacitor electrode 25.

[0041] The capacitor is a 20-series cylindrical capacitor or other three-dimensional capacitor. Alternatively, other capacitors with a charge-accumulating structure can be used as the capacitor in this embodiment.

[0042] Specifically, capacitor electrode 24 is located below lower electrode 32. Capacitor electrode 24 has an upper end facing the lower end of conductor 21, and a columnar shape extending downward from this upper end. Conductor 21 is formed to cover both lower electrode 32 and capacitor electrode 24. Insulating film 22 is formed to cover conductor 21. Capacitor electrode 25 surrounds a portion below insulating film 22 and has a lower end that abuts against the upper end face of conductor 23.

[0043] The capacitor electrode 24 may contain materials such as SiGe, which contains silicon and germanium. The insulating film 22 may contain materials such as ZrAlO, which contains zirconium, aluminum, and oxygen. The conductor 21 may contain materials such as titanium nitride, which contains nitrogen and titanium. The conductor 23 and the capacitor electrode 25 may contain materials such as tungsten and titanium nitride.

[0044] Figure 3 shows a detailed cross-sectional view of the semiconductor device 30 as viewed from a section 70ZX parallel to the ZX plane and encompassing the oxide semiconductor layer 70. Figure 4 shows a detailed cross-sectional view of the semiconductor device 30 as viewed from a section 70YZ parallel to the YZ plane and encompassing the oxide semiconductor layer 70. Figure 5 is a cross-sectional view at the cut-off line VV shown in Figures 3 and 4. Furthermore, in Figure 5, to illustrate the arrangement of the conductive layer 42, conductive layer 51, and oxide semiconductor layer 70, the conductive layer 51 as viewed from above is shown overlaid.

[0045] As shown in Figures 3-5, the conductive layer 42 extends along the Y-axis direction (an example of the "first direction"), which intersects the vertical direction. A plurality of conductive layers 42 are provided. The plurality of conductive layers 42 are repeatedly provided in the X-axis direction (an example of the "second direction").

[0046] A plurality of conductive layers 42 are spaced apart from each other in the X-axis direction. Specifically, in the conductive layers 42 and the insulating film 45b, grooves 45ca are formed that divide the conductive layers 42 and extend in the Y-axis direction. The grooves 45ca are filled by the insulating film 45c. The insulating film 45c, for example, contains silicon and oxygen. That is, two adjacent conductive layers 42 are separated by the insulating film 45c. The conductive layers 42 correspond to character lines WL (see Figure 1).

[0047] The conductive layer 42 separates a plurality of gate insulating films 43, which respectively surround a plurality of oxide semiconductor layers 70 disposed along the Y-axis direction.

[0048] Specifically, the conductive layer 42 includes: a plurality of surrounding portions 42b, each of which is surrounded by an equally spaced gate insulating film 43, which surrounds a plurality of oxide semiconductor layers 70; and at least one connecting portion 42c, which connects the surrounding portions 42b to each other. In this embodiment, the width of the conductive layer 42 in the X-axis direction is substantially constant.

[0049] A conductive layer 51 extends along the X-axis above the conductive layer 42. A plurality of conductive layers 51 are provided. The plurality of conductive layers 51 are repeatedly provided along the Y-axis.

[0050] A plurality of conductive layers 51 are spaced apart from each other in the Y-axis direction. Specifically, a groove 66ca extending in the X-axis direction is formed between two adjacent conductive layers 51, separating the two conductive layers 51. An insulating layer and an air gap are provided in the groove 45ca, for example. That is, two adjacent conductive layers 51 are separated by the groove 66ca. The conductive layer 51 corresponds to a bit line BL (see Figure 1). In this embodiment, the width of the conductive layer 51 in the Y-axis direction is approximately constant.

[0051] When observing the conductive layer 42 and the conductive layer 51 along the vertical direction, there are multiple areas where the conductive layers 42 and 51 intersect (hereinafter, sometimes referred to as the intersection area IA) (see Figure 5).

[0052] The oxide semiconductor layer 70 is arranged according to each intersection region IA. That is, a plurality of oxide semiconductor layers 70 are arranged in two dimensions. Specifically, a portion of the plurality of oxide semiconductor layers 70 is repeatedly arranged along the Y-axis direction. Also, a portion of the plurality of oxide semiconductor layers 70 is repeatedly arranged along the X-axis+ direction.

[0053] In detail, when the conductive layer 42 and the conductive layer 51 are viewed along the vertical direction, the conductive layer 42, through one of the plurality of cross regions IA, namely cross region IA1 (an example of "first region"), is separated from the gate insulating film 43 and faces the oxide semiconductor layer 70 corresponding to the cross region IA1. Here, the oxide semiconductor layer 70 corresponding to the cross region IA1 is, for example, an oxide semiconductor layer 70 that overlaps with the cross region IA1 when viewed along the vertical direction.

[0054] In this embodiment, when viewed along the vertical direction, the conductive layer 42 of the cross region IA1 blocks the gate insulating film 43 and surrounds the oxide semiconductor layer 70 corresponding to the cross region IA1. In other words, when viewed along the vertical direction, the oxide semiconductor layer 70 corresponding to the cross region IA1 penetrates through the conductive layer 42 of the cross region IA1.

[0055] Furthermore, when observing the conductive layer 42 and the conductive layer 51 along the vertical direction, the conductive layer 51 through the cross region IA1 is connected to the oxide semiconductor layer 70 corresponding to the cross region IA1 through the upper electrode 50.

[0056] Furthermore, when observing two adjacent oxide semiconductor layers 70 along the X-axis in the vertical direction, one oxide semiconductor layer 70 protrudes from the conductive layer 51 towards the + side in the Y-axis direction (an example of the "first side"). And the other oxide semiconductor layer 70 protrudes from the conductive layer 51 towards the - side in the Y-axis direction (an example of the "second side").

[0057] The cross-section CS1 of the oxide semiconductor layer 70, perpendicular to the vertical direction, has an elliptical shape. Here, the elliptical shape is a shape formed by compressing a perfect circle into an ellipse, oblong, or oval shape. Alternatively, the elliptical shape can be a shape in which the corners of a rectangle are rounded.

[0058] The length of the major axis LA1 of section CS1 is at least 1.1 times the length of the minor axis SA1 of section CS1. Furthermore, the major axis LA1 and the minor axis SA1 are along the X-axis and Y-axis directions, respectively. In this embodiment, the major axis LA1 and the minor axis SA1 are approximately parallel to the X-axis and Y-axis, respectively.

[0059] Section CS1 is located at the opposing portion 70c of the oxide semiconductor layer 70 and the conductive layer 42. Furthermore, the cross-sectional shape of the first connection portion connecting the oxide semiconductor layer 70 and the upper electrode 50 (i.e., the upper end 70a) and the cross-sectional shape of the second connection portion connecting the oxide semiconductor layer 70 and the lower electrode 32 (i.e., the lower end 70b) are the same elliptical shape as section CS1.

[0060] (Effect) As described above, by configuring the long axis LA1 of the cross section CS1 along the width direction of the conductive layer 42 (i.e., the X-axis), the amount of protrusion of the oxide semiconductor layer 70 from the conductive layer 51 can be reduced when observing the oxide semiconductor layer 70 in the vertical direction. Specifically, when observing the oxide semiconductor layer 70 in the vertical direction, the distance Dm1 between the protruding oxide semiconductor layer 70 and the conductive layer 51 on the non-protruding side of two adjacent conductive layers 51 can be ensured. This suppresses the electrical short circuit between two adjacent conductive layers 51 through the upper electrode 50 due to manufacturing deviations. Furthermore, compared to the case where the shape of the cross section CS1 is a perfect circle, the contact area between the oxide semiconductor layer 70 and the upper electrode 50 or lower electrode 32 can be increased, thus reducing the resistance between the oxide semiconductor layer 70 and the upper electrode 50 or lower electrode 32.

[0061] [Manufacturing method of semiconductor device 30] The following describes a method for manufacturing a semiconductor device 30 as an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0062] First, as shown in Figure 6, an insulating film 45b, a conductive layer 42, and insulating films 45c and 45a are laminated above the lower electrode 32 and the insulating layer 35. Insulating films 45a and 45b extend substantially parallel to the XY plane. The conductive layer 42 and the insulating film 45c are columnar bodies extending in the Y-axis direction.

[0063] Next, as shown in Figure 7, a transistor hole TH is formed in the insulating film 45a, conductive layer 42, and insulating film 45b with the lower electrode 32 exposed, and then cleaned. The transistor hole TH extends approximately parallel to the Z-axis. The lower electrode 32 is exposed at the bottom of the transistor hole TH. The cross-section of the transistor hole TH perpendicular to the vertical direction has an elliptical shape.

[0064] Next, as shown in Figure 8, a gate insulating film 43 is formed on the surface above the covered insulating film 45a and inside the transistor hole TH.

[0065] Next, as shown in Figure 9, a portion of the gate insulating film 43 is etched using reactive ion etching. This exposes the lower electrode 32 at the bottom of the transistor aperture TH.

[0066] Next, as shown in Figure 10, an oxide semiconductor layer 70 is formed on the surface above the insulating film 45a and the transistor hole TH. The oxide semiconductor layer 70 is in contact with the upper surface of the lower electrode 32 exposed at the bottom of the transistor hole TH. In this way, the transistor hole TH is filled by the oxide semiconductor layer 70.

[0067] Next, as shown in Figure 11, a portion of the oxide semiconductor layer 70 is removed, exposing the surface above the insulating film 45a. At this point, the surface of the upper end 70a of the oxide semiconductor layer 70 and the surface above the insulating film 45a are aligned in the Z-axis direction.

[0068] Next, as shown in FIG12, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top above the insulating film 45a and the oxide semiconductor layer 70. Furthermore, an LPHM (Landing Pad Hard Mask) film 50f, for example containing silicon oxide, is formed above the metal film 50c.

[0069] Next, as shown in Figure 13, after forming a mask by photolithography on the surface of the LPHM film 50f, including film deposition, resist coating, exposure, development, and stripping, an upper electrode 50, which functions as a bonding pad, is formed by etching. The upper electrode 50 includes a barrier metal layer 51a, a barrier metal layer 50b, a metal film 50c, and an insulating film 50d. The insulating film 50d covers the area surrounding the barrier metal layer 50b and the metal film 50c. The insulating film 50d is formed, for example, by atomic layer deposition.

[0070] Next, as shown in FIG14, an LP substrate 50e, for example containing silicon oxide, is formed on the surface above the insulating film 45a and the upper electrode 50. An insulating layer 63 is formed above the LP substrate 50e to fill the gaps in the LP substrate 50e. The insulating layer 63 contains, for example, silicon oxide. Furthermore, the exposed surface is subjected to chemical mechanical polishing.

[0071] Next, as shown in FIG15, a barrier metal layer 51a, a conductive layer 51, and a barrier metal layer 51b are formed from bottom to top on the exposed surface. The barrier metal layers 51a and 51b may contain, for example, titanium nitride. The conductive layer 51 may contain, for example, tungsten.

[0072] Furthermore, BLHM (Bit Line Hard Mask) films 66a and 66b are formed from bottom to top on the surface above the barrier metal layer 51b. BLHM films 66a and 66b each contain, for example, silicon nitride and silicon oxide.

[0073] Next, as shown in Figures 3 and 4, after forming a mask by performing film deposition, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30 using photolithography, a trench 66ca is formed in the semiconductor device 30 by etching, extending substantially parallel to the X-axis and penetrating to the insulating layer 63 and the metal film 50c. Here, the barrier metal layer 51a, the conductive layer 51, and the barrier metal layer 51b extend substantially parallel to the X-axis and are separated into electrodes that are repeatedly arranged in the Y-axis+ direction. These electrodes correspond to bit lines BL (see Figure 1).

[0074] [Second Implementation] The semiconductor device 30B of the second embodiment will be described. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and only the differences will be explained. In particular, the same effects of the same structure will not be mentioned sequentially in each embodiment.

[0075] Figure 16 is a cross-sectional view of the semiconductor device 30B at the cut line VV shown in Figures 3 and 4. The viewing angle of Figure 16 is the same as that of Figure 5.

[0076] As shown in Figure 16, the difference between the semiconductor device 30B in the second embodiment and the semiconductor device 30 in the first embodiment is that the long axis LA1 in the cross-section CS1 of the oxide semiconductor layer 70 is along the Y-axis direction. In this embodiment, the long axis LA1 and the short axis SA1 are approximately parallel to the Y-axis and X-axis, respectively.

[0077] (Effect) As described above, by configuring the long axis of the cross section CS1 along the Y-axis direction, i.e., the extension direction of the conductive layer 42, the area of ​​the cross section CS1 of the oxide semiconductor layer 70 can be maintained, while the width of the conductive layer 42 in the X-axis direction can be reduced. In this way, since a plurality of conductive layers 42 can be arranged closely, the integration density of the semiconductor device 30B can be improved.

[0078] [Third Implementation Form] The semiconductor device 30C of the third embodiment will be described. Figure 17 is a cross-sectional view of the semiconductor device 30C at the cut line VV shown in Figures 3 and 4. The viewing angle of Figure 17 is the same as that of Figure 5.

[0079] As shown in Figure 17, the difference between the semiconductor device 30B in the third embodiment and the semiconductor device 30 in the first embodiment is that the direction of the long axis LA1 of the cross section CS1 of the oxide semiconductor layer 70 intersects the Y-axis and X-axis directions. In this embodiment, the direction of the long axis LA1 intersects the X-axis direction at approximately 30°.

[0080] (Effect) As described above, by the configuration where the long axis LA1 of the cross section CS1 intersects with the Y-axis and X-axis, the aforementioned distance Dm1 can be ensured when observing the oxide semiconductor layer 70 along the vertical direction, and the area of ​​the cross section CS1 of the oxide semiconductor layer 70 can be maintained, while reducing the width of the conductive layer 42 in the X-axis direction. This suppresses the electrical short circuit between two adjacent conductive layers 51 through the upper electrode 50 due to manufacturing deviations. Furthermore, since a plurality of conductive layers 42 can be densely arranged, the integration density of the semiconductor device 30B can be improved.

[0081] [Fourth Implementation Form] The semiconductor device 30D of the fourth embodiment will be described. Figure 18 shows a detailed cross-sectional view of the semiconductor device 30D as viewed from a cross-section 70ZX parallel to the ZX plane and encompassing the oxide semiconductor layer 70. Figure 19 shows a detailed cross-sectional view of the semiconductor device 30D as viewed from a cross-section 70YZ parallel to the YZ plane and encompassing the oxide semiconductor layer 70. Figure 20 is a cross-sectional view at the cut line XX-XX shown in Figures 18 and 19.

[0082] As shown in Figures 18 to 20, the difference between the semiconductor device 30D in the fourth embodiment and the semiconductor device 30 in the first embodiment is that the surrounding portion 42b in the conductive layer 42 is formed by a self-aligning process.

[0083] Compared to the semiconductor device 30 shown in Figures 3 and 4, the semiconductor device 30D further includes a spacer film 311. In the semiconductor device 30D, the width of the connecting portion 42c in the X-axis direction is narrower than the width of the surrounding portion 42b in the X-axis direction.

[0084] In other words, when the conductive layer 42 is viewed along the vertical direction, the width of the conductive layer 42 in the X-axis direction becomes narrower between two adjacent oxide semiconductor layers 70 in the Y-axis direction.

[0085] A spacer membrane 311 (an example of a "second insulating membrane") is disposed above the conductive layer 42. The spacer membrane 311 is, for example, an oxide of silicon. The spacer membrane 311 includes a cylindrical portion 311a and a plate-shaped portion 311b.

[0086] A cylindrical portion 311a is disposed above the surrounding portion 42b in the conductive layer 42 and extends substantially parallel to the Z-axis. Specifically, the lower end of the cylindrical portion 311a forms an annular surface that contacts the upper surface 42a of the conductive layer 42. The cylindrical portion 311a is separated from the oxide semiconductor layer 70 by a gate insulating film 43. A plate-like portion 311b is disposed above the connecting portion 42c in the conductive layer 42 and extends substantially parallel to the XY plane.

[0087] [Manufacturing Method of Semiconductor Device 30D] The following describes a method for manufacturing a semiconductor device 30D as an example of a method for manufacturing a semiconductor device according to the fourth embodiment.

[0088] First, as shown in Figure 21, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are sequentially disposed above the lower electrode 32 and the insulating layer 35. The insulating film 45b, conductive layer 42, and insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH is formed, extending substantially parallel to the Z-axis and penetrating the insulating film 45ba, conductive layer 42, and insulating film 45b, and then cleaned. At the bottom of the transistor hole TH, the lower electrode 32 is exposed. The cross-section of the transistor hole TH perpendicular to the vertical direction has an elliptical shape.

[0089] Next, as shown in Figure 22, a sacrificial amorphous silicon layer 170 is formed on the surface above the insulating film 45ba and the transistor hole TH. In this way, the transistor hole TH is filled by the sacrificial amorphous silicon layer 170.

[0090] Next, as shown in Figure 23, by etching back the sacrificial amorphous silicon layer 170, a portion of the upper part of the sacrificial amorphous silicon layer 170 is removed, exposing the surface above the insulating film 45ba. At this time, the upper end surface of the sacrificial amorphous silicon layer 170 is aligned, for example, with the surface above the insulating film 45ba in the Z-axis direction.

[0091] Next, as shown in Figure 24, the insulating film 45ba is removed by etching.

[0092] Next, as shown in FIG25, a sacrificial amorphous silicon layer 170 exposed above the more conductive layer 42 and a spacer film 311 above the conductive layer 42 are formed.

[0093] Next, as shown in Figure 26, after forming a mask by photolithography on the surface above the spacer film 311 through film deposition, resist coating, exposure, development, and stripping, a groove 45ca extending substantially parallel to the Y-axis and penetrating to the insulating film 45b is formed by etching. In this way, the spacer film 311 is separated into a cylindrical portion 311a and a plate-shaped portion 311b. Furthermore, the conductive layer 42, extending substantially parallel to the Y-axis, is separated into a plurality of electrodes repeatedly disposed in the X-axis+ direction. These electrodes correspond to the character line WL (see Figure 1).

[0094] Furthermore, the surrounding portion 42b in the conductive layer 42 is formed by a self-aligned process. In detail, even if the mask formation position of the photolithography is offset, the cylindrical portion 311a of the spacer film 311 located on the side of the sacrificial amorphous silicon layer 170 also functions as a mask, so the surrounding portion 42b is self-aligned and formed around the transistor hole TH.

[0095] Next, as shown in Figure 27, the insulating film 45c of the landfill 45ca and the insulating film 45a disposed above the spacer 311 are integrally formed. Furthermore, by chemical mechanical polishing, a portion of the insulating film 45a is removed, exposing the surface above the sacrificial amorphous silicon layer 170 from the insulating film 45a.

[0096] Next, as shown in Figure 28, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0097] The subsequent manufacturing steps are the same as those shown in Figures 8 to 15, so detailed descriptions are omitted.

[0098] [Fifth Implementation Form] The semiconductor device 30E of the fifth embodiment will be described. Figure 29 is a cross-sectional view of the semiconductor device 30E at the cut line XX-XX shown in Figures 18 and 19. The viewing angle of Figure 29 is the same as that of Figure 20.

[0099] As shown in Figure 29, the difference between the semiconductor device 30E in the fifth embodiment and the semiconductor device 30D in the fourth embodiment is that the long axis LA1 in the cross-section CS1 of the oxide semiconductor layer 70 is along the Y-axis direction. In this embodiment, the long axis LA1 and the short axis SA1 are approximately parallel to the Y-axis and X-axis, respectively.

[0100] [Sixth Implementation Form] The semiconductor device 30F of the sixth embodiment will be described. Figure 30 is a cross-sectional view of the semiconductor device 30F at the cut line XX-XX shown in Figures 18 and 19. The viewing angle of Figure 30 is the same as that of Figure 20.

[0101] As shown in Figure 30, the difference between the semiconductor device 30F in the sixth embodiment and the semiconductor device 30D in the fourth embodiment is that the direction of the long axis LA1 of the cross section CS1 of the oxide semiconductor layer 70 intersects the Y-axis and X-axis directions. In this embodiment, the direction of the long axis LA1 intersects the X-axis direction at approximately 30°.

[0102] Alternatively, the cross-section CS1 of the oxide semiconductor layer 70, which is perpendicular to the vertical direction, can be configured as follows: having a first length in the Y-axis direction and a second length greater than the first length in the X-axis direction, which intersects the vertical direction and the Y-axis direction.

[0103] (a) A semiconductor device comprising: An oxide semiconductor having an upper end and a lower end, extending along the vertical direction; The upper electrode is connected to the upper end of the oxide semiconductor. The lower electrode is connected to the lower end of the aforementioned oxide semiconductor; and A gate electrode, extending along a first direction intersecting the aforementioned vertical direction, is positioned between the upper and lower ends of the oxide semiconductor, separated by a first insulating film and facing the oxide semiconductor; and The cross-section of the oxide semiconductor intersecting the above-mentioned vertical direction has a first length in the first direction and a second length greater than the first length in the second direction intersecting the above-mentioned vertical direction and the first direction.

[0104] (b) A semiconductor device, When viewed along the aforementioned vertical direction, the oxide semiconductor corresponding to the first region penetrates through the gate electrode of the first region. When the gate electrode is viewed along the above-mentioned up-down direction, the width of the gate electrode in the second direction becomes narrower between two adjacent oxide semiconductors in the first direction.

[0105] The above description has been based on specific examples and describes this embodiment. However, this disclosure is not limited to these specific examples. Any design modifications made by those skilled in the art in these specific examples that possess the features of this disclosure are included within its scope. The elements, their configurations, conditions, shapes, etc., of the above-described specific examples are not limited to those illustrated and can be appropriately modified. The combinations of the elements of the above-described specific examples can be appropriately changed as long as they do not create technical contradictions.

[0106] [Reference to related applications] This application enjoys priority based on Japanese Patent Application No. 2024-162719 (filed on September 19, 2024). This application includes all contents of the basic application by reference to that basic application.

[0107] 10: Semiconductor substrate 11: Circuit 20: Capacitor 21,23: Conductors 22: Insulating film 24, 25: Capacitor electrodes 30, 30B, 30C, 30D, 30E, 30F: Semiconductor devices 32: Lower electrode 33: Conductor 34, 35: Insulation layer 40: Field-effect transistor 42: Conductive layer 42a: Face 42b: Enclosure 42c: Connecting part 43: Gate insulating film 45: Insulation layer 45a, 45b, 45ba, 45c: Insulating film 45ca: Groove 50: Upper electrode 50a: Metal oxide layer 50b: Barrier metal layer 50c: Metallic film 50d: Insulating film 50e:LP liner 50f:LPHM membrane 51: Conductive layer 51a, 51b: Barrier metal layer 63: Insulation layer 66a, 66b: BLHM membrane 66c: Insulating film 66ca: Groove 70: Oxide semiconductor layer 70a: Upper end 70b: Lower end 70c: Opposing part 70YZ: Section 70ZX: Section 101: Semiconductor memory device 170: Sacrificial amorphous silicon layer 301: Liner 311: Spare membrane 311a: Cylindrical section 311b: plate-shaped part BLm: Bitline BLm+1: Bit line BLm+2: Bit line CS1: Profile Dm1: Distance IA, IA1: Intersection region LA1: Long wheelbase MC: Memory Cell MCP: Memory Capacitor MTR: Memory Transistor SA1: Short axis TH: Transistor aperture WLn: Character Line WLn+1: Character line WLn+2: Character Line

Claims

1. A semiconductor device comprising: a plurality of gate electrodes extending along a first direction intersecting a vertical direction and spaced apart from each other in a second direction intersecting the vertical direction and the first direction; a plurality of bit electrodes extending above the gate electrodes along the second direction and spaced apart from each other in the first direction; and a plurality of oxide semiconductors, which, when viewed along the vertical direction, are disposed according to each region where the gate electrodes and the bit electrodes intersect, extending along the vertical direction; and when viewed along the vertical direction, the gate electrodes in the region, i.e., the first region, are separated by a gate insulating film and face the oxide semiconductor corresponding to the first region, and the bit electrodes in the first region are connected to the oxide semiconductor corresponding to the first region via upper electrodes; the cross-section of the oxide semiconductor perpendicular to the vertical direction has an elliptical shape.

2. The semiconductor device of claim 1, wherein the long axis of the cross section is along the second direction.

3. The semiconductor device of claim 1, wherein the direction of the major axis of the cross section intersects the first direction and the second direction.

4. The semiconductor device of claim 1, wherein the length of the major axis of the aforementioned cross-section is at least 1.1 times the length of the minor axis of the aforementioned cross-section.

5. The semiconductor device of claim 1, wherein the cross-section is located at the first connection portion of the oxide semiconductor and the upper electrode, the second connection portion of the oxide semiconductor and the lower electrode, or the opposing portion of the oxide semiconductor and the gate electrode.

6. The semiconductor device of claim 1, wherein when two adjacent oxide semiconductors are viewed along the above-mentioned vertical direction in the above-mentioned second direction, one protrudes from the above-mentioned bit electrode toward the first side of the above-mentioned first direction, and the other protrudes from the above-mentioned bit electrode toward the second side of the above-mentioned first direction.

7. The semiconductor device of claim 1, wherein the gate electrode includes a plurality of surrounding portions that enclose a plurality of oxide semiconductors respectively through the gate insulating film, and at least one connecting portion that connects the surrounding portions to each other, and the width of the connecting portion in the second direction is narrower than the width of the surrounding portions in the second direction.

8. A semiconductor memory device comprising: the semiconductor device as claimed in claim 1; a first capacitor electrode connected to the oxide semiconductor via a lower electrode; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode.

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