Semiconductor structure and manufacturing method thereof

Abstract

A manufacturing method includes: forming a gate spacer layer around a sacrificial gate structure disposed above a substrate; performing processing operations on a first material layer including the gate spacer layer to make the first material layer more resistant to germanium (Ge) diffusion during a metal gate replacement operation; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer prevents Ge from entering the metal gate.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer and a semiconductor material layer on a semiconductor substrate; and using photolithography to pattern the material layers to form circuit components and elements on these material layers.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting.

[0007] For the sake of brevity, conventional techniques related to the manufacture of conventional semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionalities not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the description may represent multiple components.

[0008] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, parts, and / or segments, these elements, components, regions, layers, parts, and / or segments are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, part, or segment from another region, layer, or segment. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, part, or segment discussed below may be referred to as the second element, component, region, layer, part, or segment.

[0009] Furthermore, for ease of description, spatially related terms such as "above," "overlapping," "on," "above," "top," "below," "under," "below," "below," "under," "bottom," etc., may be used herein to describe the relationship between one element or feature and another element or feature, as illustrated in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptive terms used herein may be interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be located directly above the other element, or there may be intermediate elements or layers present.

[0010] Furthermore, the component symbols and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0011] It should be noted that the embodiments described by references to "an embodiment," "an embodiment," "an exemplary embodiment," "illustrative," "an example," etc., in the specification may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing these features, structures, or characteristics in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0012] In some embodiments herein, a "material layer" is a layer comprising at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of an identified material; and a layer as "material" comprises at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of an identified material. For example, in some embodiments, an aluminum layer and each of the aluminum layers is a layer of at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of aluminum.

[0013] It should be understood that the phrases or terms used herein are for descriptive rather than limiting purposes, and that the terms or phrases used herein shall be interpreted by those skilled in the art in accordance with the teachings herein.

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the disclosed subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature as described below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Throughout this description, unless otherwise stated, the same element symbols in different figures refer to the same or similar components formed using the same or similar materials by the same or similar methods.

[0015] This document discusses various embodiments in a specific context, namely, semiconductor structures for forming fin-like field-effect transistor (FinFET) devices. For example, the semiconductor structure may be a complementary metal-oxide-semiconductor (CMOS) device, including P-type metal-oxide-semiconductor (PMOS) FinFET devices and N-type metal-oxide-semiconductor (NMOS) FinFET devices. Embodiments will now be described with reference to specific examples, including FinFET manufacturing processes. However, the embodiments are not limited to the examples provided herein, and these ideas can be implemented in various embodiments. Therefore, various embodiments can be applied to other semiconductor devices / processes, such as planar transistors. Furthermore, the embodiments discussed herein are discussed in the case of devices formed using a post-gate process.

[0016] Although the drawings illustrate various embodiments of a semiconductor device, additional features may be added to the semiconductor device depicted in the drawings, and some features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0017] Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some features described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in another logical order.

[0018] As used herein, a “layer” is a region, such as a region containing arbitrary boundaries, and not necessarily containing uniform thickness. For example, a layer can be a region containing at least some thickness variation.

[0019] This disclosure generally relates to semiconductor devices and their fabrication, and in some cases to multi-gate devices. Multi-gate devices include transistors with gate structures formed on at least two sides of a channel region. These multi-gate devices may include n-type metal-oxide-semiconductor (MOSFET) devices or p-type MOSFET multi-gate devices. Specific examples presented herein may be represented and referred to herein as a multi-gate transistor, referred to as a gate-all-around (GAA) device. A GAA device includes any device with a gate structure or a portion thereof formed on all four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. The device embodiments described herein may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will recognize that this teaching can be applied to single-channel or any number of channels, such as FinFET devices, due to fin structures. Other examples of semiconductor devices that may benefit from the present disclosure will be recognized by those skilled in the art.

[0020] Figure 1 is a flowchart illustrating an exemplary method 100 of semiconductor manufacturing including a multi-gate device according to various aspects of this disclosure. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate materials disposed on at least one channel of the device on a plurality of sides. In some instances, a multi-gate device may be referred to as a GAA device having gate materials disposed on four sides of at least one channel member of the device. The channel member may be referred to as a "nanostructure" or "nanosheet," and herein is used to refer to any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, as used herein, the term "nanostructure" or "nanosheet" refers both to an elongated material portion with a circular or substantially circular cross-section, and to a beam or strip-shaped material portion, including, for example, cylindrical or substantially rectangular cross-sections.

[0021] Figure 1 is described in conjunction with Figures 2, 3, 4A to 4C, 5, 6A, 6B, and 7 to 15, which illustrate semiconductor devices 200 or structures at various stages of manufacturing according to some embodiments. Method 100 is merely an example and is not intended to limit this disclosure to the scope expressly described in the claims. Additional steps may be provided before, during, and after method 100, and some steps described may be moved, replaced, or eliminated for additional embodiments of method 100. Additional features may be added to the semiconductor device 200 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0022] As with other method embodiments and exemplary devices discussed herein, it should be understood that components of a semiconductor device can be manufactured using semiconductor technology process flows; therefore, only some processes are briefly described herein. Furthermore, exemplary semiconductor devices may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses, and / or other logic devices, but simplification is provided for a better understanding of the concepts disclosed herein. In some embodiments, exemplary devices include a plurality of interconnectable semiconductor devices (e.g., transistors), including p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc. Furthermore, it should be noted that the process steps of method 100 (including any descriptions given with reference to the accompanying drawings) are illustrative only, as are the remainder of the methods and exemplary drawings provided herein, and are not intended to limit the scope beyond what is specifically described in the claims below.

[0023] Figures 2, 3, 4A to 4C, 5, 6A, 6B, and 7 to 15 are schematic diagrams illustrating exemplary semiconductor device structures at various manufacturing stages according to some embodiments. In some figures, some element symbols of components or features illustrated therein may be omitted to avoid obscuring other components or features, for ease of depiction of these figures.

[0024] At block 102, exemplary method 100 includes providing a substrate. Referring to the example of Figure 2, in the embodiment of block 102, a substrate 202 is provided to form a transistor device 200. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 202 may contain single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 may include various doping configurations according to design requirements. For example, different doping profiles (e.g., n-wells, p-wells) can be formed in regions on substrate 202 designed for different device types (e.g., n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 has isolation features (e.g., shallow trench isolation (STI) features) between regions providing different device types. Furthermore, substrate 202 may be strained to enhance performance, and may include silicon-on-insulator (SOI) structures and / or have other suitable enhancing features.

[0025] At block 104, exemplary method 100 then includes forming an epitaxial stack over a substrate, the epitaxial stack comprising a plurality of epitaxial layers. Referring to the example of Figure 3, in the embodiment of block 104, an epitaxial stack 212 is formed over a substrate 202. The epitaxial stack 212 includes sacrificial epitaxial layers 214 of a first composition, with channel epitaxial layers 216 of a second composition inserted between these sacrificial epitaxial layers 214. The first and second compositions may be different. In an embodiment, the sacrificial epitaxial layers 214 are formed of silicon germanium (SiGe), and the channel epitaxial layers 216 are formed of silicon (Si). However, other embodiments are also possible, including embodiments providing first and second compositions with different oxidation rates and / or etch selectivity. In some embodiments, the sacrificial epitaxial layers 214 comprise silicon germanium, and the channel epitaxial layers 216 comprise silicon (Si). However, other embodiments are also possible, including embodiments providing a first composition and a second composition with different oxidation rates and / or etching selectivity. In some embodiments, the sacrificial epitaxial layer 214 comprises silicon germanium, and when the channel epitaxial layer 216 comprises silicon, the silicon oxidation rate of the channel epitaxial layer 216 is less than the silicon germanium oxidation rate of the sacrificial epitaxial layer 214. It should be noted that Figure 3 illustrates three (3) layers each of epitaxial layers 214 and 216, which is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. In various embodiments, any number of epitaxial layers may be formed in the epitaxial stack 212; the number of layers depends on the number of channel regions required by the device 200. In some embodiments, the number of channel epitaxial layers 216 is between 2 and 10, such as 3, 4, or 5.

[0026] In some embodiments, the thickness of the sacrificial epitaxial layer 214 ranges from about 4 nanometers to about 12 nanometers. The thickness of the sacrificial epitaxial layer 214 may be substantially uniform. In some embodiments, the thickness of the channel epitaxial layer 216 ranges from about 3 nanometers to about 6 nanometers. In some embodiments, the thickness of the stacked channel epitaxial layers 216 is substantially uniform.

[0027] As described in more detail below, the channel epitaxial layer 216 can be used as a channel region for a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. The sacrificial epitaxial layer 214 can be used to reserve the spacing (or gap) between adjacent channel regions for a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations.

[0028] For example, the epitaxial growth of the epitaxial stack 212 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (such as the channel epitaxial layer 216) comprises the same material as the substrate 202, such as silicon (Si). In some embodiments, the epitaxial growth layers 214 and 216 comprise materials different from the substrate 202. As described above, in at least some instances, the sacrificial epitaxial layer 214 comprises an epitaxially grown Si1-xGex layer (e.g., x is about 25-55%), while the channel epitaxial layer 216 comprises an epitaxially grown Si layer. Alternatively, in some embodiments, either the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may comprise other materials (such as germanium), compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials of the sacrificial epitaxial layer 214 and the channel epitaxial layer 216 may be selected to provide different oxidation and etch selectivity characteristics. In various embodiments, epitaxial layers 214 and 216 are substantially dopant-free (i.e., having an external dopant concentration of about 0 cm⁻³ to about 1 × 10¹⁷ cm⁻³), for example, without any intentional doping during the epitaxial growth process.

[0029] At block 106, exemplary method 100 includes patterning an epitaxial stack to form semiconductor fins (also referred to as fins). Referring to examples in Figures 4A, 4B, and 4C, in the embodiment of block 106, a plurality of fins 220 extending from substrate 202 are formed. In various embodiments, each fin 220 includes upper portions of staggered epitaxial layers 214 and 216 and a bottom portion protruding from substrate 202.

[0030] The fins 220 can be manufactured using suitable processes, including lithography and etching processes. The lithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epitaxial stack 212), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element comprising the photoresist. In some embodiments, an electron beam lithography process may be used to pattern the photoresist to form the mask element. The mask element can then be used to protect areas of the substrate 202 and the epitaxial stack 212 formed thereon, while the etching process forms trenches in the unprotected areas via the mask layer (such as a hard mask), thereby leaving a plurality of extended fins. Dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes can be used to etch the trenches. The trenches may be filled with a dielectric material to form, for example, shallow trench isolation features between the fins.

[0031] At block 108, exemplary method 100 includes forming one or more sacrificial layers / features over a substrate. Referring to the example in Figure 5, in the embodiment of block 108, a sacrificial gate dielectric layer (not shown) is blanket-deposited over a fin 220 formed over a substrate 202. Then, a sacrificial gate electrode layer 228 is blanket-deposited over the sacrificial gate dielectric layer and over the substrate 202. The sacrificial gate electrode layer 228 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer 228 can be deposited using chemical vapor deposition (CVD, including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0032] At block 110, exemplary method 100 includes: patterning one or more sacrificial layers / features to form a dummy gate structure on a channel region of the fin. Referring to the examples in Figures 6A and 6B, in the embodiment of block 110, a sacrificial gate structure 224 is formed over a portion of the fin 220 that will become a channel region. The sacrificial gate structure 224 defines a channel region of the GAA device. The sacrificial gate structure 224 includes a sacrificial gate dielectric layer and a sacrificial gate electrode layer 228. The sacrificial gate structure 224 is formed by forming a masking layer over the sacrificial gate electrode layer. The masking layer may include a pad silicon oxide layer and a silicon nitride masking layer. Subsequently, the masking layer is patterned, and the sacrificial gate dielectric layer and electrode layer are patterned into the sacrificial gate structure 224. By patterning the sacrificial gate structure 224, fins 220 are exposed on opposite sides of the sacrificial gate structure 224, thereby defining the source / drain (S / D) region. In this disclosure, the source and drain are interchangeable and have essentially the same structure.

[0033] Subsequently, as described in block 132 of reference method 100, the sacrificial gate structure 224 is removed and will be replaced by the final gate stack in subsequent processing stages of device 200. Specifically, the sacrificial gate structure 224 is replaced by a high-K dielectric (HK) layer and a metal gate electrode (MG) in subsequent processing stages, as described below.

[0034] At block 112, exemplary method 100 includes forming a gate sidewall spacer on the sidewall of the sacrificial gate structure. Referring to the example of Figure 7, in the embodiment of block 112, a gate sidewall spacer 232 is formed on the sidewall of the sacrificial gate structure 224. In various embodiments, the gate sidewall spacer 232 may include a dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), SiCN film, silicon oxycarbonate (SiOC), silicon oxynitride (SiOCN) film, and / or combinations thereof. In some embodiments, the gate sidewall spacer 232 includes a plurality of layers, such as a main spacer wall, a liner layer, etc. For example, the gate sidewall spacer 232 may be formed by depositing a dielectric material layer over the sacrificial gate structure 224 using processes such as CVD, sub-atmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. In some embodiments, after the deposition of the dielectric material layer, an etch-back process (e.g., anisotropic) is performed to expose portions of the fin 220 adjacent to and not covered by the sacrificial gate structure 224 (e.g., S / D regions). The dielectric material layer may remain as the gate sidewall spacer 232 on the sidewall of the sacrificial gate structure 224. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The thickness of the gate sidewall spacer 232 may be from about 5 nanometers to about 20 nanometers.

[0035] At block 114, exemplary method 100 optionally includes: treating the gate sidewall spacer 232 to make it more resistant to germanium (Ge) permeation during subsequent manufacturing operations (such as sacrificial gate removal and replacement gate manufacturing operations). In various embodiments, treating the gate sidewall spacer 232 involves performing a curing operation to cure and solidify the gate sidewall spacer 232. In various embodiments, the curing operation involves an ultraviolet (UV) curing operation. In various embodiments, the UV curing operation involves exposing the gate sidewall spacer 232 to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, the UV curing operation involves exposing the gate sidewall spacer 232 to UV light with a power of about 30 watts (W) to about 80 W for about 1.5 minutes to about 3 minutes. In various embodiments, treating the gate sidewall spacer 232 can make it harder or more robust. In various embodiments, hardening the gate sidewall spacer 232 can reduce its thickness by about 5% to about 20%. In various embodiments, hardening the gate sidewall spacer 232 can improve device performance, such as reducing leakage.

[0036] At block 116, an exemplary method includes: recessing fins in the source / drain regions. Referring to the example in Figure 8, in the embodiment of block 116, fin 220 is recessed in the source / drain regions. Stacked epitaxial layers 214 and 216 are etched at the S / D regions to form recess 234. In various embodiments, the recess is performed by a suitable etching process, such as a dry etching process, a wet etching process, or a reactive-ion etching (RIE) process. Dry etching can be achieved using etchants including bromine-containing gases (e.g., HBr and / or CHBR3), fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof.

[0037] At block 118, exemplary method 100 includes: forming an inner spacer. Forming the inner spacer may include: recessing the sacrificial epitaxial layer (e.g., silicon germanium); depositing an inner spacer material; and etching back the inner spacer material. Referring to the example in Figure 9, in the embodiment of block 118, an inner spacer 238 is formed. The sacrificial epitaxial layer 214 has been etched back. The sacrificial epitaxial layer 214 may be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Alternatively, at block 118, the lateral ends of the sacrificial epitaxial layer 214 exposed in the recess 234 may be selectively oxidized to increase the etch selectivity between epitaxial layers 214 and 216. In some instances, an oxidation process can be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0038] The inner spacer 238 may include silicon oxide, silicon nitride, silicon carbide, silicon carbide-nitride, silicon carbide-oxygenated, silicon carbide-oxygenated and / or other suitable dielectric materials. In some embodiments, the inner spacer material layer is deposited as a conformal layer. The inner spacer material layer may be formed by ALD or any other suitable method. After the inner spacer material layer is formed, an etching operation may be performed to partially remove the inner spacer material layer. In various embodiments, the inner spacer 238 is formed of the same material as the gate sidewall spacer 232. In various embodiments, both the gate sidewall spacer 232 and the inner spacer 238 are formed of SiOCN.

[0039] At block 120, exemplary method 100 optionally includes: treating the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 to make the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 more resistant to germanium (Ge) permeation during subsequent manufacturing operations (such as sacrificial gate removal and replacement gate manufacturing operations). In various embodiments, treating the inner spacer 238, or the gate sidewall spacer 232 and the inner spacer 238, involves performing a curing operation to cure and solidify the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238. In various embodiments, the curing operation involves an ultraviolet (UV) curing operation. In various embodiments, the UV curing operation involves exposing the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 to UV light in the presence of helium, argon, or nitrogen, while heating at a temperature between about 150°C and 405°C. In various embodiments, the UV curing operation involves exposing the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. In various embodiments, treating the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 can cause the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 to become harder or more robust. In various embodiments, curing both the inner spacer 238 or the gate sidewall spacer 232 and the inner spacer 238 results in a reduction in the thickness of the cured spacer of about 5% to about 20%.

[0040] At block 122, exemplary method 100 includes forming a source / drain (S / D) feature. Referring to the example in Figure 10, in the embodiment of block 122, an epitaxial S / D feature 240 is formed in a recess 234. In some embodiments, the epitaxial S / D feature 240 includes silicon for an NFET and silicon-germanium for a PFET. In some embodiments, the epitaxial S / D feature 240 is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The epitaxial S / D feature 240 is formed in contact with the channel epitaxial layer 216 and is separated from the sacrificial epitaxial layer 214 by an inner spacer 238.

[0041] At block 124, exemplary method 100 includes forming a contact etch stop layer (CESL layer). Referring to the example in Figure 11, in the embodiment of block 124, a CESL layer 242 is formed over the S / D feature 240. The CESL layer 242 may comprise silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials; and may be formed by CVD, physical vapor deposition (PVD), ALD, or other suitable methods. In various embodiments, the CESL layer 242 is formed of SiN.

[0042] At block 126, exemplary method 100 optionally includes: treating CESL layer 242 to make CESL layer 242 more resistant to germanium (Ge) permeation during subsequent manufacturing operations (such as sacrificial gate removal and replacement gate manufacturing operations). In various embodiments, treating CESL layer 242 involves performing a curing operation to cure and solidify CESL layer 242. In various embodiments, the curing operation involves an ultraviolet (UV) curing operation. In various embodiments, the UV curing operation involves exposing CESL layer 242 to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, the UV curing operation involves exposing CESL layer 242 to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. In various embodiments, treating CESL layer 242 may make CESL layer 242 harder or more robust. In various embodiments, the hardened CESL layer 242 can reduce the thickness of the hardened CESL by about 5% to about 20%.

[0043] At block 128, exemplary method 100 includes forming an interlayer dielectric (ILD) layer. Referring to the example in Figure 12, in the embodiment of block 128, an interlayer dielectric (ILD) layer 244 is formed over a CESL layer 242. The ILD layer 244 may include tetraethylorthosilicate (TEOS) oxide, undoped silica glass, or doped silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 may be formed by PECVD, flowable CVD (FCVD), or other suitable methods. In some embodiments, forming the ILD layer 244 further includes performing a chemical-mechanical polishing (CMP) process to planarize the top surface of the device 200, thereby exposing the top surface of the sacrificial gate structure 224.

[0044] At block 130, exemplary method 100 includes: removing a dummy gate stack to form a gate trench. Referring to the example in Figure 13, in the embodiment of block 130, a sacrificial gate structure 224 has been removed to form a gate trench 254. The gate trench 254 exposes fins 220 in the channel region. During the removal of the sacrificial gate structure 224, the ILD layer 244 and the CESL layer 242 protect the epitaxial S / D features 240. The sacrificial gate structure 224 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the ILD layer 244 is oxide, the sacrificial gate electrode layer can be selectively removed using a wet etchant (such as a TMAH solution). The sacrificial gate dielectric layer is then removed using plasma dry etching and / or wet etching.

[0045] At block 132, exemplary method 100 includes: removing a sacrificial epitaxial layer to form a nanosheet. Referring to the example in Figure 14, in the embodiment of block 132, the sacrificial epitaxial layer 214 has been removed, thereby releasing a channel member from the channel region of the GAA device. In the illustrated embodiment, the channel member is a channel epitaxial layer 216 in the form of a nanosheet. In various embodiments, the channel epitaxial layer 216 comprises silicon, and the sacrificial epitaxial layer 214 comprises silicon germanium. In various embodiments, these sacrificial epitaxial layers 214 are selectively removed via a selective removal process, which includes oxidizing these sacrificial epitaxial layers 214 using a suitable oxidant (such as ozone). Subsequently, the oxidized sacrificial epitaxial layer 214 is selectively removed via a dry etching process, for example, by applying HCl gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or by applying a gas mixture of CF4, SF6, and CHF3.

[0046] At block 134, exemplary method 100 includes forming a high-k metal gate structure. Referring to the example in Figure 15, in the embodiment of block 134, a gate structure 260 is formed. In various embodiments, the gate structure is the gate of a multi-gate transistor. In various embodiments, the gate structure is a high-k metal gate stack; however, other compositions are also possible. In various embodiments, the high-k metal gate stack includes a gate dielectric layer, which includes an interface layer and a high-k dielectric layer. The high-k dielectric layer encapsulates each nanosheet 216, and the interface layer is located between the high-k dielectric layer and the nanosheet 216. The interface layer may include a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and / or other suitable methods. The high-k dielectric layer may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), other suitable high-k dielectric materials, and / or combinations thereof. The high-k material may be further selected from metal oxides, metal nitrides, metallic silicon, transition metal oxides, transition metal nitrides, transition metal silicon, metal oxynitrides, metallic aluminum, zirconium silicate, zirconium aluminate, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable materials, and / or combinations thereof. The high-k dielectric layer can be formed by any suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), sputtering, electroplating, other suitable processes, and / or combinations thereof. In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process (such as ALD) to ensure that a gate dielectric layer of uniform thickness is formed around each channel layer. The high-k metal gate structure may include additional material layers.

[0047] At block 136, exemplary method 100 includes performing further manufacturing. The semiconductor device may be further processed to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multilayer interconnect features (e.g., metal layers and interlayer dielectric layers) on a substrate to connect various features to form a functional circuit that may include one or more multi-gate devices. In a further example, the multilayer interconnect may include vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal lines). Various interconnect features may be made of various conductive materials, including copper, tungsten, and / or silicates. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure. Furthermore, additional process steps may be performed before, during, and after method 100, and some of the process steps described above may be replaced or eliminated according to various embodiments of method 100.

[0048] Figure 16 is a flowchart illustrating an exemplary method 1600 of semiconductor manufacturing according to various forms of the present disclosure. Figure 16 is described in conjunction with Figures 17A to 17D, which are schematic diagrams illustrating exemplary fin-like field-effect transistor (FinFET) devices 1700 at various manufacturing stages according to some embodiments. In some figures, some element symbols of components or features illustrated therein may be omitted to avoid obscuring other components or features, for ease of depiction. Method 1600 is merely an example and is not intended to limit the present disclosure to the scope expressly described in the claims. Additional steps may be provided before, during, and after method 1600, and some steps described may be moved, replaced, or eliminated for other embodiments of method 1600. Additional features may be added to the FinFET device 1700 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0049] As with the other method embodiments and exemplary devices discussed herein, it should be understood that the various parts of the FinFET device 1700 can be manufactured by semiconductor technology process flows, and therefore only some processes are briefly described herein. Furthermore, it should be noted that the process steps of method 1600 (including any descriptions given with reference to the accompanying drawings) are illustrative only, as are the remainder of the methods and exemplary drawings provided in this disclosure, and are not intended to limit the scope specifically described in the following claims.

[0050] In operation 1602, exemplary method 1600 includes forming a gate spacer layer around a sacrificial gate structure disposed above a substrate. Referring to the example in Figure 17A, in the embodiment of operation 1602, a plurality of sacrificial gate structures 1704 are disposed above fins 1706 on a substrate (not shown). The sacrificial gate structure 1704 includes a dielectric layer 1708 and a polysilicon layer 1710. A first material layer 1712 including the gate spacer layer 1714 is disposed around the sacrificial gate structure 1704.

[0051] At operation 1604, exemplary method 1600 includes performing processing operations on a first material layer (including a spacer layer) to make the first material layer more resistant to germanium (Ge) diffusion during a metal gate replacement operation. In various embodiments, performing processing operations on the first material layer includes performing curing operations to make the first material layer harder. In various embodiments, performing curing operations to make the first material layer harder includes exposing the first material layer to UV light while heating. In various embodiments, exposing the first material layer to UV light while heating includes exposing the first material layer to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, exposing the first material layer to UV light while heating includes exposing the first material layer to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. Referring to the example in Figure 17B, in the embodiment of operation 1604, the first material layer 1712 (including the gate spacer layer 1714) has been UV-cured to produce a hardened first material layer 1716. In various embodiments, the thickness of the hardened first material layer 1716 has been reduced from about 5% to about 20% of the thickness of the first material layer 1712.

[0052] In various embodiments, the hardened first material layer 1716 comprises SiOCN and has a higher carbon concentration than the first material layer 1712 after the curing operation. In various embodiments, the carbon concentration in the hardened first material layer 1716 is increased by about 3% compared to the carbon concentration in the first material layer 1712. In various embodiments, the first material layer 1712 may have a carbon concentration of 11.37%, while the hardened first material layer 1716 may have a carbon concentration of 14.26%. In various embodiments, the increase in carbon concentration may occur due to a decrease in oxygen (O) concentration. In various embodiments, the increase in carbon concentration results in the hardened first material layer 1716 being harder and more resistant to germanium diffusion than the first material layer 1712.

[0053] In various embodiments, the hardened first material layer 1716 has a higher nitrogen concentration after the curing operation. In various embodiments, the nitrogen concentration in the hardened first material layer 1716 is approximately 4% higher than the nitrogen concentration in the first material layer 1712. In various embodiments, the increase in nitrogen concentration may occur due to a decrease in oxygen concentration. In various embodiments, the increase in nitrogen concentration results in the hardened first material layer 1716 being harder and more resistant to germanium diffusion than the first material layer 1712.

[0054] In various embodiments, the hardened first material layer 1716 forms a channel protection layer that protects the metal gate 1720 from germanium infiltration during metal gate formation. In various embodiments, the protective layer may be formed by UV curing, plasma treatment, and electron beam therapy.

[0055] In various embodiments, the FinFET device 1700 may be a GAA FinFET device. When the FinFET device 1700 is a GAA FinFET device, the first material layer may further include an inner gate spacer (not shown), and a curing operation may also be performed on the inner gate spacer.

[0056] In operation 1606, exemplary method 1600 includes forming a source / drain (S / D) region, and in operation 1608, forming a second material layer comprising a contact etch stop layer (CESL) adjacent to the first material layer 1712 and located above the S / D region. Referring to the example in Figure 17C, in the embodiment of operation 1608, a second material layer 1718 comprising the CESL is formed near the first material layer 1712 and above the S / D region (e.g., in the region between the two illustrated sacrificial gate structures 1704).

[0057] In operation 1610, exemplary method 1600 includes replacing the sacrificial gate structure with a metal gate. Referring to the example in Figure 17D, in an embodiment of operation 1610, the sacrificial gate structure 1704 has been replaced by a metal gate 1720. Furthermore, as shown, for example during the metal gate replacement operation, a hardened first material layer 1716 blocks germanium 1722 (e.g., from the S / D region and / or the sacrificial epitaxial layer) from entering the metal gate 1720. Blocking germanium 1722 can improve device performance, such as lower voltage peak deviation due to less leakage. In various embodiments, germanium 1722 diffuses into the hardened first material layer 1716 and the second material layer 1718, but not into the metal gate 1720. In various embodiments, germanium 1722 can be detected in the hardened first material layer 1716 and second material layer 1718 near the S / D region and / or the sacrificial epitaxial layer, but not near the top of the hardened first material layer 1716 or the top of the second material layer 1718. In various embodiments, the concentration of germanium 1722 in the hardened first material layer 1716 and second material layer 1718 exhibits a gradient, with a higher concentration near the bottom portion of the S / D region and / or the sacrificial epitaxial layer, but a zero concentration near the top portion of the hardened first material layer 1716 or the top portion of the second material layer 1718. Germanium 1722 is not chemically bonded to the hardened first material layer 1716 or second material layer 1718.

[0058] Figure 18 is a flowchart illustrating an exemplary method 1800 of semiconductor manufacturing according to various forms of the present disclosure. Figure 18 is described in conjunction with Figures 19A to 19D, which are schematic diagrams illustrating exemplary FinFET devices 1900 at various manufacturing stages according to some embodiments. In some figures, some element symbols of components or features illustrated therein may be omitted to avoid obscuring other components or features, for ease of depiction. Method 1800 is merely an example and is not intended to limit the present disclosure to the scope expressly described in the claims. Additional steps may be provided before, during, and after method 1800, and some steps described may be moved, replaced, or eliminated for other embodiments of method 1800. Additional features may be added to the FinFET device 1900 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0059] As with the other method embodiments and exemplary devices discussed herein, it should be understood that the various parts of the FinFET device 1900 can be manufactured by semiconductor technology process flows, and therefore only some processes are briefly described herein. Furthermore, it should be noted that the process steps of method 1800 (including any descriptions given with reference to the accompanying drawings) are illustrative only, as are the remainder of the methods and exemplary drawings provided in this disclosure, and are not intended to limit the scope specifically described in the following claims.

[0060] In operation 1802, exemplary method 1800 includes forming a gate spacer layer around a sacrificial gate structure disposed above a substrate. Referring to the example of Figure 19A, in the embodiment of operation 1802, a plurality of sacrificial gate structures 1904 are disposed above fins 1906 on a substrate (not shown). The sacrificial gate structure 1904 includes a dielectric layer 1908 and a polysilicon layer 1910. A first material layer 1912 including the gate spacer layer 1914 is disposed around the sacrificial gate structure 1904.

[0061] In operation 1804, exemplary method 1800 includes forming a source / drain (S / D) region, and in operation 1806, forming a second material layer comprising a contact etch stop layer (CESL) adjacent to the first material layer 1912 and located above the S / D region. Referring to the example in Figure 19B, in the embodiment of operation 1806, a second material layer 1916 comprising the CESL is formed near the first material layer 1912 and above the S / D region (e.g., in the region between the two depicted sacrificial gate structures 1904).

[0062] At operation 1808, exemplary method 1800 includes performing treatment operations on a second material layer to make the second material layer more resistant to germanium (Ge) permeation during a metal gate replacement operation. In various embodiments, performing the treatment operations on the second material layer includes performing curing operations to make the second material layer harder or more robust. In various embodiments, performing the curing operation to make the second material layer harder includes exposing the second material layer to UV light while heating. In various embodiments, exposing the second material layer to UV light while heating includes exposing the second material layer to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, exposing the second material layer to UV light while heating involves exposing the second material layer to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. Referring to the example in Figure 19C, in the embodiment of operation 1808, the second material layer 1916 has been UV-cured to produce a hardened second material layer 1918. In various embodiments, the thickness of the hardened second material layer 1918 has been reduced from about 5% to about 20% of the thickness of the second material layer 1916.

[0063] In various embodiments, the hardened second material layer 1918 comprises silicon nitride and has a higher nitrogen concentration after the curing operation. In various embodiments, the nitrogen concentration in the hardened second material layer 1918 is approximately 4% higher than the nitrogen concentration in the second material layer 1916. In various embodiments, the increase in nitrogen concentration may occur due to a decrease in silicon concentration. In various embodiments, the increase in nitrogen concentration results in the hardened second material layer 1918 being harder and more resistant to germanium diffusion than the second material layer 1916.

[0064] In various embodiments, the hardened second material layer 1918 forms a channel protection layer that protects the metal gate 1920 from germanium infiltration during metal gate formation. In various embodiments, the protective layer may be formed by UV curing, plasma treatment, and electron beam therapy.

[0065] In operation 1810, exemplary method 1800 includes replacing the sacrificial gate structure with a metal gate. Referring to the example in Figure 19D, in an embodiment of operation 1810, the sacrificial gate structure 1904 has been replaced by a metal gate 1920. Furthermore, as shown, for example during the metal gate replacement operation, a hardened second material layer 1918 prevents germanium 1922 (e.g., from the S / D region and / or the sacrificial epitaxial layer) from entering the metal gate 1920. Blocking germanium can improve device performance, such as lower voltage peak deviation due to less leakage. In various embodiments, in the EPI region, G% >= (1E20), and the germanium% between the metal gate electrode (MG) and the epitaxy (EPI) is less than 1% of the germanium% at the silicon-germanium edge.

[0066] Figure 20 is a flowchart depicting an exemplary method 2000 for semiconductor manufacturing according to various forms of the present disclosure. Figure 20 is described in conjunction with Figures 21A to 21D, which are schematic diagrams illustrating exemplary FinFET devices 2100 at various manufacturing stages according to some embodiments. In some figures, some element symbols of components or features illustrated therein may be omitted to avoid obscuring other components or features, for ease of depiction. Method 2000 is merely an example and is not intended to limit the present disclosure to the scope expressly described in the claims. Additional steps may be provided before, during, and after method 2000, and some steps described may be moved, replaced, or eliminated for other embodiments of method 2000. Additional features may be added to the FinFET device 2100 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0067] As with the other method embodiments and exemplary devices discussed herein, it should be understood that the various parts of the FinFET device 2100 can be manufactured by semiconductor technology process flows, and therefore only some processes are briefly described herein. Furthermore, it should be noted that the process steps of method 2000 (including any descriptions given with reference to the accompanying drawings) are illustrative only, as are the remainder of the methods and exemplary drawings provided in this disclosure, and are not intended to limit the scope specifically described in the following claims.

[0068] In operation 2002, exemplary method 2000 includes forming a gate spacer layer around a sacrificial gate structure disposed above a substrate. Referring to the example of Figure 21A, in an embodiment of operation 2002, a plurality of sacrificial gate structures 2104 are disposed above fins 2106 on a substrate (not shown). The sacrificial gate structure 2104 includes a dielectric layer 2108 and a polycrystalline silicon layer 2110. A first material layer 2112 comprising the gate spacer layer 2114 is disposed around the sacrificial gate structure 2104. In various embodiments, the first material layer comprises silicon carbonitride (SiOCN).

[0069] At operation 2004, exemplary method 2000 includes performing processing operations on a first material layer (including a spacer layer) to make the first material layer more resistant to germanium (Ge) permeation during a metal gate replacement operation. In various embodiments, performing processing operations on the first material layer includes performing curing operations to make the first material layer harder or more robust. In various embodiments, performing curing operations to make the first material layer harder includes exposing the first material layer to UV light while heating. In various embodiments, exposing the first material layer to UV light while heating includes exposing the first material layer to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, exposing the first material layer to UV light while heating includes exposing the first material layer to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. Referring to the example in Figure 21B, in the embodiment of operation 2004, the first material layer 2112 (including the gate spacer layer 2114) has been UV-cured to produce a hardened first material layer 2115. In various embodiments, curing the first material layer results in a reduction in the thickness of the hardened first material layer 2112 from about 5% to about 20%.

[0070] In various embodiments, the hardened first material layer 2115 comprises SiOCN and has a higher carbon concentration than the first material layer 2112 after the curing operation. In various embodiments, the carbon concentration in the hardened first material layer 2115 is increased by about 3% compared to the carbon concentration in the first material layer 2112. In various embodiments, the first material layer 2112 may have a carbon concentration of 11.37%, while the hardened first material layer 2115 may have a carbon concentration of 14.26%. In various embodiments, the increase in carbon concentration may occur due to a decrease in oxygen concentration. In various embodiments, the increase in carbon concentration results in the hardened first material layer 1716 being harder and more resistant to germanium diffusion than the first material layer 1712.

[0071] In various embodiments, the hardened first material layer 2115 has a higher nitrogen concentration after the curing operation. In various embodiments, the nitrogen concentration in the hardened first material layer 2115 is approximately 4% higher than the nitrogen concentration in the first material layer 2112. In various embodiments, the increase in nitrogen concentration may occur due to a decrease in silicon concentration. In various embodiments, the increase in nitrogen concentration results in the hardened first material layer 2115 being harder and more resistant to germanium diffusion than the first material layer 2112.

[0072] In various embodiments, the FinFET device 2100 may be a GAA FinFET device. When the FinFET device 2100 is a GAA FinFET device, the first material layer may further include an inner gate spacer (not shown), and a curing operation may also be performed on the inner gate spacer.

[0073] In operation 2006, exemplary method 2000 includes forming a source / drain (S / D) region, and in operation 2008, forming a second material layer comprising a contact etch stop layer (CESL) adjacent to the first material layer 2112 and located above the S / D region. Referring to the example in Figure 21C, in the embodiment of operation 2008, a second material layer 2116 including the CESL is formed additionally to the first material layer 2112 and located above the S / D region (e.g., in the region between the two illustrated sacrificial gate structures 2104).

[0074] At operation 2010, exemplary method 2000 includes performing treatment operations on a second material layer to make the second material layer more resistant to germanium (Ge) permeation during a metal gate replacement operation. In various embodiments, performing the treatment operations on the second material layer includes performing curing operations to make the second material layer harder or more robust. In various embodiments, performing the curing operations to harden the second material layer includes exposing the second material layer to UV light while heating. In various embodiments, exposing the second material layer to UV light while heating includes exposing the second material layer to UV light in the presence of helium, argon, or nitrogen while heating at a temperature between about 150°C and 405°C. In various embodiments, exposing the second material layer to UV light while heating includes exposing the second material layer to UV light with a power of about 30W to about 80W for about 1.5 minutes to about 3 minutes. Referring to the example in Figure 21D, in the embodiment of operation 2008, the second material layer 2116 has been UV-cured to produce a hardened second material layer 2118. In various embodiments, curing the second material layer results in a reduction in the thickness of the hardened second material layer 2118 from about 5% to about 20%.

[0075] In various embodiments, the hardened second material layer 2118 comprises silicon nitride and has a higher nitrogen concentration after the curing operation. In various embodiments, the increase in nitrogen concentration may occur due to a decrease in silicon concentration. In various embodiments, the increase in nitrogen concentration results in the hardened second material layer 1918 being harder and more resistant to germanium diffusion than the first material layer 1912.

[0076] In various embodiments, the hardened first material layer 2115 and the hardened second material layer 2118 form a channel protection layer that protects the metal gate 2120 from germanium infiltration during metal gate formation. In various embodiments, the protection layer may be formed by UV curing, plasma treatment, and electron beam therapy.

[0077] In operation 2012, exemplary method 2000 includes replacing the sacrificial gate structure with a metal gate. Referring to the example in Figure 21D, in the embodiment of operation 2012, the sacrificial gate structure 2104 has been replaced by a metal gate 2120. Furthermore, as shown, during the metal gate replacement operation, a hardened first material layer 2115 and a hardened second material layer 2118 prevent germanium 2122 (e.g., from the S / D region and / or the sacrificial epitaxial layer) from entering the metal gate 2120. Blocking germanium can improve device performance, such as lower voltage peak deviation due to less leakage.

[0078] Figures 22A and 22B are schematic diagrams illustrating a semiconductor structure 2200 having a first transistor 2202 and a second transistor 2222 at different manufacturing stages according to some embodiments. Figure 22A is a schematic diagram illustrating the semiconductor structure 2200 at a first manufacturing stage according to some embodiments. Figure 22B is a schematic diagram illustrating the semiconductor structure 2200 at a second manufacturing stage according to some embodiments.

[0079] In the first manufacturing stage, the first transistor 2202 includes a first sacrificial gate structure 2204, which includes a first dielectric layer 2206 and a first polysilicon region 2208. The first transistor 2202 further includes a first hardened gate spacer 2210 (e.g., formed of SiOCN) cured by UV light and a first etch stop layer (first ESL) 2212 (e.g., formed of silicon nitride). The first transistor 2202 is formed above the fin 2214. The first hardened gate spacer 2210 has a first sidewall thickness 2216 and a first top thickness 2218.

[0080] In the first manufacturing stage, the second transistor 2222 includes a second sacrificial gate structure 2224, which includes a second dielectric layer 2226 and a second polysilicon region 2228. The second transistor 2222 further includes a second hardened gate spacer 2230 (e.g., formed of SiOCN) cured by UV light and a second etch-stop layer (second ESL) 2232 (e.g., formed of silicon nitride). The second transistor 2222 is formed above the fin 2234. The second hardened gate spacer 2230 has a second sidewall thickness 2236 and a second top thickness 2238.

[0081] UV curing causes the first sidewall thickness 2216 of the first hardened gate spacer 2210 to be greater than the second sidewall thickness 2236 of the second hardened gate spacer 2230. In addition, the first top thickness 2218 of the first hardened gate spacer 2210 is greater than or equal to the second top thickness 2238 of the second hardened gate spacer 2230.

[0082] Figure 22B is a schematic diagram illustrating a semiconductor structure 2200 after polysilicon removal and metal gate replacement operations according to some embodiments. The first transistor 2202 after the metal gate replacement operation includes a first metal gate 2250 and a first high-k gate dielectric layer 2252, and the second transistor 2222 after the metal gate replacement operation includes a second metal gate 2254 and a second high-k gate dielectric layer 2256. A first hardened gate spacer 2210 and a second hardened gate spacer 2230 resist germanium diffusion (from germanium 2262 and germanium 2264) and protect the first metal gate 2250 and the second metal gate 2254 from germanium infiltration during the metal gate replacement operation. Since the first sidewall thickness 2216 is greater than the second sidewall thickness 2236, the first metal gate 2250 can be larger than the second metal gate 2254. During the polysilicon removal operation, the sidewalls of the first hardened gate spacer 2210 are etched away more than the sidewalls of the second hardened gate spacer 2230. In various embodiments, the first metal gate 2250 has a first thickness 2258 near the top of the first metal gate 2250, which is greater than the second thickness 2260 near the top of the second metal gate 2254.

[0083] Improved systems, manufacturing methods, manufacturing techniques, and articles have been described. These systems, methods, techniques, and articles can be used with a variety of semiconductor devices, including FinFETs, Gate-all-around FETs (GAAFETs / NSFETs), forked FETs, CFETs, VFETs, MOSFETs, 2D material devices, planar devices, BEOL devices, NAND, 3D NAND, NMOS, or PMOS.

[0084] In some embodiments, the technology described herein relates to a manufacturing method comprising: forming a gate spacer layer around a sacrificial gate structure disposed above a substrate; performing processing operations on a first material layer including the gate spacer layer to make the first material layer more resistant to germanium (Ge) diffusion during a metal gate replacement operation; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer prevents germanium from entering the metal gate.

[0085] In some embodiments, the technology described herein relates to a method in which processing operations on a first material layer include performing a plurality of curing operations to make the material layer harder.

[0086] In some embodiments, the technology described herein relates to a method in which performing a curing operation to harden a first material layer includes exposing the first material layer to UV light while heating.

[0087] In some embodiments, the technology described herein relates to a method in which a first material layer further includes a plurality of inner gate spacers.

[0088] In some cases, the techniques described herein relate to a method in which a first material layer comprises silicon carbonitride (SiOCN) and has a higher carbon concentration level after these processing operations are performed.

[0089] In some embodiments, the technology described herein relates to a method that further includes performing multiple additional processing operations on a second material layer to make the second material layer more resistant to germanium diffusion during a metal gate replacement operation.

[0090] In some cases, the techniques described herein relate to a method in which a second material layer comprises silicon nitride (SiN) and has a higher nitrogen concentration level after the processing operation is performed.

[0091] In some embodiments, the technology described herein relates to a semiconductor structure, including: a metal gate structure; a source region and a drain region; a first material layer formed around the metal gate structure, wherein germanium diffuses in the bottom portion of the first material layer near the source / drain region, but not near the top portion of the first material layer, wherein germanium is not bonded to the first material layer; and a second material layer disposed near the first material layer.

[0092] In some embodiments, the technology described herein relates to a semiconductor structure in which a second material layer includes a second material layer in which germanium diffuses at the bottom portion of the first material layer near the source / drain region, but not near the top portion of the first material layer, wherein germanium is not bonded to the first material layer.

[0093] In some embodiments, the technology described herein relates to a semiconductor structure in which a first material layer comprises silicon carbonitride (SiOCN) and a second material layer comprises silicon nitride (SiN).

[0094] In some embodiments, the technology described herein relates to a semiconductor structure in which the first material layer includes a gate spacer layer.

[0095] In some embodiments, the technology described herein relates to a semiconductor structure in which the first material layer further includes an inner gate spacer layer disposed between the source / drain region and a metal gate structure formed around the nanosheet.

[0096] In some embodiments, the technology described herein relates to a semiconductor structure in which a metal gate structure is disposed above the channel region of a FinFET device.

[0097] In some embodiments, the technology described herein relates to a semiconductor structure in which a metal gate structure is disposed above the channel region of a GAA FinFET device.

[0098] In some cases, the technology described herein relates to a semiconductor structure in which a metal gate structure is disposed above the channel region of a planar MOSFET device.

[0099] In some embodiments, the technology described herein relates to a manufacturing method comprising: performing a plurality of curing operations to harden a first material layer, the first material layer including a spacer layer formed around a sacrificial gate structure; removing the sacrificial gate structure; forming a metal gate to replace the sacrificial gate structure; and, during the formation of the metal gate, preventing germanium (Ge) from entering the metal gate via the first material layer.

[0100] In some embodiments, the technology described herein relates to a method that further includes: forming a source / drain (S / D) feature, wherein the S / D feature includes silicon germanium, and preventing germanium from entering a metal gate includes: preventing germanium from silicon germanium in the S / D feature from entering the metal gate.

[0101] In some embodiments, the technology described herein relates to a method in which removing a sacrificial gate structure includes: removing a sacrificial epitaxial layer from the epitaxial stack, the first material layer further including an inner gate spacer disposed between the source / drain (S / D) feature and the epitaxial stack, and preventing germanium from entering the metal gate includes: preventing germanium from silicon germanium in the sacrificial epitaxial layer from entering the metal gate.

[0102] In some cases, the technology described herein relates to a method in which performing these curing operations includes exposing a first material layer to UV light while heating.

[0103] In some embodiments, the technology described herein relates to a method that further includes: forming a second material layer adjacent to a first material layer; performing a plurality of additional curing operations to make the second material layer harder; and preventing germanium (Ge) from entering the metal gate via the second material layer when forming a metal gate.

[0104] Although at least one exemplary embodiment has been presented in the foregoing detailed description of this disclosure, it should be understood that numerous variations exist. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing exemplary embodiments of this disclosure. It should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the disclosure as set forth in the claims. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a flowchart depicting an exemplary method of semiconductor manufacturing according to some embodiments. Figures 2, 3, 4A to 4C, 5, 6A, 6B, and 7 to 15 are schematic diagrams illustrating the structures of exemplary semiconductor devices at various manufacturing stages according to some embodiments. Figure 16 is a flowchart depicting an exemplary method of semiconductor manufacturing according to some embodiments. Figures 17A to 17D are schematic diagrams of exemplary semiconductor devices at different manufacturing stages after the formation of a sacrificial gate according to some embodiments. Figure 18 is a flowchart depicting another exemplary method of semiconductor manufacturing according to some embodiments. Figures 19A to 19D are schematic diagrams of another exemplary semiconductor device at different manufacturing stages after the formation of a sacrificial gate according to some embodiments. Figure 20 is a flowchart depicting another exemplary method of semiconductor manufacturing according to some embodiments. Figures 21A to 21D are schematic diagrams of another exemplary semiconductor device at different manufacturing stages after the formation of a sacrificial gate according to some embodiments. Figures 22A and 22B are schematic diagrams of another exemplary semiconductor device at different manufacturing stages according to some embodiments. [Biomaterial Storage]

[0106] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of manufacturing a semiconductor structure, comprising: forming a gate spacer layer around a sacrificial gate structure disposed above a substrate; performing a plurality of processing operations on a first material layer including the gate spacer layer, the processing operations including exposing the first material layer to ultraviolet light while heating, for making the first material layer more resistant to germanium diffusion during a plurality of metal gate replacement operations; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer prevents germanium from entering the metal gate.

2. The method as described in claim 1, wherein the first material layer further comprises a plurality of inner gate spacers.

3. The method of claim 1, further comprising: performing a plurality of additional processing operations on the second material layer, the additional processing operations including exposing the second material layer to ultraviolet light while heating, so as to make the second material layer more resistant to germanium diffusion during a plurality of metal gate replacement operations.

4. The method of claim 3, wherein the second material layer comprises silicon nitride and has a higher nitrogen concentration level after the additional processing operations are performed.

5. A semiconductor structure comprising: a metal gate structure; a first material layer formed around the metal gate structure, wherein germanium diffuses in a bottom portion of the first material layer near a source / drain region, but not near a top portion of the first material layer, wherein the germanium is not bonded to the first material layer, and the first material layer prevents the germanium from entering the metal gate structure; and a second material layer disposed adjacent to the first material layer.

6. The semiconductor structure of claim 5, wherein germanium of the second material layer diffuses at a bottom portion of the second material layer near the source / drain region, but not near a top portion of the second material layer, wherein the germanium is not bonded to the second material layer.

7. A method of manufacturing a semiconductor structure, comprising: performing a plurality of curing operations, the curing operations including exposing a first material layer to ultraviolet light while heating to harden the first material layer, the first material layer including a spacer layer formed around a sacrificial gate structure; removing the sacrificial gate structure; forming a metal gate to replace the sacrificial gate structure; and while forming the metal gate, preventing germanium from entering the metal gate via the first material layer.

8. The method of claim 7, further comprising: forming a plurality of source / drain features, wherein the source / drain features comprise silicon germanium, and preventing the germanium from entering the metal gate comprises: preventing the germanium from the silicon germanium in the source / drain features from entering the metal gate.

9. The method of claim 7, wherein removing the sacrificial gate structure comprises: removing a plurality of sacrificial epitaxial layers from an epitaxial stack, the first material layer further comprising a plurality of inner gate spacers disposed between a plurality of source / drain features and the epitaxial stack, and preventing germanium from entering the metal gate comprises: preventing germanium from silicon germanium in the sacrificial epitaxial layers from entering the metal gate.

10. The method of claim 7, further comprising: forming a second material layer adjacent to the first material layer; performing a plurality of additional curing operations, the additional curing operations comprising exposing the second material layer to ultraviolet light while heating.

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