Semiconductor structure and method for forming the same

Abstract

A method includes forming a shallow trench isolation region adjacent to a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. A doping process is performed to dope a dopant into the top portion of the shallow trench isolation region to form a protective layer. The method further includes forming a dummy gate stack over the protruding fin, removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure, and forming a disposable interposer in the space. The dummy gate stack is then removed, followed by an etching process using an etchant to remove the disposable interposer. During the etching process, the protective layer is exposed to the etchant. A replacement gate stack is then formed, wherein a portion of the replacement gate stack fills the space.

Description

[Technical Field]

[0001] This application claims the benefit of the following provisional U.S. patent application: U.S. Application No. 63 / 647143, filed May 14, 2024, entitled “Semiconductor Device and Method of Forming Thereof,” which is incorporated herein by reference. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. [Summary of the Invention]

[0004] None.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific instances of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and the like may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0008] This disclosure provides a Gate-All-Around (GAA) transistor, a protective layer for protecting shallow trench isolation regions, and a method for forming the same. According to some embodiments of this disclosure, the GAA transistor is formed using a Disposable Oxide Interposing (DOI) process, which includes forming and removing a sacrificial layer containing oxide. Because the sacrificial layer does not have sufficient etch selectivity relative to the shallow trench isolation (STI) region, the STI region may undesirably dent, resulting in an undesirable increase in the effective capacitance Ceff between conductive features and an undesirable increase in the off-edge capacitance. Therefore, a protective layer (also known as a hard mask) is formed by implantation and / or directional plasma processing to prevent the STI region from denting during the removal of the sacrificial layer.

[0009] The embodiments discussed herein are intended to provide examples so that the subject matter of this disclosure can be made or used, and modifications will be readily understood by those skilled in the art while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0010] Figures 1 to 16A, 16B, and 16C illustrate cross-sectional views of intermediate stages in the formation of GAA transistors according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in process flow 200 as shown in Figure 18.

[0011] Referring to Figure 1, a perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, or the like, while other substrates and / or structures, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium on insulator, or the like, may also be used. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0012] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes involving alternating materials. A particular process is illustrated as process 202 in process flow 200 as shown in Figure 18. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0013] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed with a first thickness ranging from about 30 Å to about 300 Å. However, any suitable thickness can be used while remaining within the scope of the embodiments.

[0014] Once the first layer 22A is deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or comprises a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B may be formed of silicon, and vice versa. It should be understood that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

[0015] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a thickness different from that of the first layer 22A. According to some embodiments, the second layer 22B may be formed to a second thickness, for example, ranging from about 10 Å to about 500 Å.

[0016] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process, and alternatively, it is referred to throughout as the sacrificial layer 22A. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0017] According to some embodiments, a masking layer 25 is formed. According to some embodiments, the masking layer 25 includes a pad oxide layer 25A (not shown in Figure 1, see Figure 3B) and (a plurality of) hard masking layers 25B formed over the multilayer stack 22. According to some embodiments, the pad oxide layer 25A comprises silicon oxide and the hard masking layers 25B comprise silicon nitride, while other materials may also be used.

[0018] According to some embodiments, a well implantation process can be performed to form a well region 21, which may be p-type or n-type. The well region 21 has a conductivity type opposite to that of the subsequently formed source / drain region 48 (Figures 16A and 16C). According to an alternative embodiment, the well implantation process can be performed in a later process, such as after forming the structure shown in Figure 3A.

[0019] Referring to Figure 2, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned in (multiple) etching processes to form trenches 23. A specific process illustration is process 204 in process flow 200 as shown in Figure 18. The formation of trenches 23 may include forming a patterned etch mask, such as a patterned photoresist, and etching a hard mask layer 25B to define a pattern within the hard mask layer 25B. The patterned hard mask layer 25B can then be used to etch the underlying pad oxide layer 25A, the multilayer stack 22, and the substrate 20 to form trenches 23.

[0020] Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Underlying multilayer stack 22' leaves a portion of substrate 20, hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. In the following, semiconductor layer 22A may alternatively be referred to as sacrificial layer, and semiconductor layer 22B may alternatively be referred to as nanostructure. The portion of multilayer stack 22' and underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0021] In the above embodiments, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0022] Figure 3A illustrates the formation of isolation region 26, which is also referred to as a shallow trench isolation (STI) region. A specific process illustration is process 206 in process flow 200 as shown in Figure 18. STI region 26 may include a liner oxide (not shown), which may be a thermally oxidized oxide formed through the surface layer of substrate 20, or may be deposited. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or similar methods.

[0023] The STI region 26 may also include dielectric material above the lining oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, HDPCVD, or similar methods. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to make the top surface of the dielectric material flush, with the remaining portion of the dielectric material constituting the STI region 26.

[0024] Next, the STI region 26 is recessed such that the top portion of the semiconductor strip 24 protrudes higher than the top surface 26T of the remaining portion of the STI region 26, thereby forming a protruding fin 28. The protruding fin 28 includes the top portion of the multilayer stack 22' and the substrate strip 20'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. Etching chemicals may include, for example, HF.

[0025] Figure 3B illustrates a cross-section A1-A1 in Figure 3A. As shown in Figure 3B, the STI region 26 may include a plurality of dielectric linings, such as dielectric linings 26A, 26B, and 26C, and a dielectric region 26D on dielectric lining 26C. According to some embodiments, dielectric lining 26A is formed of or contains silicon oxide, which may be formed by a thermal oxidation process or a deposition process. Dielectric linings 26B and 26C may be formed of, for example, silicon nitride, while other materials may also be used.

[0026] Dielectric region 26D may be formed of or contain silicon oxide. Dielectric region 26D may have a lower density and a higher etching rate than dielectric substrates 26A, 26B, and 26C. For example, when dielectric region 26D is formed by FCVD, spin-on coating, or the like, it may have a lower density than dielectric substrates 26A, 26B, and 26C. Dielectric region 26D may also be formed by another deposition process such as ALD, CVD, or the like.

[0027] Referring to Figure 4, doping process 124 is performed. A specific process illustration is process 208 in process flow 200 as shown in Figure 18. The dopant element (species) may include nitrogen, carbon, oxygen, and / or the like. For example, N2, N2O, CO2, or a combination of N2 and N2O may be used for doping. Inert gases such as Ar, He, and / or the like may also be used.

[0028] According to an alternative embodiment, a dopant may be used, which is a p-type dopant (such as boron and / or indium) or an n-type dopant (such as phosphorus, arsenic, antimony, or combinations thereof). The conductivity type of the p-type or n-type dopant may be the same as that of the dopant used to form well region 21, and may be opposite to the doping type of the source / drain region of the corresponding transistor. For example, when the subsequently formed source / drain region 48 (Figures 16A and 16C) is a p-type source / drain region, the dopant introduced by doping process 124 is n-type. Conversely, when the subsequently formed source / drain region 48 (Figures 16A and 16C) is an n-type source / drain region, the dopant introduced by doping process 124 is p-type.

[0029] According to an alternative embodiment, the p-type or n-type dopant introduced by the doping process 124 has a conductivity type opposite to that of well region 21, and therefore has the same conductivity type as the subsequently formed source / drain region 48. According to these embodiments, the concentration of the dopant is lower than the doping concentration in well region 21, so as not to change the conductivity type of well region 21.

[0030] According to some embodiments, the doping process 124 may be performed via a vertical implantation process and / or a plasma processing process. The plasma processing may be performed using plasma generated by the aforementioned gas.

[0031] As a result of the doping process 124, the top portion of the STI region 26 is transformed into a protective layer 126, which has a higher concentration (and atomic percentage) of dopants (such as carbon, nitrogen, oxygen, and / or inert gases) than before the implantation process. The concentration and atomic percentage are also higher than in the unimplanted portions of the STI region 26, such as the bottom portion of the STI region 26. Depending on the implanted species, the protective layer 126 may include SiOC, SiON, SiOCN, or the like, and may incorporate other elements such as He, Ar, and / or the like. The thickness of the protective layer 126 may be in the range of about 1 nm to about 20 nm.

[0032] According to some embodiments employing implantation, the implantation energy is controlled such that all or most of the implanted dopant is in the masking layer 25, rather than in the underlying nanostructure 22B. According to some embodiments, the nanostructure 22B may not contain the dopant introduced by the doping process 124. According to alternative embodiments, the nanostructure 22B may include a low concentration of dopant. The concentration (atomic percentage) of the dopant is low enough that the properties of the nanostructure 22B are not adversely altered.

[0033] According to some embodiments, the dopant can be implanted at an energy range between about 1 keV and about 20 keV. The dose of each of the above-listed species and / or the total dose of implanted species can be in the range between about 5E13 / cm2 and 1E16 / cm2. The concentration of the dopant in the protective layer 126 can be in the range between about 1E20 / cm3 and about 3E22 / cm3.

[0034] When plasma processing is performed, a low bias power can be provided, allowing the dopant to be directional and diffuse vertically to the desired depth without diffusing horizontally from the sidewalls of the multilayer stack 22' too deep into the multilayer stack 22'. According to some embodiments, the bias power can be in the range of about 20 eV to about 120 eV.

[0035] According to some embodiments, the sidewalls of the multilayer stack 22' are exposed when the doping process 124 is performed. According to an alternative embodiment, a conformal sacrificial layer may be formed on the structure shown in Figure 4 prior to the doping process 124. After the doping process 124, the conformal sacrificial layer is removed, and the dopant diffuses laterally into the vertical portion of the conformal sacrificial layer. Therefore, the vertical portion of the conformal sacrificial layer on the sidewalls of the multilayer stack 22' acts as a sacrificial layer to reduce the amount of dopant diffused laterally into the multilayer stack 22'. The conformal sacrificial layer may be formed of or contain a dielectric material different from the material of the STI region 26 and the multilayer stack 22', and may contain SiC, SiCN, or the like.

[0036] According to some embodiments, the doping process 124 can be performed at room temperature (e.g., in the range of about 18˚C to about 22˚C). According to alternative embodiments, the doping process 124 can be performed at high temperatures, such as in the range of about 18˚C to about 500˚C.

[0037] Next, the mask layer 25 is removed. A specific process illustration is process 210 in process flow 200 as shown in Figure 18. The resulting structure is shown in Figure 5. The multilayer stack 22' and the protective layer 126 are exposed.

[0038] In subsequent processes, dummy gate stacks and gate spacers are formed. Figure 6 illustrates the formation of the dummy gate dielectric layer 32, the dummy gate electrode layer 34, and the hard mask layer 36. The dummy gate dielectric layer 32 can be formed by oxidizing the surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate electrode layer 34 can be formed by depositing polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon can be used. A planarization process can be performed to make the top surface of the dummy gate electrode layer 34 flush.

[0039] The hard mask layer 36 can be formed by deposition over the gate electrode layer 34. The hard mask layer 36 can be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. Then, multiple patterning processes are performed to pattern the hard mask layer 36, the dummy gate electrode layer 34, and the dummy gate dielectric layer 32 to form a plurality of dummy gate stacks 30, as shown in Figure 7A, which illustrates a perspective view of the structure. A separate process illustration is process 212 in process flow 200 as shown in Figure 18.

[0040] Next, as shown in Figure 7A, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, followed by performing an anisotropic etching process on the dielectric layers(s). The remaining portion of the dielectric layers(s) constitutes the gate spacer 38.

[0041] As shown in Figure 7A, the protective layer 126 includes a first portion directly below and overlapping the dummy gate stack 30, and a second portion not directly below the dummy gate stack 30 (and laterally offset from it). The thickness of the first portion may be the same as the thickness of the second portion. Figure 7B illustrates a cross-sectional view of the cross-section BB shown in Figure 7A.

[0042] Figure 8 illustrates the source / drain recess process. A specific process illustration is process 214 in process flow 200 as shown in Figure 18. In an anisotropic etching process, protruding fins 28 that do not directly lie under the dummy gate stack 30 and gate spacers 38 are etched. This forms the source / drain recess 42.

[0043] Figures 9A, 9B, 10A, and 10B illustrate the replacement of sacrificial layer 22A with a disposable interposer layer 29. Referring to Figures 9A and 9B, which respectively illustrate cross-sections BB and A2-A2 in Figure 7A, the sacrificial layer 22A is first removed, forming openings 27 between the nanostructures 22B. A specific process illustration is process 216 in process flow 200 as shown in Figure 18.

[0044] Referring to Figures 10A and 10B, a disposable interposer 29 is formed between nanostructures 22B. A specific process illustration is process 218 in process flow 200 as shown in Figure 18. According to some embodiments, the disposable interposer 29 comprises an oxide, such as silicon oxide, and is therefore also referred to as a disposable oxide interposer (DOI) 29. According to other embodiments, the disposable interposer 29 may comprise other types of dielectric materials, such as AlO, SiON, SiC, SiCN, or the like.

[0045] The formation of the disposable interposer 29 may include depositing a dielectric layer using a conformal deposition process, such that the dielectric layer includes filling a portion of the opening 27 and other portions outside the opening 27. A finishing process is then performed, which may include an isotropic etching process or an isotropic etching process followed by an isotropic etching process, to etch and remove portions of the dielectric layer outside the opening 27. Therefore, the remaining portion of the dielectric layer constitutes the disposable interposer 29.

[0046] Referring to Figures 11A and 11B, the disposable interposer 29 is laterally recessed and filled to form internal spacers 44 (Figure 11A). A separate process illustration is shown as process 220 in process flow 200 as shown in Figure 18. The lateral recess of the disposable interposer 29 can be achieved through a wet etching process or a dry etching process. The wet etching process can be performed using an immersion process, a spraying process, a spin-on process, or similar methods. The nanostructure 22B is not etched.

[0047] Next, internal spacers 44 are formed. According to some embodiments, the formation of internal spacers 44 includes depositing a conformal dielectric layer extending into the lateral recess. Next, an etching process (also known as a spacer trimming process) is performed to trim portions of the dielectric layer outside the lateral recess, leaving portions of the dielectric layer within the lateral recess. The remaining portion of the dielectric layer is referred to as internal spacer 44.

[0048] Referring to Figures 12A and 12B, which respectively illustrate cross-sections identical to those in Figure 7A (sections BB and A1-A1), an epitaxial source / drain region 48 is formed in the groove 42 through selective epitaxy. A specific process illustration is step 222 in process flow 200 as shown in Figure 18. Depending on whether the resulting transistor is a p-type or n-type transistor, p-type or n-type dopants can be doped in situ during the epitaxial process. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), or similar materials can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphide (SiP), silicon arsenide (SiAs), silicon carbon phosphide (SiCP), or similar materials can be grown.

[0049] Figures 13A and 13B illustrate cross-sectional views of the structure after the formation of the Contact Etch Stop Layer (CESL) 50 and the Inter-Layer Dielectric (ILD) 52. Individual process illustrations are shown as process 224 in process flow 200 as shown in Figure 18. Figures 13A and 13B respectively illustrate cross-sections BB and A2-A2 in Figure 7A. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. ILD 52 may be formed from an oxygen-containing dielectric material, which may include silicon oxide, silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silicon phosphate glass (BPSG), silica-free glass (USG), or the like.

[0050] CESL 50 and ILD 52 are planarized via a planarization process such as CMP or mechanical polishing. According to some embodiments, the planarization process may result in the removal of the hard mask 36 to expose the dummy gate electrode 34, as shown in Figures 13A and 13B. According to alternative embodiments, the planarization process may expose the hard mask 36 and stop thereon. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within the process variation range.

[0051] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form a recess 58, as shown in Figures 14A and 14B. A specific process illustration is process 226 in process flow 200 as shown in Figure 18. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed via anisotropic dry etching processes. For example, the etching process can be performed using multiple reactive gases that selectively etch the dummy gate electrode 34 and dummy gate dielectric 32 at a faster rate than etching the ILD 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22', including future channel regions in the subsequently completed transistor.

[0052] Next, the disposable interposer 29 is removed to extend the grooves 58 between the nanostructures 22B. A specific process illustration is process 228 in process flow 200 as shown in Figure 18. The disposable interposer 29 can be removed by performing an isotropic etching process, such as a wet etching process or a dry etching process, using an etchant selective to the material of the disposable interposer 29, while the nanostructures 22B and the substrate 20 remain relatively unetched compared to the disposable interposer 29. According to some embodiments where the disposable interposer 29 includes, for example, silicon oxide, a mixture of NF3 and NH3, a mixture of HF and NH3, or HF can be used to remove the disposable interposer 29.

[0053] During the etching of the disposable interposer 29, as shown in Figure 14B, the protective layer 126 protects the STI region 26 from the etching chemicals used to remove the disposable interposer 29. Accordingly, due to high etch selectivity, the STI region 26 is not etched (or substantially not etched, e.g., the loss is less than about 2 Å), where etch selectivity is the ratio of the etch rate of the disposable interposer 29 to the etch rate of the protective layer 126. For example, etch selectivity may be greater than about 5, greater than about 10, greater than about 20, or higher.

[0054] Referring to Figures 15A and 15B, a gate dielectric 62 and a gate electrode 68 are formed to form an alternative gate stack 70. A particular process illustration is process 230 in process flow 200 as shown in Figure 18. According to some embodiments, each of the gate dielectrics 62 includes an interface layer and a high-k dielectric layer above the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited (or formed by thermal oxidation) through a conformal deposition process such as ALD or CVD. According to some embodiments, the high-k dielectric layer comprises one or more high-k dielectric layers. For example, the high-k dielectric layers may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0055] When the interface layer is formed by deposition, the top surface of the protective layer 126 contacts the bottom surface of the interface layer to form an interface. When the interface layer is formed by thermal oxidation, the top surface of the protective layer 126 contacts the bottom surface of the high-k dielectric layer to form an interface.

[0056] A gate electrode 68 is also formed. In the formation process, a conductive layer is first formed on a high-k dielectric layer and the remaining portion of the groove 58 is filled. The gate electrode 68 may include a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and possible filling materials. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the bottom of nanostructure 22B and the underlying substrate strip 20'.

[0057] After filling the groove 58, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess portions of the gate dielectric 62 and the gate electrode 68, which are located above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0058] In the process shown in Figures 16A, 16B, and 16C, the gate stack 70 is recessed, so that the grooves are formed directly above the gate stack 70 and between the opposing portions of the gate spacer 38. Each of the grooves is filled with a gate mask 74 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like), followed by a planarization process to remove excess dielectric material extending above the ILD 52.

[0059] As further shown in Figures 16A, 16B, and 16C, ILD 76 is deposited over ILD 52 and gate mask 74. An etch stop layer (not shown) may be deposited (or not deposited) prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed via FCVD, CVD, PECVD, or the like. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0060] Next, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form grooves (occupied by contact plugs 80A and 80B) exposing the surfaces of the source / drain regions 48 and / or gate stack 70. Although Figure 16A illustrates contact plugs 80A and 80B in the same cross-section, in various embodiments, contact plugs 80A and 80B may be formed in different cross-sections to reduce the risk of short-circuiting each other.

[0061] After forming the groove, a siliconized region 78 is formed above the source / drain region 48. Then, a contact plug 80B is formed above the siliconized region 78. Furthermore, a contact 80A (also referred to as a gate contact plug) is formed in the groove and is above and in contact with the gate electrode 68. The corresponding structure is also shown in Figure 16A. This forms the transistor 82.

[0062] Figure 17 illustrates some example distribution profiles of dopant concentration (or atomic percentage) introduced by doping process 124 (Figure 4) according to some embodiments. The dopant profile represents a profile caused by implantation process 124, where, due to the distribution of the implanted dopant (such as a Gaussian distribution), some ions / atoms in the dopant are implanted deeper than others. It should be understood that the concentrations shown reflect trends rather than actual concentrations.

[0063] The upper chart illustrates the concentration (or atomic percentage) of the dopant along the path indicated by arrow 84A in Figure 16B. The lower chart illustrates the concentration (or atomic percentage) of the dopant along the path indicated by arrow 84B (Figure 16B). The position in the upper chart corresponds to a specific position in the lower chart. Both the upper and lower charts illustrate the variation of the dopant concentration (or atomic percentage) along the path indicated by arrows 84A and 84B.

[0064] As shown in the upper figure, since the dopant can be implanted into the sacrificial layer 22A (Figure 4), which is subsequently removed and replaced by the gate stack 70 (Figure 16B), the gate stack 70 has a suddenly decreasing dopant concentration, lower than that of the individual overlying and underlying semiconductor strips 20'. The upper nanostructure 22B has a higher concentration than the individual underlying nanostructure 22B. In addition, the concentration profile in the nanostructure 22B can be fitted with a curve. The peak concentration can be inside the top nanostructure 22B and can be close to the top surface of the top nanostructure 22B.

[0065] The lower chart shows the peak concentration of the dopant in the protective layer 126, which may be close to the top surface of the protective layer 126, or in the middle between the top and bottom surfaces of the protective layer 126.

[0066] The embodiments disclosed herein have several advantageous features. According to some embodiments, by forming a protective layer on top of the STI region, the protective layer protects the STI region from denting during the removal of the disposable interposer. Therefore, the unwanted increase in parasitic capacitance between the gate electrode and the semiconductor strip is reduced.

[0067] According to some embodiments of the present disclosure, a method includes forming a shallow trench isolation region next to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into the top portion of the shallow trench isolation region to form a protective layer; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interposer in the space; removing the dummy gate stack; performing an etching process using an etchant to remove the disposable interposer, wherein the protective layer is exposed to the etchant during the etching process; and forming a replacement gate stack, wherein a portion of the replacement gate stack fills the space.

[0068] In an embodiment, the shallow trench isolation region is exposed during the doping process. In an embodiment, the method further includes forming a hard mask over the protruding fins, wherein the hard mask is doped with a dopant during the doping process. In an embodiment, the method further includes removing the hard mask after the doping process. In an embodiment, the doping process includes nitrogen doping. In an embodiment, the doping process is performed using a process gas comprising N2, N2O, or a combination thereof.

[0069] In an embodiment, the dopant comprises an n-type or p-type dopant. In an embodiment, the method further comprises forming a source / drain region adjacent to the dummy gate stack, wherein the dopant has a conductivity type opposite to that of the source / drain region. In an embodiment, the doping process includes an implantation process. In an embodiment, the doping process includes a plasma processing process. In an embodiment, the doping process is performed at a temperature above room temperature. In an embodiment, the doping process is performed prior to the formation of the dummy gate stack.

[0070] According to some embodiments of the present disclosure, a structure includes a semiconductor strip; a first semiconductor nanostructure that overlaps with and is spaced apart from the semiconductor strip; a shallow trench isolation region that contacts the edge of the semiconductor strip; a gate stack that includes a first portion and a second portion, wherein the first portion is between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack includes a gate dielectric and a gate electrode above the gate dielectric; and a protective layer between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer includes a dielectric material different from the material of the shallow trench isolation region and the gate dielectric.

[0071] In an embodiment, the protective layer comprises a dopant, and the dopant concentration in the lower portion of the protective layer is lower than that in some of the upper portions of the protective layer. In an embodiment, the bottom portion of the shallow trench isolation region comprises silicon oxide, and the protective layer comprises silicon oxynitride. In an embodiment, the bottom portion of the shallow trench isolation region comprises silicon oxide, and the protective layer comprises silicon carbonitride. In an embodiment, the protective layer comprises an n-type dopant or a p-type dopant.

[0072] According to some embodiments of the present disclosure, a structure includes a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is adjacent to and in contact with the shallow trench isolation region to act as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack above and surrounding the semiconductor layer; a source / drain region adjacent to the gate stack; and a dielectric protective layer above and in contact with the shallow trench isolation region, wherein the dielectric protective layer includes a first portion directly underlying the gate stack and a second portion directly underlying the source / drain region.

[0073] In an embodiment, the dielectric protective layer contacts the gate dielectric layer of the gate stack. In an embodiment, the dielectric protective layer contains a dopant, and wherein a first concentration of the lower portion of the dielectric protective layer is lower than a second concentration of the upper portion of the dielectric protective layer.

[0074] The foregoing summarizes the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The embodiments disclosed herein are best understood by reading in conjunction with the accompanying figures from the following detailed description. It should be noted that, in accordance with industry standards, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1, 2, 3A, 3B to 16A, 16B, and 16C illustrate views of intermediate stages in the formation of transistors and STI protective layers according to some embodiments. Figure 17 illustrates a schematic cross-sectional view of dopant distribution according to some embodiments. Figure 18 illustrates a process flow diagram for forming transistors according to some embodiments. [Biomaterial Storage]

[0076] No domestic storage information (please note in order of storage institution, date, and number) No international storage information (please note in order of storage country, institution, date, and number) None

Claims

1. A method of forming a semiconductor device, comprising the steps of: forming a shallow trench isolation region adjacent to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into a top portion of the shallow trench isolation region to form a protective layer, wherein the dopant concentration of a plurality of lower portions of the protective layer is lower than that of a plurality of individual upper portions of the protective layer; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interposer in the space; removing the dummy gate stack; performing an etching process using an etchant to remove the disposable interposer, wherein the protective layer is exposed to the etchant during the etching process; and forming a replacement gate stack, wherein a portion of the replacement gate stack fills the space.

2. The method as described in claim 1, wherein the shallow trench isolation region is exposed during the doping process.

3. The method as described in claim 1, further comprising the step of forming a hard mask over the protruding fin, wherein the hard mask is doped with the dopant during the doping process.

4. The method as described in claim 1, wherein the doping process is performed at a temperature above a room temperature.

5. The method as described in claim 1, wherein the doping process is performed prior to the formation of the dummy gate stack.

6. A semiconductor structure comprising: a semiconductor strip; a first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack comprising a first portion and a second portion, wherein the first portion is between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack comprises a gate dielectric and a gate electrode above the gate dielectric; and a protective layer between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer comprises a dielectric material different from a plurality of materials of the shallow trench isolation region and the gate dielectric, wherein the protective layer comprises a dopant, and the concentration of a plurality of dopants in a plurality of lower portions of the protective layer is lower than that in a plurality of individual upper portions of the protective layer.

7. The semiconductor structure as claimed in claim 6, wherein the dopant comprises an n-type dopant or a p-type dopant.

8. The semiconductor structure as claimed in claim 6, wherein a bottom portion of the shallow trench isolation region comprises silicon oxide, and the protective layer comprises silicon oxynitride.

9. The semiconductor structure as claimed in claim 6, wherein a bottom portion of the shallow trench isolation region comprises silicon oxide, and the protective layer comprises silicon carbonitride.

10. A semiconductor structure comprising: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is adjacent to and in contact with the shallow trench isolation region to serve as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack above and surrounding the semiconductor layer; a source / drain region adjacent to the gate stack; and a dielectric protective layer above and in contact with the shallow trench isolation region, wherein the dielectric protective layer includes a first portion directly underlying the gate stack and a second portion directly underlying the source / drain region, wherein the dielectric protective layer includes a dopant, and the dopant concentrations of a plurality of lower portions of the dielectric protective layer are lower than those of a plurality of individual upper portions of the dielectric protective layer.

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