Stacked memory cell structure and method of forming the same

Abstract

The semiconductor memory cell structure and manufacturing method of the same structure include one or more bit cells, including stacked read transistors and write transistors. Each bit cell further includes read bit lines, read word lines, write bit lines, write word lines, and storage nodes isolated from other bit cell structures. The bit cell further includes a read word line-to-storage node voltage coupling structure located adjacent to the read word lines and the storage node, and the voltage coupling is configured as a wing gate or a wraparound read word line.

Description

Prior Technology

[0001] The following content relates to semiconductor integrated circuits (ICs) that employ transistor memory cells, such as dynamic random-access memory (DRAM) transistor cells and arrays, and their manufacturing methods. [, , ] Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity. Figure 1A is a cross-sectional view of an integrated circuit (IC) structure (Embodiment 1) including a 3x1 vertically stacked array of dynamic random access memory cells. According to the embodiments disclosed herein, each memory cell includes a read transistor read word line (RWL) to storage node (SN) voltage coupled (VCoupler) having a winged gate adjacent to the RWL. Figure 1B is a schematic diagram of the IC (Example 1) shown in Figure 1A. Figure 1C is a simplified top view of the IC (Example 1) shown in Figure 1A according to an embodiment of the present disclosure. Figure 1D is an enlarged detail view of the wing gate RWL to SN Vcoupler shown in Figures 1A-1C. Figure 1E is a graph showing the relationship between the readout transistor drain current (Id) and the SN voltage (Vsn) according to an embodiment of the present disclosure. Figure 2A is a top view of an IC structure including a 3x3 vertically stacked array of dynamic random access memory cells or a memory bank. According to an embodiment disclosed herein, each memory cell includes a read transistor RWL to an SN VCoupler, the coupler having a wing-shaped gate adjacent to the RWL. Figure 2B is a schematic diagram of the IC structure, including selecting or determining a read operation of one RWL while other RWLs are not determined, and the operating state of the memory cells in the memory according to the embodiments of this disclosure. Figures 3A-3H illustrate the various manufacturing stages associated with the fabrication of an IC structure comprising a 3x1 vertically stacked array of dynamic random access memory cells (Example 1), wherein, according to an embodiment disclosed herein, each memory cell includes a read transistor RWL to an SN VCoupler having a wing-shaped gate adjacent to the RWL. Figure 4 is a cross-sectional view of an IC structure including a 3x1 vertically stacked dynamic random access memory cell array (Embodiment 2). According to the embodiments disclosed herein, each memory cell includes a read transistor RWL to a storage node SN VCoupler, the coupler having an enclosing RWL adjacent to the SN. Figure 5 illustrates a method for forming an IC including a vertically stacked array of dynamic random access memory cells according to an embodiment of the present disclosure, each memory cell including a read transistor RWL to SN VCoupler with wing-shaped gates. Figure 6 illustrates a method for forming an IC including a vertically stacked array of dynamic random access memory cells according to an embodiment of the present disclosure, wherein each memory cell includes a read transistor RWL to an SN Vcoupler having an RWL covering it. Implementation

[0003] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Numerical values ​​in this disclosure and the claims should be understood to include values ​​that remain the same when reduced to the same number of significant figures, as well as values ​​that differ from those determined by experimental errors less than those determined by conventional measurement techniques of the type described in this disclosure. All scopes of this disclosure include the stated endpoints.

[0005] The term "approximately" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "approximately" also reveals a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also reveals a range "from 2 to 4". The term "approximately" can refer to a numerical value ±10%.

[0006] This disclosure relates to structures composed of different layers. When the terms "on" or "on" are used to refer to two different layers (including a substrate), it simply means that one layer is on or on another layer. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between them. For example, all layers of the structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other, with no layers in between. Furthermore, when referring to performing process steps on the substrate, this should be understood to mean, depending on the context, that such steps are also performed on any layers that may be present on the substrate.

[0007] Additionally, for ease of explanation, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0008] The term "layer" as used in this article may include a single layer or multiple layers.

[0009] The term "conductive feature" as used in this article may refer to metallized layer contacts, patterned metallized layer contacts, or other electrically conductive metal contacts.

[0010] The term "intermetallic dielectric" (IMD) film or layer, as may be used in this article, refers to a dielectric / insulating material layer between two metal layers.

[0011] The term "interlayer dielectric" (ILD) may be used in this article to refer to a material insulating structure placed between two conductive layers.

[0012] The terms "wire" and "metal wire" as used in this article refer to conductive paths created during back-end processing (BEOL) to transmit electrical signals within the circuit pattern of a semiconductor wafer.

[0013] The terms “coupler” and “voltage coupler” as used herein refer to a semiconductor structure that provides (i.e. couples) a first / input voltage from a first semiconductor structure feature to a second / output semiconductor feature, while the terms “coupler ratio” and “coupling ratio” used herein to describe “coupler” and “voltage coupler” refer to the ratio of the second / output voltage of the coupler to the first / input voltage.

[0014] As used herein, the terms “stacked” and “vertically stacked” refer to the stacking or formation of two or more transistor structures, wherein the first and second transistors are substantially arranged or formed in an elongated pattern, as opposed to a planar structure comprising two or more transistor structures arranged side by side. The terms “vertical” or “perpendicularly” are not related to gravity and may include lateral arrangements in which the first transistors are laterally stacked and formed next to a second lateral transistor, having the structure disclosed herein.

[0015] Generally, some embodiments disclosed herein relate to semiconductor devices, including vertically stacked memory cell structures and methods of forming the same. Specifically, this disclosure provides optimizations to memory cell integrated circuit structures, such as dynamic random access memory transistor (DRAM) cells, arrays, and storage banks, by providing a transistor memory cell structure with vertically stacked non-destructive read DRAM transistor cells. This structure has a winged gate (Embodiment 1) adjacent to the memory cell storage node (SN) and a surrounding read word line (Embodiment 2). By using a storage node (SN) coupler structure to couple the write transistor source / drain to the read word line of a 2T, 3T, or 4T memory cell transistor structure, the sensing window of the memory cell device is enhanced. Although this disclosure focuses on 2T memory cell field-effect transistor (FET) structures, it should be understood that other transistor memory structures are also within the scope of this disclosure.

[0016] The dual-transistor memory cell disclosed in this paper is a type of dynamic random access memory (DRAM) cell that uses two transistors, or 2T, instead of one capacitor and one transistor. One transistor acts as the write transistor, and the other as the read transistor. DRAM cells store bit data, or bit signals representing two logical state values ​​(including 0 and 1). Typically, DRAM is volatile memory, rapidly losing its data after power loss. To prevent this, DRAM requires external memory reflow circuitry to periodically rewrite the data in the capacitor. Furthermore, a sensing circuit is operatively connected to the memory cell bit output during reads to provide signal processing of the stored bit value signal, which is necessary for computer processing, etc. The 2T memory cell offers several advantages over larger memory cell structures, including but not limited to low power consumption, high density, and long retention time.

[0017] Some traditional 2T, 3T, and 4T memory cell structures suffer from problems or design limitations due to the planar side-by-side structure and layout of the memory cell read and write transistors, resulting in relatively large cell sizes. Furthermore, the relatively large bit cells electrically connected to common bit lines generate relatively large parasitic or leakage currents, which may weaken or disrupt the sensing signal output required by the memory cell structure or device, thus preventing the reading and processing of bit signals. Specifically, in a traditional 2T memory cell structure, the digital memory states (0 and 1) are defined by the high and low conductivity states of the memory cell read transistor, respectively. Therefore, when the read transistor is turned on, i.e., when the read word line is selected or asserted to read the relevant storage node state, the high conductivity states of unselected cells in adjacent and connected bit cells in the array reduce the sensing window of the selected cell. This is because the high conductivity states of other adjacent read transistors not selected by the read word line in the memory structure array cause other unselected cells to generate parasitic currents of opposite polarity.

[0018] In other words, the conventional approach of using side-by-side write and read transistors and planar transistor memory cell structures may have a limited or problematic sensing window that is susceptible to noise generated by parasitic currents. The sensing window refers to the window between state 1 and state 0 used by the sensing amplifier to identify the relevant bit memory state 1 or 0.

[0019] This disclosure and the embodiments described herein provide a transistor memory cell structure that minimizes or reduces the memory cell size by stacking read and write transistors for dynamic random access memory cells. Furthermore, according to Embodiment 1, this disclosure and the embodiments described herein reduce or minimize parasitic / leakage current by coupling read word lines to the storage node of the memory cell, wherein the overlapping region structure of the winged gate of the read transistor on the read word line is located close to the winged gate, and the overlapping structure is designed to provide the required coupling ratio for the input read word line voltage (i.e., the determine or select line) to the storage node region of the memory device, thereby reducing noise generated by parasitic current. According to Embodiment 2, parasitic / leakage current is reduced or minimized by coupling read word lines to the storage node of the memory cell, wherein the read word line covers the overlapping region structure of the gate at the end of the read transistor gate structure furthest from the storage node, and the overlapping or covered read word line structure is designed to provide the required coupling ratio for the input read word line voltage (i.e., the determine or select line) to the storage node region of the memory device, thereby reducing noise generated by parasitic current.

[0020] The non-destructive operation of the disclosed memory cell structure or device means that the storage node signal will not degrade after a read operation because there is no charge sharing. However, once the storage node signal is lost after the data retention time (e.g., >100 ms) due to leakage current from the write transistor, an update is required. Parasitic current is leakage current from unselected memory cells during a read operation, which causes a reduction in the sensing window due to higher noise caused by the leakage current.

[0021] According to one embodiment, the read transistor read word line to storage node coupler generates a coupling voltage of 200mV to 500mV at the storage node by selecting or determining the read word line, which is required for proper operation of the read transistor according to a memory cell structure example. The coupling ratio for generating the required coupling voltage from the read word line to the storage node depends on (1) the overlap area between the storage node and the read word line, and (2) the thickness and dielectric constant of the high-K dielectric layer and conductive channel between the storage node and the read word line. For example, if the selected read word line voltage is 1V, the coupling ratio should be approximately 0.2 to 0.5 to generate a coupling voltage of approximately 200mV to 500mV from 1V to the read word line to the storage node. Another feature of the disclosed embodiments (including embodiments 1 and 2) is the use of island-shaped or isolated metal storage node regions, which contrasts with and is distinguishable from other memory cell designs that include common metal lines electrically connecting adjacent or other memory cell storage nodes. The isolated metal storage node is formed on the gate structure of the read transistor and is electrically isolated from other memory cell storage nodes. In other words, no common storage node metal lines are used.

[0022] As further described below with reference to the figures, the disclosed memory cell includes a read transistor, read bit lines, and a read word line structure / layout, including a read word line-to-storage node voltage coupler structure. In operation, both memory states (0 and 1), i.e., storage node voltage states, keep the read transistor in an off state, but at different storage node voltage levels corresponding to memory state 1 and memory state 0. This is achieved using the disclosed read word line-to-storage node coupler structure, which effectively provides different effective threshold voltage (Vt) levels to the read transistor depending on whether the read word line is determined (i.e., the read word line voltage). In practice, when the read word line is determined, the read transistor becomes a read transistor with a relatively low Vt state, which can be turned on (i.e., become highly conductive) by voltage coupling to the selected read word line (read word line). In contrast, when the read word line is unselected, the read transistor becomes a read transistor with a relatively high Vt state and will not turn on (i.e., becomes low-conductivity) because there is no voltage coupling from the unselected read word line (read word line), for example, 0 V. Furthermore, since the disclosed read word line to storage node coupler structure only operates to provide coupling voltage to the storage node when the read word line is selected, thus providing the input voltage to the coupler, the read transistor remains in the off state regardless of whether the memory state (i.e., the storage node voltage) of the device or structure is high or low. In other words, when the read transistor is in the unselected state, the transistor's conductive path is in a low-conductivity state, and parasitic current is minimized or approximately zero.

[0023] The advantages / benefits of the embodiments disclosed and described herein include, but are not limited to, higher memory cell density layouts achieved due to smaller cell sizes and vertical stacking of read and write transistors. Furthermore, performance improvements are achieved in terms of relatively high operating speeds and low power consumption due to the elimination or minimization of parasitic currents.

[0024] The disclosed embodiments provided herein pertain to dynamic random access memory (DRAM) comprising a 2T0C (2 transistors and 0 capacitors) layout or configuration. However, other DRAM cells comprising independent write and read transistors, such as 3T, 4T, etc., are also within the scope of this disclosure, as they may benefit from integrating the read word lines to the storage node couplers using a vertically stacked transistor structure, as described herein, to minimize or reduce cell size, increase operating speed, and minimize or reduce parasitic and leakage currents, without departing from the basic structural design details described herein.

[0025] Referring to FIG1A, a cross-sectional view of an integrated circuit structure (Embodiment 1) including a 3x1 vertically stacked dynamic random access memory cell array 1001 is shown. Each memory cell 1001A, 1001B, and 1001C includes a read transistor read word line (RWL) to storage node (SN) voltage coupler (VCoupler). According to an embodiment of the present disclosure, the coupler has a winged gate adjacent to the RWL. Further referring to FIG1B, FIG1C is a schematic diagram of the integrated circuit shown in FIG1A; FIG1C is a simplified top view of the integrated circuit shown in FIG1A; FIG1D is an enlarged detail view of the winged gate RWL to SN Vcoupler shown in FIG1A-1C; and FIG1E is a graph showing the relationship between the read transistor drain current (Id) and the SN voltage (Vsn) according to an embodiment of the present disclosure.

[0026] As shown in Figure 1A, the memory cell array 1001 includes a 3-bit layout, including a 2T bit 1 structure 1001A, a 2T bit 2 structure 1001B, and a 2T bit 3 structure 1001C.

[0027] In operation, referring to Figure 1B, each 2T (e.g., field-effect transistor) memory cell bit structure is formed to provide a functionally equivalent circuit as shown in Figure 1B. Each 2T bit cell 1001A, 1001B, and 1001C typically operates to provide write, store, and read operations for a single bit or memory state associated with logic 1 or 0. Although the following description focuses on the operation of bit cell 1001A, it should be understood that the other bit cells 110B and 1001C operate similarly.

[0028] During the write operation of cell 1001A, the write word line WWL(A) is determined, and the write transistor is turned on by applying a voltage to the write transistor gate G(WTA). Therefore, the bit value or representative bit value signal is effectively transmitted to the storage node SN(A) of the write transistor source / drain (S / D(WTA)). The write transistor S / D(WTA) provides the necessary charge retention function by reading the coupling structure from the transistor gate G(RTA) and the source / drain region (S / D(RTA)) to RWL(A) to maintain the written bit signal at storage node SN(A) after the write word line is de-determined.

[0029] During a read operation, the read word line RWL(A) is determined, the read transistor RTA is turned on, and the logic voltage value stored in the storage node SN(A) can be read or detected on the read bit line RBL(A).

[0030] According to the embodiments described herein, including an RWL-SN voltage coupling region structure and an isolated SN structure, during a read operation, when SN(A) is 1, the read transistor RTA is in a high-conductivity channel state, i.e., on; during a read operation, when SN(A) is 0, the read transistor RTA is in a low-conductivity channel state, i.e., off. When the read word line RWL(A) is not determined or selected, for example, at 0V, the read transistor RTA is in a low-conductivity channel state (i.e., off) for the storage node SN(A) in a low state (i.e., logic bit value 0), and is also off for a high state condition (i.e., logic bit value 1).

[0031] As shown in the figure, and further referring to Figure 1A, the 1x3 bit memory array 1001 includes the following: The first memory cell 1001A includes a read transistor (e.g., a field-effect transistor) 100A, a stacked write transistor (e.g., a field-effect transistor) 200A, and read bit lines RBL(A), read word lines RWL(A), write bit lines WBL(A), and write word lines WWL(A) integrated with the stacked bit cell structure. The read transistor 100B's metal gate G(RTA), source / drain region S / D(RTA), and storage node SN(A) provide the functionality for receiving and storing bit values ​​in the bit cell 1001A, as previously described, receiving from the write transistor WTA's write bit line WBL(A) when the write word line WWL(A) is determined. The metal gate G(WTA) and source / drain region S / D(WTA) provide the operation of the write transistor 200A. The second-bit memory cell 1001B includes a read transistor (e.g., a field-effect transistor) 100B, a stacked write transistor (e.g., a field-effect transistor) 200B, and read bit lines RBL(B), read word lines RWL(B), write bit lines WBL(B), and write word lines WWL(B) integrated with the stacked bit cell structure. The metal gate G (RTB), source / drain region S / D (RTB), and storage node SN(B) of the read transistor 100B provide the functionality for receiving and storing bit values ​​in the bit cell 1001B, as previously described, when the write word line WWL(B) is determined, it is received from the write transistor WTA and the write bit line WBL(B). The metal gate G (WTB) and the source / drain region S / D (WTB) provide the operation of the write transistor 200A. The third-bit memory cell 1001C includes a read transistor (e.g., a field-effect transistor) 100C, a stacked write transistor (e.g., a field-effect transistor) 200C, and read bit lines RBL(C), read word lines RWL(C), write bit lines WBL(C), and write word lines WWL(C) integrated with the stacked bit cell structure. The metal gate G (RTC), source / drain region S / D (RTC), and storage node SN(C) of the read transistor 100C provide the functionality for receiving and storing bit values ​​in the bit cell 1001C, as previously described, when the write word line WWL(C) is determined, it is received from the write transistor WTC and the write bit line WBL(C). The metal gate G (WTC) and the source / drain region S / D (WTC) provide the operation of the write transistor 200A.

[0032] The various details of Embodiment 1 shown in Figure 1A are as follows.

[0033] According to one embodiment, the write bit lines WBL(A), WBL(B), WBL(C), and WBL(D) regions D are all part of a common metal line, while the read word lines RWL(A), RWL(B), RWL(C), and RWL(D) are part of another common metal line.

[0034] According to one embodiment, the conductive channel layers 105A, 105B, 105C, 205A, 205B, and 205C are made of indium gallium zinc oxide (IGZO) and / or indium gallium zinc tin oxide (IGZTO); the high-k dielectric layers 104A, 104B, 104C, 204A, 204B, and 204C are made of hafnium oxide (HfO2), zirconium dioxide (ZrO2), and / or aluminum oxide (Al2O3); and the metal gates G(RTA), G(RTB), G(RTC), G(WTA), G(WTB), and G(WTC) are made of titanium nitride (TiN) and / or ruthenium (Ru). The materials for IMD regions / layers 300A1 and 300A2 are chemical vapor-deposited silicon dioxide (CVD SiO2) or other low-k materials.

[0035] According to the described embodiment, the DRAM cell is an n-channel metal-oxide-semiconductor field-effect transistor; however, other types of field-effect transistors are also within the scope of this disclosure, including but not limited to p-channel metal-oxide-semiconductor field-effect transistors.

[0036] According to one embodiment, IC 1001 is formed on a wafer made of semiconductor material, wherein IC 1001 is built or formed thereon by conventional semiconductor manufacturing techniques, including but not limited to photolithography, such as applying a photoresist layer, patterning a photoresist layer, developing a photoresist layer, then etching, followed by planarization and cleaning, to apply a pattern / structure in a given layer. While the specific semiconductor manufacturing process required to form the illustrated IC 1001 is not the focus of this disclosure, a general description of semiconductor manufacturing processes is provided below for completeness.

[0037] Semiconductor substrate materials may include silicon, for example, in the form of crystalline silicon or polycrystalline silicon. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In a particular embodiment, the wafer substrate is silicon.

[0038] Typically, photoresist layers can be applied by methods such as spin coating, spray coating, roller coating, dip coating, or extrusion coating. In spin coating, the substrate is typically placed on a rotating platform, which may include a vacuum clamp to hold the substrate in place. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to allow the photoresist to diffuse uniformly from the center of the substrate to its periphery. The rotational speed of the platform is then fixed, which controls the final thickness of the photoresist layer.

[0039] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate or oven, or similar equipment. Thus, a photoresist layer is formed on the substrate.

[0040] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the desired masking pattern. In a particular embodiment, extreme ultraviolet light with a wavelength of about 13.5 nm is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation, while other portions are not. This exposure makes some portions of the photoresist soluble in the developer, while other portions remain insoluble in the developer.

[0041] An additional photoresist baking step (post-exposure baking, or PEB) may be performed after exposure to radiation. For example, this may help release acid leaving groups (ALGs) or other molecules that are important in chemically amplified photoresists.

[0042] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. The soluble portions of the photoresist layer dissolve and are washed away during the development step, leaving the photoresist pattern. A common example of a developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers may include 2-heptanone, butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate or propylene glycol monomethyl ether acetate, amyl acetate, butyl propionate, hexyl acetate, butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" may be performed after development to stabilize the photoresist pattern after development for optimal performance in subsequent steps.

[0043] Next, a portion of the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, using various solvents such as N-methylpyrrolidone (NMP) or alkaline media or other stripping agents at elevated temperatures, or by dry etching using oxygen plasma.

[0044] Generally, any etching step used herein may employ wet etching, dry etching, or plasma etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or combinations thereof, as applicable. Etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), fluorides, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), oxygen (O2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), or similar substances, or combinations thereof, in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4 and / or H2.

[0045] Planarization can be performed to obtain a flat surface. Planarization can be performed, for example, using a chemical mechanical polishing (CMP) process. Typically, CMP is performed using a rotating platform with a polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier rotate, which creates mechanical and chemical effects on the surface of the wafer substrate and / or the top layer thereon, removing unwanted material and creating a highly flat surface. A post-CMP cleaning step is then performed using a rotating brush and cleaning solution to clean one or both sides of the wafer substrate.

[0046] Finally, cleaning steps such as wet cleaning can be performed between various process steps. The cleaning solution will depend on the etching formulation and the exposed layers. Examples of cleaning solutions may include deionized water, diluted HF, and other conventional solutions.

[0047] The dielectric structure can be made from any suitable combination of dielectric materials. Examples of dielectric materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiOxNy), hafnium oxynitride (HfOxNy), or zirconium oxynitride (ZrOxNy), or hafnium silicate (ZrSixOy), or zirconium silicate (ZrSixOy), or silicon carbonitride (SiCxOyNz), or hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilate glass (PSG), fluorosilate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0048] Any conductive material discussed herein can generally be any conductive metal or conductive oxide. Examples of suitable metals may include copper, aluminum, nickel, chromium, gold, germanium, silver, titanium, tungsten, platinum, tantalum, ruthenium, cobalt, rhenium, palladium, or zirconium; composite materials such as TiN, WN, or TaN; or alloys thereof such as AlCu. Examples of suitable conductive oxides may include indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), zinc aluminum oxide (AlZnO), indium oxide (InO), or cadmium oxide (CdO). Metallic or oxide materials may be deposited, for example, by evaporation or sputtering, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods.

[0049] Referring to Figure 1D, a detailed view of the read transistor 100A is shown, specifically displaying various dimensional parameters of the RWL(A) to SN(A) interface and coupling structure to provide voltage coupling and associated voltage coupling ratio.

[0050] CHlength indicates the length of the conductive channel; CHwidth indicates the width of the conductive channel; CHthickness indicates the thickness of the conductive channel; SNmetalthickness indicates the thickness of the top metal layer of the S / D (WTA); SNwinglength indicates the length of the overlapping region or wing-shaped portion, overlapping the read word line RWL(A) to provide voltage coupling from RWL(A) to SN(A); hkDEthicknesses indicates the thickness of the high-K dielectric layer 104A; Gthickness indicates the thickness of the metal gate G (RTA).

[0051] The voltage coupling ratio from RWL(A) to SN(A) is provided based on CHwidth, CHthickness, SNmetalthickness, SNwinglength, hkDEthicknesses, and Gthickness. According to some embodiments, one or more of these dimensional characteristics of the voltage coupling region 400A are designed to provide the desired voltage coupling from RWL(A) to SN(A) as previously described and further described below.

[0052] Referring to FIG1E, a graph showing the relationship between the read transistor drain current (Id) and the SN voltage (Vsn) according to an embodiment of the present disclosure is displayed. Specifically, the graph shows the conductivity of bit memory cells in states 1 and 0 during a read operation, including whether the memory cell is selected or determined by the read word line RWL. State 1 or 0 depends on the SN voltage level and results in different channel conductivity of the read transistor (RTA, RTA, and / or RTC).

[0053] Figure 1E illustrates four states or conditions during the read character line determination and selection operation, or during the undetermined read character line determination period, wherein:

[0054] 1) RWL is determined and is approximately 0.5V to 1V, where state 0 (off) (e.g., SN = 0V + RWL to SN coupling voltage) is a low-conductivity channel state and the read transistor is off;

[0055] 2) RWL is determined and is approximately 0.5V to 1V, where "State 1 (On)" (e.g., SN is approximately 0.5V to approximately 1V, +RWL to SN coupling voltage, e.g., approximately 0.5V to approximately 1V) is a high-conductivity channel state and the read transistor is on;

[0056] 3) RWL is undetermined and approximately 0V, where state 0 (off) (e.g., SN=0V) is a low-conductivity channel state and the read transistor is off; and

[0057] 4) RWL is undetermined and is approximately 0.5V to 1V, where "State 1 (On)" (e.g., SN is approximately 0.5V to approximately 1V) is a low conductivity channel state and the read transistor is off.

[0058] In other words, the graph showing the relationship between the read transistor drain current (Id) and the SN voltage (Vsn) indicates that both the high and low channel conductivity Vt states of the read transistor are defined at Vt > 0 (i.e., enhancement mode). According to an embodiment, in the standard transfer Id-Vg curve representing the read transistor structure, Vt is approximately 10 nA * W / L. According to this equation, "W" is the width of the conductive channel (not shown), and "L" is the conductive channel length CHlength as shown in Figure 1D. According to an embodiment, CHlength is approximately 20 nm to approximately 200 nm. According to some embodiments, the W / L ratio varies and is a function of power, performance, area, and cost (PPAC) optimization.

[0059] According to an embodiment, the readout transistor has a Vt of approximately 0.2V to 0.4V in the low conductivity channel state and approximately 0.6V to 0.8V in the high conductivity channel state. To adjust the Vt for this purpose, several techniques can be used in amorphous oxide semiconductors (e.g., IGZO, IGZTO, indium(III) oxide (In₂O₃), ITO, ...). Furthermore, thinner channel thicknesses are formed, for example, from approximately 2 nm to approximately 8 nm; lower indium concentrations are used when forming the conductive channels to reduce the electron carrier concentration, for example, indium ranging from approximately 5% to approximately 30%; and high work function metal gates, such as TiN, tungsten (W), or Ru, are provided.

[0060] Referring to Figure 2A, a top view of an IC structure including a 3x3 vertically stacked DRAM memory cell array or library is shown. According to an embodiment of the present disclosure, each memory cell includes a read transistor RWL-SN voltage coupler with a winged gate adjacent to the read transistor RWL. Figure 2B is a schematic diagram of the IC structure, including a read operation that selects or determines an RWL while other RWLs are not determined, and the operating state of the memory cells in the library according to an embodiment of the present disclosure.

[0061] As shown in Figure 2A, the IC memory cell array includes a 3x3 memory cell array with stacked memory cells 1001(1), 1001(2) and 1001(3) as previously described with reference to the 1x3 memory cell 1001 and shown in Figures 1A-1E.

[0062] The visible features of each of the 1x3 memory cells 1001(1), 1001(2), and 1001(3) include write bit lines WBL(A), WBL(B), WBL(C), and WBL(D), write word lines WWL(A), WWL(B), and WWL(C), read word lines RWL(A), RWL(B), and RWL(C), and read bit lines RBL(A), RBL(B), and RBL(C). The write transistor gates G(WTA), G(WTB), and G(WTC) and the read transistor wing gates G(RTA), G(RTB), and G(RTC) of the 1x3 memory cell 1001(1) are also shown. The transistor gates G(WTA), G(WTB), and G(WTC) are shown as rectangular or square wing gate outlines; however, other wing gate shape outlines, such as circles, polygons, etc., may be used.

[0063] To provide the functionality of the 3x3 memory cell array shown in Figure 2B, in addition to the structural features of each 1x3 memory cell 1001(1), 1001(2) and 1001(3) previously described with reference to Figures 1A-1E, 1) read bit lines (AC) (vertically as shown) are connected to the respective bit row positions of the 1x3 memory array of each 1x3 memory cell 1001(1), 1001(2) and 1001(3), and 2) word write lines (AC) (vertically as shown) are connected to the respective bit row positions of the 1x3 memory array of each 1x3 memory cell 1001(1), 1001(2) and 1001(3).

[0064] Referring to the operation diagram of Figure 2B, a read operation of a 3x3 memory cell array or library is shown, wherein the first 1x3 bit array 1001(1) includes memory cells 1001A, 1001B, and 1001C as previously described with reference to Figures 1A-1E; the second 1x3 bit array 1001(2) includes memory cells 1001AA, 1001BB, and 1001CC as previously described with reference to Figures 1A-1E; and the third 1x3 bit array 1001(3) includes memory cells 1001AAA, 1001BBB, and 1001CCC as previously described with reference to Figures 1A-1E. Furthermore, the read word line RWL corresponds to RWL(AC) in Figure 2A, and the bit outputs A, B, and C correspond to the read bit line RBL(AC) in Figure 2A. The VDD voltage represents the voltage applied to RWL to determine or select the desired read word line, for example, 1 volt.

[0065] When the RWL of the 1x3 memory cell array 1001(2) is selected or determined, while the memory cell arrays 1001(1) and 1001(3) are not selected, the read transistors of the cells 1001AA and 1001CC are ON, thus having a high conductivity channel and generating Idrain (high), while all the read transistors of the memory cells 1001A, 1101B, 1001C, 1001BB, 1001AA, 1001BB and 1001CC are OFF and generating Idrain (low), which is a minimum amount of leakage current or creep current, or essentially zero.

[0066] Referring to Figures 3A-3H, various manufacturing stages related to the fabrication of an IC structure comprising a 3x1 vertically stacked DRAM memory cell array (Example 1) are shown. According to the embodiments disclosed herein, each memory cell includes a read transistor RWL to SN VCoupler with a wing-shaped gate adjacent to the RWL.

[0067] Figure 3A shows the initial stage after the semiconductor substrate has been previously processed to provide a read bit line metallization layer. As shown, the RBL metal layer is patterned and etched to form RBL(A), RBL(B) and RBL(C), and the etched cavities are filled by an epitaxial growth process to form the intermetallic dielectric (IMD) region 300A1.

[0068] Figure 3B shows the next manufacturing stage, where IMD region 300A1 is completed and the read word line metal layer RWL(AD) is formed using a metallization process.

[0069] Figure 3C shows the next manufacturing stage, in which an etching process is used to form a channel hole 601 between each read word line RWL(AD). The channel hole 601 extends from the read bit line RBL(AC) to the read word line RWL(AD) and provides a channel for subsequent processing to form the gate and conductive layer of each read transistor.

[0070] Figure 3D shows the next fabrication stage, in which channel layers 104A-104C (e.g., IGZO, IGZTO), high-k layers 105A-105C (e.g., hafnium(IV) oxide (HfO2), ZrO2, or Al2O3), metal gates G(RTA), G(RTB), and G(RTC) (e.g., TiN or Ru), and top metal layer S / D (WTA, WTB, WTC) are formed. The fabrication stage shown includes the top metal layer S / D (WTA, WTB, WTC) to provide the S / D for the write transistors formed in subsequent fabrication stages.

[0071] Figure 3E shows the next manufacturing stage, in which an etching process is performed to create discrete wing-shaped gates for each gate G(RTA), G(RTB), and G(RTC), as well as discrete metal storage nodes SN(A), SN(B), and SN(C), wherein the storage nodes are electrically isolated from each other and electrically connected only to their respective metal gates.

[0072] Figure 3F shows the next manufacturing stage, where IMD region 300A2 is completed and the write-word line metal layer WWL(AD) is formed using a metallization process.

[0073] Figure 3G shows the next manufacturing stage, in which an etching process is used to form a channel hole 602 between each write bit line RWBL (AD). The channel hole 602 extends from the storage node SN (AD) and provides a channel for subsequent processing to form the gate and conductive layer of each write transistor.

[0074] Figure 3H shows the next manufacturing stage in which channel layers 204A-204C (e.g., IGZO, IGZTO), high-k layers 205A-205C (e.g., hafnium(IV) oxide (HfO2), ZrO2, or Al2O3), metal gates G (WTA), G (WTB), and G (WTC) (e.g., TiN or Ru) and write word line metal layer WWL (AC) are formed to provide a stacked transistor memory cell 1001 with winged gates and isolated storage nodes as shown in Figure 1A.

[0075] Referring to FIG4, a cross-sectional view of another IC structure 2001 (Embodiment 2) is shown, including a 3x1 vertically stacked DRAM memory cell array, each memory cell including a read transistor RWL to a storage node SN voltage coupling region, having a surrounding RWL adjacent to the SN according to the embodiments disclosed herein.

[0076] Compared to the wing-shaped gate structure of Embodiment 1 1001, the read word lines RWL(A)', RWL(B)', and RWL(C)' surround or cover the first distal ends of the read transistor gate structures G(RTA), G(RTB)', and G(RTC), respectively, while the read bit lines RBL(A)', RBL(B)', and RBL(C)' are formed near the second distal ends of the read transistor gate structures G(RTA), G(RTB)', and G(RTC), respectively. In other words, the RBL and RWL regions are reversed relative to the RBL and RWL positions of Embodiment 1 1001. According to Embodiment 2 2001, the RWL to storage node SN voltage coupling region is formed by an overlapping area provided by the SN gate region adjacent to the read transistor surrounding the RWL. Compared to Embodiment 1 Similar to 1001, the physical characteristics of the overlapping area, such as the depth, width, length, and material of the RWL metal recess, are selected to provide the desired voltage coupling or coupling ratio of RWL(A)' to SN(A)', RWL(B)' ​​to SN(B)', and RWL(C)' to SN(C)' for operation of the 1x3 memory cell bit array as previously described with reference to Figures 1A-1E, 2A, and 2B. The manufacturing steps and stages of Example 2 2001 are similar to those previously described with reference to Figures 3A-3H, with appropriate modifications to recess the bottom metal read word lines during hole etching of the vertical read transistor, thereby providing a coupling ratio between the read word lines and the gate of the storage node.

[0077] Referring to FIG5, a method for forming an IC including a vertically stacked DRAM memory cell array according to an embodiment of the present disclosure is shown, wherein each memory cell includes a read transistor RWL to SN voltage coupling region having a winged gate.

[0078] In step 701, the method forms a read transistor structure, including a read bit line (RBL) metallization layer, a first intermetallic dielectric (IMD) region formed on the RBL, the RBL being at a first end of the IMD, a read word line (RWL) metallization layer formed at a second end of the IMD region relative to the first end, a first channel hole formed in the IMD and extending from the RBL metallization layer to the RWL metallization layer, a first field-effect transistor (FET) conductive channel layer extending from the RBL metallization layer to the RWL metallization layer, and a metal wing gate and storage node (SN) structure formed in the first channel hole on the conductive channel layer.

[0079] In step 702, the method forms a write transistor structure by vertically stacking on the read transistor structure SN metal layer. The write transistor includes a second IMD region formed on the SN metal layer, the SN metal layer at a first end of the second IMD, a second channel formed in the second IMD region and extending from the SN metal layer to a WBL metallization layer formed near a second end of the second IMD region, a field-effect transistor (FET) conductive channel layer extending from the SN metal layer to the WBL metallization layer formed near a second end of the second IMD region, and a gate structure formed on the conductive channel layer to a write word line (WWL) near a second end of the second IMD region.

[0080] Referring to FIG6, a method for forming an IC including a vertically stacked DRAM memory cell array according to an embodiment of the present disclosure is shown, wherein each memory cell includes a read transistor RWL to SN voltage coupling region covering the read transistor RWL.

[0081] In step 801, the method forms a read transistor structure, the read transistor structure including a read word line (RWL) metallization layer with a recessed portion, a first inter-metal dielectric (IMD) region formed on the RWL, the RWL being a first end of the first IMD region, a read bit line (RBL) metallization layer formed at a second end of the IMD region opposite to the first end, a first channel hole formed in the IMD and extending from the recessed portion of the RWL metallization layer to the length of the RBL metallization layer, a first field-effect transistor (FET) conductive channel layer extending from the recessed portion of the RWL metallization layer to the RBL metallization layer, and a metal gate and storage node (SN) structure formed in the first channel hole on the conductive channel layer, the gate and SN structure forming including a first end of the gate covered by the RWL recess, and the gate having an SN metal layer formed at a second end of the gate, wherein the SN metal layer is electrically isolated from any other memory cell.

[0082] In step 802, the method forms a write transistor structure by vertically stacking on the read transistor structure SN metal layer. The write transistor includes a first end of a second IMD region formed on the SN metal layer, a second channel formed in the second IMD region and extending from the SN metal layer to a WBL metallization layer formed near the second end of the second IMD region, a field-effect transistor (FET) conductive channel layer extending from the SN metal layer to the WBL metallization layer formed near the second end of the second IMD region, and a gate structure formed on the conductive channel layer to a write word line (WWL) near the second end of the second IMD region.

[0083] Based on the foregoing discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor are specific advantages required in all embodiments. One advantage is that the disclosed IC structures, devices, and methods of forming them provide transistor memory cells including RWL-SN voltage-coupled region structures, which in turn may improve the sensing window associated with memory arrays, such as DRAM.

[0084] Some further embodiments are described below.

[0085] In a non-limiting illustrative embodiment, a method of forming a stacked transistor memory cell includes: forming a read transistor structure in a substrate, the read transistor structure including a read bit line (RBL) metallization layer formed on the substrate, a first end of a first inter-metal dielectric (IMD) region formed on the RBL, a read word line (RWL) metallization layer formed at a second end of the IMD region opposite to the first end, a first channel hole formed in the IMD extending from the RBL metallization layer to the length of the RWL metallization layer, a first field-effect transistor (FET) conductive channel layer extending from the RBL metallization layer to the RWL metallization layer, and a metal wing gate and storage node (SN) structure formed in the first channel hole on the first FET conductive channel layer, the wing gate and SN structure forming a metal wing gate and storage node (SN) structure adjacent to the first FET conductive channel layer. The read transistor has a wing-shaped portion at the RWL end of the channel layer and substantially perpendicular to the channel length, and the wing-shaped gate has an SN metal layer formed thereon, which is electrically isolated from any other memory cell; and a write transistor structure is formed vertically stacked on the SN metal layer of the read transistor structure, the write transistor including a first end of a second IMD region formed on the SN metal layer, a second channel formed in the second IMD region and extending from the SN metal layer to a WBL metallization layer formed near the second end of the second IMD region, a second field-effect transistor (FET) conductive channel layer extending from the SN metal layer to the WBL metallization layer formed near the second end of the second IMD region, and a gate structure formed on the second FET conductive channel layer to a write word line (WWL) near the second end of the second IMD region.

[0086] In another non-limiting illustrative embodiment, a vertically stacked transistor device includes: a read transistor structure comprising: a read bit line (RBL) metallization layer formed on a substrate; a first end of a first inter-metal dielectric (IMD) region formed on the RBL; a read word line (RWL) metallization layer formed at a second end of the IMD region opposite to the first end; a first channel via formed in the IMD and extending from the RBL metallization layer to the length of the RWL metallization layer; a first field-effect transistor (FET) conductive channel layer extending from the RBL metallization layer to the RWL metallization layer; and a metal wing gate and storage node (SN) structure formed on the first FET conductive channel layer, the wing gate and SN structure including a portion adjacent to the RWL end of the conductive channel layer and substantially perpendicular to... The passage comprises a wing-shaped portion of the channel length, and a wing-shaped gate having an SN metal layer formed thereon, the SN metal layer being electrically isolated from any other memory cell; and a write transistor structure vertically stacked on the SN metal layer of the read transistor structure, the write transistor comprising: a first end of a second IMD region formed on the SN metal layer; a second channel formed in the second IMD region and extending from the SN metal layer to a WBL metallization layer formed near the second end of the second IMD region; a second field-effect transistor (FET) conductive channel layer extending from the SN metal layer to the WBL metallization layer formed near the second end of the second IMD region; and a gate structure formed on the second conductive channel layer to a write word line (WWL) near the second end of the second IMD region.

[0087] In another non-limiting illustrative embodiment, a method of forming a stacked transistor memory cell includes: forming a read transistor structure in a substrate, the read transistor structure including a read word line (RWL) metallization layer having a recessed portion formed on the substrate, a first end of a first inter-metal dielectric (IMD) region formed on the RWL, a read bit line (RBL) metallization layer formed at a second end of the IMD region opposite to the first end, forming a first channel hole in the IMD extending from the RWL metallization layer recessed portion to the length of the RBL metallization layer, a first field-effect transistor (FET) conductive channel layer extending from the RWL metallization layer recessed portion to the RBL metallization layer, and forming a metal gate and storage node (SN) structure in the first channel hole on the conductive channel layer, the gate and SN structure... The structure comprises a first end of a gate covered by an RWL recess, and a second end of the gate having a formed SN metal layer, the SN metal layer being electrically isolated from any other memory cell; and a vertically stacked write transistor structure formed on the SN metal layer of the read transistor structure, the write transistor comprising a first end of a second IMD region formed on the SN metal layer, a second channel formed in the second IMD region and extending from the SN metal layer to a length of a WBL metallization layer formed near the second end of the second IMD region, a second field-effect transistor (FET) conductive channel layer extending from the SN metal layer to the WBL metallization layer formed near the second end of the second IMD region, and a gate structure formed on the second FET conductive channel layer extending to a write word line (WWL) near the second end of the second IMD region.

[0088] The features of the above embodiments are intended to facilitate understanding of all aspects of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0089] 1001: Memory Cell 100A~100C: Reading transistor 104A~104C, 204A~204C: High-K dielectric layer 104A~104C, 204A~204C: Channel layer 105A~105C, 205A~205C: Conductive channel layer 110B, 1001A~1001C, 1001AA~1001CC, 1001AAA~1001CCC: Cell 2001: IC Structure 200A~200C: Write transistor 205A~205C: High K floor 300A1, 300A2: IMD area / floor 400A: Voltage Coupling Region 601, 602: Channel holes 701, 702, 801, 802: Steps G(RTA)~G(RTC), G(RTA)'~G(RTC)', G(WTA)~G(WTC): Gate RBL(A)~RBL(D), RBL(A)'~RBL(D)': Read bit lines RWL(A)~RWL(D), RWL(A)'~RWL(C)': Read character lines S / D(RTA)~S / D(RTD), S / D(WTA)~S / D(WTD): Source / Drain SN(A)~SN(C), SN(A)'~SN(C)': Storage nodes WBL(A)~WBL(D): Write bit lines WWL(A)~WWL(C): Write character lines

Claims

1. A method for forming stacked transistor memory cells, comprising: A read transistor structure is formed in a substrate, the read transistor structure comprising: a read bit line (RBL) metallization layer formed on the substrate; a first intermetallic dielectric (IMD) region formed on the RBL metallization layer, the RBL metallization layer at a first end of the first IMD region; a read word line (RWL) metallization layer formed at a second end of the first IMD region opposite to the first end; a first channel via formed in the first IMD region and extending from the RBL metallization layer to the RWL metallization layer; a conductive channel layer forming a first field-effect transistor (FET) extending from the RBL metallization layer to the RWL metallization layer; and a winged gate and a storage node formed in the first channel via and on the conductive channel layer. The read transistor structure includes a wing-shaped gate and the SN structure comprising a wing-shaped portion adjacent to the RWL end of the conductive channel layer and substantially perpendicular to the channel length of the conductive channel layer, and the wing-shaped gate having an SN metal layer formed thereon, the SN metal layer being electrically isolated from any other memory cell; and a write transistor structure formed by vertically stacking the read transistor structure and the SN metal layer, the write transistor comprising: a second IMD region formed on the SN metal layer at a first end of the second IMD region; a second channel formed in the second IMD region and extending from the SN metal layer to a write bit line (WBL) metallization layer formed near a second end of the second IMD region; a second field-effect transistor (FET) conductive channel layer formed from the SN metal layer to the WBL metallization layer formed near a second end of the second IMD region; and a gate structure formed on the second field-effect transistor (FET) conductive channel layer to a write word line (WWL) adjacent to the second end of the second IMD region. The RWL, the wing-shaped gate, and the SN structure are formed to provide a voltage coupler from the RWL metallization layer to the SN structure, and the associated voltage coupling ratio.

2. The method as described in claim 1 further includes: A high-k dielectric layer is formed between the wing-shaped gate and the first FET conductive channel layer.

3. The method described in claim 1 further includes: The voltage coupler is formed to provide the voltage coupling ratio determined by the overlap area of ​​the wing portion of the wing gate and the RWL metallization layer.

4. The method as described in claim 1 further includes: The first FET conductive channel layer is formed to follow the wing portion of the wing gate.

5. A stacked memory cell structure, comprising: A read transistor structure includes: a read bit line (RBL) metallization layer formed on a substrate; a first intermetallic dielectric (IMD) region formed on the RBL metallization layer, the RBL metallization layer being at a first end of the first IMD region; a read word line (RWL) metallization layer formed at a second end of the first IMD region opposite to the first end; a first channel via formed in the IMD region, extending from the RBL metallization layer to the RWL metallization layer; a first field-effect transistor (FET) conductive channel layer extending from the RBL metallization layer to the RWL metallization layer; and a metal wing gate and storage node formed on the first FET conductive channel layer. The read transistor structure includes a wing-shaped gate and the SN structure comprising a wing-shaped portion adjacent to the RWL end of the first FET conductive channel layer and substantially perpendicular to the length of the first FET conductive channel layer. The wing-shaped gate has an SN metal layer formed on the wing-shaped gate, the SN metal layer being electrically isolated from any other memory cell. The write transistor structure is vertically stacked on the SN metal layer of the read transistor structure, the write transistor structure comprising: a second IMD region formed on the SN metal layer, the SN metal layer being located at a first end of the second IMD region; a second channel formed in the second IMD region and extending from the SN metal layer to a write bit line (WBL) metallization layer formed near a second end of the second IMD region; a second field-effect transistor (FET) conductive channel layer formed extending from the SN metal layer to the WBL metallization layer, the second FET conductive channel layer being formed near the second end of the second IMD region of the WBL metallization layer; and a gate structure formed on the second FET conductive channel layer, extending to a write word line near the second end of the second IMD region. The RWL, the wing-shaped gate, and the SN structure are formed to provide a voltage coupler from the RWL metallization layer to the SN structure, and the associated voltage coupling ratio.

6. The structure as described in claim 5, further comprising: Multiple adjacent vertically stacked transistor devices on a single substrate.

7. The structure as described in claim 5, wherein the read transistor and the write transistor are MOSFET transistors, and the stacked memory cell structure is DRAM.

8. A method for forming stacked transistor memory cells, comprising: A read transistor structure is formed in a substrate, the read transistor structure comprising: a read word line (RWL) metallization layer having a recessed portion formed on the substrate; a first intermetallic dielectric (IMD) region formed on the RWL metallization layer, the RWL metallization layer at a first end of the first IMD region; a read bit line (RBL) metallization layer formed at a second end opposite to the first end of the IMD region; a first channel via formed in the IMD region and extending from the recessed portion of the RWL metallization layer to the RBL metallization layer; a conductive channel layer forming a first field-effect transistor (FET) extending from the recessed portion of the RWL metallization layer to the RBL metallization layer; and a metal gate and a storage node formed in the first channel via and on the conductive channel layer. The read transistor structure includes a metal gate and the SN structure formed to include a first end of the metal gate covered by the recessed portion of the RWL metallization layer, and the metal gate having an SN metal layer formed at a second end of the metal gate, wherein the SN metal layer is electrically isolated from any other memory cell; and a write transistor structure is formed by vertically stacking the read transistor structure and the SN metal layer, the write transistor including: a second IMD region formed on the SN metal layer, with the SN metal layer at the first end of the second IMD region; a second channel formed in the second IMD region and extending from the SN metal layer to a write bit line (WBL) metallization layer formed near a second end of the second IMD region; a second field-effect transistor (FET) conductive channel layer formed from the SN metal layer to the WBL metallization layer formed near the second end of the second IMD region; and a gate structure formed on the second FET conductive channel layer to the write word line (WWL) near the second end of the second IMD region. The RWL metallization layer, the metal gate, and the SN structure are formed to provide a voltage coupler from the RWL metallization layer to the SN structure, and the associated voltage coupling ratio.

9. The method of claim 8, wherein the overlapping area of ​​the first end of the metal gate covered by the recessed portion of the RWL metallization layer is formed to the voltage coupler from the RWL metallization layer to the SN structure, and the associated voltage coupling ratio.

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