Semiconductor structures and methods for forming the same

Abstract

The semiconductor structure for suppressing moisture-induced delamination can be provided by: forming an interposer layer including first redistribution interconnects embedded within a first redistribution dielectric layer; forming a plurality of die-side bump structures and a plurality of dummy bump structures on each of the first redistribution interconnects; and attaching at least one semiconductor die, which includes respective arrays of on-die bump structures and respective subsets of the die-side bump structures attached to the interposer layer. Due to the vertical gap between the dummy bump structures and the at least one semiconductor die, the dummy bump structures are not bonded to any of the at least one semiconductor die.

Description

Prior Technology

[0001] Redistributed structures and microbump structures are commonly used in advanced packaging technologies to interconnect various components within a semiconductor package. However, stress caused by moisture around redistributed dielectric structures and microbump structures can lead to peeling and cracking during thermal processing, impairing the reliability and yield of the semiconductor package. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a top view of a first carrier wafer according to an embodiment of the present disclosure. Figure 2 is a vertical cross-sectional view of a unit region of an intermediate structure including a first carrier wafer after attaching an interposer through-hole structure, according to an embodiment of the present disclosure. Figure 3 is a vertical cross-sectional view of an intermediate structure after attaching local silicon interconnect grains according to an embodiment of the present disclosure. Figure 4 is a schematic vertical cross-sectional view of a local silicon interconnect grain. Figure 5 is a vertical cross-sectional view of an intermediate structure after the formation of a first molding compound matrix, according to an embodiment of the present disclosure. Figure 6 is a vertical cross-sectional view of an intermediate structure after forming a first subset of the first redistributed conductor interconnects and a first subset of the first redistributed dielectric layer, according to an embodiment of the present disclosure. Figure 7 is a vertical cross-sectional view of an intermediate structure after forming a second subset of the first redistributed conductor interconnects and a second subset of the first redistributed dielectric layer, according to an embodiment of the present disclosure. Figure 8 is a vertical cross-sectional view of an intermediate structure after a separation opening is formed in the topmost first redistributed dielectric layer according to an embodiment of the present disclosure. Figure 9A is a vertical cross-sectional view of an intermediate structure after forming a grain-side bump structure, a virtual bump structure, a solder material portion, and a virtual solder material portion, according to an embodiment of the present disclosure. Figure 9B is a first example layout of a second subset of the first redistributed conductor interconnect, a grain-side bump structure, and a virtual bump structure according to an embodiment of the present disclosure. Figure 9C is a second example layout of a second subset of the first redistributed conductor interconnect, a grain-side bump structure, and a virtual bump structure according to an embodiment of the present disclosure. Figures 9D, 9E and 9F illustrate a plurality of components that can be used in a second subset of a first redistributed conductor interconnect according to an embodiment of the present disclosure. Figure 10A is a vertical cross-sectional view of an intermediate structure after a semiconductor die is attached to an interposer in each cell region, according to an embodiment of the present disclosure. Figure 10B is a top view of the unit region of the intermediate structure in Figure 10A. Figure 11 is a vertical cross-sectional view of the intermediate structure after the formation of the second molding compound matrix according to an embodiment of the present disclosure. Figure 12 is a vertical cross-sectional view of an intermediate structure after the second carrier wafer is attached to the redistribution wafer, according to an embodiment of the present disclosure. Figure 13 is a vertical cross-sectional view of the intermediate structure after separation of the first carrier wafer according to an embodiment of the present disclosure. Figure 14 is a vertical cross-sectional view of an intermediate structure after forming a second redistributed conductor interconnect embedded in a second redistributed dielectric layer, a substrate-side bump structure, and a substrate-side solder material portion, according to an embodiment of the present disclosure. Figure 15 is a vertical cross-sectional view of a composite package formed by separating a second carrier wafer from a redistribution wafer and cutting the redistribution wafer according to an embodiment of the present disclosure. Figure 16 is a vertical cross-sectional view of a semiconductor package formed by attaching a packaging substrate to a composite package according to an embodiment of the present disclosure. Figure 17 is a vertical cross-sectional view of a semiconductor structure formed by attaching a semiconductor package to a printed circuit board according to an embodiment of the present disclosure. Figure 18 is a first flowchart illustrating the steps of forming a semiconductor structure according to an embodiment of the present disclosure. Figure 19 is a second flowchart illustrating the steps of forming a semiconductor structure according to an embodiment of the present disclosure. Implementation

[0003] The following disclosure provides numerous different embodiments or examples for implementing various components in the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and not intended to be limiting. Illustrations are not drawn to scale. Components with the same reference numerals refer to the same component and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. All components of the original embodiments are assumed to exist in any derived embodiments unless explicitly disclosed otherwise. Therefore, components described in the illustrations and / or description with reference to related embodiments support components in the embodiments. Embodiments that repeat multiple instances of any described component are explicitly contemplated unless explicitly stated otherwise. Embodiments that omit non-essential components are explicitly contemplated, even if such embodiments are not explicitly disclosed but are well known to those skilled in the art.

[0004] Furthermore, for ease of explanation, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the geometric characteristics between the components shown in the illustrations. These spatially relative terms are intended to encompass not only the orientations depicted in the illustrations but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Unless otherwise expressly stated, each component with the same reference number is assumed to have the same material composition and a thickness within the same thickness range.

[0005] The embodiments disclosed herein relate to semiconductor structures, particularly semiconductor structures comprising an interposer and at least one semiconductor die. The interposer includes redistribution interconnects, die-side bump structures (also referred to as first bump structures), and dummy bump structures formed in a redistribution dielectric layer. The redistribution interconnects may include components for mitigating peeling, such as through holes, acute angles between line segments, fine line structures, or fine array structures. The redistribution dielectric layer may include additional components for mitigating peeling, such as vertically extending openings that may subsequently be filled with downwardly projecting portions of an underfill material. The die-side bump structures (also referred to as first bump structures) face at least one semiconductor die and can be used to provide solder-mediated bonding between the interposer and at least one semiconductor die. The dummy bump structures may be formed simultaneously with the die-side bump structures and mitigate the effects of moisture absorption by enhancing the mechanical stability of the interposer.

[0006] The redistribution dielectric layer typically comprises a polymeric material that enhances moisture absorption, while adjacent material portions, such as molded compound materials and / or underfill material layers, may be resistant to moisture absorption. Differences in moisture absorption tendency may provide a peeling mechanism at the interface between different types of materials. According to one aspect of this disclosure, a delamination-resistant redistribution layer pattern and a degassing-conducive structure can mitigate the risk of peeling or cracking at the material interface between the hygroscopic polymeric material and the moisture-absorbing polymeric and / or metallic material. In some embodiments, the underfill material may fill the openings in the upper layer of the redistribution dielectric layer. Virtual solder material portions provided on the virtual bump structure do not contact any semiconductor die. Various aspects of the embodiments disclosed herein are described with reference to the accompanying drawings.

[0007] Referring to Figure 1, a top view of the first carrier wafer 810 is shown. The first carrier wafer 810 can be any planar structure suitable for forming a reconfigurable wafer. For example, the first carrier wafer 810 may comprise a silicon wafer, a glass substrate, or any other suitable substrate with a flat top surface. The first carrier wafer 810 may comprise an optically transparent substrate such as a glass substrate or a sapphire substrate, or may comprise a semiconductor substrate such as a silicon substrate. The lateral dimensions (e.g., diameter) of the first carrier wafer 810 may range from 150 mm to 450 mm, although smaller and larger diameters may also be used. The thickness of the first carrier wafer 810 may range from 500 micrometers to 2,000 micrometers, although smaller and larger thicknesses may also be used. Alternatively, the first carrier wafer 810 may be provided in the form of a rectangular panel. The first carrier wafer 810 may be large enough to accommodate a two-dimensional array of unit areas UA.

[0008] Referring to FIG2, a unit region UA ​​comprising the intermediate structure of the first carrier wafer 810 is drawn along a vertical plane corresponding to the X-X' vertical plane in FIG1. ​​A first adhesive layer 811 may be applied to the front surface of the first carrier wafer 810. In one embodiment, the first adhesive layer 811 may be a light-to-heat conversion (LTHC) layer. Alternatively, the first adhesive layer 811 may comprise a thermally decomposable adhesive material.

[0009] Two-dimensional repeats of unit via assemblies can be formed on a first carrier wafer 810. Each example of a unit via assembly can be formed within a respective unit region UA ​​having a rectangular area. Multiple examples of unit via assemblies can be repeated along a first horizontal direction hd1 and along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The unit region UA ​​corresponds to the area of ​​the interposer grain to be formed subsequently. For example, each unit region UA ​​can have a rectangular shape, a first side length along the first horizontal direction hd1, and a second side length along the second horizontal direction hd2. The first side length can be the length of a pair of first sides of the rectangular shape. The second side length can be the length of a pair of second sides of the rectangular shape. The first side length is referred to herein as the first grain lateral dimension dld1. The second side length is referred to herein as the second grain lateral dimension dld2. Each of the first grain lateral dimension dld1 and the second grain lateral dimension dld2 can independently range from 800 micrometers to 6 centimeters, although smaller and larger dimensions can also be used.

[0010] Each example of a unit via assembly can be formed within a repeating respective unit region UA ​​and includes a set of corresponding through interposer via (TIV) structures 386. The TIV structure 386 can be a conductive via structure that provides vertical electrical connections within the interposer, i.e., includes an interposer with a redistributed structure providing a fan-out configuration, such that the bonding pads on one side of the interposer and the bonding pads on the other side of the interposer have different pitches.

[0011] In one embodiment, a sacrificial matrix layer (not shown) may be formed on the first adhesive layer 811. The sacrificial matrix layer comprises a sacrificial material (e.g., amorphous carbon), diamond-like carbon (DLC), a semiconductor material (e.g., amorphous silicon or silicon-germanium alloy), or a dielectric material (e.g., silicate glass or organosilicon glass). The thickness of the sacrificial matrix layer may range from 8 micrometers to 60 micrometers, although smaller and larger thicknesses are also possible. A photoresist layer (not shown) may be applied to the sacrificial matrix layer. The photoresist layer may be photolithographically patterned to form a plurality of openings that have the same pattern in top view as the TIV structure 386 to be subsequently formed. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer. A cylindrical cavity may be formed in the sacrificial matrix layer below the openings in the photoresist layer. The photoresist layer may be removed, for example, by ashing. At least one conductive material, such as at least one metallic material, may be deposited in the cylindrical cavity. For example, at least one conductive material may comprise a conductive metallic barrier material (e.g., TiN, TaN, WN, or MoN) and a metallic filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). Excess portions of the at least one conductive material can be removed from above the horizontal plate containing the sacrificial matrix layer. The remaining portion of the at least one conductive material filling the cylindrical cavity comprises the TIV structure 386. Subsequently, the sacrificial matrix layer can be selectively removed relative to the TIV structure 386.

[0012] In another embodiment, at least one conductive material layer may be deposited as a single, unpatterned material layer of uniform thickness. For example, the at least one conductive material layer may comprise a conductive metal barrier material (e.g., TiN, TaN, WN, or MoN) and a metal filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). The thickness of the at least one conductive material layer may range from 8 micrometers to 60 micrometers, although smaller and larger thicknesses are also possible. A photoresist layer (not shown) may be applied to the at least one conductive material layer. The photoresist layer may be photolithographically patterned to form discrete photoresist portions that have the same pattern in top view as the TIV structure 386 to be subsequently formed. An anisotropic etching process may be performed to transfer the pattern of the discrete photoresist portions to the at least one conductive material layer. The patterned portions of the at least one conductive material layer comprise the TIV structure 386.

[0013] Alternatively, a pick-and-place tool can be used to place the TIV structure 386 onto the first adhesive layer 811. In one embodiment, multiple TIV structures 386, and / or an entire group of TIV structures 386 within a unit region UA, can be simultaneously transferred onto the first carrier wafer 810.

[0014] In another alternative embodiment, the TIV structure 386 may be formed on another carrier wafer and may be attached to the top surface of the first adhesive layer 811. The TIV structure 386 may then be detached from the additional carrier wafer.

[0015] Figure 3 is a vertical cross-sectional view of the intermediate structure after attaching a local silicon interconnect (LSI) bridge 305 according to an embodiment of the present disclosure. Figure 4 is a schematic vertical cross-sectional view of the LSI bridge 305. Referring to Figures 3 and 4, a plurality of LSI bridges 305 may be attached to a first carrier wafer 810. Each LSI bridge 305 includes a silicon substrate 310 (thinned and diced during the fabrication of the LSI bridge 305), a silicon through-hole structure 314 extending vertically through the silicon substrate 310, a through-substrate opening extending vertically through the silicon substrate 310, a dielectric liner 312 providing electrical isolation for the silicon through-hole structure 314, a back-side dielectric material layer 320, and a metal interconnect structure 380 embedded in the dielectric material layer 360 and electrically connected to the silicon through-hole structure 314 and / or electrically connected to each other. A metal pad (referred to herein as LSI metal pad 388) may be disposed on the topmost metal interconnect structure 380.

[0016] LSI bridge 305 can be placed in an opening in the TIV structure 386 array on the top surface of the first adhesive layer 811. Generally, at least one LSI bridge 305 can be placed in each cell region UA ​​using a pick-and-place tool. At least one local silicon interconnect (LSI) bridge 305 can be placed in each repeating cell region UA ​​using a pick-and-place tool. In one embodiment, multiple LSI bridges 305 can be placed in each repeating cell region UA ​​using a pick-and-place tool.

[0017] Referring to Figure 5, an encapsulation, such as a molding compound (MC), can be applied to the gap within the assembly of the LSI bridge 305 and the TIV structure 386. The molding compound comprises an epoxy-containing compound that can be cured (i.e., hardened) to provide a dielectric portion with sufficient hardness and mechanical strength. The molding compound may include epoxy resin, hardener, silica (as a filler material), and other additives. The molding compound can be provided in liquid or solid form depending on viscosity and flowability. Liquid molding compounds typically offer better handling, good flowability, fewer voids, better filling, and fewer flow marks. Solid molding compounds typically offer less curing shrinkage, better stand-off distance, and less die drift. High filler content (e.g., 85% by weight) in the molding compound can shorten mold time, reduce mold shrinkage, and reduce mold warpage. Uniform filler size distribution in the molding compound can reduce flow marks and enhance flowability.

[0018] The molding compound can be cured at a curing temperature to form a molding compound matrix, referred to herein as the first molding compound matrix 370L or interposer-level molding compound (MC) matrix. The first molding compound matrix 370L laterally surrounds each LSI bridge 305 and TIV structure 386. The first molding compound matrix 370L may be a continuous material layer extending across the entire region of the reconstructed wafer overlaid on the first carrier wafer 810.

[0019] Subsequently, an excess portion of the first molding compound matrix 370L above the horizontal plane containing the top surface of the LSI bridge 305 and the TIV structure 386 can be removed using a planarization process, which may employ chemical mechanical planarization (CMP). This planarization process can expose the surface of the silicon perforated structure 314 in the solid. The top surface of the remaining portion of the first molding compound matrix 370L may lie within the horizontal plane containing the top surface of the LSI bridge 305 and the TIV structure 386.

[0020] The first molding compound matrix 370L includes a plurality of molding compound (MC) interposer frames located within their respective cell regions UA and laterally adjacent to each other. Each MC interposer frame corresponds to a portion of the first molding compound matrix 370L within the cell region UA, i.e., the region of the single interposer layer to be subsequently formed. Each MC interposer frame laterally surrounds a corresponding set of at least one LSI bridge 305 and a corresponding array of TIV structures 386. A bridge-level interposer layer 300 can be formed.

[0021] Subsequently, first redistributed conductor interconnects 480 in the first redistributed dielectric layer 460 can be formed. Figure 6 is a vertical cross-sectional view of the intermediate structure after forming the first subset of the first redistributed conductor interconnects 480 and the first subset of the first redistributed dielectric layer 460. The total number of metal wire layers of the first redistributed conductor interconnects 480 can be in the range of 1 to 10, for example, 1 to 4. Although this disclosure describes an embodiment with a total number of metal wire layers of 1, embodiments using two or more metal wire layers as the first redistributed conductor interconnects 480 are explicitly contemplated herein.

[0022] The first redistribution dielectric layer 460 comprises a respective dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Each first redistribution dielectric layer 460 can be formed by spin-coating and drying the respective dielectric polymer material. The thickness of each first redistribution dielectric layer 460 can range from 2 micrometers to 30 micrometers, for example, 3 micrometers to 20 micrometers. Each first redistribution dielectric layer 460 can be patterned, for example, by applying and patterning a respective photoresist layer thereon, and transferring the pattern in the photoresist layer into the first redistribution dielectric layer 460 using an etching process (e.g., anisotropic etching process). The photoresist layer can then be removed, for example, by ashing.

[0023] Each first redistribution interconnect 480 may be formed by sputtering a metal seed layer, applying and patterning a photoresist layer on the metal seed layer to form an opening pattern through the photoresist layer, electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between portions of the electroplated metal filler material. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may range from 40 nm to 800 nm, and the thickness of the copper seed layer may range from 100 nm to 400 nm. The metal filler material of the first redistribution interconnect 480 may include copper, nickel, or copper and nickel. The thickness of the metal filler material deposited on each first redistribution interconnect 480 may range from 2 μm to 30 μm, for example, 3 μm to 10 μm, although smaller or larger thicknesses may also be used.

[0024] A first subset of the first redistributed conductor interconnects 480 may include all first redistributed conductor interconnects 480 except for the topmost first redistributed conductor interconnect 480. In one embodiment, the first subset of the first redistributed conductor interconnects 480 may include a metal via structure 482, a metal wire structure 484, and a virtual metal wire structure 484D. The metal via structure 482 provides a vertically extending conductive path, the metal wire structure 484 provides a horizontally extending conductive path, and the virtual metal wire structure 484D is electrically floating and therefore does not provide any conductive path.

[0025] According to one aspect of this disclosure, a first subset of the first redistributed conductor interconnect 480 may include components for increasing mechanical stability and adhesion. For example, a virtual metal wire structure 484D may be positioned in a manner that increases the contact area between the first redistributed conductor interconnect 480 and the first redistributed dielectric layer 460. Furthermore, the metal wire structure 484 may have a layout that enhances adhesion between the first redistributed conductor interconnect 480 and the first redistributed dielectric layer 460. In one embodiment, a subset of the first redistributed conductor interconnect 480 may form at least one component for enhancing adhesion. For example, at least one component may include one or more of the following: a first component comprising a plurality of interconnected metal segments such that adjacent pairs of segments have different horizontal propagation directions, these directions being separated by an acute angle; a second component comprising a one-dimensional array of a plurality of straight metal lines having a uniform width less than the width of each grain-side bump structure 488 and having uniform spacing less than the width of each grain-side bump structure 488 (i.e., the first bump structure 488); and a third component comprising a two-dimensional array of a plurality of metal pads, each metal pad having a width not greater than 250% of the width of each grain-side bump structure 488 and a length not greater than 250% of the width of each grain-side bump structure 488.

[0026] In one embodiment, a subset of the first redistributed conductor interconnect 480 may include vertically extending vias 485. For example, a subset of the metal wire structure 484 may have vias 485 extending therethrough. The vias 485 may contain voids (i.e., volumes not filled with any solid or liquid phase material) or may be filled by corresponding portions of the first redistributed dielectric layer 460.

[0027] Referring to FIG7, a second subset of the first redistribution interconnect 480 and a topmost first redistribution dielectric layer 460 may be formed. The second subset of the first redistribution interconnect 480 includes the topmost first redistribution interconnect 480. In one embodiment, the topmost first redistribution interconnect 480 may include a metal via structure closest to the semiconductor die when subsequently bonding the semiconductor die to the interposer. Therefore, the topmost first redistribution interconnect 480 is referred to herein as a proximal metal via structure 486. A first subset of the proximal metal via structure 486 may be formed on a respective metal line structure 484, and a second subset of the proximal metal via structure 486 may be formed on a respective virtual metal line structure 484D. The top surface of the proximal metal via structure 486 may be coplanar with the topmost surface of the first redistribution dielectric layer 460.

[0028] In one embodiment, a subset of the first redistributed conductor interconnects 480 includes vertically extending vias 485 therein. In this embodiment, the vertically extending vias 485 may be filled with the dielectric material of the first redistributed dielectric layer 460 (e.g., the topmost first redistributed dielectric layer 460). A first redistribution structure 400 may be formed within each cell region UA. Each first redistribution structure 400 includes first redistributed conductor interconnects 480 embedded in the first redistributed dielectric layer 460. Each combination of the grain-level interposer 300 and the first redistribution structure 400 within the cell region UA ​​constitutes an interposer (300, 400). A reconstructed wafer including a two-dimensional array of interposers (300, 400) may be formed on the first carrier wafer 810.

[0029] Referring to Figure 8, a topographical element can be formed to enhance the adhesion between the first redistributed dielectric layer 460 and the subsequently formed moisture-proof material. For example, a photoresist layer (not shown) can be applied to the first redistributed dielectric layer 460, and photolithography can be performed in the area covering segments of the metal wire structure 484 and the virtual metal wire structure 484D. An anisotropic etching process can be performed to form an opening 461 in the topmost first redistributed dielectric layer 460. The opening 461 extends vertically downward from the topmost surface of the first redistributed dielectric layer 460 to substantially expose the top surface segments of a subset of the first redistributed conductor interconnects 480 below the opening 461. The top surface segments of the metal wire structure 484 and the virtual metal wire structure 484D can be substantially exposed below the opening 461 through the topmost first redistributed dielectric layer 460. The photoresist layer can then be removed, for example, by ashing. A degassing process, such as annealing in an anhydrous environment, can be performed to remove moisture from the first redistributed dielectric layer 460. In this embodiment, the opening 461 in the topmost first redistributed dielectric layer 460 and the aperture 485 in the metal wire structure 484 can be used as an outgassing path during the degassing process.

[0030] Figure 9A is a vertical cross-sectional view of the intermediate structure after forming the grain-side bump structure 488, the virtual bump structure 488D, the solder material portion 192, and the virtual solder material portion 192D according to an embodiment of the present disclosure. Figure 9B is a first example layout of the second subset of the first redistributed conductor interconnect 480, the grain-side bump structure 488, and the virtual bump structure 488D according to an embodiment of the present disclosure. Figure 9C is a second example layout of the second subset of the first redistributed conductor interconnect 480, the grain-side bump structure 488, and the virtual bump structure 488D according to an embodiment of the present disclosure. Figures 9D, 9E, and 9F illustrate components that can be used for the second subset of the first redistributed conductor interconnect 480 according to an embodiment of the present disclosure.

[0031] Referring to Figures 9A to 9F, a grain-side bump structure 488 and a virtual bump structure 488D may be formed on the topmost subset of the first redistributed conductor interconnect 480, such as a near-end metallized via structure 486. In an illustrative example, an under-bump metallization (UBM) layer (not shown) may be deposited on the near-end metallized via structure 486 and the first redistributed dielectric layer 460. The UBM layer may comprise a stack of at least one adhesive layer and a metal seed layer, which serves as a template to initiate subsequent electroplating processes. In embodiments where an opening 461 exists in the topmost first redistributed dielectric layer 460, the UBM layer may be deposited in the peripheral region of the opening 461. For example, the UBM layer may comprise a stack of layers from bottom to top, including a titanium layer, a titanium nitride layer, a copper seed layer, and a nickel layer. The nickel layer may function as a barrier layer to prevent copper from diffusing into the solder material, thereby enhancing the long-term reliability of the bump structure.

[0032] A photoresist layer (not shown) can be deposited on the UBM layer, and openings can be formed in the region of the near-end metal via structure 486 by photolithography. In one embodiment, an opening through the photoresist layer can be formed on each near-end metal via structure 486. An electroplating process can then be performed to deposit an electroplatable material (e.g., copper) within the opening of the photoresist layer. Copper pillar structures are electroplated within the opening of the photoresist layer. The lateral dimension of each copper pillar structure can range from 5 micrometers to 50 micrometers. The height of each copper pillar structure can range from 10 micrometers to 40 micrometers. In one embodiment, the copper pillar structure can be formed as a microbump structure. The photoresist layer can then be removed, for example by ashing. Unmasked portions of the UBM layer (portions not covered by the copper pillar structures) can then be removed by performing an etching process, which can include an isotropic etching process, such as a wet etching process. The remaining continuous combination of the respective patterned portions of the UBM layer and the respective copper pillar structures includes a grain-side bump structure 488 (i.e., a bump structure facing the semiconductor grain for bonding) and a virtual bump structure 488D.

[0033] A grain-side bump structure 488 and a virtual bump structure 488D are formed on each of the first redistributed conductor interconnects 480, for example, on each of the near-end metal via structures 486. If the opening 461 extends vertically through the topmost first redistributed dielectric layer 460, and the grain-side bump structure 488 is formed above the opening 461 in the topmost first redistributed dielectric layer 460, the top surface segment of a subset of the first redistributed conductor interconnects 480 is exposed.

[0034] The grain-side bump structure 488 and the virtual bump structure 488D can be formed using the same set of material deposition and patterning processes, and therefore can have the same material composition and the same vertical extent. The difference between the grain-side bump structure 488 and the virtual bump structure 488D is that the grain-side bump structure 488 subsequently serves as a bonding structure for attaching semiconductor dies, while the virtual bump structure 488D does not serve as a bonding structure. Therefore, the virtual bump structure 488D is subsequently not used to provide a conductive path to any semiconductor die. In one embodiment, the grain-side bump structure 488 can be formed as a periodic array, and the virtual bump structures 488D can be located between respective adjacent pairs of the grain-side bump structures 488.

[0035] According to one aspect of this disclosure, a first subset of virtual bump structures 488D may be formed such that each virtual bump structure 488D in the first subset of virtual bump structures 488D is electrically connected to a respective grain-side bump structure 488 selected from the grain-side bump structures 488 of each interposer layer (300, 400). For example, each virtual bump structure 488D in the first subset of virtual bump structures 488D may be formed on a respective near-end via structure 486, which contacts a respective metal wire structure 484, which contacts the bottom surface of another near-end via structure 486, which in turn contacts the bottom surface of the grain-side bump structure 488. In one embodiment, a second subset of virtual bump structures 488D may be formed such that each virtual bump structure 488D in the second subset of virtual bump structures 488D is electrically disconnected from each grain-side bump structure 488. For example, each virtual bump structure 488D in the second subset of virtual bump structures 488D may be formed on its respective near-end metal via structure 486, which contacts its respective dummy metal wire structure 484D, which does not contact any other first redistributed conductor interconnect 480 except its respective near-end metal via structure 486.

[0036] Subsequently, solder material portion 192 and virtual solder material portion 192D can be formed. Specifically, solder material portion 192 can be attached to die-side bump structure 488, and virtual solder material portion 192D can be attached to virtual bump structure 488D. In one embodiment, solder material portion 192 and virtual solder material portion 192D can be deposited by screen printing solder paste onto die-side bump structure 488 and virtual bump structure 488D. Alternatively, solder material portion 192 and virtual solder material portion 192D can be configured by placing pre-made solder balls on top of die-side bump structure 488 and virtual bump structure 488D. Solder material portion 192 and virtual solder material portion 192D may comprise lead-free alloys, such as tin-silver-copper alloys.

[0037] A reflow process can be performed to heat the intermediate structure, which includes a first carrier wafer 810, a bridging-level interposer 300, and a first redistribution structure 400, to the reflow temperature. During solder material reflow, solder material portion 192 is attached to the grain-side bump structure 488, and virtual solder material portion 192D is attached to the virtual bump structure 488D.

[0038] In one embodiment, a subset of the first redistributed conductor interconnects 480 may form at least one component selected from the following: a first component comprising a plurality of interconnecting metal segments such that adjacent pairs of segments have different horizontal propagation directions, these directions differing by an acute angle α (as shown in FIG. 9D); a second component comprising a one-dimensional array of a plurality of straight metal lines having a uniform width smaller than the width of each grain-side bump structure 488 and a uniform spacing smaller than the width of each grain-side bump structure 488 (as shown in FIG. 9E); and a third component comprising a two-dimensional array of a plurality of metal pads, each metal pad having a width not greater than 250% of the width of each grain-side bump structure 488 and a length not greater than 250% of the width of each grain-side bump structure 488 (as shown in FIG. 9F). In one embodiment, the width of each grain-side bump structure 488 may be in the range of 5 micrometers to 50 micrometers, for example from 10 micrometers to 40 micrometers (e.g., 20 micrometers), although smaller and larger widths may also be used.

[0039] Figures 9B and 9C illustrate the layout of the metal wire structure 484, the grain-side bump structure 488, and the virtual bump structure 488D. Figure 9B illustrates the vertically extending holes 485 in the metal wire structure 484. The metal wire structure 484 illustrated in Figure 9C includes components described with reference to Figures 9D and 9E.

[0040] Referring to Figures 10A and 10B, a group of at least one semiconductor die 100 can be bonded to a respective group of die-side bump structures 488 within each unit area UA. Each group of at least one semiconductor die 100 includes at least one semiconductor die 100, and may include multiple semiconductor dies 100. In one embodiment, each group of at least one semiconductor die 100 may include at least one processor die 101 and / or at least one memory die 102. Each processor die 101 may include at least one central processing unit (CPU), at least one graphics processing unit (GPU), at least one neural processing unit (NPU), and / or at least one digital signal processor (DSP). In one embodiment, at least one processor die 101 may include a system-on-a-chip (SoC) die, such as an application processor die. In one embodiment, at least one memory die 102 may include high-bandwidth memory (HBM) dies, which include a vertical stack of static random access memory dies. Each HBM die may contain a vertically stacked static random access memory (SRAM) die, which are interconnected by an array of microbumps and are laterally surrounded by their respective molded material shell frames.

[0041] Each semiconductor die 100 may include its own array of on-die bump structures 188 (i.e., second bump structures 188). Each semiconductor die 100 may be positioned face-down such that the on-die bump structures 188 face the solder material portion 192. The placement of the semiconductor dies 100 may be performed using a pick-and-place device such that each of the on-die bump structures 188 faces a corresponding one of the solder material portions 192. At least one semiconductor die 100 in each group may be placed within its respective cell region.

[0042] In one embodiment, the on-die bump structure 188 and the grain-side bump structure 488 can be configured for microbump bonding. In this embodiment, each of the on-die bump structure 188 and the grain-side bump structure 488 can be configured as a copper pillar structure having a diameter ranging from 10 micrometers to 50 micrometers and a corresponding height ranging from 10 micrometers to 40 micrometers. The spacing of the microbumps in the periodic direction can range from 20 micrometers to 100 micrometers, but smaller or larger spacing can also be used. During reflow, the solder material portion 192 provides solder-mediated bonding between vertically adjacent pairs of on-die bump structures 188 and grain-side bump structures 488.

[0043] Generally, in each cell region UA, at least one semiconductor die 100, comprising a respective array of on-die bump structures 188, may be attached to a corresponding subset of the die-side bump structures 488 of the interposer (300, 400). In one embodiment, at least one semiconductor die 100 is attached to the interposer (300, 400) using at least one array of solder material portions 192. According to one embodiment, a virtual bump structure 488D is not bonded to any of the at least one semiconductor die 100. In one embodiment, each of the at least one semiconductor die 100 comprises a respective array of on-die bump structures 188 that is bonded to a corresponding subset of the die-side bump structures 488 of the interposer (300, 400) when at least one semiconductor die 100 is attached to the interposer (300, 400).

[0044] Within each cell region UA, an assembly of an interposer layer (300, 400) and at least one semiconductor die 100 may be formed. The interposer layer (300, 400) includes first redistribution interconnects 480 embedded in a first redistribution dielectric layer 460, and die-side bump structures 488 and virtual bump structures 488D contacting corresponding ones of the first redistribution interconnects 480. Each of the at least one semiconductor die 100 includes a respective array of on-die bump structures 188, which is bonded to a corresponding subset of the die-side bump structures 488 via a corresponding array of solder material portions 192. The virtual bump structures 488D are not bonded to any of the at least one semiconductor die 100. Generally, due to the lack of any covered on-die bump structures 188, the virtual bump structures 488D do not contact any of the at least one semiconductor die 100. Therefore, a vertical gap exists between each virtual bump structure 488D and at least one semiconductor die 100. The height of each vertical gap can be on the order of 188 times the thickness of the bump structure on the grain.

[0045] In one embodiment, each virtual bump structure 488D may be contacted by a respective virtual solder material portion 192D. In one embodiment, the virtual solder material portion 192D does not directly contact any of at least one of the semiconductor dies 100. Therefore, a gap exists between each virtual solder material portion 192D and the bottom surface of the semiconductor die 100 covering it. In one embodiment, in a planar view within each cell region UA ​​(as shown in FIG. 10B), the entire virtual bump structure 488D overlaps in area with at least one semiconductor die 100. In one embodiment, the top surface of the first redistribution dielectric layer 460 includes recesses (i.e., openings 461) that extend vertically through the topmost first redistribution dielectric layer 460 selected from the first redistribution dielectric layers 460.

[0046] Generally, after at least one semiconductor die 100 is attached to the interposer (300, 400), the virtual bump structure 488D is not bonded to any of the at least one semiconductor die 100. The on-die bump structure 188 is bonded to the die-side bump structure 488 via solder material portions 192. In each cell region UA, after at least one semiconductor die 100 is bonded to the interposer (300, 400), the virtual bump structure 488D does not contact at least one semiconductor die 100.

[0047] Referring to FIG11, a first underfill material (also referred to as a dielectric layer) may be applied to each gap between the interposer (300, 400) and at least one semiconductor die 100 of a corresponding group. The first underfill material may include any underfill material known to those skilled in the art. The first underfill material may be applied within each cell region UA, surrounding solder material portion 192 and dummy solder material portion 192D, between the interposer (300, 400) and the semiconductor die 100. The underfill material portion 195 may be formed by implanting material around the solder material portion 192 and the dummy solder material portion 192D. Any known underfill material application method may be used, such as capillary underfill method, molding underfill method, or printing underfill method.

[0048] Therefore, an underfill material portion 195 can be formed between the interposer (300, 400) within each cell region UA ​​and at least one semiconductor die 100 of a corresponding set. At least one semiconductor die 100, including a corresponding set of on-die bump structures 188, is attached to the interposer (300, 400) via a corresponding set of solder material portions 192. The underfill material portion 195 can laterally surround and contact all solder material portions 192 and dummy solder material portions 192D within the cell region UA. The underfill material portion 195 can contact the solder material portions 192, the die-side bump structures 488, the dummy bump structures 488D, and the on-die bump structures 188. In one embodiment, all surfaces of the dummy solder material portion 192D can be contacted by a combination of the underfill material portion 195 and the dummy bump structures 488D.

[0049] In one embodiment, the bottom filler portion 195 fills the opening 461 extending downward from the topmost surface of the first redistribution dielectric layer 460. In this embodiment, the bottom filler portion 195 may include a downward protrusion 195P that fills a recess on the top surface of the first redistribution dielectric layer 460 (i.e., through the opening 461 of the topmost first redistribution dielectric layer 460). In each cell region UA, each solder material portion 192 and each dummy solder material portion 192D are laterally surrounded and contacted by the bottom filler portion 195.

[0050] A second molding compound (MC) can be applied to the gap between a corresponding set of semiconductor die 100 and a corresponding underfill material portion 195. The second MC may include any material that can be used in the first molding compound matrix 370L described above. The second MC may include epoxy resin, hardener, silica (as a filler material), and other additives. The second MC can be cured at a curing temperature to form a molding compound matrix, referred herein as a grain-level molding compound matrix or the second molding compound matrix 170L. The second molding compound matrix 170L laterally surrounds and fits into each combination of a set of semiconductor die 100 and underfill material portion 195. The second molding compound matrix 170L includes a plurality of molding compound (MC) die frames that may laterally abut each other. Each MC die frame is a portion of the second molding compound matrix 170L located within a corresponding cell region UA. Thus, each MC die frame laterally surrounds and fits into a corresponding set of semiconductor die 100 and a corresponding underfill material portion 195. The Young's modulus of pure epoxy resin is approximately 8.35 gigapascals (GPa), and the Young's modulus of MC may be higher than that of pure epoxy resin due to the additives contained therein. Therefore, the Young's modulus of the second molding compound matrix 170L can be greater than 8.5 gigapascals.

[0051] A portion of the second molding compound matrix 170L covering the horizontal surface including the top surface of the semiconductor die 100 can be removed using a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the second molding compound matrix 170L covering the horizontal surface. The reconstructed wafer covering the first carrier wafer 810 includes a combination of the second molding compound matrix 170L, the semiconductor die 100, the underfill material portion 195, and a two-dimensional array of interposers (300, 400). Each portion of the second molding compound matrix 170L located within a unit region UA ​​constitutes the MC die framework.

[0052] Referring to Figure 12, a second adhesive layer 821 may be applied to the second molding compound matrix 170L. Depending on the removal mechanism to be used subsequently, the second adhesive layer 821 may include a photothermal conversion (LTHC) layer or a thermally decomposable adhesive layer. The second carrier wafer 820 may be attached to the second molding compound matrix 170L and the semiconductor die 100 via the second adhesive layer 821. The second carrier wafer 820 may contain any material that can be used with the first carrier wafer 810 and may typically have a thickness range substantially the same as that of the first carrier wafer 810.

[0053] Referring to FIG13, the first carrier wafer 810 can be self-reconstructed wafer separated. In some embodiments, the first carrier wafer 810 and the first adhesive layer 811 can be removed by back-side grinding. Optionally, at least one selective etching process (e.g., wet etching or reactive ion etching) can be employed in conjunction with the back-side grinding process to minimize incidental removal of surface portions of the LSI bridge 305 and the TIV structure 386. Alternatively or additionally, in embodiments where the first carrier wafer 810 comprises an optically transparent material and the first adhesive layer 811 comprises a photothermal conversion material, the first carrier wafer 810 can be separated using irradiation through the first carrier wafer 810. In embodiments where the first adhesive layer 811 comprises a thermally decomposable adhesive material, the first carrier wafer 810 can be separated using an annealing process or laser irradiation. A suitable cleaning process can be performed to remove any remaining portions of the first adhesive layer 811.

[0054] Referring to FIG14, a second redistribution layer structure 500 can be formed on the two-dimensional repeating solid exposed side of the interposer layers (300, 400) within each unit region UA. The second redistribution layer structure 500 includes second redistribution conductor interconnects 580, a second redistribution dielectric layer 560, and a substrate-side bonding structure 588. Generally, the second redistribution layer structure 500 can be formed in the same manner as the first redistribution structure 400, with appropriate modifications to the lithography pattern and / or the thickness and material composition of the material layers. The substrate-side bonding structure 588 can be formed as a bonding pad configured for controlled collapse chip connection (C4) bonding. A solder material portion 592 (also referred to as a substrate-side solder material portion) can be attached to the substrate-side bonding structure 588. If the substrate-side bonding structure 588 is formed as a C4 bonding pad, the solder material portion 592 can be formed as a C4 solder ball. The second redistribution layer structure 500 within each unit region UA ​​is incorporated into the intermediary layers (300, 400) within their respective unit regions UA to provide a composite intermediary layer 600. Each composite intermediary layer 600 includes a bridge-level intermediary layer 300, a first redistribution structure 400, and a second redistribution layer structure 500.

[0055] Referring to Figure 15, the second carrier wafer 820 can be separated from the reconstructed wafer. In embodiments where the second carrier wafer 820 comprises an optically transparent material and the second adhesive layer 821 comprises a photothermal conversion material, the second carrier wafer 820 can be separated using irradiation through it. In embodiments where the second adhesive layer 821 comprises a thermally decomposable adhesive material, the second carrier wafer 820 can be separated using an annealing process or laser irradiation. A suitable cleaning process can be performed to remove any remaining portions of the second adhesive layer 821. The horizontal surface of the second molding compound matrix 170L can be physically exposed. A reconstructed wafer unattached to any carrier wafer can be obtained.

[0056] The reconstructed wafer includes a two-dimensional array of composite interposers 600 and further includes a two-dimensional array of at least one group of semiconductor dies 100 bonded to their respective composite interposers 600. The reconstructed wafer can be diced along dicing channels (corresponding to boundaries between adjacent cell regions UA) by performing a dicing process. Each cell diced from the reconstructed wafer includes a composite package 800, which may be a fan-out package providing fan-out connectivity. Each diced portion of the second molding compound matrix 170L constitutes a die-level molding compound frame 170. Each diced portion of the first molding compound matrix 370L constitutes an interposer-level molding compound frame 370.

[0057] The diced portion of the reconstructed wafer includes a composite package 800. Each composite package 800 includes at least one array of a semiconductor die 100, a composite interposer 600, an underfill material portion 195, a die-level molded compound framework 170, and a solder material portion 192. Each composite interposer 600 includes a bridging-level interposer 300, a first redistribution structure 400, and a second redistribution structure 500.

[0058] Referring to Figure 16, a packaging substrate 200 may be provided. The packaging substrate 200 may be a cored packaging substrate including a core substrate, or a coreless packaging substrate excluding a packaging core. Alternatively, the packaging substrate 200 may include a system-on-integrated packaging substrate (SoIS) comprising a redistribution layer, a dielectric interlayer, and / or at least one embedded interposer (e.g., a silicon interposer). Such a system-on-integrated packaging substrate may include layer-to-layer interconnects using solder material portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. It should be understood that the scope of this disclosure is not limited to any particular type of substrate packaging. For example, SoIS may be used instead of a cored packaging substrate. In embodiments using SoIS, the core substrate may include a glass epoxy board with an array of through-holes.

[0059] In one embodiment, the package substrate 200 may include a substrate redistribution dielectric layer 260 in which substrate redistribution conductor interconnects 280 are formed. In one embodiment, the package substrate 200 may include board-side surface laminate (SLC) and chip-side SLC. A package-side bonding pad array 238 may be provided on the package substrate 200 side facing the composite package 800. A board-side bonding pad array 288 may be formed on the side of the package substrate 200 that is subsequently connected to a printed circuit board. The board-side bonding pad array 288 may be configured to allow bonding via solder contacts having a size larger than C4 solder balls.

[0060] The composite package 800 can be attached to the package substrate 200 using an array of solder balls 592. Specifically, each solder ball 592 can be bonded to its respective board-side bonding structure 588 and its respective package-side bonding pad 238. A reflow process can be performed during the bonding process to reflow the solder balls 592.

[0061] An underfill material may be applied to the gap between the composite package 800 and the package substrate 200. The underfill material may include any underfill material known to those skilled in the art. An underfill material portion may be formed in the gap between the composite package 800 and the package substrate 200, around the array of solder balls 592. This underfill material portion formed between the composite package 800 and the package substrate 200 is therefore referred to herein as interposer-package (IP) underfill material portion 295, or IP underfill material portion 295.

[0062] Referring to FIG17, a printed circuit board (PCB) 900 including a PCB substrate 910 and PCB bonding pads 938 is provided. The PCB 900 includes printed circuitry (not shown) located on at least one side of the PCB substrate 910. An array of solder contacts 992 can be formed to bond an array of board-side bonding pads 288 to the array of PCB bonding pads 938. The solder contacts 992 can be formed by arranging an array of solder balls between the array of board-side bonding pads 288 and the array of PCB bonding pads 938, and by reflowing the array of solder balls. Additional underfill material portions, referred to herein as board-substrate (BS) underfill material portions 995 or BS underfill material portions 995, can be formed around the solder contacts 992 by applying and shaping an underfill material. A package substrate 200 is attached to the PCB 900 via the array of solder contacts 992.

[0063] Referring to FIG18, a first flowchart illustrates the steps of forming a semiconductor structure according to an embodiment of the present disclosure.

[0064] Referring to step 1810 and Figures 1 to 8, an interposer layer (300, 400) can be formed, which includes a first redistributed conductor interconnect 480 formed within the first redistributed dielectric layer 460.

[0065] Referring to step 1820 and Figures 9A to 9F, a first bump structure 488 and a virtual bump structure 488D are formed on one of the first redistributed conductor interconnects 480.

[0066] Referring to step 1830 and Figures 10A to 17, at least one semiconductor die 100 containing a corresponding array of the second bump structure 188 can be attached to a corresponding subset of the first bump structure 488 of the interposer layer 600.

[0067] Referring to step 1840 and Figures 11 through 17, a dielectric layer (bottom filler layer 195) may be formed between the virtual bump structure 488D and the semiconductor die 100. The virtual bump structure 488D is not bonded to any of the at least one semiconductor die 100.

[0068] Referring to FIG19, a second flowchart illustrates the steps for forming a semiconductor structure according to an embodiment of the present disclosure.

[0069] Referring to step 1910 and Figures 1 to 7, an interposer 600 can be formed, which includes a first redistributed conductor interconnect 480 formed within a first redistributed dielectric layer 460.

[0070] Referring to step 1920 and Figure 8, an opening 461 extending vertically downward from the top surface of the first redistributed dielectric layer 460 can be formed to physically expose the top surface segment of a subset of the first redistributed conductor interconnects 480 below the opening 461.

[0071] Referring to step 1930 and Figures 9A to 17, at least one semiconductor die 100 can be attached to the interposer 600.

[0072] Referring to all figures and various embodiments disclosed herein, a semiconductor structure comprising an assembly of an interposer 600 and at least one semiconductor die 100 is provided. The interposer 600 includes first redistribution interconnects 480 formed within a first redistribution dielectric layer 460, and first (die-side) bump structures 488 and dummy bump structures 488D contacting each of the first redistribution interconnects 480; each of the at least one semiconductor die 100 includes a corresponding array of second bump structures 188 (also referred to as on-die bump structures 188), which is bonded to a corresponding subset of the first bump structures 488 via a corresponding array of solder material portions 192; and a dielectric layer is formed between the dummy bump structures 488D and the semiconductor die 100.

[0073] In one embodiment, each of the virtual bump structures 488D contacts a respective virtual solder material portion 192D. In one embodiment, the virtual solder material portion 192D does not directly contact any of the at least one semiconductor die 100. In one embodiment, the virtual bump structure 488D overlaps in area with at least one semiconductor die 100 in a planar view. In one embodiment, the top surface of the first redistribution dielectric layer 460 includes a recess; each array of solder material portions 192 is laterally surrounded by a bottom fill material portion 195; and the bottom fill material portion 195 includes a downward protrusion that fills the recess on the top surface of the first redistribution dielectric layer 460.

[0074] The embodiments disclosed herein provide a semiconductor structure that enhances reliability by addressing moisture-induced peeling issues in redistribution interconnects 480 and redistribution dielectric layer 460. A combination of a first bump structure 488 and a dummy bump structure 488D can be used to improve mechanical stability and reduce the effects of moisture absorption. Components such as vias 485, fine-wire structures, and vertically extending openings 461 filled with downward protrusions of bottom filler material portions 195 can be used to improve adhesion between the redistribution interconnects 480 and the redistribution dielectric layer 460, thereby reducing the risk of peeling and cracking during thermal processes. The dummy bump structure 488D can be placed in critical areas to provide additional mechanical support, particularly in areas prone to peeling. The redistribution interconnects 480 may include patterns designed to reduce moisture stress, the configuration of which limits contact between the redistribution dielectric layer 460 and the moisture-absorbing material. In embodiments including openings 461 in the topmost first redistribution dielectric layer 460, these openings expose multiple segments of the redistribution conductor interconnects 480 during manufacturing and can be used as venting channels to allow moisture to escape during heating. The various embodiments disclosed herein improve the structural integrity of the composite package 800, increase the manufacturing yield of the composite package 800, and enhance the long-term reliability of the composite package 800 in applications where thermal and moisture stresses have adverse effects.

[0075] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Each embodiment described using the term “comprising” also inherently discloses that the term “comprising” may be replaced in some embodiments with “substantially constitutes…” or the term “consisting of…” unless otherwise explicitly disclosed herein. Whenever two or more components are listed as alternatives in the same or different paragraphs, it may also imply a disclosure comprising a group of two or more lists of components. Whenever the auxiliary verb “may” is used in this disclosure to describe the execution of a component formation or processing step, embodiments in which that component or processing step is not performed are also explicitly contemplated, provided that the resulting apparatus or device provides an equivalent result. Therefore, the auxiliary verb “may” applied to the execution of a component formation or processing step should also be interpreted as “may” or “may, or may not”, provided that omitting the formation of that component or processing step provides the same or equivalent result, including slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

[0076] 100: Semiconductor die 101: Processor die 102: Memory Chip 170: Grain-level molded compound matrix 170L: Second molding compound matrix 188: Grain-on bump structure / Second bump structure 192: Solder Material Section 192D: Virtual Solder Material Section 195, 295, 995: Bottom filling material portion 200: Packaging substrate 238: Package side bonding pad 288: Plate side joint gasket 300: Intermediary Layer 305: Partial Silicon Interconnect Bridge / LSI Bridge 310: Silicon substrate 312: Dielectric sheath 314, 482, 486: Structure 370: Intermediate-level molded compound framework 370L: First molding compound matrix 380: Metal interconnect structure 386: TIV structure 400: First redistribution junction / intermediate layer 460: First redistributed dielectric layer 461: Opening 480: Redistributed conductor interconnect 484: Metal Wire Structure 484D: Virtual Metal Wire Structure 485: Hole 486: Structure 488: Grain-side bump structure / First bump structure 488D: Virtual convex structure 500: Second redistribution layer structure 588: Substrate-side bonding structure 592: Solder Material Section / Solder Ball 600: Intermediary Layer / Composite Intermediary Layer 800: Composite Package 810: First carrier wafer 811: First adhesive layer 820: Second carrier wafer 821: Second adhesive layer 900: Printed Circuit Board / PCB 910: PCB substrate 938: PCB bonding pad 992: Solder Joint 1810, 1820, 1830, 1910, 1920, 1930: Steps UA: Cell Region dld1: Lateral dimension of the first grain dld2: Lateral dimension of the second grain hd1: First horizontal direction hd2: Second horizontal direction

Claims

1. A method for forming a semiconductor structure, comprising: An interposer layer is formed, the interposer layer including a plurality of first redistributed conductor interconnects formed within a plurality of first redistributed dielectric layers and a plurality of openings extending vertically downward from the top surface of the first redistributed dielectric layers, wherein the top surface segment of a subset of the first redistributed conductor interconnects is exposed by the openings; a plurality of first bump structures and a plurality of dummy bump structures are formed on each of the first redistributed conductor interconnects; at least one semiconductor die comprising a respective array of a plurality of second bump structures is attached to a respective subset of the first bump structures of the interposer layer; and a dielectric layer is formed between the dummy bump structures and the semiconductor die.

2. The method of forming a semiconductor structure as claimed in claim 1 further includes attaching a plurality of solder material portions to the first bump structure, wherein the second bump structure is bonded to the first bump structure via the solder material portions.

3. The method of forming a semiconductor structure as claimed in claim 2 further includes attaching a plurality of virtual solder material portions to the virtual bump structure, wherein the virtual bump structure does not contact the at least one semiconductor die after the at least one semiconductor die is bonded to the interposer layer.

4. The method of forming a semiconductor structure as claimed in claim 3 further includes applying an underfill material between the interposer and the at least one semiconductor die, around the solder material portion and the dummy solder material portion, to form an underfill material portion, wherein all surfaces of each dummy solder material portion are in combined contact with a combination of the underfill material portion and each of the dummy bump structures.

5. A method of forming a semiconductor structure as claimed in claim 1, wherein a first subset of the virtual bump structures is formed such that each virtual bump structure within the first subset of the virtual bump structures is electrically connected to a respective first bump structure selected from the first bump structures of the interposer layer.

6. The method of forming a semiconductor structure as claimed in claim 5, wherein a second subset of the virtual bump structure is formed such that each virtual bump structure within the second subset of the virtual bump structure is electrically disconnected from each first bump structure of the interposer layer.

7. The method of forming a semiconductor structure as claimed in claim 1, further comprising performing a degassing process on the first redistributed dielectric layer, wherein the opening serves as a venting channel.

8. A method of forming a semiconductor structure as claimed in claim 1, wherein a subset of the first redistributed interconnects is formed with at least one component, the component being selected from: a first component comprising a plurality of interconnected metal segments such that adjacent pairs of segments have different horizontal propagation directions, these directions differing by an acute angle; a second component comprising a plurality of one-dimensional arrays of straight metal lines having a uniform width less than the width of each first bump structure and having a uniform spacing less than the width of each first bump structure; and a third component comprising a two-dimensional array of a plurality of metal pads, each metal pad having a width not greater than 250% of the width of each first bump structure and a length not greater than 250% of the width of each first bump structure.

9. A method for forming a semiconductor structure, comprising: An intermediate layer is formed, the intermediate layer comprising a plurality of first redistributed conductor interconnects formed within a plurality of first redistributed dielectric layers; Multiple openings are formed that extend vertically downward from the topmost surface of the first redistributed dielectric layer to physically expose the top surface segments of a subset of the first redistributed conductor interconnects below the openings. And attaching at least one semiconductor die to the interposer layer.

10. A semiconductor structure comprising an interposer and an assembly of semiconductor wafers, wherein: The interposer layer includes a plurality of first redistributed conductor interconnects embedded within a plurality of first redistributed dielectric layers, a plurality of openings extending vertically downward from the top surface of the first redistributed dielectric layers and exposing a top surface segment of a subset of the first redistributed conductor interconnects, and a plurality of first bump structures and a plurality of dummy bump structures contacting each of the first redistributed conductor interconnects; the semiconductor die includes respective arrays of a plurality of second bump structures, each array of the second bump structures being coupled to a respective subset of the first bump structures; and a dielectric material formed between the dummy bump structures and the semiconductor die.

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