Thermally enhanced package and process for making the same

Abstract

This application relates to a thermally enhanced package comprising a carrier, a thinned die above the carrier, a molding compound, and a thermal extractor. The thinned die includes a device layer above the carrier and a dielectric layer above the device layer. The molding compound is located above the carrier, surrounds the thinned die, and extends beyond the top surface of the thinned die to define an opening within the molding compound above the thinned die. The top surface of the thinned die is at the bottom of the opening. At least a portion of the thermal extractor is inserted into the opening and in thermal contact with the thinned die. The thermal extractor is formed of metal or alloy.

Description

Technical Field

[0001] The present disclosure relates to a package and a method of manufacturing the same, and more particularly to a thermally enhanced package and a method of applying at least one heat extractor to the package to enhance thermal performance. Prior Art

[0002] With the increasing popularity of portable communication devices and the advancement of manufacturing technology, high-speed and high-performance transistors are increasingly integrated into device modules. Consequently, the large number of transistors integrated into the device module, the large amount of power passing through the transistors, and the high operating speeds of the transistors significantly increase the heat generated by the device module. Therefore, it is desirable to package the device module in a structure that better manages heat.

[0003] Typically, these high-power device modules are positioned directly above a heat sink for heat dissipation. However, such components are unattractive for low-profile applications. In some applications, the heat sink can be embedded within the printed circuit board (PCB). Excellent thermal conductivity is required between the high-power device module and the heat sink within the PCB. Furthermore, heat sinks embedded within the PCB can block electrical traces within the PCB to ensure adequate heat dissipation.

[0004] To accommodate the increased heat generation of device modules, the present disclosure therefore aims to provide an improved package design with enhanced thermal performance. Furthermore, there is a need to enhance the performance of the device module without increasing the package size or sacrificing electrical performance. Summary of the Invention

[0005] The present disclosure relates to a thermally enhanced package and a method for manufacturing the same. The disclosed thermally enhanced package includes a carrier having a top surface, a first thinned die, a first molding compound, and a first heat extractor. The first thinned die includes a first device layer above the top surface of the carrier and a first dielectric layer above the first device layer. The first molding compound is located on the top surface of the carrier, surrounds the first thinned die, and extends beyond the top surface of the first thinned die to define a first opening within the first molding compound and above the first thinned die. The first molding compound is not located above the first thinned die and provides vertical walls of the first opening that are aligned with edges of the first thinned die in both the X and Y directions. The X and Y directions are parallel to the top surface of the carrier and are orthogonal to each other. The top surface of the first thinned die is at the bottom of the first opening. Furthermore, at least a portion of the first heat extractor is inserted into the first opening and is in thermal contact with the first thinned die. The first heat extractor is formed of a metal or an alloy.

[0006] In one embodiment of the thermally enhanced package, the top surface of the first dielectric layer is a top surface of the first thinned die.

[0007] In one embodiment of the thermally enhanced package, the first heat extractor is attached to the first thinned die by an attachment layer formed of a thermally conductive epoxy, thermally conductive silicone, or alumina thermal adhesive.

[0008] In one embodiment of the thermally enhanced package, the first heat extractor has substantially the same X-direction and Y-direction dimensions as the first thinned die.

[0009] In one embodiment of the thermally enhanced package, the first heat extractor completely fills the first opening. A top surface of the first heat extractor and a top surface of the first molding compound are substantially in the same plane.

[0010] In one embodiment of the thermally enhanced package, a top surface of the first heat extractor is lower than a top surface of the first mold compound.

[0011] According to another embodiment, the thermally enhanced package further includes a second heat extractor. Here, at least a portion of the second heat extractor is inserted into the first opening and above the first heat extractor. The second heat extractor, the first heat extractor, and the first thinned die are thermally connected.

[0012] In one embodiment of the thermally enhanced package, the second heat extractor is attached to the first heat extractor by an attachment layer formed of a thermally conductive epoxy, thermally conductive silicone, or alumina thermal adhesive.

[0013] In one embodiment of the thermally enhanced package, the first thinned die further includes a plurality of interconnects extending from a bottom surface of the first device layer to a top surface of the carrier.

[0014] According to another embodiment, the thermally enhanced package further includes an underfill layer positioned between the first molding compound and the top surface of the carrier, and underfilling the first thinned die between the bottom surface of the first device layer and the top surface of the carrier. The underfill layer is formed of the same material as the first molding compound.

[0015] In one embodiment of the thermally enhanced package, the carrier includes a plurality of antenna patches on a bottom surface of the carrier, each antenna patch being electrically connected to a corresponding interconnect.

[0016] In one embodiment of the thermally enhanced package, the carrier is one of a laminate carrier, a wafer level fan-out (WLFO) carrier, a wafer level fan-in (WLFI) carrier, a lead frame, and a ceramic carrier.

[0017] According to another embodiment, the thermally enhanced package further includes a second thinned die having a second device layer above the top surface of the carrier and a second dielectric layer above the second device layer. Herein, a first mold compound surrounds the second thinned die and extends beyond the top surface of the second thinned die to define a second opening within the first mold compound above the second thinned die. The first mold compound is not positioned above the second thinned die and provides vertical walls of the first opening that are aligned with edges of the second thinned die in both the X and Y directions. The top surface of the second thinned die is at the bottom of the second opening. A first portion of a first heat extractor is inserted into the first opening and in thermal contact with the first thinned die, and a second portion of the first heat extractor is inserted into the second opening and in thermal contact with the second thinned die. The first heat extractor has a multi-finger comb structure.

[0018] In one embodiment of the thermally enhanced package, the carrier includes a plurality of carrier contacts at a top surface of the carrier, and each interconnect is electrically connected to a corresponding carrier contact.

[0019] According to another embodiment, the thermally enhanced package further includes at least one through-mold via (TMV), the at least one through-mold via being electrically connected to the first thinned die through a corresponding carrier contact and extending from a bottom surface of the first mold compound through the first mold compound to a top surface of the first mold compound.

[0020] According to another embodiment, a thermally enhanced package is included in a system component. In addition to the thermally enhanced package, the system component also includes a printed circuit board (PCB) having at least one board contact on a bottom surface of the PCB. Here, the bottom surface of the PCB is above a top surface of a first molding compound, and at least one TMV is electrically connected to the at least one board contact via at least one solder pad or at least one solder ball.

[0021] In one embodiment of the system component, the PCB further includes a heat sink structure on a bottom surface of the PCB. The heat sink structure is in thermal contact with the first heat extractor in the thermally enhanced package.

[0022] According to another embodiment, the thermally enhanced package further includes a second mold compound formed over the first mold compound and encapsulating the first heat extractor. Here, at least one TMV extends through the first and second mold compounds. At least one solder pad or at least one solder ball is formed over the second mold compound and electrically connected to the at least one TMV.

[0023] According to an exemplary method, a precursor package is provided, comprising a carrier, a first die attached to a top surface of the carrier, and a first molding compound. The first molding compound is formed over the top surface of the carrier and encapsulates the first die. The first die comprises a first device layer, a first dielectric layer over the first device layer, and a first die substrate over the first dielectric layer. The first molding compound is then thinned to expose a backside of the first die substrate. Next, the entire first die substrate is removed to create a first opening within the first molding compound, and a first thinned die is provided. The first opening is formed over the first thinned die, with the top surface of the first thinned die at the bottom of the first opening. Finally, at least a portion of a heat extractor made of metal is inserted into the first opening, such that the heat extractor is in thermal contact with the first thinned die.

[0024] Those skilled in the art will understand the scope of the present disclosure and recognize other aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. Simple diagram description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0026] [ FIG. 1 ] shows an exemplary thermally enhanced package according to one embodiment of the present disclosure.

[0027] [FIG. 2] to [FIG. 8] illustrate an alternative thermally enhanced package according to one embodiment of the present disclosure.

[0028] [FIGS. 9A] to [FIGS. 9E] provide exemplary steps illustrating a method of manufacturing the exemplary thermally enhanced package shown in FIG. 1 .

[0029] It should be understood that for clarity of illustration, Figures 1 to 9E may not be drawn to scale. Implementation Method

[0030] The embodiments set forth below provide those skilled in the art with the necessary information to practice the embodiments and illustrate the best mode for practicing the embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts underlying the present disclosure and will recognize applications of these concepts not specifically mentioned herein. These concepts and applications should be understood to fall within the scope of the present disclosure and the appended claims.

[0031] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” or “extending onto” another element, the element can be directly on or directly extending onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on” or “extending directly onto” another element, there are no intervening elements present. Similarly, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being “over” or extending “over” another element, the element can be directly over or extending directly over the other element, or there may be no intervening elements present. In contrast, when an element is referred to as being “directly over” or “extending directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0033] Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontally" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when used herein, the terms "comprise," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that, unless expressly defined as such herein, the terms used herein should be interpreted as having a meaning consistent with the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0036] The present disclosure relates to a thermally enhanced package and method for manufacturing the same. FIG1 illustrates an exemplary thermally enhanced package 10 according to one embodiment of the present disclosure. For illustrative purposes, the exemplary thermally enhanced package 10 includes a carrier 12, a first thinned die 14, an underfill layer 16, a first mold compound component 18, a first heat extractor 20, and a first attachment layer 22. In various applications, the thermally enhanced package 10 may include multiple thinned dies.

[0037] Specifically, the carrier 12 may be a laminate carrier, a wafer-level fan-out (WLFO) carrier, a wafer-level fan-in (WLFI) carrier, a lead frame, or a ceramic carrier. The carrier 12 includes a plurality of first carrier contacts 24 formed on the top surface of the carrier 12 and configured to electrically connect to the first thinned die 14 (for clarity, only one first carrier contact is labeled). The first thinned die 14 includes a first device layer 26, a first dielectric layer 28 above the top surface of the first device layer 26, and a plurality of first interconnects 30 extending from the bottom surface of the first device layer 26 to the top surface of the carrier 12 (for clarity, only one first interconnect is labeled). Each first interconnect 30 is electrically connected to a corresponding first carrier contact 24. The first device layer 26, having a thickness between 10 nm and 20,000 nm, may be formed of silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like. The first dielectric layer 28 with a thickness between 10 nm and 20,000 nm may be formed of silicon oxide, silicon nitride, or aluminum nitride. The first interconnect 30 with a height between 5 μm and 200 μm may be a copper pillar bump, a solder ball bump, or the like.

[0038] In one embodiment, the first thinned die 14 may be formed from a silicon-on-insulator (SOI) structure, which refers to a structure comprising a silicon substrate, a silicon epitaxial layer, and a buried oxide (BOX) layer sandwiched between the silicon substrate and the silicon epitaxial layer. The first device layer 26 of the first thinned die 14 is formed by integrating electronic components (not shown) within or on the silicon epitaxial layer of the SOI structure. The first dielectric layer 28 of the first thinned die 14 is the BOX layer of the SOI structure. Furthermore, the silicon substrate of the SOI structure is substantially removed to complete the first thinned die 14 (see discussion below for further details). In some applications, the top surface of the first thinned die 14 may be the top surface of the first dielectric layer 28.

[0039] The underfill layer 16 is positioned above the top surface of the carrier 12 such that the underfill layer 16 encapsulates the first interconnect 30 and underfills the first thinned die 14 between the bottom surface of the first device layer 26 and the top surface of the carrier 12. The underfill layer 16 may be formed of a conventional polymer that is used to mitigate stress effects caused by a coefficient of thermal expansion (CTE) mismatch between the first thinned die 14 and the carrier 12.

[0040] A first mold compound component 18 is positioned above the underfill layer 16, surrounding the first thinned die 14 and extending beyond the top surface of the first thinned die 14 to define a first opening 32 within the first mold compound 18 and above the first thinned die 14. The top surface of the first thinned die 14 is at the bottom of the first opening 32. Here, the first mold compound 18 is not positioned above the first thinned die 14 and provides vertical walls of the first opening 32 in the Z direction. The vertical walls of the first opening 32 are aligned with the edges of the first thinned die 14 in both the X and Y directions. Here, the X and Y directions are parallel to the top surface of the carrier 12, and the Z direction is perpendicular to the top surface of the carrier 12. The X, Y, and Z directions are all orthogonal to each other. The first mold compound 18 can be formed of the same material as or different from the underfill layer 16. When the first mold compound 18 and the underfill layer 16 are formed of the same material, they can be formed simultaneously. One exemplary material for forming the first mold compound 18 is an organic epoxy resin system.

[0041] Additionally, at least a portion of the first heat extractor 20 is inserted into the first opening 32 and attached to the top surface of the first thinned die 14 via a first attachment layer 22. The first heat extractor 20 may be a metal slug with a large heat-radiating area. The first heat extractor 20 may be formed from copper, aluminum / aluminum alloy, brass, or other metals or alloys with high thermal conductivity. The first attachment layer 22 may be formed from a thermal adhesive or thermal grease, such as a thermally conductive epoxy, thermally conductive silicone, alumina thermal adhesive, or other material that can serve as an intermediate thermal interface between the first thinned die 14 and the first heat extractor 20. Various viscosity, hardness, and cure speed specifications for the first attachment layer 22 are available. Thus, the first heat extractor 20 is in thermal contact with the first thinned die 14 and is configured to absorb heat generated from the first thinned die 14. For illustrative purposes, the first heat extractor 20 has substantially the same X- and Y-dimensions as the first thinned die 14, and has a thickness (along the Z-dimension) substantially the same as the depth of the first opening 32. In this context, "substantially the same" means between 95% and 100%. Specifically, the X-dimension of the first heat extractor 20 may be between 95% and 100% of the X-dimension of the first thinned die 14, and the Y-dimension of the first heat extractor 20 may be between 95% and 100% of the Y-dimension of the first thin-walled mold 14. In this manner, the first heat extractor 20 completely fills the first opening 32, and the top surface of the first heat extractor 20 and the top surface of the first molding compound 18 are substantially coplanar. In different applications, the thickness of the first heat extractor 20 may vary from the depth of the first opening 32, such that the top surface of the first heat extractor 20 may be lower or higher than the top surface of the first molding compound 18 (not shown here).

[0042] In cases where the thickness of the first heat extractor 20 is shorter than the depth of the first opening 32, the thermally enhanced package 10 may further include a second heat extractor 34 and a second attachment layer 36, as shown in FIG2 . Here, the first heat extractor 20 is positioned within the lower region of the first opening 32, while at least a portion of the second heat extractor 34 is inserted into the upper region of the first opening 32 and attached to the top surface of the first heat extractor 20 via the second attachment layer 36. The second heat extractor 34 may be a metal block with a large heat-radiating area. The second heat extractor 34 may be formed from copper, aluminum / aluminum alloy, brass, or other metals or alloys with high thermal conductivity. The second attachment layer 36 may be formed from a thermal adhesive or thermal grease, such as a thermally conductive epoxy, thermally conductive silicone, alumina thermal adhesive, or other materials that can serve as an intermediary for the thermal interface between the first heat extractor 20 and the second heat extractor 34. Various viscosity, hardness, and cure speed specifications are available for the second attachment layer 36. Here, the second heat extractor 34, the first heat extractor 20, and the first thinned die 14 are thermally coupled. The combination of the first heat extractor 20 and the second heat extractor 34 is configured to absorb heat generated from the first thinned die 14. For illustrative purposes, the second heat extractor 36 has substantially the same X- and Y-direction dimensions as the first thinned die 14. The combined thickness of the first heat extractor 20 and the second heat extractor 36 is substantially the same as the depth of the first opening 32. Thus, the top surface of the second heat extractor 34 and the top surface of the first mold compound 18 are substantially coplanar.

[0043] In some applications, as shown in FIG3 , the thermally enhanced package 10 includes multiple thinned dies. Here, in addition to the first thinned die 14, the thermally enhanced package 10 also includes a second thinned die 38. The second thinned die 38 includes a second device layer 40, a second dielectric layer 42 above the top surface of the second device layer 40, and a plurality of second interconnects 44 extending from the bottom surface of the second device layer 40 to the top surface of the carrier 12 (for clarity, only one second interconnect is labeled). The second device layer 40, with a thickness between 10 nm and 20,000 nm, can be formed from silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like. The second dielectric layer 42, with a thickness between 10 nm and 20,000 nm, can be formed from silicon oxide, silicon nitride, or aluminum nitride. The second interconnects 44, with a height between 5 μm and 200 μm, can be copper pillar bumps, solder ball bumps, or the like.

[0044] Underfill layer 16 encapsulates second interconnect 44 and underfills second thinned die 38 between the bottom surface of second device layer 40 and the top surface of carrier 12. First mold compound 18 is located above underfill layer 16, surrounds second thinned die 38, and extends beyond the top surface of second thinned die 38 to define a second opening 46 within first mold compound 18. Second opening 46 is located above second thinned die 38, with the top surface of second thinned die 38 at the bottom of second opening 46. Here, first mold compound 18 is not located above second thinned die 38 and provides vertical walls of second opening 46 in the Z direction. The vertical walls of second opening 46 are well aligned with the edges of second thinned die 38 in both the X and Y directions.

[0045] In this embodiment, the first portion 20-1 of the first heat extractor is inserted into the first opening 32 and is in thermal contact with the first thinned die 14, while the second portion 20-2 of the first heat extractor is inserted into the second opening 46 and is in thermal contact with the second thinned die 28. The first heat extractor 20 may have a "multi-finger comb-like structure" (also described as a combined T-shape in some cases). Note that the first heat extractor 20 may be a metal block, a metal comb, or other suitable structure with a large heat radiation area. The first portion 20-1 of the first heat extractor is attached to the top surface of the first thinned die 14 via a first attachment layer 22, and the second portion 20-2 of the first heat extractor is attached to the top surface of the second thinned die 38 via a third attachment layer 48. The third attachment layer 48 may be formed of a thermal adhesive or thermal grease, such as a thermally conductive epoxy, thermally conductive silicone, alumina thermal adhesive, or other material that can serve as an intermediary for the thermal interface between the second thinned die 38 and the second portion 20-2 of the first heat extractor. Various viscosity, hardness, and cure speed specifications of the third attachment layer 48 are available. The first portion 20 - 1 of the first heat extractor is configured to absorb heat generated from the first thinned die 14 , while the second portion 20 - 2 of the first heat extractor is configured to absorb heat generated from the second thinned die 38 .

[0046] Furthermore, the carrier 12 further includes a plurality of second carrier contacts 50 (for clarity, only one second carrier contact is labeled with a reference numeral) formed at a top surface of the carrier 12 and configured to electrically connect to the second thinned die 38. Each second interconnect 44 is electrically connected to a corresponding second carrier contact 50.

[0047] In one embodiment, the second thinned die 38 can be formed from a silicon-on-insulator (SOI) structure. The second device layer 40 of the second thinned die 38 is formed by integrating electronic components (not shown) within or on the silicon epitaxial layer of the SOI structure. The second dielectric layer 42 of the second thinned die 38 is the BOX layer of the SOI structure. Furthermore, the silicon substrate of the SOI structure is substantially removed to complete the second thinned die 38. In some applications, the top surface of the second thinned die 38 is the top surface of the second dielectric layer 42.

[0048] In some applications, as shown in FIG4 , the carrier 12 may also include multiple antenna patches 52 on the bottom surface of the carrier 12 to provide an antenna array. Here, each antenna patch 52 can be electrically connected to a corresponding first carrier contact 24 via a carrier via 54 (for clarity, only one antenna patch and one carrier via are labeled). Thus, each antenna patch 52 is electrically connected to the first thinned die 14. Forming the antenna patches 52 on the bottom surface of the carrier 12 minimizes the length of the interconnection between the first thinned die 14 and the antenna array. The antenna patches 52 can be formed from a metal plate made of copper, aluminum / aluminum alloy, TLCC material, or other metals or alloys with high conductivity to reduce insertion loss. If the carrier 12 is a WLFO carrier or a WLFO carrier, the first carrier contact 24, carrier vias 54, and antenna patches 52 can be implemented when a redistribution layer (RDL) is formed in the carrier 12.

[0049] Figures 5 and 6 show that the thermally enhanced package 10 further includes a second mold compound 56 to enclose the first heat extractor 20. The second mold compound 56 is formed above the first mold compound 18 and the first opening 32. Regardless of the thickness of the first heat extractor 20 (the top surface of the first heat extractor 20 can be higher, lower, or flush with the top surface of the first mold compound 18), the second mold compound 56 completely encapsulates and is directly connected to the first heat extractor 20. The second mold compound 56 is a high thermal conductivity mold compound. Compared to conventional mold compounds with a thermal conductivity of 1 W / m∙K, high thermal conductivity mold compounds have a thermal conductivity of 2.5 W / m∙K to 10 W / m∙K or higher. The second mold compound 56 can be formed from a thermoplastic or thermoset material, such as PPS (polyphenylene sulfide), an overmold epoxy resin doped with boron nitride or aluminum oxide thermal additives, or the like. The second mold compound 56 can be formed of the same or different material as the first mold compound 18. However, unlike the second mold compound 56, the first mold compound 18 does not have thermal conductivity requirements.

[0050] In addition, the thermally enhanced package 10 may also include one or more through-mold vias (TMVs) 58 that provide electrical connections to the first thinned die 14. Each TMV 58 is electrically connected to the first thinned die 14 through a corresponding first carrier contact 24 and extends through the underfill layer 16, the first mold compound 18, and the second mold compound 56. If the carrier 12 includes an antenna patch 52, the TMV 58 may be electrically connected to the antenna patch 52. There may be solder pads 60 (FIG. 5) or solder balls (FIG. 6) formed above the second mold compound 56 and electrically connected to corresponding TMVs 58.

[0051] FIG7 illustrates a system component 64 that includes the thermally enhanced package 10. In this embodiment, the thermally enhanced package 10 may not include the second mold compound 56 for encapsulating the first heat extractor 20, such that the TMVs 58 extend only through the underfill layer 16 and the first mold compound 18. Each solder pad 60 is formed above the first mold compound 18 and electrically connected to a corresponding TMV 58. In addition to the thermally enhanced package 10, the system component 64 also includes a printed circuit board (PCB) 66 having a plurality of board contacts 68 on the bottom surface of the PCB 66. The PCB 66 is positioned above the thermally enhanced package 10, and each solder pad 60 on the first mold compound 18 is electrically connected to a corresponding board contact 68. Furthermore, the PCB 66 may include a heat sink structure 70 on the bottom surface of the PCB 66, which is in thermal contact with the first heat extractor 20 via a thermal attach layer 72. Metal attachment layer 72 can be formed from a thermal adhesive or thermal grease, such as thermally conductive epoxy, thermally conductive silicone, aluminum oxide thermal adhesive, or other materials that can serve as an intermediary for the thermal interface between first heat extractor 20 and heat sink structure 70. Various viscosity, hardness, and cure speed specifications for thermal attachment layer 72 are available. Thermal attachment layer 72 can have a thermal conductivity greater than 0.5 W / m∙K or between 1 W / m∙K and 3 W / m∙K. If PCB 66 does not include heat sink structure 70, thermally coupling first heat extractor 20 to PCB 66 may not be necessary. In some applications, solder balls 62 are used instead of solder pads 60 to electrically connect TMVs 58 to corresponding board contacts 68, as shown in FIG8 . Heat sink structure 70 and thermal attachment layer 72 can be omitted from PCB 66.

[0052] Figures 9A through 9E provide exemplary steps for a method of manufacturing the exemplary thermally enhanced package 10 shown in Figure 1. Although the exemplary steps are shown sequentially, the exemplary steps are not necessarily sequentially dependent. Certain steps may be performed in a different order than presented. Furthermore, methods within the scope of the present disclosure may include fewer or more steps than the method shown in Figures 9A through 9E. If the carrier 12 is a laminate carrier, the exemplary steps are manufactured at the module level. If the carrier 12 is a WLFO carrier or a WLFI carrier, the exemplary steps are manufactured at the wafer level.

[0053] First, as shown in FIG9A , a precursor package 74 is provided. For illustrative purposes, the precursor package 74 includes a carrier 12 having first carrier contacts 24, a first die 14D, an underfill layer 16, and a first mold compound component 18. In various applications, the precursor package 74 may include multiple dies. Herein, the first die 14D includes a first device layer 26, a first dielectric layer 28 above the top surface of the first device layer 26, first interconnects 30 extending from the bottom surface of the first device layer 26 to the top surface of the carrier 12 (for clarity, only one first interconnect is labeled), and a first die substrate 76 above the top surface of the first dielectric layer 28. Thus, the backside of the first die substrate 76 is the top surface of the first die 14D. Herein, each first interconnect 30 is electrically connected to a corresponding first carrier contact 24 in the carrier 12.

[0054] In one embodiment, the first die 14D may be formed from a SOI structure. The first device layer 26 of the first die 14D is formed by integrating electronic components (not shown) within or on the silicon epitaxial layer of the SOI structure. The first dielectric layer 28 of the first die 14D is the BOX layer of the SOI structure. The first die substrate 76 of the first die 14D is the silicon substrate of the SOI structure. The first die 14D has a thickness between 25 μm and 250 μm, or between 25 μm and 750 μm, and the first die substrate 76 has a thickness between 25 μm and 250 μm, or between 25 μm and 750 μm, respectively.

[0055] Additionally, underfill layer 16 is positioned above the top surface of carrier 12, encapsulating first interconnect 30 and underfilling first die 14D between the bottom surface of first device layer 26 and the top surface of carrier 12. A first molding compound 18 is positioned above underfill layer 16 and encapsulates first die 14D. In the following steps, first molding compound 18 may serve as an etchant barrier to protect first die 14D from etching chemicals such as tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH).

[0056] Next, as shown in FIG9B , the first mold compound 18 is thinned to expose the backside of the first die substrate 76 of the first die 14D. The thinning process can be accomplished by mechanical grinding. The next step is to substantially remove the first die substrate 76 of the first die 14D to create a first opening 32 and provide a first thinned die 14, as shown in FIG9C . As used herein, substantially removing the first die substrate 76 refers to removing at least 99% of the entire first die substrate 76, and possibly removing a portion of the first dielectric layer 28. In desired cases, the first die substrate 76 is completely removed. Thus, the first thinned die 14 can refer to a thinned die comprising the first device layer 26, the first dielectric layer 28 above the first device layer 26, and the first interconnect 30 extending from the first device layer 24 to the carrier 12. Herein, the top surface of the first dielectric layer 28 is the top surface of the first thinned die 14 and is exposed in the first opening 32. Substantially removing the first die substrate 76 may be performed by an etching process using a wet / dry etchant chemistry such as TMAH, KOH, ACH, NaOH, or the like.

[0057] Next, a first attachment layer 22 is applied at the bottom of first opening 32, over the top surface of first thinned die 14, as shown in FIG9D . First attachment layer 22 can be applied using a rough spread, a smooth spread, or a specially shaped application method. Typical shapes for applying first attachment layer 22 include: a dot in the middle, two rice-like dots, a thin line, a thick line, multiple lines, a spiral pattern, an X-shape, a circle, a circle with a dot in the middle, and the like. Finally, at least a portion of first heat extractor 20 is inserted into first opening 32 and in thermal contact with first attachment layer 22, as shown in FIG9E . Thus, first heat extractor 20 is in thermal contact with first thinned die 14 and is configured to absorb heat generated from first thinned die 14.

[0058] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

[0059] 10: Thermally enhanced package 12: Bearing 14: First thinning grain 14D: First grain 16: Lower filling layer 18: First molding compound 20: First heat extractor 20(1):Part 1 20(2):Part II 22: First attachment layer 24: First carrier contact 26: First device layer 28: first dielectric layer 30: First interconnection 32: First Opening 34: Second heat extractor 36: Second attachment layer 38: Second thinning grain 40: Second device layer 42: Second dielectric layer 44: Second interconnection 46: Second opening 48: Third attachment layer 50: Second carrier contact 52: Antenna patch 54: Carrier via 56: Second molding compound 58:Through molded via (TMV) 60: Solder pad 62: Solder ball 64: System components 66: Printed Circuit Board (PCB) 68: Board contact 70: Radiator structure 72: thermal adhesive layer 74: Precursor package 76: first chip substrate

Claims

1. A method for manufacturing a package with enhanced thermal properties, comprising: A precursor package is provided, the precursor package including a carrier, a first die attached to a top surface of the carrier, and a first molding compound formed above the top surface of the carrier and encapsulating the first die, wherein the first die includes a first device layer, a first dielectric layer above the first device layer, and a first die substrate above the first dielectric layer; the first molding compound is thinned to expose the back side of the first die substrate; substantially the entire first die substrate is removed to create a first opening within the first molding compound, and a first thinned die is provided, wherein: the first opening is formed above the first thinned die; and the top surface of the first thinned die is at the bottom of the first opening; after removing the first die substrate, an attachment layer is applied directly to the top surface of the first thinned die at the bottom of the first opening; After applying the attachment layer, at least a portion of the first thermal extractor is inserted into the first opening such that the first thermal extractor contacts the attachment layer and is attached to the first thinned grain via the attachment layer, wherein the first thermal extractor is formed of metal or alloy; and a second molding compound is formed on top of the first molding compound to completely encapsulate the first thermal extractor, wherein: the first molding compound, the second molding compound, and the first thermal extractor are formed of different materials; no portion of the first molding compound is above the top surface of the first thermal extractor; and the second molding compound is a molding compound with high thermal conductivity.

2. The method as described in claim 1, wherein the adhesion layer is formed of one of the group consisting of thermally conductive epoxy resin, thermally conductive silicone, or alumina thermal adhesive.

3. The method as described in claim 1, wherein within the first die, the first device layer, the first dielectric layer, and the first die substrate have substantially the same dimensions in the X and Y directions, such that the first opening has substantially the same X and Y dimensions as the first thinned die, and the attachment layer does not extend vertically beyond the first thinned die in either the X or Y directions.

4. The method as described in claim 3, wherein the first thermal extractor has substantially the same X-direction dimension and Y-direction dimension as the first opening.

5. The method as described in claim 4, wherein: The first thermal extractor completely fills the first opening; and the top surface of the first thermal extractor and the top surface of the first molded compound are substantially in the same plane.

6. The method as described in claim 4, wherein the top surface of the first thermal extractor is lower than the top surface of the first molded compound.

7. The method as described in claim 6, further comprising: The second attachment layer is directly applied above the first thermal extractor within the first opening; And after applying the second attachment layer, inserting at least a portion of the second thermal extractor into the first opening, such that the second thermal extractor is thermally connected to the first thermal extractor via the second attachment layer, wherein the second thermal extractor is formed of metal or alloy.

8. The method as described in claim 1, wherein the first thinned die further includes a plurality of interconnects extending from the bottom surface of the first device layer to the top surface of the carrier.

9. The method as described in claim 8, further comprising an underfill layer located between the first molding compound and the top surface of the carrier, and underfilling the first thinned grains between the bottom surface of the first device layer and the top surface of the carrier.

10. The method as described in claim 9, wherein the lower filler layer is formed of the same material as the first molding compound.

11. The method as described in claim 8, wherein the carrier includes a plurality of carrier contacts at the top surface of the carrier, wherein, Each of the plurality of interconnects is electrically connected to the corresponding carrier contact among the plurality of carrier contacts.

12. The method as described in claim 8, wherein: The carrier includes a plurality of antenna patches on the bottom surface of the carrier; the first thinned die and the plurality of antenna patches are located on opposite sides of the carrier; and each of the plurality of antenna patches is electrically connected to a corresponding interconnect among the plurality of interconnects.

13. The method as described in claim 1, wherein the carrier is one of the group consisting of a laminated carrier, a wafer-level fan-out (WLFO) carrier, a wafer-level fan-in (WLFI) carrier, a lead frame, and a ceramic carrier.

14. The method as described in claim 1, wherein the top surface of the first dielectric layer is the top surface of the first thinned grain.

15. The method as described in claim 1, wherein the aforementioned thinning step is performed by mechanical polishing.

16. The method of claim 1, wherein the first die substrate is removed by etching with an etching chemical substance, the etching chemical substance being at least one of the group consisting of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH).

17. The method as described in claim 9, wherein the lower filler layer is formed of a material different from the first molding compound.

18. The method as described in claim 1, wherein the attachment layer is applied by a rough spreading, smooth spreading, or special-shaped application method.

19. The method of claim 1, further comprising forming at least one through-molded via (TMV) electrically connected to the first thinned grain, wherein the at least one through-molded via is positioned around the first thinned grain and extends vertically through the first molding compound and the second molding compound without being covered by the second molding compound.

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