Titanium silicon nitride barrier layer

Abstract

The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more specifically to a barrier layer for non-volatile memory devices, and a method for forming the same. In one embodiment, a method of forming an electrode for a phase-change memory device includes forming an electrode comprising titanium silicon nitride (TiSiN) on a phase-change memory element configured to store memory states over a semiconductor substrate. Forming the electrode includes exposing the semiconductor substrate to one or more periodic vapor deposition cycles, wherein the plurality of such periodic vapor deposition cycles include exposure to a Ti precursor, exposure to an N precursor, and exposure to a Si precursor.

Description

[Technical Field]

[0001] The present invention relates generally to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for non-volatile memory devices, and a method thereof for forming the same. [Previous Technology]

[0002] Non-volatile memory or storage devices can switch between memory states (e.g., logic 1 and logic 0 states) by changing the physical state of the storage element. For example, some non-volatile memory devices (e.g., flash memory devices) can switch between memory states by transferring charge back and forth across a floating gate configured as a storage element. Some other non-volatile or storage devices can switch between memory states by changing the resistance across the storage element. A subsequent type of non-volatile memory device includes phase-change memory (PCM) devices, which contain a phase-change material in the storage element. PCM devices can switch by inducing a phase change in the phase-change material of the storage element, including crystalline and amorphous phases.

[0003] Diffusion barriers for PCM devices have numerous applications utilizing structural, thermal, and electrical properties. However, among other trends, the demand for continuous scaling of PCM devices, improved performance, low-temperature integration, conformal properties, tunable resistance, voltage / current scaling, and / or three-dimensional (3D) integration is driving the corresponding demand for improved diffusion barriers for PCM devices and their formation methods. [Summary of the Invention]

[0004] In one embodiment, a method of forming an electrode for a phase-change memory device includes forming an electrode comprising titanium silicon nitride (TiSiN) on a phase-change memory element configured to store a memory state over a semiconductor substrate. Forming the electrode includes exposing the semiconductor substrate to one or more vapor deposition cycles, wherein the plurality of vapor deposition cycles includes exposure to a Ti precursor, exposure to an N precursor, and exposure to a Si precursor.

[0005] In another embodiment, a method of forming a phase-change memory device includes forming a memory cell over a semiconductor substrate, the memory cell including a diffusion barrier comprising titanium silicon nitride (TiSiN) and a phase-change storage element. Forming the diffusion barrier includes exposing the semiconductor substrate to one or more vapor deposition cycles, wherein the plurality of vapor deposition cycles includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to a silicon (Si) precursor.

[0006] In another embodiment, the non-volatile memory device includes a diffusion barrier formed over a semiconductor substrate, wherein the diffusion barrier comprises titanium silicon nitride (TiSiN) and is interposed between the phase-change storage element and an adjacent structure including a selection device or a metallization structure. The diffusion barrier has a silicon concentration such that the diffusion barrier has a resistivity between about 500 μΩ-cm and about 30,000 μΩ-cm.

[0007] In another embodiment, a method for forming a barrier layer comprising titanium silicon nitride (TiSiN) at a temperature between 200 °C and 390 °C includes exposing a semiconductor substrate to one or more vapor deposition cycles, wherein at least one of the vapor deposition cycles includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor and exposure to a silicon (Si) precursor.

Implementation Method

[0017] As described above, among other trends, the demand for continuous scaling of PCM devices, improved performance, voltage / current scaling, and / or three-dimensional (3D) integration drives a corresponding demand for improved diffusion barriers and their formation methods that can be used as electrodes. Areas of improved material properties include resistivity tunability for voltage / cell scaling and / or for optimizing heat generation; diffusion barrier capabilities to reduce contamination and cross-contamination between adjacent elements containing phase-change storage elements; thermal insulation capabilities to reduce energy consumption during write / erase operations; and reduced film roughness to reduce device parameter variability, as well as other material properties. Furthermore, as PCM devices continue to scale, electrodes can be formed in features with increasingly smaller dimensions, higher aspect ratios, and more complex morphologies. For example, some electrodes can be configured as heater electrodes, which can be formed in high (e.g., >1) aspect ratio vias or trenches. Furthermore, as technology nodes scale down to 10 nm and even smaller, electrode layers may be required. These electrode layers can be conformally laminated onto high aspect ratio trenches and vias (e.g., with dimensions as small as a few nanometers) for lateral memory cell scaling and / or 3D integration. Additionally, for PCM devices integrated at one or more metallization levels, the deposition temperature for the electrode layers should not exceed the thermal budget of the back-to-order process (BEOL), which can be as low as 400 °C or lower.

[0018] While various materials have been used to form diffusion barriers or electrodes in various PCM devices, further improvements can be made relative to one or more of the aforementioned areas of improvement. For example, TiN has been used due to its relatively high diffusion barrier performance. However, because TiN has a relatively low resistivity, when formed for use as a heating electrode, the electrode can have very small lateral or cross-sectional dimensions to increase the electrode's resistance. Tunable resistivity provides more flexibility in feature size. In addition, because TiN has a relatively low thermal resistivity, the energy consumed during write / erase operations can be relatively high. Furthermore, although electrodes for PCM devices are typically deposited using techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), the increasing demand for conformal properties of the electrode layer, as described above, ultimately limits their use.

[0019] Therefore, recognizing these and other needs, methods for depositing layers including TiSiN are disclosed herein, and various memory structures formed using these methods. According to various embodiments, a method for forming a thin film including titanium silicon nitride (TiSiN) includes exposing a semiconductor substrate to one or more periodic vapor deposition cycles, such periodic vapor deposition cycles being ALD cycles, such as thermal ALD cycles, including exposure to a Ti precursor, exposure to an N precursor, and exposure to a Si precursor. The thin film can be used as an electrode, diffusion barrier, and / or heater for various IC devices including phase-change memory devices, and for other applications.

[0020] As described herein, unless explicitly limited, a compound referred to by its constituent elements that does not have a specific stoichiometric ratio should be understood to encompass all possible non-zero concentrations of each element. For example, titanium nitride (TiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be represented by the general formula Ti xN, where x > 0, including TiN, Ti 3N 4, Ti 4N 3, Ti 6N 5, Ti 2N, and TiN 2, as well as other non-stoichiometric compositions of Ti and N. Similarly, silicon nitride (SiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of silicon nitride that can be represented by the general formula Si yN, where y > 0. Similarly, titanium silicon nitride (TiSiN) should be understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium silicon nitride that can be represented by the general formula Ti xSi yN, where x > 0 and y > 0.

[0021] FIG1 illustrates an exemplary structure (e.g., a portion) of a memory cell stack of a non-volatile memory device 100 (e.g., a PCM device) that can be manufactured using the methods disclosed herein, according to embodiments. According to various embodiments, the non-volatile memory device 100 includes an electrode 120 comprising titanium silicon nitride (TiSiN), for example, a diffusion barrier electrode, interposed between a phase-change storage element 110 and an adjacent structure 130. The phase-change storage element 110 is configured to store a plurality of memory states that can be non-volatile or persistent memory states. In some embodiments, the adjacent structure 130 includes a selector device connected in series with the phase-change storage element 110. The selector device is configured to control a switch that can be supplied to the phase-change storage element 110 by a voltage or current source to switch the phase-change storage element 110 between or between a plurality of memory states. In some other embodiments, the adjacent structure 130 may be a metallized structure, which may include metallized lines, contact structures, or other conductive paths formed of a metallic material for electrically connecting the phase change storage element 110 to a control circuit. In some embodiments, the electrode 120 may contact one or both of the phase change storage element 110 and the adjacent structure 130. However, in other embodiments, an interlayer or structure exists between the electrode 120 and one or both of the phase change storage element 110 and the adjacent structure 130.

[0022] FIG2 schematically illustrates an exemplary access operation that can be performed on the non-volatile memory device 100 illustrated in FIG1 above. An operation to induce a crystal-to-amorphous transition or a reset operation in the phase change storage element 110 (FIG. 1) is performed by applying a reset pulse 210 (e.g., a current or voltage pulse) to the phase change storage element 110 (FIG. 1), which comprises a substantially crystalline phase change material, in a low resistance state or a set state. The pulse can be applied using a selector device (e.g., adjacent structure 130 in FIG. 1) to control its duration and / or magnitude. The reset pulse 210 causes the phase change material of the phase change storage element 110 (FIG. 1) to at least partially melt at its melting temperature (Tmelt). After reaching the peak value of the reset pulse 210, the phase change storage element rapidly quenches for a sufficiently short time to prevent substantial recrystallization of the phase change material.

[0023] Referring again to FIG. 2, the operation or setting operation that initiates the amorphous to crystalline transformation of the phase change material is performed by applying a setting pulse 220 (e.g., a current or voltage pulse) to the phase change storage element 110 (FIG. 1), which comprises a substantially amorphous phase change material, in a high-resistance reset state. The duration and / or magnitude of the pulse can be controlled by applying a selector device (e.g., adjacent structure 130 in FIG. 1). The setting pulse 220 causes the phase change material of the phase change storage element 110 (FIG. 1) to recrystallize at least partially at the crystallization temperature (Tcrys).

[0024] The operation of determining the state of the phase change storage element 110 (FIG. 1) or the read operation can be performed by applying a read pulse 230 (e.g., a current or voltage pulse) and sensing the obtained electrical signal using a sense amplifier. The pulse can be applied using a selector device to control its duration and / or magnitude.

[0025] It will be understood that various operations of non-volatile memory devices, as described herein, can subject regions of the phase-change storage element to relatively high electric fields and temperatures reaching or exceeding the melting temperature of the phase-change material (which can exceed several hundred degrees). When a PCM device is subjected to these conditions periodically for tens or hundreds of thousands of cycles, one or more of the set, reset, or read voltages or currents can degrade over time, leading to reliability failures. Some failures are attributed to cross-contamination of different regions of the PCM device containing the phase-change storage element. Therefore, satisfying the competing characteristics that enable electrode 120 to function as an effective diffusion barrier, as well as the various other functionalities described herein, can be particularly challenging.

[0026] Referring again to FIG. 1, the inventors have discovered that, according to embodiments, one or more of the setting, resetting, and reading operations can be improved by forming an electrode 120 comprising TiSiN using an ALD (e.g., thermal ALD). For example, according to embodiments, the improved thermal insulation provided by the TiSiN material of electrode 120 can subsequently provide improved heat conservation during setting and / or resetting operations, thereby reducing the energy and / or time of each operation. As another example, in some embodiments, electrode 120 can be configured as a heating element to provide at least a portion of the heat used to melt the phase change storage element 110 during setting and / or resetting operations. In these embodiments, by tuning the composition of the TiSiN material of electrode 120, the power generated by the resistive heating of electrode 120 can be advantageously tuned to optimize each operation. These and other advantages are further described below. Forming a barrier or electrode comprising TiSiN for a phase change memory device.

[0027] Figure 3A illustrates a flowchart of a method 300 for forming a memory structure (e.g., a memory cell) including a phase-change memory device comprising an electrode containing TiSiN, according to an embodiment. Method 300 includes forming a phase-change memory element 310 over a semiconductor substrate. Furthermore, method 300 includes forming a diffusion barrier 320, which can also be used as an electrode, comprising titanium silicon nitride (TiSiN), by exposing the semiconductor substrate to one or more vapor deposition cycles, wherein the plurality of vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to a silicon (Si) precursor.

[0028] As described herein and throughout the specification, it will be understood that the semiconductor substrate on which the diffusion barrier including TiSiN is formed can be implemented on various substrates, including (but not limited to) doped semiconductor substrates that can be formed from: group IV element materials (e.g., Si, Ge, C or Sn) or alloys formed from group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from group III-V materials; group II-VI semiconductor materials (CdSe, CdS, ZnSe, etc.) or alloys formed from group II-VI materials.

[0029] According to a particular embodiment, the substrate may also be implemented as a semiconductor-on-insulator, such as a silicon-on-insulator (SOI) substrate. SOI substrates typically comprise silicon-insulator-silicon structures in which the various structures described above are isolated from the supporting substrate using an insulating layer such as a buried SiO2 layer (BOX). Furthermore, it will be understood that the various structures described herein may be at least partially formed in an epitaxial layer formed in or near the surface region.

[0030] Although not shown for clarity and ease of illustration, it will be understood that method 300 (FIG. 3) can be performed on a substrate that has been processed through a front-end process and may include various peripheral and / or support devices (e.g., CMOS transistors forming parts of word line and bit line driver circuits and sense amplifier circuits). Furthermore, the semiconductor substrate may include one or more of various structures pre-formed thereon, such as phase-change memory elements, selector devices, diffusion regions, isolation regions, electrodes, and metallization structures (to name a few, such as contacts and metallization lines), on which method 300 can be performed. Diffusion barriers, including TiSiN, can therefore be formed on various structures including morphological features (such as vias, cavities, holes, or trenches). The surface on which a diffusion barrier including TiSiN can be formed according to the embodiments includes: a phase change material surface, such as a chalcogenide material surface; a metal surface, such as the surface of a metallized structure; a semiconductor surface, such as a doped or undoped Si surface; and / or a dielectric surface, to name a few, such as an interlayer dielectric (ILD) surface, a mask or hard mask surface, or a gate dielectric surface.

[0031] Referring again to FIG. 3A, the method 300 for forming a memory structure includes forming a phase-change storage element 110 310 (FIG. 1) on a semiconductor substrate. The phase-change material of the phase-change storage element 110 may include (but is not limited to): a chalcogenide alloy composition containing at least two of the elements in the GeSbTe (GST) alloy system, such as Ge 8Sb 5Te 8, Ge 2Sb 2Te 5, Ge 1Sb 2Te 4, Ge 1Sb 4Te 7, Ge 4Sb 4Te 7, etc.; or a chalcogenide alloy composition containing at least two of the elements in the InSbTe (IST) alloy system, such as In 2Sb 2Te 5, In 1Sb 2Te 4, In 1Sb 4Te 7, etc.; and other chalcogenide alloy systems. Other chalcogenide alloy systems containing one or more chalcogenide elements and capable of undergoing a phase change directly or indirectly in response to an electrical signal may be used. Suitable deposition techniques can be used to form thin film layers, from which phase change storage devices can be formed. For example, physical vapor deposition, chemical vapor deposition, and atomic layer deposition can be used (to name a few) to deposit thin film layers of phase change materials, and phase change storage devices 110 (Figure 1) can be formed from these thin film layers by a combination of suitable patterning techniques.

[0032] As described above with respect to FIG. 1, in some embodiments, a diffusion barrier layer comprising titanium silicon nitride (TiSiN) that can be used as an electrode may be interposed between a phase-change storage element (110 in FIG. 1) and an adjacent structure including a selector device (130 in FIG. 1) to serve as a diffusion barrier between them (among other functionalities). In these embodiments, the selector device comprises a suitable two-terminal or three-terminal device that can be used to switch the memory state of the phase-change storage element. In some embodiments, the selector device may comprise a semiconductor device, such as, for example, a metal oxide silicon (MOS) transistor, a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a bidirectional diode thyristor, a PN junction diode, and a Schottky diode. In some other embodiments, the selector device may comprise a bidirectional limit switch (OTS), which is a bidirectional symmetrical two-terminal switch. Some OTSs comprise a chalcogenide composition. However, unlike phase change materials, the chalcogenide materials of OTS do not crystallize or undergo phase transitions. Instead, after applying a voltage or electric field exceeding a threshold value across the OTS, the OTS can be turned on to conduct current through it, and after removing the voltage or electric field, the OTS can be turned off to prevent current from conducting through it. Examples of chalcogenide alloy systems that can form OTS include (but are not limited to) TeAsGeSi, GeTePb, GeSeTe, AlAsTe, SeAsGeSi, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe. A suitable combination of processing techniques can be used to form a thin film layer from which the OTS can be formed. For example, (for example,) physical vapor deposition, chemical vapor deposition, and atomic layer deposition can be used to deposit a thin film layer of OTS material, from which a selector device can be formed by a suitable combination of patterning techniques.

[0033] In some embodiments, a diffusion barrier layer comprising titanium silicon nitride (TiSiN) that can be used as an electrode may be interposed between a phase change storage element (110 in FIG. 1) and an adjacent structure comprising a metallized structure (130 in FIG. 1) to serve as a diffusion barrier between them (among other functionalities). In these embodiments, the metallized structure may comprise metallized lines, contact structures, or other conductive structures formed of metal or metallic materials for electrically connecting the phase change storage element 110 to other portions of the PCM device. Metallized structures can be formed from any suitable metal or metallic material, to name just a few, including: metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicon, tungsten silicon, nickel silicon, cobalt silicon, and titanium silicon; and conductive metal oxides including RuO2.

[0034] The location of the diffusion barrier layer disclosed is not limited thereto, and it can be formed at any suitable location within the memory cell. For example, the diffusion barrier layer can be formed on any surface or interface of the phase change storage element 110 or on any surface or interface of the selector device.

[0035] Referring again to FIG3A, the method 300 for forming a memory structure further includes forming a diffusion barrier 320 comprising titanium silicon nitride (TiSiN) usable as an electrode by exposing a semiconductor substrate in a reactor chamber to one or more vapor deposition or atomic layer deposition (ALD) cycles, wherein at least one of the ALD cycles includes one or more exposures to a titanium (Ti) precursor, one or more exposures to a nitrogen (N) precursor and one or more exposures to a silicon (Si) precursor.

[0036] As described herein and throughout the specification, a reactor chamber refers to any reactor chamber suitably configured for periodic vapor deposition or atomic layer deposition (ALD) (e.g., thermal periodic vapor deposition or ALD) that contains a single wafer processing reactor chamber or a batch wafer processing reactor chamber. In a thermal ALD reactor, a substrate may be placed on a suitable substrate such as a pedestal or a carrier boat. The substrate may be heated directly by conduction through a heated pedestal, or indirectly by radiation from a radiation source (such as a lamp) or by convection through heated chamber walls.

[0037] Typically, in periodic vapor deposition or ALD processes, reactants or precursors (e.g., oxidizing and reducing reactants) are alternately introduced into a reaction chamber in which a substrate is housed. This introduction of one or more reactants or precursors may alternate sequentially with a scavenging or extraction process for removing excess reactants or precursors from the reaction chamber. Reactants may be introduced into the reaction chamber under conditions that expose surfaces that would otherwise impede deposition diffusion to the reactants, thereby at least partially saturating the substrate surface with the precursors or reactants and / or the reaction products of the reactants. Excess or residual precursors or reactants can then be scavenged and / or extracted from the reaction chamber. Extraction processes may be performed using a suitable vacuum pumping procedure, and scavenging steps may be performed by introducing a non-reactive or inert gas (e.g., nitrogen or a rare gas) into the reaction chamber. Other techniques exist for preventing the mixing of reactants in the gas phase.

[0038] Figures 3B and 3C are flowcharts and diagrams illustrating a method for forming a diffusion barrier including TiSiN according to embodiments. Referring to Figure 3B, according to various embodiments, exposing a semiconductor substrate 320 (Figure 3A) to one or more vapor deposition cycles (such as ALD cycles) includes exposing the substrate 325 to one or more first vapor deposition stages ("first deposition stages"), wherein at least one of the first deposition stages includes exposure to a Ti precursor and exposure to an N precursor. Furthermore, exposing a semiconductor substrate 320 (Figure 3A) to one or more vapor deposition cycles (such as ALD cycles) includes exposing the substrate 330 to one or more second vapor deposition stages ("second deposition stages"), wherein at least one of the second deposition stages includes exposure to a Si precursor or a combination of exposure to a Si precursor and further exposure to an N precursor. One or more first deposition stages and one or more second deposition stages may be combined to form a single cycle, which may then be repeated multiple times. A combination of exposing the substrate to 325 to one or more first deposition stages and exposing the substrate to 330 to one or more second deposition stages results in an electrode layer comprising a TiSiN layer or region. Each of exposing the substrate to 325 to one or more first deposition stages and exposing the substrate to 330 to one or more second deposition stages may then include one or more exposures to a respective precursor (such as in a pulse), as described below.

[0039] Referring again to Figures 3B and 3C, in various embodiments, exposing the substrate to one or more first deposition stages includes subjecting the substrate to one or more exposures to a Ti precursor and one or more exposures to an N precursor. Each exposure to the Ti precursor exposes the surface of the substrate, which is a diffusion barrier, to the Ti precursor, thereby substantially or partially saturating the surface with the Ti precursor. After exposing the substrate to the Ti precursor, excess or residual Ti precursor or its reaction products that are not retained adsorbed or chemisorbed on the surface of the substrate can be removed from the substrate surface, for example by pumping or purging the process chamber. Similarly, each exposure to the N precursor exposes the substrate, which is a diffusion barrier, to the N precursor, thereby substantially or partially saturating the surface with the N precursor. After exposing the substrate to the N precursor, excess or residual N precursor or its reaction products that are not adsorbed or chemically adsorbed on the substrate surface can be removed from the substrate surface by means of pumping or purging the process chamber. Subjecting the substrate to one or more first deposition stages, including one or more exposures to the Ti precursor and one or more exposures to the N precursor, can locally form one or more monolayers or regions substantially formed of the deposited TiN.

[0040] In some embodiments, exposure to the Ti precursor in a given first deposition stage can be performed sequentially multiple times. Similarly, exposure to the N precursor in a given first deposition stage can be performed sequentially multiple times. Advantageously, in some situations, such as when there is a substantial steric hindrance effect due to exposure to more reaction sites for adsorption of the respective precursors, exposing the substrate to the Ti and / or N precursors more than once can result in a higher surface saturation level.

[0041] Referring again to Figures 3B and 3C, in various embodiments, exposing the substrate to one or more second deposition stages includes subjecting the substrate to one or more exposures to a Si precursor. Each exposure to the Si precursor exposes the surface of the substrate, which would otherwise impede deposition diffusion, to the Si precursor, thereby substantially or partially saturating the surface with the Si precursor. After exposing the substrate to the Si precursor, excess or residual Si precursor or its reaction products that have not been retained adsorbed or chemisorbed on the surface of the substrate can be removed from the substrate surface, for example by pumping or purging the process chamber. Subjecting the substrate to one or more second deposition stages, including one or more exposures to a Si precursor, can locally form one or more monolayers or regions substantially formed of deposited Si.

[0042] In some embodiments, exposure to the Si precursor in a given second deposition stage can be performed sequentially multiple times. Advantageously, in some situations, such as when there is a substantial steric hindrance effect due to exposure to more reaction sites for adsorption of the respective precursors, exposing the substrate to the Si precursor more than once can lead to a higher surface saturation level.

[0043] Referring again to Figures 3B and 3C, in some embodiments, exposing the substrate to 330 to each of one or more second deposition stages includes exposing the substrate to one or more Si precursors and further exposing the substrate to one or more N precursors (which may be the same as or different from the N precursor of the first deposition stage). Each exposure to the Si precursor exposes the surface of the substrate, which is a diffusion barrier, to the Si precursor, thereby substantially or partially saturating the surface with the Si precursor. After exposing the substrate to the Si precursor, excess or residual Si precursor or its reaction products that are not retained adsorbed or chemisorbed on the surface of the substrate can be removed from the substrate surface, for example by pumping or purging the process chamber. Each exposure to the N precursor exposes the surface of the substrate, which is a diffusion barrier, to the N precursor, thereby substantially or partially saturating the surface with the N precursor. Following one or more further exposures to the N precursor, excess or residual N precursor or its reaction products that are not retained adsorbed or chemisorbed on the substrate surface can be removed from the substrate surface, for example by pumping or purging the process chamber. Subjecting the substrate to one or more second deposition stages, including one or more exposures to the Si precursor and one or more exposures to the N precursor, can locally form one or more monolayers or regions substantially formed of the deposited SiN.

[0044] In some embodiments, exposure to the Si precursor in a given second deposition stage can be performed sequentially multiple times. Similarly, further exposure to the N precursor can be performed sequentially multiple times. Advantageously, in some situations, such as when there is a substantial steric hindrance effect by exposing more reaction sites for adsorption of the respective precursors, exposing the substrate to the Si and / or N precursors more than once can lead to a higher surface saturation level, as discussed herein.

[0045] It will be understood that, in various embodiments, based on various considerations including susceptibility to the steric hindrance effect of the precursor, the number of cycles of each of the first and second deposition stages, or both, as described herein, the frequency and number of repetitions of the first and second deposition stages, the frequency and number of repetitions of the substrate exposure to the Ti and N precursors during the first deposition stage, and the frequency and number of repetitions of the substrate exposure to the Si or Si and N precursors during the second deposition stage, can be varied to obtain the desired thickness, stoichiometry, and other properties of the resulting diffusion barrier layer including TiSiN as described herein.

[0046] Referring again to Figures 3B and 3C, depending on the circumstances or the desired improvement, it may be advantageous to initiate the deposition of the diffusion barrier including TiSiN by exposing the substrate to one or the other of the first or second deposition stage. For example, the inventors have found that, for example, when the substrate surface includes a non-metallic surface (e.g., an insulating surface, such as the sidewalls of trenches or vias formed in an interlayer dielectric (ILD) layer; or a semiconductor surface, such as a Si diffusion region), it may be particularly advantageous to first expose the substrate to 330 to one or more second deposition stages (Si precursor or N precursor), and then expose the substrate to 325 to one or more first deposition stages (Ti precursor or N precursor) to enhance the layer-by-layer growth pattern of the diffusion barrier layer, thereby improving conformability and reducing surface roughness.

[0047] However, the embodiments are not limited thereto, and in other embodiments, for example, when the substrate surface includes a metal surface (e.g., W, Al or Cu metal metallization), it may be more advantageous to first expose the substrate to one or more first deposition stages (Ti precursor or N precursor) at 325, and then expose the substrate to one or more second deposition stages (Si precursor or N precursor) at 330, in order to reduce contact resistance while maintaining good conformability and surface roughness.

[0048] According to various embodiments, non-limiting examples of Ti precursors used to form diffusion barrier layers or regions include titanium tetrachloride (TiCl4), tetradecyl (dimethylamino)titanium (TDMAT) or tetradecyl (diethylamino)titanium (TDEAT).

[0049] According to various embodiments, non-limiting examples of N precursors used to form diffusion barrier layers or regions include ammonia (NH3), hydrazine (N2H4), or methylhydrazine (CH3(NH)NH2, "MMH"). As mentioned above, different N precursors may be used for the first deposition stage and the second deposition stage, and practically different precursors may be used for different cycles of the same stage.

[0050] According to various embodiments, non-limiting examples of inert gases used for purging include nitrogen (N2) or rare gases (such as Ar).

[0051] According to some embodiments, the Si precursor used to form the diffusion barrier layer may be a hydride precursor. Examples of such hydride precursors include silane (SiH4) and ethoxysilane (Si2H6). According to some other embodiments, the Si precursor used to form the diffusion barrier layer may be silica or chlorosilane. Examples include silica tetrachloride (SiCl4), monochlorosilane (SiH3Cl, "MCS"), dichlorosilane (SiH2Cl2, "DCS"), trichlorosilane (SiHCl3), hexachloroethoxysilane (Si2Cl6, "HCDS"), and octachloroethoxysilane (Si3Cl8, "OCTS"). The inventors have discovered that silicon- and chlorine-containing Si precursors are desirable for forming diffusion barrier layers including TiSiN when a higher saturation level on the surface of the precursor is desired under various conditions. Without being constrained by any theory, the inventors have found that these Si precursors, when introduced as the first non-nitrogen precursor, are particularly advantageous for enhancing the layer-by-layer growth pattern of the TiSiN layer compared to other Si precursors. This layer-by-layer growth pattern is achieved by improving the wetting of the substrate surface through the core of the TiSiN layer during the early stages of growth, which can be characterized by a small contact angle between the core and the substrate surface. Due to the layer-by-layer growth pattern, improved conformability and reduced surface roughness can be achieved, which is particularly advantageous for forming diffusion barriers by deposition at high aspect ratios with small dimensions. Furthermore, without being constrained by any theory, chlorine-containing Si precursors allow for more precise control of the composition in the growth direction by inhibiting or self-limiting adsorption.

[0052] According to embodiments, the various technical advantages and benefits described herein can be achieved when a diffusion barrier layer comprising TiSiN is formed at a substrate temperature of 200 °C to 250 °C, 250 °C to 300 °C, 300 °C to 350 °C, 350 °C to 390 °C, 350 °C to 400 °C, 400 °C to 450 °C, 450 °C to 500 °C, 500 °C to 550 °C, 550 °C to 600 °C, 600 °C to 650 °C, or at a temperature within a range defined by any of these equivalents (e.g., about 400 °C). As discussed above, the disclosed method can be advantageously performed at deposition temperatures that do not exceed the thermal budget of most of the back-to-office (BEOL) portion of the process flow (which can be as low as 400 °C or below). Furthermore, when forming a diffusion barrier layer after the formation of a phase change memory element, it is advantageous to form the diffusion barrier layer at a deposition temperature that substantially alters the nanostructure or microstructure of the phase change memory element. For example, when the phase change memory element advantageously contains a pre-formed amorphous phase, the low deposition temperature of the subsequent diffusion barrier layer can suppress substantial crystallization of the amorphous phase. Therefore, according to an embodiment, the diffusion barrier layer is formed at a temperature below the crystallization temperature of the phase change memory element. The presence of a pre-formed amorphous phase in the memory element (e.g.) can be advantageous for reliability testing after the fabrication of the phase change memory device.

[0053] Therefore, according to embodiments, the total reaction chamber pressure or partial pressure of any of the individual precursors in the reaction chamber during exposure of the substrate to the Ti precursor, Si precursor, and / or N precursor can be 1.0 Torr to 3.0 Torr, 3.0 Torr to 5.0 Torr, 5.0 Torr to 7.0 Torr, 7.0 Torr to 10.0 Torr, or pressure within the range defined by any of these equivalent values. In each of the Ti precursor, N precursor, and / or Si precursors, the individual precursor can constitute 1% to 2%, 2% to 5%, 5% to 10%, 10% to 20%, 20% to 50%, 50% to 100% of the total amount of gas molecules in the reaction chamber, or a percentage within the range defined by any of these equivalent values. The inventors have found that in some cases, when the total pressure or partial pressure is outside these equivalent values, conformability or step coverage can begin to degrade.

[0054] In various embodiments, the exposure time or pulse time of various precursors is in the range of about 0.1 seconds and 60 seconds.

[0055] According to various embodiments, when forming a diffusion barrier layer including TiSiN, the ratio of the number of times the substrate is exposed to the first deposition stage (each including a combination of exposures to the Ti precursor and the N precursor) to the number of times the substrate is exposed to the second deposition stage (each including exposures to the Si precursor or a combination of exposures to the Si precursor and the N precursor) can be approximately 1:30 to 1:15, 1:15 to 1:6, 1:6 to 1:3, 1:3 to 1:2, 1:2 to 2:3, 2:3 to 5:6, 5:6 to 1:1, 1:1 to 6:5, 6:5 to 3:2, 3:2 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a ratio within the range defined by any of these equivalent values. Alternatively, the exposures to the Ti precursor and the Si precursor can have this ratio. Under the combination of procedural conditions described herein for forming a diffusion barrier including TiSiN, the ratio of exposure to the first deposition stage to exposure to the second deposition stage is such that Si exists in the diffusion barrier at an average concentration exceeding approximately 1%, 3%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or within a range defined by any of these equivalents, based on the total number of atoms in the diffusion barrier.

[0056] In summary, forming a diffusion barrier 320 comprising TiSiN that can be used as an electrode includes exposing a substrate to one or more cycles comprising one or more first deposition stages and / or one or more second deposition stages. Each of the first deposition stages then includes one or more exposures to a Ti precursor, alternating with one or more exposures to an N precursor. According to some embodiments, each of the second deposition stages then includes one or more exposures to a Si precursor. According to some other embodiments, each of the second deposition stages includes one or more exposures to a Si precursor, alternating with one or more exposures to an N precursor. The resulting diffusion barrier layer comprises a TiSiN layer or region. According to various embodiments, the frequency and number of exposures of the substrate to each of the Ti precursor, N precursor, and Si precursor, the frequency and number of exposures of the substrate to each of the cycles, first deposition stages, and second deposition stages, and the order of exposure can be customized to obtain desired stoichiometry, thickness, and crystallinity, as described below.

[0057] The diffusion barrier formed according to the embodiment may have a thickness not exceeding about 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, or 2 nm, which can be customized for a specific memory cell architecture, or have a thickness within a range defined by any of these equivalent values.

[0058] The inventors have found that, advantageously, when a diffusion barrier layer is formed according to the embodiments disclosed herein, surface roughness can be reduced compared to other diffusion barrier materials (e.g., TiN or TiSiN) formed using other techniques (e.g., CVD or PVD) for phase-change memory devices. This reduced surface roughness is particularly advantageous when the surface on which the diffusion barrier is deposited includes a non-metallic surface (e.g., a dielectric surface and / or a semiconductor surface) exposed by openings such as vias or trenches, compared to other materials or techniques. During deposition, a diffusion barrier having the aforementioned thickness can have a root mean square (RMS) surface roughness of 0.1%, 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, and 5% based on the average thickness of the diffusion barrier, or within a range defined by any of these equivalents. Alternatively, during deposition, the diffusion barrier having the aforementioned thickness can have a root mean square (RMS) surface roughness value less than 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or within a range defined by any of these equivalents. The reduced RMS roughness can then improve the conformality of the diffusion barrier layer. Furthermore, by reducing asperities, the diffusion barrier layer, including TiSiN, can reduce the variability of the switching parameters (e.g., current, voltage, and / or duration of setting and resetting switching operations) of the phase change storage element in contact with the TiSiN layer. The resistivity and crystallinity of the exposed Si precursor can be tuned.

[0059] Phase-change memory devices can have different memory cell architectures. In some cell architectures, the majority of the heat initiating the phase change in the phase-change memory element can be provided externally, for example, by resistive heating of an electrode in contact with the phase-change memory element. In these cell architectures, it is advantageous to configure the electrode providing heat to the phase-change memory element to have a relatively high resistance to function as an effective heater. In some other cell architectures, the majority of the heat initiating the phase change can be generated by resistive self-heating of the phase-change memory element. In these cell architectures, it is advantageous to configure the electrode of the phase-change memory element to have a relatively low resistance to reduce excessive voltage drop across it. Advantageously, the method of forming electrodes according to the embodiments disclosed herein can be used to tune the resistivity of the electrode over a relatively wide range of values ​​by tuning the relative Si content of the electrode. Therefore, electrodes according to the different embodiments disclosed herein can be used as electrodes in various PCM cell architectures.

[0060] Figure 4 is a graph of experimentally measured resistivity varying according to the silicon content of the TiSiN electrode, based on the embodiment. This graph illustrates that the resistivity of the electrode can be tuned over a wide range of values ​​by tuning the relative Si content in the electrode, which in turn can be tuned by tuning the number of exposures to the Si precursor during the ALD cycle. The inventors have found that while the resistivity of the electrode increases relatively slowly with respect to the Si precursor exposure for relatively low numbers of exposures, it increases relatively rapidly in a non-linear manner with respect to the Si precursor exposure for relatively high numbers of exposures. The inventors have further found that, experimentally verified by transmission electron microscopy, the relatively rapid increase in resistivity with respect to the Si precursor exposure for relatively high numbers of exposures generally coincides with the onset 410 of the appearance of the amorphous phase of TiSiN.

[0061] Therefore, in PCM devices having a memory cell architecture with an electrode system having relatively high resistivity, relatively high diffusion barrier capability, relatively high thermal resistivity and / or relatively low surface roughness, the composition of the electrode layer can be advantageously tuned such that the electrode system comprising TiSiN is at least partially amorphous. In these embodiments, the electrode may be substantially completely amorphous or comprise nanocrystalline regions surrounded by an amorphous matrix. For example, the electrode may comprise TiSi, TiN and / or TiSiN nanocrystals comprising Ti, Si and N in an amorphous matrix. In the illustrated embodiment, the start at about 1600 μΩ-cm corresponds to an average atomic concentration of about 8% Si in the TiSiN layer. However, the embodiments are not limited thereto, and in other embodiments, depending on the deposition conditions and the precursor used, the start may occur at an average atomic concentration of about 5%, 10%, 15%, 20% or 25% Si in the TiSiN layer or within a range defined by any of these equivalents. Alternatively, the start 410 corresponds to a ratio of 1:1 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a ratio within a range defined by any of these equivalents, to the number of times the substrate is exposed to one or more first deposition stages (each including exposure to a combination of exposure to a Ti precursor and an N precursor).

[0062] The TiSiN electrode may have a value of <500 μΩ-cm, 500 μΩ-cm to 1000 μΩ-cm, 1000 μΩ-cm to 2000 μΩ-cm, 2000 μΩ-cm to 3000 μΩ-cm, 3000 μΩ-cm to 4000 μΩ-cm, 4000 μΩ-cm to 5000 μΩ-cm, 5000 μΩ-cm to 6000 μΩ-cm, 6000 μΩ-cm to 7000 μΩ-cm, 7000 μΩ-cm to 8000 μΩ-cm, 8000 μΩ-cm to 9000 μΩ-cm, 9000 μΩ-cm to 10,000 μΩ-cm, 10,000 μΩ-cm to 15,000 μΩ-cm, 15,000 μΩ-cm to 20,000 μΩ-cm. Resistivity of μΩ-cm, 20,000 μΩ-cm to 25,000 μΩ-cm, 25,000 μΩ-cm to 30,000 μΩ-cm or greater than 30,000 μΩ-cm, or values ​​within the range defined by any of these equivalents. Example embodiments of TiSiN electrodes in phase-change memory devices.

[0063] FIG5 is an example of a phase-change memory (PCM) device 500 or cell that may include at least one electrode of TiSiN according to an embodiment. The PCM device 500 includes a phase-change storage element 510, which has an electrode 520 (e.g., a heater electrode) formed on its bottom side and a top electrode 550 formed on its top side. According to an embodiment, one or both of the electrode 520 and the top electrode 550 include TiSiN. As illustrated, the electrode 520 including TiSiN may have a vertical contact structure formed through an insulator 540 (e.g., an interlayer dielectric (ILD)) extending vertically to electrically connect the phase-change storage element 510 to a metallization structure 560. The metallization structure 560 (which may be a metallization line) may then be connected to any of the selector devices formed on the substrate as described above, such as a transistor device (not shown). In the illustrated PCM device 500, the majority of the heat that initiates the phase change in the phase change storage element 510 is provided by resistive heating of the electrode 520 in contact with the phase change storage element 510. To increase resistance and heat generation, the width or cross-sectional area of ​​the electrode 520 contacting the phase change storage element 510 may be designed to be smaller than the width or cross-sectional area of ​​the phase change storage element 510, as shown. However, the embodiments are not limited thereto, and particularly in view of the ability to tune the resistivity of the electrode 520 as taught herein, the width or cross-sectional area of ​​the electrode 520 and the phase change storage element 510 may be designed to be substantially similar (e.g., within 20% or 10%).

[0064] To increase the resistance and heat generation of electrode 520, various parameters of electrode 520, including resistivity, length, and cross-sectional area, can be optimized to increase the resistance of electrode 520 for Joule heating. In various existing memory cell architectures similar to the cell architecture illustrated in Figure 5, electrode materials with relatively low resistivity (e.g., C, TiN, TaN, W, and WN) are used, and to enhance heating, the length of electrode 520 can be increased, the cross-sectional area of ​​electrode 520 can be decreased, or both. However, it will be understood that both increasing the length and decreasing the cross-sectional area increase the aspect ratio of the vias or trenches that can be filled to form electrode 520. In addition, as memory cell sizes continue to scale proportionally, it becomes increasingly difficult to form such contact structures by filling high aspect ratio vias or trenches using existing techniques such as PVD or CVD.

[0065] Furthermore, while plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) can effectively form conformal films on surfaces with relatively low aspect ratios, these processes may not be effective at depositing films inside vias and cavities with relatively high aspect ratios. Without theoretical constraints, one possible reason for this is that, in some cases, the plasma may not be able to reach deeper portions of high aspect ratio vias, or the reactivity of the plasma reactants may vary with depth. In such cases, different portions of the via may be exposed to different amounts of plasma energy or reactivity, resulting in undesirable structural effects of non-uniform deposition, such as thicker films deposited near the opening of the via compared to deeper portions (sometimes referred to as sharpening or keyhole formation). For these reasons, thermal ALD may be more advantageous because thermal ALD does not depend on the ability of the plasma to reach portions of the deposited surface.

[0066] The inventors have discovered that the method for forming an electrode comprising TiSiN according to embodiments addresses these and other technical challenges by: providing a method for filling high (e.g., >1) aspect ratio vias or trenches by continuously depositing conformal TiSiN layers therein as described above; and providing a method for tuning the resistivity of the resulting electrode by tuning the Si content (e.g., by controlling the exposure ratio of deposition stages and / or respective precursors). It will be understood that when using techniques such as PVD or CVD to fill high aspect ratio vias or trenches, the deposition rate can be higher near the opening of the vias or trenches than in the bottom region, which can result in the resulting electrode enclosing voids or "keyholes". Such voids can even occur when using plasma-enhanced ALD, because plasma may not be able to be maintained in deep and narrow structures. Such voids can uncontrollably increase the resistance of the electrode and cause other integration problems, such as electrical short circuits further downstream in the process flow of integrating the PCM device 500. Advantageously, in the thermal periodic vapor deposition or ALD method disclosed herein, the resulting electrode 520 has the further advantage of substantially reducing or eliminating the formation of voids or "keyholes" because each of the continuous layers formed according to the disclosed ALD method is conformally clad onto the deposition surface to fill vias or trenches. Furthermore, the thermal periodic deposition or ALD method according to the embodiments is adapted to fill vias or trenches having aspect ratios exceeding 1, 2, 5, 10, 20, or within a range defined by any of these values, by successively depositing conformal TiSiN layers. Therefore, in a cell architecture in which the electrode 520 (which can be configured as a heater electrode providing at least a portion of the heat for switching) has a vertical contact structure, the TiSiN-complementing electrode 520 can be formed by filling vias or trenches formed through the insulator 540. The via or trench can be formed by exposing the surface of the via or trench (which may include non-metallic surfaces, such as the surface of an ILD material) to one or more vapor deposition cycles, wherein at least one of the vapor deposition cycles includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to a silicon (Si) precursor, as described above. After filling the via or trench with TiSiN, excess TiSiN deposited outside the via or trench can be removed using, for example, chemical mechanical polishing. A phase change storage element 510 can then be formed on electrode 520.

[0067] In addition to the improved ability to fill high aspect ratio vias or trenches as described above, the ability to tune the resistivity of the electrode material can also provide further advantages by enabling a reduction in the aspect ratio (e.g., the ratio of depth to opening width) of the vias or trenches that can be filled to form electrode 520, while maintaining or increasing the relatively high resistance of electrode 520 for use as an effective heater. As described with reference to FIG4, the method of forming electrode 520 according to the embodiment allows tuning of the resistivity of the deposited TiSiN material over a wide range across decimal units (e.g., from less than 1000 μΩ-cm to greater than 10000 μΩ-cm). By increasing the resistivity of the electrode material, the ratio of electrode length to cross-sectional area can be reduced proportionally. In some embodiments, the composition of the tunable electrode 520 is such that the average atomic concentration of Si corresponds to or is greater than the start 410 of the amorphous phase of TiSiN as described above (FIG. 4).

[0068] There are additional advantages to the TiSiN electrode 520. Due to the lower thermal conductivity of TiSiN compared to other electrode materials (e.g., TiN and W), the heat energy dissipated to initiate the phase change in the phase change storage element 510 can be substantially reduced. In addition, since the electrode 520 has the relatively low surface roughness as described above, the variability of the switching and readout parameters used in the phase change storage element 510 can be improved. Furthermore, since the electrode 520 has the improved diffusion barrier properties as described above, contamination of the phase change storage element 510 by adjacent materials or cross-contamination with adjacent materials can be substantially suppressed.

[0069] In some embodiments, the top electrode 550 comprises TiSiN according to embodiments to further enhance the resistive heating, thermal insulation, diffusion barrier capabilities, and / or switching / reading parameter uniformity of the phase change storage element 510 in a manner similar to that described above. However, the embodiments are not limited thereto, and the top electrode 550 may be formed of any other suitable electrode material, for example, including: carbon (C); n-doped polycrystalline silicon and p-doped polycrystalline silicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, W, and WN; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicon, tungsten silicon, nickel silicon, cobalt silicon, and titanium silicon; and conductive metal oxides including RuO2.

[0070] Although not shown, a top metallization line may be formed on the top electrode 550 and may comprise Al, Cu, and W, as well as other suitable materials. When the top electrode 550 comprises TiSiN according to an embodiment, it can serve as an effective diffusion barrier between the phase change storage element 510 and the metallization line.

[0071] FIG6 is another example of a phase-change memory (PCM) device 600 or cell that may include at least one electrode of TiSiN according to an embodiment. The PCM device 600 includes a cell stack 605 including a phase-change storage element 610, which has an electrode 620 (e.g., a diffusion barrier electrode) formed on its bottom side and a top electrode 650 formed on its top side. According to an embodiment, one or both of the electrode 620 and the top electrode 650 include TiSiN. In addition, the cell stack 605 may include a selector device 630 separable from the phase-change storage element 610 by means of the electrode 620, and a bottom electrode 660. The selector device 630 may be any of the selector devices described above, such as a two-terminal device (such as an OTS). The cell stack 605, which includes the phase-change storage element 610 and the selector device 630, can then be connected at one end to a top metallization line 670 (e.g., one of the word line and the bit line) via a top electrode 650, and at the other end to a bottom metallization line 680 (e.g., the other of the word line and the bit line) via a bottom electrode 660.

[0072] Unlike the cell architecture described above with respect to FIG. 5, in which the majority of the heat for the phase change in phase change element 510 is provided by resistive heating of the electrodes in contact with the phase change storage element, the PCM device 600 has a cell architecture in which the majority of the heat for initiating the phase change in phase change element 610 is generated by resistive self-heating of the phase change storage element 610. In such cell architectures, it is advantageous to configure the electrodes of the phase change storage element to have relatively low resistance to reduce excessive voltage drop across them. Therefore, the width or cross-sectional area of ​​the electrode 620 contacting the phase change storage element 610 can be designed to be equivalent to (e.g., within about 20% or 10%) the width or cross-sectional area of ​​the phase change storage element 610.

[0073] Partly due to the enhanced diffusion barrier properties and reduced surface roughness of electrode 620 compared to other electrode materials (e.g., TiN or W, or TiSiN formed by other methods), the thickness of electrode 620 can be substantially reduced without sacrificing barrier capability, surface smoothness, and / or thermal insulation, as well as other advantages. This reduction in thickness, in turn, enables a substantial reduction in the overall height of the cell stack 605 and the operating voltage, thereby facilitating the integration of the PCM device 600, and other advantages. Various other advantages and benefits of the TiSiN-included electrode 620 described above with respect to FIG. 5 can be realized in the PCM device 600, and details relating to these advantages and benefits are omitted herein for the sake of brevity.

[0074] In some embodiments, the top electrode 650 comprises TiSiN according to embodiments to further enhance the resistive heating, thermal insulation, diffusion barrier properties, and / or switching parameter uniformity of the phase change storage element 610 in a manner similar to that described above. Although not shown, a top metallization line may be formed on the top electrode 650 and may comprise Al, Cu, and W, as well as other suitable materials. Thus, the electrode 620 may serve as a diffusion barrier against contamination between the phase change storage element 610 and the selector device 630 on one side of the phase change storage element 610, and the top electrode 650 may serve as a diffusion barrier against contamination between the phase change storage element 610 and the top metallization line 670 on the other side of the phase change storage element 610.

[0075] However, the top electrode 650 may be formed of any other suitable electrode material, to name a few, including: carbon (C); n-doped polycrystalline silicon and p-doped polycrystalline silicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, W and WN; conductive metal nitrides including TiN, TaN, WN and TaCN; conductive metal silicides including tantalum silicon, tungsten silicon, nickel silicon, cobalt silicon and titanium silicon; and conductive metal oxides including RuO2.

[0076] Examples of suitable materials for the top metallization line 670 include Al, Cu and W, as well as other suitable materials, and in a manner similar to how the electrode 620 serves as an effective diffusion barrier between the phase change storage element 610 and the selector device 630, including the top electrode 650 of TiSiN according to the embodiment, which can serve as an effective diffusion barrier between the phase change storage element 610 and the metallization line 670.

[0077] Although the present invention has been described herein with reference to specific embodiments, these embodiments are not intended to limit the invention and are set forth for illustrative purposes. Those skilled in the art will understand that modifications and improvements can be made without departing from the spirit and scope of the invention.

[0078] Such simple modifications and improvements to the various embodiments disclosed herein are within the scope of the present invention, and furthermore, the specific scope of the present invention will be defined by the appended claims.

[0079] As will be understood from the foregoing, any feature of any embodiment may be combined with or replaced by any other feature of any other embodiment.

[0080] Unless otherwise clearly required by the background context, the words "comprise / comprising," "include / including," and similar terms throughout the description and scope of the invention claim shall be interpreted as encompassing, the opposite of exclusive or exhaustive; that is, as "including but not limited to." As commonly used herein, the word "coupled" refers to two or more elements that can be directly connected or connected by one or more intermediate elements. Similarly, as commonly used herein, the word "connected" refers to two or more elements that can be directly connected or connected by one or more intermediate elements. Furthermore, the words "in this document," "above," "below," and similar terms, when used in this application, shall refer to the entire application and not any particular part of the application. Where the background context permits, the use of singular or plural terms in the [Implementation] section above may also include both singular and plural terms respectively. The word "or" in relation to a list of two or more items covers all of the following interpretations: any one of the items in the list, all the items in the list, and any combination of the items in the list.

[0081] Furthermore, unless otherwise expressly stated or otherwise understood within the context of the context in which they are used, the conditional language used herein (especially terms such as "can / could," "might," "may," "eg / for example," "such as," and the like) is generally intended to convey that certain embodiments include certain features, elements, and / or states that are not included in other embodiments. Therefore, this conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any case, or whether such features, elements, and / or states are included in or performed in any particular embodiment.

[0082] Although certain embodiments have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. In fact, the novel apparatuses, methods, and systems described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the invention. For example, although features are presented in a given configuration, alternative embodiments may perform similar functionality using different components and / or sensor morphologies, and some features may be deleted, moved, added, subdivided, combined, and / or modified. These features may be implemented in many different ways. Any suitable combination of elements and actions of the various embodiments described above may be combined to provide further embodiments. The various features and procedures described above may be implemented independently of each other or may be combined in various ways. All possible combinations and sub-combinations of the features of the invention are intended to fall within the scope of the invention. [Simplified Explanation of the Diagram]

[0008] Embodiments of the present invention will now be described with reference to the accompanying drawings by way of non-limiting examples.

[0009] Figure 1 schematically illustrates a phase-change memory device according to an embodiment.

[0010] Figure 2 schematically illustrates an example access operation that can be performed on a phase-change memory device.

[0011] Figure 3A is a flowchart illustrating a method for manufacturing a phase-change memory device according to an embodiment.

[0012] Figure 3B is a flowchart illustrating a method for forming a diffusion barrier including TiSiN according to an embodiment.

[0013] Figure 3C is a diagram illustrating a method for forming a diffusion barrier including TiSiN according to an embodiment.

[0014] Figure 4 is a graph of resistivity measured experimentally according to the embodiment, which varies with the silicon content of the diffusion barrier layer including TiSiN.

[0015] Figure 5 is an example of a phase change memory cell comprising a phase change storage element formed on a TiSiN electrode configured as a heater electrode, according to an embodiment.

[0016] Figure 6 is an example of a phase change memory cell comprising a phase change storage element formed on an electrode including TiSiN, according to an embodiment.

Claims

1. A method for forming a diffusion barrier for an integrated circuit device, the method comprising: By exposing a substrate to one or more vapor deposition cycles to form a diffusion barrier including titanium silicon nitride (TiSiN), each of the vapor deposition cycles includes alternating exposure to one or more first deposition stages, followed by one or more second deposition stages, wherein each of the one or more first deposition stages includes sequentially exposing the substrate to alternating titanium (Ti) precursor and nitrogen (N) precursor, wherein each of the one or more second deposition stages includes sequentially exposing the substrate to alternating silicon (Si) precursor and nitrogen (N) precursor, and wherein in at least one of the first deposition stages, after exposure to the Ti precursor, exposure to the N precursor is performed without exposure to the Si precursor in between.

2. The method of claim 1, wherein forming the diffusion barrier includes exposing the substrate to one or more vapor deposition cycles at a temperature below 400°C.

3. The method of claim 1, wherein forming the diffusion barrier includes exposing the substrate to one or more vapor deposition cycles at a temperature above 200°C and below 400°C.

4. The method of claim 1, wherein the diffusion barrier is at least partially amorphous.

5. The method of claim 1, wherein forming the diffusion barrier includes adjusting the silicon concentration such that the diffusion barrier has a resistivity between about 500 μΩ-cm and about 30,000 μΩ-cm.

6. The method of claim 1, wherein the diffusion barrier has a silicon concentration of more than about 5 atomic percent.

7. The method of claim 1, wherein the Si precursor system is selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8.

8. The method of claim 1, wherein the substrate includes vias or trenches formed through an insulating layer, and wherein forming the diffusion barrier includes filling the vias or trenches by continuously growing a conformal TiSiN layer.

9. The method of claim 1, wherein at least some of the first deposition stages locally form TiN.

10. The method of claim 1, wherein at least some of the second deposition stages locally form SiN.

11. A method for forming an integrated circuit structure, the method comprising: A diffusion barrier layer comprising titanium silicon nitride (TiSiN) is formed on a substrate by exposing it to one or more vapor deposition cycles at a temperature between 200°C and 390°C. Each of the one or more vapor deposition cycles includes exposure to one or more of a titanium (Ti) precursor, a nitrogen (N) precursor, and a silicon (Si) precursor. In each of the one or more vapor deposition cycles, after exposure to the Si precursor, at least one of the N precursors is exposed, without exposure to the Ti precursor in between. Metallization lines are formed on the diffusion barrier layer.

12. The method of claim 11, wherein the substrate includes a trench, and wherein forming the diffusion barrier layer includes lining the trench with the diffusion barrier layer.

13. The method of claim 11, wherein the metallization line includes word lines for non-volatile memory devices.

14. The method of claim 11, wherein forming the diffusion barrier layer includes forming it by thermal atomic layer deposition without the addition of plasma.

15. The method of claim 11, wherein the Si precursor system is selected from the group consisting of SiH4, Si2H6, SiH2Cl2, SiH3Cl, Si2Cl6 and Si3Cl8.

16. The method of claim 11, wherein exposing the substrate to the one or more vapor deposition cycles comprises: The substrate is exposed to one or more first deposition stages, each of which includes exposure to the Ti precursor and exposure to the N precursor; and the substrate is exposed to one or more second deposition stages, each of which includes exposure to the Si precursor.

17. The method of claim 16, wherein each of the second deposition stages further includes further exposure to the N precursor.

18. The method of claim 16, wherein the TiSiN is at least partially amorphous.

19. The method of claim 16, wherein at least some of the first deposition stages locally form TiN.

20. The method of claim 16, wherein at least some of the second deposition stages locally form SiN.

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