Resistive random access memory device
Patent Information
- Application Number
- TW114109859
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2026-10-11
- Estimated Expiration
- 2045-03-16
Smart Images

Figure TWG2TB001915376_001 
Figure TWG2TB001915376_002 
Figure TWG2TB001915376_003
Abstract
Claims
1. A resistive random access memory, characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; a lower electrode disposed on the contact plug; an impedance conversion layer disposed on the lower electrode; and a cover layer disposed on the impedance conversion layer, wherein the cover layer comprises one or more cover layers and the one or more cover layers comprise ruthenium dioxide (RuO2) with an oxygen concentration gradient.
2. The resistive random access memory as described in claim 1, wherein the masking layer comprises: a first masking layer disposed on the impedance conversion layer; and a second masking layer disposed on the first masking layer.
3. The resistive random access memory as described in claim 2, wherein the first cover layer comprises ruthenium dioxide and the second cover layer comprises ruthenium.
4. The resistive random access memory as described in claim 1, wherein the cover layer comprises: a first cover layer disposed on the impedance conversion layer; a second cover layer disposed on the first cover layer; and a third cover layer disposed on the second cover layer.
5. The resistive random access memory as described in claim 4, wherein the first masking layer comprises ruthenium dioxide.
6. The resistive random access memory as described in claim 4, wherein the second overlay layer comprises ruthenium.
7. The resistive random access memory as described in claim 4, wherein the third overlay layer comprises ruthenium dioxide.
8. The resistive random access memory as described in claim 1, further comprising: an upper electrode disposed on the cover layer; a first intermetallic dielectric layer surrounding the upper electrode; a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer; and a metal interconnect disposed in the second intermetallic dielectric layer and connected to the upper electrode.
9. A resistive random access memory, characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; a lower electrode disposed on the contact plug; an impedance conversion layer disposed on the lower electrode; and a cover layer disposed on the impedance conversion layer, wherein the cover layer comprises ruthenium dioxide (RuO2) with an oxygen concentration gradient.
10. The resistive random access memory as described in claim 9, wherein the masking layer comprises: a first masking layer disposed on the impedance conversion layer; and a second masking layer disposed on the first masking layer.
11. The resistive random access memory as described in claim 10, wherein the first masking layer contains ruthenium dioxide and does not contain an oxygen concentration gradient.
12. The resistive random access memory as described in claim 10, wherein the second overlay layer contains ruthenium dioxide and contains an oxygen concentration gradient.
13. The resistive random access memory as described in claim 12, wherein the surface near the bottom of the second overlay contains a higher concentration of oxygen.
14. The resistive random access memory as described in claim 10, wherein the first masking layer comprises ruthenium dioxide and contains an oxygen concentration gradient.
15. The resistive random access memory as described in claim 14, wherein the area near the bottom surface of the first overlay layer contains a higher concentration of oxygen.
16. The resistive random access memory as described in claim 10, wherein the second overlay layer comprises ruthenium.
17. The resistive random access memory as described in claim 9, wherein the overlay layer comprises a single-layer structure.
18. The resistive random access memory as described in claim 17, wherein the area near the bottom surface of the cover layer contains a higher concentration of oxygen.
Citation Information
Patent Citations
Rare earth metal & metal oxide electrode interfacing of oxide memory element in resistive random access memory cell
TW201633512A
Integrated chip and method for forming an integrated chip
TW202510694A
