Resistive random access memory device

Abstract

This invention discloses a resistive random access memory, which mainly includes an interlayer dielectric layer disposed on a substrate, a contact plug disposed within the interlayer dielectric layer, a lower electrode disposed on the contact plug, an impedance conversion layer disposed on the lower electrode, and an upper electrode disposed on the impedance conversion layer, wherein the upper electrode includes more than one upper electrode and the more than one upper electrode includes titanium nitride.

Claims

1. A resistive random access memory, characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; a lower electrode disposed on the contact plug; an impedance conversion layer disposed on the lower electrode; and an upper electrode disposed on the impedance conversion layer, wherein the upper electrode comprises one or more upper electrodes and the one or more upper electrodes comprise titanium nitride, and the titanium nitride comprises a nitrogen concentration gradient, and the nitrogen concentration near the impedance conversion layer is higher than the nitrogen concentration away from the impedance conversion layer.

2. The resistive random access memory as described in claim 1, wherein the upper electrode comprises: a first upper electrode disposed on the impedance conversion layer; and a second upper electrode disposed on the first upper electrode.

3. The resistive random access memory as described in claim 2, wherein the first upper electrode comprises titanium nitride and the second upper electrode comprises titanium.

4. The resistive random access memory as described in claim 1, wherein the upper electrode comprises: a first upper electrode disposed on the impedance conversion layer; a second upper electrode disposed on the first upper electrode; and a third upper electrode disposed on the second upper electrode.

5. The resistive random access memory as described in claim 4, wherein the first upper electrode comprises titanium nitride.

6. The resistive random access memory as described in claim 4, wherein the second upper electrode comprises titanium.

7. The resistive random access memory as described in claim 4, wherein the third upper electrode comprises titanium nitride.

8. The resistive random access memory as described in claim 1, further comprising: a cover layer disposed next to the upper electrode; a first intermetallic dielectric layer surrounding the cover layer; a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer; and a metal interconnect disposed in the second intermetallic dielectric layer and connected to the upper electrode.

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