Memory device and method for forming the same

TWI942211BActive Publication Date: 2026-10-11POWERCHIP SEMICON MFG CORP
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Patent Information

Application Number
TW114111979
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-03-28
Publication Date
2026-10-11
Estimated Expiration
2045-03-27

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  • Figure TWG2TB001915388_001
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    Figure TWG2TB001915388_002
  • Figure TWG2TB001915388_003
    Figure TWG2TB001915388_003
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Abstract

This disclosure provides a memory device and a method for forming the same. The memory device includes memory cells, and each memory cell includes a bottom electrode, a variable resistance layer, an oxygen trapping layer, and a top electrode. The bottom electrode is disposed on a substrate. The variable resistance layer is disposed on the bottom electrode. The oxygen trapping layer is disposed on the variable resistance layer. The top electrode structure is disposed on the oxygen trapping layer and includes a top electrode adjacent to the oxygen trapping layer and a conductive top cap layer disposed on the top electrode, wherein the resistance of the conductive top cap layer is greater than the resistance of the top electrode.
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Claims

1. A memory device comprising a plurality of memory cells, each memory cell comprising: The bottom electrode is disposed on the substrate; A variable resistance layer is disposed on the bottom electrode; An oxygen trapping layer is disposed on the variable resistance layer; The memory device further includes: a top electrode structure disposed on the oxygen trapping layer and including a top electrode adjacent to the oxygen trapping layer and a conductive top cap layer disposed on the top electrode, wherein the resistance of the conductive top cap layer is greater than the resistance of the top electrode; an air gap disposed on the substrate and between the plurality of memory cells; a first dielectric layer disposed on the substrate and conformally covering the top surface and sidewalls of the plurality of memory cells; and a second dielectric layer disposed on the first dielectric layer and positioned above the top electrode structure to define, with respect to, the space in which the air gap is formed.

2. The memory device as claimed in claim 1, wherein the top electrode comprises titanium nitride (TiN) and the conductive capping layer comprises tantalum nitride (TaN).

3. The memory device as claimed in claim 1, wherein the top electrode comprises nitrogen-rich titanium nitride (TiN).

4. A memory device comprising a plurality of memory cells, each memory cell comprising: The bottom electrode is disposed on the substrate; A variable resistance layer is disposed on the bottom electrode; An oxygen trapping layer is disposed on the variable resistance layer; The memory device further includes: a top electrode disposed on the oxygen trapping layer and comprising nitrogen-rich titanium nitride (TiN); an air gap disposed on the substrate and between the plurality of memory cells; a first dielectric layer disposed on the substrate and conformally covering the top surface and sidewalls of the plurality of memory cells; and a second dielectric layer disposed on the first dielectric layer and positioned above the top electrode to define, together with the first dielectric layer, the space in which the air gap is formed.

5. The memory device as claimed in claim 4, wherein in the nitrogen-rich titanium nitride (TiN), the molar ratio of N to Ti (N / Ti) is greater than or equal to 1 and less than or equal to 10.

6. A method of forming a memory device, comprising: A plurality of memory cells are formed on a substrate, each memory cell comprising: a bottom electrode formed on the substrate; a variable resistance layer formed on the bottom electrode; an oxygen trapping layer formed on the variable resistance layer; and a top electrode formed on the oxygen trapping layer; a first dielectric layer conformally covering the top surface and sidewalls of the plurality of memory cells is formed on the substrate; a sacrificial material layer is formed on the first dielectric layer, wherein the sacrificial material layer is formed above the substrate and between the plurality of memory cells; a second dielectric layer is formed on the first dielectric layer and the sacrificial material layer; and the sacrificial material layer is removed to form an air gap between the plurality of memory cells.

7. The method of claim 6, wherein the top electrode is made of nitrogen-rich titanium nitride (TiN).

8. The method of claim 7, wherein in the nitrogen-rich titanium nitride (TiN), the molar ratio of N to Ti (N / Ti) is greater than or equal to 1 and less than or equal to 10.

9. The method of claim 6, wherein each memory cell includes a conductive capping layer formed on the top electrode, and the conductive capping layer is made of a material with a resistance greater than that of the top electrode.

Citation Information

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