Display driver and operating method thereof, and display panel

Abstract

A method of operating a display driver for driving a display panel. The display panel includes a plurality of pixel circuits arranged on a plurality of display lines. The method of operating the display driver includes: providing an initial voltage having a reference value to the pixel circuits during at least one refresh frame; and providing an initial voltage having a plurality of different voltage values ​​to the pixel circuits during at least one non-refresh frame. The plurality of different voltage values ​​of the initial voltage respectively correspond to the distances between the plurality of display lines and the display driver.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a display driver, a method of operating the same, and a display panel. Prior Technology

[0002] Generally, display drivers are suitable for driving display panels. Figure 1 is a schematic diagram of the operation of a display driver according to related technologies. In Figure 1, the horizontal axis represents the current operating time of the display driver, and the vertical axis represents the voltage value.

[0003] Referring to Figure 1, during frames FAV and FSK, the display driver provides signals (e.g., voltages Vini_P1 or Vini_P2) to the display panel to drive the pixel circuitry of the display panel. However, because the provided signals have different voltage values, the coupling voltage and hysteresis characteristics of the pixel circuitry affect the operating nodes between them. Therefore, flickering issues occur in the display panel. Summary of the Invention

[0004] This invention provides a method for operating a display driver that can reduce flickering issues in display panels.

[0005] The present invention discloses an operation method for a display driver, used to drive a display panel. The display panel includes a plurality of pixel circuits arranged on a plurality of display lines. The operation method of the display driver includes: providing an initial voltage having a reference value to the pixel circuits during at least one refresh frame; and providing an initial voltage having a plurality of different voltage values ​​to the pixel circuits during at least one non-refresh frame. The plurality of different voltage values ​​of the initial voltage respectively correspond to the distances between the plurality of display lines and the display driver.

[0006] The display driver of this invention includes a digital-to-analog converter and an output stage circuit. The digital-to-analog converter generates an initial voltage with a reference value and generates initial voltages with multiple different voltage values ​​based on the distances between multiple display lines and the display driver. The output stage circuit is coupled to the digital-to-analog converter and multiple pixel circuits arranged in the display lines. The output stage circuit outputs the initial voltage with the reference value to the pixel circuits during at least one refresh frame and outputs the initial voltages with multiple different voltage values ​​to the pixel circuits during at least one non-refresh frame.

[0007] The display panel of this invention includes a plurality of pixel circuits, a digital-to-analog converter, and an output stage circuit. The pixel circuits are arranged in a plurality of display lines. The digital-to-analog converter generates an initial voltage with a reference value and generates an initial voltage with multiple different voltage values ​​depending on the distance between the display lines and the display driver. The output stage circuit is coupled to the digital-to-analog converter and the pixel circuits. The output stage circuit outputs the initial voltage with the reference value to the pixel circuits during at least one refresh frame and outputs the initial voltage with multiple different voltage values ​​to the pixel circuits during at least one non-refresh frame.

[0008] Based on the above, in the display driver and its operating method and display panel of the embodiments of the present invention, by providing initial voltages with different voltage values ​​to the pixel circuits corresponding to each display line, the different voltage values ​​are compensated to the corresponding pixel circuits in each region. Therefore, during non-refresh frames, the display driver can reduce voltage differences affecting the pixel circuits, thereby reducing flicker and improving the uniformity of the display panel.

[0009] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0010] Figure 1 is a schematic diagram of the operation of a display driver according to related technologies. Figure 2 is a circuit block diagram of a display panel according to an embodiment of the present invention. Figure 3 is a flowchart of an operation method of a display driver according to an embodiment of the present invention. Figure 4 is a circuit block diagram of a display panel according to another embodiment of the present invention. Figure 5 is a circuit block diagram of the pixel circuit of the display panel in the embodiment of Figure 4. Figure 6 is a schematic diagram of the operation of the display panel in the embodiment of Figure 5. Figure 7 is a schematic diagram of the operation of the display panel in the embodiment of Figure 5 during a non-refresh frame. Figure 8 is a circuit block diagram of a display driver according to an embodiment of the present invention. Figure 9 is a schematic diagram of the operation of the display driver in the embodiment of Figure 8. Figure 10 is a schematic diagram of the operation of the display panel according to another embodiment of the present invention. Figure 11 is a schematic diagram of the operation of the display panel according to another embodiment of the present invention. Figure 12 is a schematic diagram of the operation of the display panel according to another embodiment of the present invention. Implementation

[0011] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Reference numerals used in the following description, when appearing in different drawings, are considered to be the same or similar elements. The embodiments are only a part of the present invention and do not disclose all embodiments of the invention. That is, the embodiments are merely exemplary embodiments of the present invention.

[0012] Figure 2 is a circuit block diagram of a display panel according to an embodiment of the present invention. Referring to Figure 2, the display panel 200 is implemented, for example, using low-temperature polycrystalline oxide (LTPO) technology. The display panel 200 includes a display driver 210 and a plurality of pixel circuits 221 to 22N and 22M1 to 22MN. N is an integer greater than 2, and M is an integer greater than 1. The pixel circuits 221 to 22N and 22M1 to 22MN are coupled to the display driver 210. The pixel circuits 221 to 22N and 22M1 to 22MN are arranged in an array and have the same circuit architecture. The pixel circuits 221 to 22N and 22M1 to 22MN are arranged in a plurality of display lines L1 to LN. The display lines L1 to LN may correspond to columns (rows) of the array.

[0013] In this embodiment, the display driver 210 is adapted to drive the display panel 200. The display driver 210 may be, for example, a display driver integrated circuit (DDIC). In this embodiment, the display driver 210 includes a digital-to-analog converter (DAC) 211 and an output stage circuit 212. The DAC 211 is coupled to the output stage circuit 212. The output stage circuit 212 is coupled to pixel circuits 221 to 22N and 22M1 to 22MN.

[0014] Figure 3 is a flowchart of a display driver operation method according to an embodiment of the present invention. Referring to Figures 2 and 3, the display driver 210 can perform the following steps S210 and S220. The order of steps S210 and S220 is for illustrative purposes only, and the present invention is not limited thereto.

[0015] In step S210, during at least one refresh frame, the display driver 210 provides an initial voltage Vinit with a reference value to the pixel circuits 221 to 22N and 22M1 to 22MN. Specifically, the digital-to-analog converter 211 generates the initial voltage Vinit with the reference value. During the refresh frame, the output stage circuit 212 outputs the initial voltage Vinit to the pixel circuits 221 to 22N and 22M1 to 22MN.

[0016] Furthermore, during the refresh frame, the display driver 210 refreshes the display screen of the display panel 200 according to the initial voltage Vinit with a reference value and multiple control signals SCs.

[0017] In this embodiment, the initial voltage Vinit can be the bias signal for pixel circuits 221 to 22N and 22M1 to 22MN. The reference value of the initial voltage Vinit can be a constant value. The control signal SCs can be a signal that controls the pixel circuits 221 to 22N and 22M1 to 22MN to turn on and off.

[0018] In other words, during the refresh frame, based on the initial voltage Vinit with a reference value, the pixel circuits 221 to 22N and 22M1 to 22MN operate according to the control signal SCs to refresh the current display screen.

[0019] In step S220, during at least one non-refresh frame, the display driver 210 provides an initial voltage Vinit with multiple different voltage values ​​to the pixel circuits 221 to 22N and 22M1 to 22MN, depending on the distance between the display lines L1 to LN and the display driver 210. Specifically, the digital-to-analog converter 211 generates initial voltage Vinit with different voltage values ​​based on the distance between the display lines L1 to LN and the display driver 210. During the non-refresh frame, the output stage circuit 212 outputs the initial voltage Vinit to the pixel circuits 221 to 22N and 22M1 to 22MN.

[0020] In other words, during non-refresh frames, based on the initial voltage Vinit with different voltage values, the pixel circuits 221 to 22N and 22M1 to 22MN operate according to the control signal SCs to not refresh the current display screen.

[0021] In this embodiment, the different initial voltage values ​​of Vinit can be different constant values ​​and different from the reference value in step S210. Furthermore, the different initial voltage values ​​of Vinit correspond to the distances between display lines L1 to LN and the display driver 210. Since display lines L1 to LN correspond to the columns of pixel circuits 221 to 22N and 22M1 to 22MN respectively, the distances between display lines L1 to LN and the display driver 210 are not the same.

[0022] For example, relative to the display driver 210, pixel circuits 221 and 22M1 arranged on display line L1 are located in the far-end region of the display panel 200. Pixel circuits 22N and 22MN arranged on display line LN are located in the near-end region of the display panel 200. During non-refresh frames, pixel circuits 221 and 22M1 operate based on an initial voltage Vinit having a voltage value corresponding to display line L1. During non-refresh frames, pixel circuits 22N and 22MN operate based on an initial voltage Vinit having a different voltage value corresponding to display line LN.

[0023] It is worth mentioning that, since different initial voltage values ​​of Vinit correspond to different distances between display lines L1 to LN and display driver 210, these different voltage values ​​can respectively compensate for the pixel circuits 221 to 22N and 22M1 to 22MN arranged in display lines L1 to LN. Therefore, the pixel circuits 221 to 22N and 22M1 to 22MN in each region of the display panel 200 (e.g., near-end region and far-end region) operate based on the compensated voltage during non-refresh frames. In this way, during non-refresh frames, display driver 210 can reduce the load on pixel circuits 221 to 22N and 22M1 to 22MN caused by voltage differences between different frames and the distances between display lines L1 to LN and display driver 210. Therefore, with the load reduced, display driver 210 can prevent the operating nodes in pixel circuits 221 to 22N and 22M1 to 22MN from being affected, thereby reducing flicker and improving the uniformity of the display screen.

[0024] Figure 4 is a block diagram of a display panel circuit according to another embodiment of the present invention. Referring to Figure 4, the display panel 400 includes a display driver 410 and a plurality of pixel circuits 421 to 42N and 42M1 to 42MN. N is an integer greater than 4, and M is an integer greater than 3. The operation of the display driver 410 and the pixel circuits 421 to 42N and 42M1 to 42MN can be deduced from that of the display panel 200.

[0025] In the embodiment of FIG4, the display panel 400 further includes a gate driving circuit 430. The gate driving circuit 430 is coupled to the display driver 410 and pixel circuits 421 to 42N and 42M1 to 42MN. The gate driving circuit 430 outputs multiple control signals SCs to the pixel circuits 421 to 42N and 42M1 to 42MN to control the on and off states of the pixel circuits 421 to 42N and 42M1 to 42MN. The gate driving circuit 430 may be a gate-on-array (GOA) driver. In another embodiment, the gate driving circuit 430 may be integrated with the display driver 410.

[0026] Referring to Figures 4 and 5, Figure 5 is a circuit block diagram of the display panel pixel circuit of the embodiment of Figure 4. In Figure 5, one of the pixel circuits 421 to 42N and 42M1 to 42MN (e.g., pixel circuit 421) is shown; the other pixel circuits 422 to 42N and 42M1 to 42MN are not shown. The other pixel circuits 422 to 42N and 42M1 to 42MN can be deduced from pixel circuit 421, and so on.

[0027] In the embodiment of FIG5, the pixel circuit 421 includes a data writing circuit 510, a light-emitting driving circuit 520, and a light-emitting circuit 530. The data writing circuit 510 is coupled to the gate driving circuit 430 to receive multiple control signals PSTV1, NSTV1, and NSTV2 in the control signals SCs. The data writing circuit 510 is coupled to the display driver 410 to receive the initial voltage Vinit1. The data writing circuit 510 processes the display data of node Q according to the control signals NSTV1, NSTV2, and PSTV1 and the initial voltage Vinit1. Node Q can be the operating node of the pixel circuit 421 in the embodiments of FIG2 and FIG3.

[0028] In this embodiment, the light-emitting driving circuit 520 is coupled to the data writing circuit 510 at node Q. The light-emitting driving circuit 520 is coupled to the gate driving circuit 430 to receive multiple control signals EMSTV and HSTV from the control signals SCs. The light-emitting driving circuit 520 is coupled to the display driver 410 to receive the initial voltage Vinit3. Based on the display data at node Q, the light-emitting driving circuit 520 drives the light-emitting circuit 530 according to the control signals EMSTV and HSTV and the initial voltage Vinit3.

[0029] In this embodiment, the light-emitting circuit 530 is coupled to the light-emitting driving circuit 520. The light-emitting circuit 530 is coupled to the gate driving circuit 430 to receive the control signal HSTV. The light-emitting circuit 530 is coupled to the display driver 410 to receive the initial voltage Vinit2. The light-emitting circuit 530 emits corresponding brightness changes according to the control signal HSTV and the initial voltage Vinit2.

[0030] It should be noted that, since the display panel 400 operates in various frames (e.g., refresh frames, non-refresh frames) to refresh and not refresh the currently displayed screen, when the display panel 400 switches from one frame to another, at least one of the control signals NSTV1, NSTV2, and PSTV1 and the initial voltages Vinit1 to Vinit3 has a voltage difference between frames. In each pixel circuit (e.g., pixel circuit 421), the voltage difference in the data writing circuit 510 and the light-emitting driving circuit 520 can be coupled to the working node Q.

[0031] Furthermore, since the pixel circuits 421 to 42N and 42M1 to 42MN are at different distances from the display driver 410, there is a voltage difference between the pixel circuits 421 to 42N and 42M1 to 42MN at their corresponding nodes (e.g., node Q). In each pixel circuit (e.g., pixel circuit 421), this voltage difference can also be coupled to the operating node Q.

[0032] For example, relative to the display driver 410, the pixel circuits 421 arranged in display line L1 are located in the far-end region of the display panel 400, while the pixel circuits 42N arranged in display line LN are located in the near-end region of the display panel 400. During each frame, current from pixel circuit 421 can flow along current resistance path IRP1, and current from pixel circuit 42N can flow along current resistance path IRP2. Because current resistance paths IRP1 and IRP2 are different, the current resistance voltage drop (IR drop) of pixel circuit 421 and pixel circuit 42N are different, resulting in different coupling voltages at corresponding nodes (e.g., node Q) of pixel circuits 421 and 42N.

[0033] Taking pixel circuit 421 as an example, the voltage of node Q affects the operation of data writing circuit 510 and light-emitting driving circuit 520, thereby affecting the light emitted by light-emitting circuit 530. In order to compensate for the different voltages of nodes Q in pixel circuits 421 to 42N and 42M1 to 42MN, display driver 410 provides at least one initial voltage among initial voltages Vinit1 to Vinit3 with step voltage values ​​during each frame (e.g., non-refresh frame).

[0034] Referring to Figures 4 to 6, Figure 6 is a schematic diagram of the operation of the display panel in the embodiment of Figure 5. In Figure 6, the horizontal axis represents the operation time of the display panel 400, and the vertical axis represents the voltage value. The initial voltages Vinit1 and Vinit3 are not shown in Figure 6. The initial voltages Vinit1 and Vinit3 can be the same as the initial voltage Vinit2, and can be deduced by referring to the initial voltage Vinit2.

[0035] In the embodiment of FIG6, the display panel 400 operates during refresh frame FAV (e.g., from time t1 to t2) according to control signals PSTV1, NSTV1, NSTV2, HSTV and EMSTV and initial voltages Vinit1 to Vinit3 to refresh the current display screen.

[0036] Specifically, during the refresh frame FAV (i.e., from time t1 to t2), control signals PSTV1, NSTV1, and NSTV2 each have at least one pulse that switches between voltage values ​​V1 and V2. During the refresh frame FAV, control signal HSTV has a pulse that switches between voltage values ​​V1 and V2, and control signal EMSTV can be a pulse signal that switches between voltage values ​​V1 and V2. During the refresh frame FAV, the initial voltage Vinit2 can be a fixed voltage with a reference value VREF.

[0037] In this embodiment, voltage value V1 can be a low power supply voltage value. Voltage value V2 can be a high power supply voltage value. Reference value VREF can be another low power supply voltage value different from voltage value V1.

[0038] Therefore, during the refresh frame FAV (i.e., from time t1 to t2), the data writing circuit 510 begins writing display data at node Q based on the pulses of control signals PSTV1, NSTV1, and NSTV2, using an initial voltage Vinit1 with a reference value VREF. During the refresh frame FAV, the light-emitting drive circuit 520 and the light-emitting circuit 530 begin resetting electronic components (e.g., transistors) based on the pulses of control signal HSTV, using initial voltages Vinit3 and Vinit2 with reference values ​​VREF. Then, the light-emitting drive circuit 520 begins driving the light-emitting circuit 530 based on the control signal EMSTV, using an initial voltage Vinit3 with a reference value VREF, causing the light-emitting circuit 530 to emit light based on an initial voltage Vinit2 with a reference value VREF, thereby refreshing the current display screen.

[0039] Next, the display panel 400 operates during the non-refresh frame FSK period (e.g., from time t2 to t3) according to control signals PSTV1, NSTV1, NSTV2, HSTV and EMSTV and initial voltages Vinit1 to Vinit3, in order to maintain the display of the current display screen and not refresh the current display screen.

[0040] Specifically, during the non-refresh frame FSK (i.e., from time t2 to t3), the control signal PSTV1 can be a fixed voltage with a voltage value V2, and the control signals NSTV1 and NSTV2 can each be a fixed voltage with a voltage value V1. During the non-refresh frame FSK, the control signals HSTV and EMSTV can be the same as the control signals HSTV and EMSTV during the refresh frame FAV, respectively.

[0041] Furthermore, during the non-refresh frame FSK, the initial voltage Vinit2 can be a step voltage switching from voltage value V3 to voltage value V4. Specifically, at time t2, the initial voltage Vinit2 switches from the reference value VREF to voltage value V3 to create a falling edge. From time t2 to time t3, the voltage value of the initial voltage Vinit2 gradually increases from voltage value V3 to voltage value V4, making the initial voltage Vinit2 approximately a sloping line. At time t3, the initial voltage Vinit2 switches from voltage value V4 to the reference value VREF to create a rising edge.

[0042] In this embodiment, during a non-refresh frame FSK (e.g., at time t2), the display driver 410 provides an initial voltage Vinit2 with a voltage value V3 to the pixel circuits 421 arranged in display line L1. During the same non-refresh frame FSK (e.g., at time t3), the display driver 410 provides an initial voltage Vinit2 with another voltage value V4 to the pixel circuits 42N arranged in display line LN. Pixel circuits 421 and 42N are arranged in the same column COL1 and different columns. These columns correspond to display lines L1 and LN, respectively, and further correspond to the far-end region and near-end region corresponding to the display driver 410, respectively.

[0043] Subsequently, voltage value V3 is arranged in display line L1. Voltage value V4 is arranged in display line LN. Voltage values ​​V3 and V4 are different from the reference value VREF. Voltage values ​​V3 and V4 are based on the column configuration of display lines L1 to LN and are different from each other. Specifically, the distance between display line L1 and display driver 410 is greater than the distance between display line LN and display driver 410.

[0044] In this embodiment, the display panel 400 can repeatedly operate during another refresh frame FAV (e.g., from time t3 to t4) and another non-refresh frame FSK.

[0045] Figure 7 is a schematic diagram of the operation of the display panel of the embodiment of Figure 5 during a non-refresh frame. Referring to Figures 5 to 7, the display panel 400 operates during the non-refresh frame FSK (i.e., from time t2 to t3) to illustrate how node Q of pixel circuit 421 is compensated by an initial voltage Vinit2 with different voltage values ​​(e.g., voltage values ​​V3 and V4). In Figure 7, the horizontal axis represents the operation time of the display panel 400, and the vertical axis represents the voltage values.

[0046] In the embodiment of Figure 7, during the non-refresh frame FSK (i.e., from time t2 to t3), the signal VGLO indicates the difference between the control signals NSTV1 or NSTV2 between the refresh frame FAV and the non-refresh frame FSK. The signal VGLO switches from voltage value VH to voltage value VL at time t2 and switches back to voltage value VH at time t3. In this embodiment, the voltage difference between voltage values ​​VH and VL may include the voltage difference between the voltage values ​​V1 and V2 of the control signals NSTV1 or NSTV2, as well as the IR load of the pixel circuit 421.

[0047] Therefore, during the non-refresh frame FSK (i.e., from time t2 to t3), based on the signal VGLO, the voltage VQ at node Q gradually decreases from voltage value V6 to voltage value V5. At time t3, entering the next refresh frame, voltage VQ switches from voltage value V5 to voltage value VD. Voltage value VD is the correct voltage value written to node Q during the non-refresh frame FSK. During the non-refresh frame FSK, voltage VQ with voltage value VD is interfered with by the signal VGLO, resulting in a coupling voltage. This coupling voltage may be voltage value V5 or V6, depending on the column configuration of the corresponding display lines L1 to LN.

[0048] In this embodiment, during the non-refresh frame FSK (i.e., from time t2 to t3), the voltage difference shown in the signal VGLO is compensated to node Q by providing an initial voltage Vinit2 with different voltage values ​​(e.g., including voltage values ​​V3 and V4). Therefore, the compensated voltage VQ' at node Q is a fixed voltage with a voltage value VD. Thus, the light-emitting driving circuit 520 and the light-emitting circuit 530 can operate based on the voltage VQ' with a fixed voltage value VD to maintain the brightness of the pixel circuit 421 during the same frame. The voltage VQ' with a fixed voltage value VD represents the consistency of brightness.

[0049] It should be noted that during the non-refresh frame FSK (i.e., from time t2 to t3), the absolute values ​​of the different voltage values ​​of the initial voltage Vinit2 are positively correlated with the distance between display lines L1 to LN and the display driver 410. In other words, the absolute value of the initial voltage Vinit2 gradually decreases from the far end region to the near end region of the display panel 400.

[0050] For example, for pixel circuit 421 arranged in the far region, relative to pixel circuit 42N arranged in the near region, the absolute value of voltage value V3 is greater than the absolute value of voltage value V4 based on the larger distance between display line L1 and display driver 410.

[0051] Figure 8 is a circuit block diagram of a display driver according to an embodiment of the present invention. Referring to Figure 8, the display driver 810 is adapted to drive a display panel (e.g., the display panel 400 shown in Figure 4). The display driver 810 includes a timing controller 811 and a bias controller 812. The timing controller 811 and the bias controller 812 can be referenced to display drivers 210 or 410 and so on.

[0052] In the embodiment of FIG8, the bias controller 812 includes a digital-to-analog converter (DAC) 812a and an output stage circuit 812b. The DAC 812a is coupled to the timing controller 811 and the output stage circuit 812b. The output stage circuit 812b is coupled to the pixel circuitry (e.g., pixel circuits 421 to 42N and 42M1 to 42MN shown in FIG4).

[0053] Referring to Figures 8 and 9, Figure 9 is a schematic diagram of the operation of the display driver according to the embodiment of Figure 8. In Figure 9, the horizontal axis represents the operation time of the display driver 810, and the vertical axis represents the voltage value. Compared with the embodiment of Figure 6, in Figure 8, the initial voltage Vinit2 is a voltage with step voltage values ​​switching from voltage value V3 to voltage V4.

[0054] In this embodiment, based on the clock signal (not shown) output by the timing controller 811, the digital-to-analog converter 812a modulates different voltage values ​​of the initial voltage Vinit2 according to the column configuration of the display lines (e.g., display lines L1 to LN shown in FIG. 4) to generate initial voltage Vinit2 with different voltage values ​​(including voltage values ​​V3 and V4). During non-refresh frames, the output stage circuit 812b outputs the initial voltage Vinit2 with different voltage values ​​to the pixel circuit.

[0055] In this embodiment, based on the clock signal output by the timing controller 811, the digital-to-analog converter 812a provides an initial voltage Vinit2 with a reference value VREF. During the refresh frame, the output stage circuit 812b outputs the initial voltage with the reference value VREF to the pixel circuit.

[0056] In this embodiment, the digital-to-analog converter 812a and the output stage circuit 812b process the initial voltages Vinit1 and Vinit3 with reference to the initial voltage Vinit2 and so on.

[0057] Figure 10 is a schematic diagram of the operation of a display panel according to another embodiment of the present invention. Referring to Figures 4 and 9, the display driver 410 of the display panel 400 operates during operation. In Figure 10, the horizontal axis represents the operation time of the display panel 400, and the vertical axis represents the voltage value.

[0058] In the embodiment of Figure 10, during operation, the number of refresh frames (FAVs) is multiple (e.g., two), and the number of non-refresh frames (FSKs) is one. The non-refresh frame (FSK) occurs between two refresh frames (FAVs).

[0059] Specifically, during refresh frame FAV (i.e., from time t91 to time t94), display driver 410 provides multiple start signals NSTV_STV, NCK, and NCB to enable control signals (e.g., control signals NSTV1 and NSTV2 shown in FIG. 5). During refresh frame FAV, display driver 410 provides multiple synchronization signals Vsync and Hsync to synchronize the operation signals in display panel 400.

[0060] During the refresh frame FAV (i.e., from time t91 to time t94), the start signal NSTV_STV has a pulse during the trailing edge BP (i.e., from time t91 to time t92) and can be a fixed voltage after the trailing edge BP (i.e., from time t92 to time t94). During the refresh frame FAV, the start signals NCK and NCB are pulse signals with opposite phases. During the refresh frame FAV, the initial voltage Vinit2 is a fixed voltage with a reference value VREF.

[0061] Therefore, during the refresh frame FAV (i.e., from time t91 to time t94), the display driver 410 drives the display panel 400 according to the synchronization signals Vsync and Hsync, the start signals NSTV_STV, NCK and NCB, the control signal SCs, and the initial voltage Vinit (including the initial voltage Vinit2) to refresh the current display screen.

[0062] Next, during the non-refresh frame FSK (i.e., from time t94 to time t97), the start signals NSTV_STV, NCK, and NCB are fixed voltages. During the non-refresh frame FSK, the initial voltage Vinit2 gradually increases from voltage value V3 to voltage value V4, as described in the embodiments of Figures 6 and 7.

[0063] Therefore, during the non-refresh frame FSK (i.e., from time t94 to time t97), the display driver 410 drives the display panel 400 according to the synchronization signals Vsync and Hsync, the start signals NSTV_STV, NCK and NCB, the control signals SCs, and the initial voltage Vinit (including the initial voltage Vinit2) so as not to refresh the current display screen.

[0064] It should be noted that in different frames FAV and FSK, the display driver 410 sets the initial voltage Vinit2 in different modes that are independent of each other. Furthermore, during non-refreshing frame FSK, the display driver 410 can compensate for voltage differences in the pixel circuits based on the initial voltage Vinit2 with various voltage values. These voltage differences are related to the corresponding nodes Q in the far and near regions of the display panel 400.

[0065] Figure 11 is a schematic diagram of the operation of a display panel according to another embodiment of the invention. Referring to Figures 4 and 10, the display driver 410 of the display panel 400 operates during operation. In Figure 11, the horizontal axis represents the operation time of the display panel 400, and the vertical axis represents the voltage value.

[0066] Compared to the embodiment of FIG10, in the embodiment of FIG11, during the operation period, the number of refresh frames FAV is one, and the number of non-refresh frames FSK is multiple (e.g., three). The non-refresh frames FSK (i.e., from time t102 to time t109) are consecutive frames following the refresh frame FAV (i.e., from time t101 to time t102).

[0067] Figure 12 is a schematic diagram of the operation of a display panel according to another embodiment of the invention. Referring to Figures 4 and 11, the display driver 410 of the display panel 400 operates during operation. In Figure 12, the horizontal axis represents the operation time of the display panel 400, and the vertical axis represents the voltage value.

[0068] Compared to the embodiment in Figure 10, in the embodiment in Figure 12, the operation period includes at least one split-screen frame (FSP), at least one refresh frame (FAV), and at least one non-refresh frame (FSK). In this embodiment, during the operation period, there is one split-screen frame (FSP), one refresh frame (FAV), and one non-refresh frame (FSK). The non-refresh frame (FSK) (i.e., from time t116 to time t118) follows the split-screen frame (FSP) (i.e., from time t111 to time t116) and precedes the refresh frame (FAV) (i.e., from time t118 to time t119).

[0069] Furthermore, the split-screen frame FSP includes one or more split-screen non-refresh frames FSP_SK and one or more split-screen refresh frames FSP_AV. In this embodiment, during operation, the number of split-screen refresh frames FSP_AV is one, and the number of split-screen non-refresh frames FSP_SK is multiple (e.g., two). The split-screen refresh frame FSP_AV is located between two split-screen non-refresh frames FSP_SK.

[0070] Specifically, during the non-refresh frame FSP_SK of the split-screen frame FSP (i.e., from time t112 to time t113), the display driver 410 provides an initial voltage Vinit2 with multiple different segmentation values ​​to the first pixel circuits 421 to 42N and 42M1 to 42MN. The first pixel circuits are arranged in the first display lines L1 to LN. For example, the first pixel circuits are arranged in the far-end region of the display panel 400 and include pixel circuit 421 arranged in display line L1.

[0071] In this embodiment, the different segment values ​​of the initial voltage Vinit2 are between voltage values ​​V3 and V4. These different segment values ​​of the initial voltage Vinit2 correspond to the distances between display lines L1 to LN and the display driver 410. Since display lines L1 to LN correspond to each column of the array, the distances between the first display lines and the display driver 410 are not the same.

[0072] Therefore, during the split-screen non-refresh frame FSP_SK (i.e., from time t112 to time t113), based on the initial voltage Vinit2 with different segmentation values, some pixel circuits (e.g., including pixel circuit 421) operate according to the control signal SCs to not refresh the first portion of the currently displayed screen. The first portion of the currently displayed screen corresponds to the first pixel circuit (e.g., including pixel circuit 421).

[0073] Next, during the screen refresh frame FSP_AV (i.e., from time t113 to time t114) of the screen refresh frame FSP, the display driver 410 provides an initial voltage Vinit2 with a reference voltage VREF to the first pixel circuit. Therefore, during this screen refresh frame FSP_AV, the display driver 410 refreshes the first portion of the display screen corresponding to the first pixel circuit according to the initial voltage Vinit2 with the reference value VREF and a plurality of control signals SCs.

[0074] In other words, during this split-screen refresh frame FSP_AV, based on the initial voltage Vinit2 with reference value VREF, some pixel circuits operate according to control signals SCs to refresh the corresponding part of the currently displayed screen.

[0075] Next, during another split-screen non-refresh frame FSP_SK (i.e., from time t114 to time t115), the display driver 410 provides an initial voltage Vinit2 with a different segmentation value to the second pixel circuits in pixel circuits 421 to 42N and 42M1 to 42MN. The second pixel circuits are arranged in the second display lines L1 to LN. For example, the second pixel circuits are arranged in the near-end region of the display panel 400 and include pixel circuit 42N arranged in display line LN.

[0076] In this embodiment, other different segment values ​​of the initial voltage Vinit2 are between voltage values ​​V3 and V4. The different segment values ​​of the initial voltage Vinit2 correspond to the second display line (e.g., including display line LN) and are different from the different segment values ​​of the initial voltage Vinit2 during the earlier split-screen non-refresh frame FSP_SK (i.e., from time t112 to time t113).

[0077] In other words, during the aforementioned two split-screen non-refresh frames FSP_SK, the voltage values ​​of the initial voltage Vinit2 are different from the initial voltage Vinit2 shown in Figure 6 or Figure 7.

[0078] Therefore, during the split-screen non-refresh frame FSP_SK (i.e., from time t114 to time t115), based on the initial voltage Vinit2 with other different segmentation values, some pixel circuits (e.g., including pixel circuit 42N) operate according to control signals SCs to not refresh the second portion of the currently displayed screen. The second portion of the currently displayed screen corresponds to the second pixel circuit (e.g., including pixel circuit 42N).

[0079] It should be noted that in different split-screen refresh frames FSP_AV and split-screen non-refresh frames FSP_SK, the display driver 410 sets the initial voltage Vinit2 in different modes that are independent of each other. Furthermore, during the split-screen non-refresh frame FSP_SK, the display driver 410 can compensate for voltage differences in the corresponding pixel circuits based on the initial voltage Vinit2 with each voltage value. These voltage differences are related to the corresponding node Q in the far-end and near-end regions of the display panel 400.

[0080] In summary, in the embodiments of the present invention, the display driver, its operating method, and the display panel compensate for voltage differences between corresponding nodes in the pixel circuits by providing initial voltages with different voltage values ​​to the pixel circuits corresponding to each column. Therefore, during non-refresh frames, pixel circuits arranged in different regions (e.g., far-end and near-end regions) can maintain the current display screen without flickering. In this way, the display driver can reduce display panel flicker and improve the uniformity of the display screen.

[0081] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0082] 200, 400: Display panel 210, 410, 810: Display drivers 211, 812a: Digital-to-Analog Converter 212, 812b: Output stage circuit 221, 222, 22N, 22M1, 22MN, 421, 42N, 42M1, 42MN: Pixel circuit 430: Gate drive circuit 510: Data writing circuit 520: Light-emitting driving circuit 530: Light-emitting circuit 811: Timing Controller 812: Bias Controller BP: trailing edge COL1: line EMSTV, HSTV, NSTV1, NSTV2, PSTV1, SCs: Control signals FAV: Refresh Frame FP: Frontier FSK: Non-refresh frame FSP: Split-screen frames FSP_AV: Split-screen refresh frame FSP_SK: Split-screen non-refresh frame Hsync, Vsync: Synchronization signals IRP1, IRP2: Current-resistance path L1, L2, LN: Display lines NCB, NCK, NSTV_STV: Start Signal Q: Node S210, S220: Steps t1~t4, t91~t98, t101~t109, t111~t119: Time V1, V2, V3, V4, V5, V6, VD, VH, VL, VR1, VR2: Voltage values VGLO: Signal Vinit, Vinit1, Vinit2, Vinit3, Vinit_P1, Vinit_P2: Initial voltage VQ, VQ': Voltage VREF: Reference value

Claims

1. A method of operating a display driver for driving a display panel, wherein the display panel includes a plurality of pixel circuits arranged on a plurality of display lines, the method of operating the display driver comprising: During at least one refresh frame, the display driver provides an initial voltage with a reference value to the plurality of pixel circuits; During at least one non-refresh frame, the display driver provides the plurality of pixel circuits with an initial voltage having a plurality of different voltage values, wherein the plurality of different voltage values ​​of the initial voltage correspond to the distances between the plurality of display lines and the display driver, wherein the plurality of different voltage values ​​of the initial voltage are generated by a digital-to-analog converter and output to the plurality of pixel circuits via an output stage circuit as compensation voltages for the plurality of pixel circuits, so that the display screen of the display panel maintains constant brightness during the at least one non-refresh frame.

2. The method of operating the display driver as claimed in claim 1, wherein the absolute values ​​of the plurality of different voltage values ​​of the initial voltage are positively correlated with the distance between the plurality of display lines and the display driver.

3. The method of operating a display driver as claimed in claim 1, wherein the step of providing the initial voltage having the plurality of different voltage values ​​to the plurality of pixel circuits by the display driver during the at least one non-refresh frame includes: During the at least one non-refresh frame, the display driver provides the initial voltage having a first voltage value to the first pixel circuit of the plurality of pixel circuits; During the at least one non-refresh frame, the display driver provides the initial voltage having a second voltage value to the second pixel circuit of the plurality of pixel circuits, wherein the first pixel circuit and the second pixel circuit are arranged in the same row and different columns.

4. The method of operating the display driver as claimed in claim 3, wherein the absolute value of the first voltage value corresponding to the first display line among the plurality of display lines is greater than the absolute value of the second voltage value corresponding to the second display line among the plurality of display lines, wherein the first distance between the first display line and the display driver is greater than the second distance between the second display line and the display driver.

5. The method of operating a display driver as claimed in claim 1, wherein during the operation of the display driver, the number of the at least one refresh frame is a plurality of multiples, and the number of the at least one non-refresh frame is one, wherein the non-refresh frame is located between the plurality of refresh frames.

6. The method of operating a display driver as claimed in claim 1, wherein during the operation of the display driver, the number of the at least one refresh frame is one, and the number of the at least one non-refresh frame is a plurality of frames, wherein the plurality of non-refresh frames are consecutive frames following the refresh frame.

7. The method of operating the display driver as described in claim 1, further comprising: During at least one split-screen refresh frame, the display driver provides the initial voltage having the reference voltage to the first pixel circuit of the plurality of pixel circuits corresponding to the first display line of the plurality of display lines; During the at least one split-screen refresh frame, the display driver refreshes a first portion of the display screen corresponding to the first pixel circuit of the display panel according to the initial voltage having the reference value and a plurality of control signals; And during at least one split-screen non-refresh frame, the display driver provides the initial voltage with a plurality of different segmentation values ​​to the second pixel circuit, wherein the plurality of different segmentation values ​​of the initial voltage correspond to the distances between the plurality of display lines and the display driver, respectively.

8. The method of operating a display driver as claimed in claim 7, wherein during the operation of the display driver, the number of the at least one split-screen refresh frame is one, and the number of the at least one split-screen non-refresh frame is a plurality of, wherein the split-screen refresh frame is located between the plurality of split-screen non-refresh frames.

9. The method of operating a display driver as claimed in claim 8, wherein during the operation of the display driver, the number of the at least one refresh frame is one, and the number of the at least one non-refresh frame is one, wherein the at least one non-refresh frame follows the plurality of split-screen non-refresh frames and precedes the at least one refresh frame.

10. The method of operating a display driver as claimed in claim 1, wherein the initial voltage having the plurality of different voltage values ​​includes step voltage values.

11. A display driver for driving a plurality of pixel circuits on a display panel, comprising: A digital-to-analog converter is used to generate an initial voltage with a reference value, and to generate the initial voltage with multiple different voltage values ​​based on the distance between multiple display lines on the display panel and the display driver; An output stage circuit, coupled to the digital-to-analog converter, is configured to output the initial voltage having the reference value to the plurality of pixel circuits during at least one refresh frame, and to output the initial voltage having the plurality of different voltage values ​​to the plurality of pixel circuits during at least one non-refresh frame, wherein the plurality of different voltage values ​​of the initial voltage are generated by the digital-to-analog converter and output to the plurality of pixel circuits via the output stage circuit as compensation voltages for the plurality of pixel circuits, so that the display screen of the display panel maintains constant brightness during the at least one non-refresh frame.

12. A display panel, comprising: Multiple pixel circuits are arranged in multiple display lines; A digital-to-analog converter is used to generate an initial voltage with a reference value, and to generate the initial voltage with multiple different voltage values ​​based on the distance between the plurality of display lines and the display driver; An output stage circuit is coupled to the digital-to-analog converter and the plurality of pixel circuits, and is used to output the initial voltage having the reference value to the plurality of pixel circuits during at least one refresh frame, and to output the initial voltage having the plurality of different voltage values ​​to the plurality of pixel circuits during at least one non-refresh frame, wherein the plurality of different voltage values ​​of the initial voltage are generated by the digital-to-analog converter and output to the plurality of pixel circuits via the output stage circuit as compensation voltages for the plurality of pixel circuits, so that the display screen of the display panel maintains constant brightness during the at least one non-refresh frame.

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