Display apparatus, display driving device and operating method thereof

Abstract

This invention provides a display device, a display driving device, and an operating method thereof. The display device includes a display panel, a touch driving device, and a display driving mechanism. The touch driving device drives the display panel to detect touch events. The display driving mechanism generates multiple gate clocks to the gate driving circuit of the display panel. The display driving mechanism generates these gate clocks in a first scan sub-period within the same frame with charge sharing disabled. The display driving mechanism generates these gate clocks in a second scan sub-period within the same frame with charge sharing enabled.

Description

[Technical Field]

[0001] This invention relates to an electronic device, and more particularly to a display device and its display driving device and operating method. [Previous Technology]

[0002] Figure 1 is a waveform diagram of the gate clock when there is no charge sharing function during the entire frame. The horizontal axis of Figure 1 represents time. The display driver can generate the gate clock GCLK1 for the touch display panel. The display driver toggle the gate clock GCLK1, that is, toggle the gate clock GCLK1 back and forth between the high gate voltage level VGH and the low gate voltage level VGL. As shown in Figure 1, the display driver pulls the gate clock GCLK1 from the low gate voltage level VGL to the high gate voltage level VGH at time t11, and pulls the gate clock GCLK1 from the high gate voltage level VGH to the low gate voltage level VGL at time t12. Due to coupling effects occurring in the touch display panel, the voltage transition of the gate clock GCLK1 can cause noise in the touch detection operation of the touch display panel. For example, as shown in Figure 1, the touch noise NOISE_TP1 has one noise surge at time points t11 and t12. Generally speaking, touch detection algorithms can filter out noise to a limited extent. For example, if "the number of noise surges NOISE_TP1 within 14 μs (microseconds) is no more than 6", the touch detection algorithm can successfully filter out the noise without affecting the accuracy of touch detection.

[0003] Because the display driver performs switching operations on the gate clock GCLK1 (the gate clock GCLK1 switches back and forth between the high gate voltage level VGH and the low gate voltage level VGL), the display driver consumes a considerable amount of power. The charge sharing function can effectively reduce the power consumption of the display driver.

[0004] Figure 2 is a waveform diagram of the gate clock when the charge sharing function is enabled throughout the entire frame. The horizontal axis of Figure 2 represents time. When the charge sharing function is enabled, the display driver first raises the voltage level of the gate clock GCLK2 from the low gate voltage level VGL to a certain charge sharing level VCS during the charge sharing period tc (the charge sharing level VCS is between the high gate voltage level VGH and the low gate voltage level VGL). Then, after the charge sharing period tc ends, the voltage level of the gate clock GCLK2 is raised from the charge sharing level VCS to the high gate voltage level VGH. Similarly, the display driver first lowers the voltage level of the gate clock GCLK2 from the high gate voltage level VGH to the charge sharing level VCS during the charge sharing period tc, and then lowers the voltage level of the gate clock GCLK2 from the charge sharing level VCS to the low gate voltage level VGL after the charge sharing period tc ends. Generally speaking, the power consumed by the display driver in transitioning the gate clock GCLK2 from the low gate voltage level VGL (or the high gate voltage level VGH) to the charge sharing level VCS is extremely small. Therefore, the charge sharing function is a feature that can effectively reduce power consumption.

[0005] As shown in Figure 2, the display driver raises the gate clock GCLK2 from the low gate voltage level VGL to the charge sharing level VCS at time t21, and then raises the voltage level of the gate clock GCLK2 from the charge sharing level VCS to the high gate voltage level VGH at time t22. The display driver lowers the gate clock GCLK2 from the high gate voltage level VGH to the charge sharing level VCS at time t23, and then lowers the voltage level of the gate clock GCLK2 from the charge sharing level VCS to the low gate voltage level VGL at time t24. The voltage transitions of the gate clock GCLK2 cause noise in the touch detection operation of the touch display panel. For example, the touch noise NOISE_TP2 shown in Figure 2 has a noise surge at each of time points t21, t22, t23, and t24. Compared to the touch noise NOISE_TP1 shown in Figure 1, the touch noise NOISE_TP2 shown in Figure 2 exhibits denser (more) noise spikes due to the activation of the charge sharing function. These denser (more) noise spikes may prevent the touch detection algorithm from successfully filtering out the noise, thus affecting the accuracy of touch detection.

[0006] It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be known to those skilled in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content was known to those skilled in the art prior to this application. [Summary of the Invention]

[0007] The present invention provides a display device and its display driving device and operating method to avoid affecting the accuracy of touch detection.

[0008] In one embodiment of the present invention, the above-described display device includes a display panel, a touch driving device, and a display driving device. The touch driving device is coupled to the display panel, wherein the touch driving device drives the display panel to detect touch events. The display driving device is used to drive the display panel, wherein the display driving device generates a plurality of gate clocks to the gate driving circuit of the display panel, and the gate driving circuit scans a plurality of scan lines of the display panel based on these gate clocks. The same frame period includes a first scan sub-period and a second scan sub-period. The display driving device generates these gate clocks in the first scan sub-period of the same frame period with charge sharing disabled. The display driving device generates these gate clocks in the second scan sub-period of the same frame period with charge sharing enabled.

[0009] In one embodiment of the present invention, the above-described display driving device includes a timing controller, a source driving circuit, and a gate clock generation circuit. The source driving circuit is coupled to the timing controller. The source driving circuit drives multiple data lines of the display panel based on the control of the timing controller. The gate clock generation circuit is coupled to the timing controller. The gate clock generation circuit generates multiple gate clocks for the gate driving circuit of the display panel based on the control of the timing controller, wherein the gate driving circuit scans multiple scan lines of the display panel based on these gate clocks. The same frame period includes a first scan sub-period and a second scan sub-period. The gate clock generation circuit generates these gate clocks in the first scan sub-period of the same frame period with the charge sharing function disabled. The gate clock generation circuit generates these gate clocks in the second scan sub-period of the same frame period with the charge sharing function enabled.

[0010] In one embodiment of the present invention, the above-described operation method includes: driving multiple data lines of a display panel by a source driving circuit of a display driving device; and generating multiple gate clocks for a gate driving circuit of the display panel by a gate clock generation circuit of the display driving device, wherein the gate driving circuit scans multiple scan lines of the display panel based on these gate clocks, the same frame period includes a first scan sub-period and a second scan sub-period, the gate clock generation circuit generates these gate clocks in the first scan sub-period of the same frame period with the charge sharing function disabled, and the gate clock generation circuit generates these gate clocks in the second scan sub-period of the same frame period with the charge sharing function enabled.

[0011] Based on the above, the gate clock generation circuit of the embodiments of the present invention disables and enables the charge sharing function during different scan sub-periods within the same frame to reduce touch noise surges. For example, based on a practical operating scenario, assume that the multiple gate clocks generated by the gate clock generation circuit include a first gate clock and a second gate clock, and that the first gate clock and the second gate clock are out of phase during the second scan sub-period. Out of phase means that the voltage transition times of the first gate clock and the second gate clock are approximately the same, and that the voltage transition directions of the first gate clock and the second gate clock are opposite. Because the first gate clock and the second gate clock are out of phase, the touch noise they cause can cancel each other out, allowing the gate clock generation circuit to enable the charge sharing function during the second scan sub-period to reduce power consumption. Assuming that the touch noise caused by these gate clocks during the first scan sub-period cannot cancel each other out, the gate clock generation circuit disables the charge sharing function during the first scan sub-period to avoid affecting the accuracy of touch detection.

[0012] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0014] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0015] Figure 3 is a circuit block diagram of a display device 300 according to an embodiment of the present invention. The display device 300 shown in Figure 3 includes a processor 310, a display driver 320, a gate driver circuit 330, a display panel 340, and a touch driver 350. Depending on the actual design and application, the processor 310 may be an application processor (AP), a central processing unit (CPU), or other processor. The touch driver 350 is coupled to the display panel 340. Based on the control of the processor 310, the touch driver drives the display panel 340 to detect touch events, and then reports the detection results of the touch events to the processor 310. This embodiment does not limit the specific implementation of the display panel 340 and the touch driver 350. For example, the display panel 340 may be a conventional touch display panel or other display panel, and the touch driver 350 may be a conventional touch driver circuit or other touch driver circuit adapted to the display panel 340.

[0016] Based on the control of the processor 310, the display driver 320 drives the display panel 340 to display images. The display driver 320 generates multiple gate clocks GCLK3 to the gate drive circuit 330 of the display panel 340. Based on practical design and application, the gate drive circuit 330 may include a gate on panel (GOP), a gate on array (GOA), or other gate line (scan line) scanning circuits. The gate drive circuit 330 scans multiple scan lines (not shown) of the display panel 340 based on the triggering of the gate clocks GCLK3. Synchronizing with the scanning timing of the scan lines of the display panel 340 by the gate drive circuit 330, the display driver 320 outputs pixel signals Vpixel to the display panel 340 to display images.

[0017] For example, in the embodiment shown in FIG3, the display driving device 320 includes a timing controller 321, a source driving circuit 322, and a gate clock generation circuit 323. The source driving circuit 322 and the gate clock generation circuit 323 are coupled to the timing controller 321. The source driving circuit 322 outputs a pixel signal Vpixel based on the pixel data Dpixel of the timing controller 321 to drive multiple data lines (not shown) of the display panel 340. The gate clock generation circuit 323 generates multiple gate clocks GCLK3 to the gate driving circuit 330 of the display panel 340 based on the control of the timing controller 321.

[0018] Figure 4 is a waveform diagram of gate clock GCLK3 when the charge sharing function is enabled during the entire frame, according to an embodiment of the present invention. The horizontal axis of Figure 4 represents time. The gate clocks GCLK4_1 and GCLK4_2 shown in Figure 4 can be one of many implementation examples of the gate clock GCLK3 shown in Figure 3. When the charge sharing function is enabled during the entire frame, the gate clock generation circuit 323 first raises the voltage level of the gate clock GCLK4_1 from the low gate voltage level VGL to a certain charge sharing level (e.g., the ground voltage level GND) during the charge sharing period tc (time points t41 to t42), and then raises the voltage level of the gate clock GCLK4_1 from the ground voltage level GND to the high gate voltage level VGH after the charge sharing period tc ends. The low gate voltage level VGL and the high gate voltage level VGH can be determined according to the actual design and application. The voltage transitions of the gate clock GCLK4_1 at times t41 and t42 cause noise in the touch detection operation of the display panel 340. For example, as shown in Figure 4, the touch noise NOISE_TP4 has one noise surge at each time point t41 and t42. Compared to the case where the charge sharing function is not enabled, the touch noise NOISE_TP4 shown in Figure 4 has more concentrated (more) noise surges at times t41 and t42 due to the enablement of the charge sharing function. The more concentrated (more) noise surges may prevent the touch detection algorithm from successfully filtering out the noise, thus affecting the accuracy of touch detection.

[0019] At time t43, the voltage level of gate clock GCLK4_1 is pulled down from the high gate voltage level VGH to the ground voltage level GND, while the voltage level of gate clock GCLK4_2 is pulled up from the low gate voltage level VGL to the ground voltage level GND. At time t44, the voltage level of gate clock GCLK4_1 is pulled down from the ground voltage level GND to the low gate voltage level VGL, while the voltage level of gate clock GCLK4_2 is pulled up from the ground voltage level GND to the high gate voltage level VGH. Because the voltage transition directions of gate clocks GCLK4_1 and GCLK4_2 at times t43 and t44 are opposite, the touch noise caused by them can cancel each other out (the touch noise NOISE_TP4 has very small or even no noise surge at times t43 and t44).

[0020] The gate clock generation circuit 323 first pulls the voltage level of the gate clock GCLK4_2 from the high gate voltage level VGH to the ground voltage level GND at time t45, and then pulls the voltage level of the gate clock GCLK4_2 from the ground voltage level GND to the low gate voltage level VGL at time t46. The voltage transition of the gate clock GCLK4_2 at time t45 and t46 will cause noise in the touch detection operation of the display panel 340. For example, the touch noise NOISE_TP4 shown in Figure 4 has a noise surge at time t45 and t46. Compared with the case where the charge sharing function is not enabled, the touch noise NOISE_TP4 shown in Figure 4 has more dense (more) noise surges at time t45 and t46 because the charge sharing function is enabled. While the charge sharing function can effectively reduce the power consumption of the display driver 320, the voltage transitions of the gate clock GCLK4_1 at time points t41 and t42, and the voltage transitions of the gate clock GCLK4_2 at time points t45 and t46, will cause more (more) noise in the touch detection operation.

[0021] FIG5 is a schematic flowchart of an operation method of a display driving device according to an embodiment of the present invention. Referring to FIG3 and FIG5, in step S510, the gate clock generation circuit 323 of the display driving device 320 generates a plurality of gate clocks GCLK3 to the gate driving circuit 330 of the display panel 340. The same frame period includes a first scan sub-period and a second scan sub-period. The gate clock generation circuit 323 generates gate clocks GCLK3 in the first scan sub-period with "charge sharing function disabled" (e.g., gate clock GCLK1 shown in FIG1), and generates gate clocks GCLK3 in the second scan sub-period with "charge sharing function enabled" (e.g., gate clocks GCLK4_1 and GCLK4_2 shown in FIG4) (step S510). Synchronizing the scanning timing of the display panel 340 with the gate drive circuit 330, in step S520, the source drive circuit 322 of the display drive device 320 outputs a pixel signal Vpixel to drive multiple data lines (not shown) of the display panel 340.

[0022] Figure 6 is a waveform diagram of the gate clock GCLK3 according to an embodiment of the present invention, showing the dynamic disabling / enabling of charge sharing function during different scan sub-periods within the same frame. The horizontal axis of Figure 6 represents time. In the embodiment shown in Figure 6, the same frame period F6 includes scan sub-periods SP6_1, SP6_2, and SP6_3. The gate clocks GCLK6_1, GCLK6_2, GCLK6_3, GCLK6_4, GCLK6_5, GCLK6_6, GCLK6_7, and GCLK6_8 shown in Figure 6 can be considered as one of many implementation examples of the gate clock GCLK3 shown in Figure 3. During the scanning sub-periods SP6_1, SP6_2, and SP6_3, the display driving device 320 can generate multiple gate clocks GCLK6_1 to GCLK6_8 to the gate driving circuit 330 of the display panel 340, and the gate driving circuit 330 scans multiple scan lines (not shown) of the display panel 340 based on the triggering of the gate clocks GCLK6_1 to GCLK6_8.

[0023] During the scan sub-period SP6_1 of frame period F6, when the gate clocks GCLK6_1 to GCLK6_4 undergo voltage transitions, the gate clocks GCLK6_5 to GCLK6_8 do not undergo voltage transitions. That is, the voltage transitions of the gate clocks GCLK6_1 to GCLK6_4 during the scan sub-period SP6_1 will cause touch noise. Therefore, the gate clock generation circuit 323 generates the gate clocks GCLK6_1 to GCLK6_8 during the scan sub-period SP6_1 with the charge sharing function disabled to reduce the number of touch noise occurrences. With the charge sharing function disabled, the display driving device 320 directly transitions each target gate clock of the gate clocks GCLK6_1 to GCLK6_8 from the first voltage level to the second voltage level. For example, the gate timing pulses GCLK6_1 to GCLK6_4 directly transition from the low gate voltage level VGL to the high gate voltage level VGH.

[0024] The gate clock generation circuit 323 generates gate clocks GCLK6_1 to GCLK6_8 during the scan sub-period SP6_2 of frame period F6 when the charge sharing function is enabled. When the charge sharing function is enabled, the display driving device 320 first switches the target gate clock from the first voltage level to the charge sharing level during the charge sharing period tc, and then switches the target gate clock from the charge sharing level to the second voltage level after the charge sharing period tc ends. For example, during the charge sharing period tc, the display driver 320 raises the gate clock GCLK6_1 from the low gate voltage level VGL to the charge sharing level (e.g., the ground voltage level GND), and lowers the gate clock GCLK6_5 from the high gate voltage level VGH to the charge sharing level (e.g., the ground voltage level GND); at the same point in time after the end of the charge sharing period tc, the display driver 320 raises the gate clock GCLK6_1 from the charge sharing level to the high gate voltage level VGH, and lowers the gate clock GCLK6_5 from the charge sharing level to the low gate voltage level VGL.

[0025] During the scan sub-period SP6_2, gate clocks GCLK6_1 and GCLK6_5 are out of phase, gate clocks GCLK6_2 and GCLK6_6 are out of phase, gate clocks GCLK6_3 and GCLK6_7 are out of phase, and gate clocks GCLK6_4 and GCLK6_8 are out of phase. "Out of phase" means that the voltage transition times of the gate clocks are approximately the same and the voltage transition directions are opposite. Because gate clocks GCLK6_1 to GCLK6_8 are out of phase during the scan sub-period SP6_2, the touch noise caused by gate clocks GCLK6_1 to GCLK6_8 can cancel each other out. Therefore, the gate clock generation circuit 323 can enable charge sharing during the scan sub-period SP6_2 to reduce the power consumption of the gate clock generation circuit 323.

[0026] During the scan sub-period SP6_3 of frame period F6, when the gate pulses GCLK6_5 to GCLK6_8 undergo voltage transitions, the gate pulses GCLK6_1 to GCLK6_4 do not undergo voltage transitions. That is, the voltage transitions of the gate pulses GCLK6_5 to GCLK6_8 during the scan sub-period SP6_3 will cause touch noise. Therefore, the gate pulse generation circuit 323 generates the gate pulses GCLK6_1 to GCLK6_8 during the scan sub-period SP6_3 with the charge sharing function disabled to reduce the number of touch noise occurrences. When the charge sharing function is disabled, the display driving device 320 directly transitions each target gate pulse of GCLK6_1 to GCLK6_8 from the second voltage level to the first voltage level. For example, GCLK6_5 to GCLK6_8 directly transition from the high gate voltage level VGH to the low gate voltage level VGL.

[0027] In summary, the gate clock generation circuit 323 dynamically disables and enables the charge sharing function during different scan sub-periods SP6_1, SP6_2, and SP6_3 within the same frame period F6. During scan sub-periods SP6_1 and SP6_3, the touch noise caused by gate clocks GCLK6_1 to GCLK6_8 cannot cancel each other out. Therefore, the gate clock generation circuit 323 disables the charge sharing function during scan sub-periods SP6_1 and SP6_3 to reduce the number of touch noise spikes, thereby avoiding affecting the accuracy of touch detection. During scan sub-period SP6_2, because gate clocks GCLK6_1 to GCLK6_8 are inverted, the touch noise caused by gate clocks GCLK6_1 to GCLK6_8 can cancel each other out. Therefore, the gate clock generation circuit 323 can enable the charge sharing function during scan sub-period SP6_2 to reduce power consumption.

[0028] FIG7 is a circuit block diagram of a gate clock generation circuit 323 according to an embodiment of the present invention. The gate clock generation circuit 323 shown in FIG7 can be one of many embodiments of the gate clock generation circuit 323 shown in FIG3. The timing controller 321, the gate clock generation circuit 323 and the gate drive circuit 330 shown in FIG7 can be referred to the relevant description in FIG3, and will not be repeated here. In the embodiment shown in FIG7, the gate clock generation circuit 323 includes a line counting circuit 710, a charge sharing circuit 720 and a clock generator 730. The line counting circuit 710 counts the currently driving scan line in the same frame period using the scan line count value. That is, the line counting circuit 710 can know which scan line of the display panel 340 the gate drive circuit 330 is currently scanning based on the scan line count value. The clock generator 730 is coupled to the line counting circuit 710. The line counting circuit 710 controls the clock generator 730 to generate the gate clock GCLK3 based on the scan line count value. The clock generator 730 outputs multiple gate clocks GCLK3 to the gate drive circuit 330 of the display panel 340 through multiple gate clock transmission lines.

[0029] The charge sharing circuit 720 is coupled to the gate clock transmission line between the line counting circuit 710 and the gate drive circuit 330. The line counting circuit 710 controls the charge sharing circuit 720 based on the scan line count value. For example, referring to Figures 6 and 7, the line counting circuit 710 disables the charge sharing circuit 720 in scan sub-period SP6_1 of frame period F6 to disable the charge sharing function for these gate clock transmission lines. The line counting circuit 710 enables the charge sharing circuit 720 in scan sub-period SP6_2 of the same frame period F6 to enable the charge sharing function for these gate clock transmission lines. The line counting circuit 710 disables the charge sharing circuit 720 again in scan sub-period SP6_3 of the same frame period F6 to disable the charge sharing function for these gate clock transmission lines.

[0030] FIG8 is a schematic flowchart of an operation method of a display driving device according to another embodiment of the present invention. Referring to FIG7 and FIG8, in step S810, the line counting circuit 710 resets the scan line count value. In step S820, the line counting circuit 710 counts the currently driven scan lines in the same frame period using the scan line count value. In step S830, the line counting circuit 710 checks the scan line count value. When the scan line count value is less than the threshold TH1 (the judgment result of step S830 is "value < TH1", that is, in the scan sub-period SP6_1 of frame period F6), the line counting circuit 710 disables the charge sharing circuit 720 to disable the charge sharing function (step S850). The threshold TH1 can be determined according to the actual design or application. After step S850, the line counting circuit 710 returns to step S820 to continue counting the currently driven scan lines.

[0031] When the scan line count value is greater than the threshold TH1 and less than the threshold TH2 (the judgment result of step S830 is "TH1 < value < TH2", that is, during the scan sub-period SP6_2 of frame period F6), the line counting circuit 710 enables the charge sharing circuit 720 to enable the charge sharing function (step S840). The threshold TH2 can be determined according to the actual design or application, and the threshold TH2 is greater than the threshold TH1. After step S840, the line counting circuit 710 returns to step S820 to continue counting the currently driven scan lines.

[0032] When the scan line count value is greater than the threshold TH2 and less than the threshold TH3 (the judgment result of step S830 is "TH2 < value < TH3", that is, during the scan sub-period SP6_3 of frame period F6), the line counting circuit 710 disables the charge sharing circuit 720 again to disable the charge sharing function (step S850). The threshold TH3 can be determined according to the actual design or application, and the threshold TH3 is greater than the threshold TH2. After step S850, the line counting circuit 710 returns to step S820 to continue counting the currently driven scan lines. In response to the scan line count value being equal to or greater than the threshold TH3 (the judgment result of step S830 is "value ≥ TH3", that is, after the scan sub-period SP6_3 of frame period F6 ends), the line counting circuit 710 returns to step S810 to reset the scan line count value (preparing to enter a new frame period).

[0033] Depending on the design, in some embodiments, the above-mentioned display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 may be implemented as hardware circuits. In other embodiments, the display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 may be implemented as hardware, firmware, software (i.e., program), or a combination thereof.

[0034] In terms of hardware, the above-mentioned display driving device 320, timing controller 321, source driving circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730 and / or touch driving device 350 can be implemented as logic circuits on integrated circuits. For example, the related functions of the display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), CPUs, and / or other processing units. The related functions of the display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0035] In software and / or firmware form, the functions of the aforementioned display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 can be implemented as programming codes. For example, the display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a non-transitory machine-readable storage medium or a computer program product. In some embodiments, the non-transitory machine-readable storage medium or computer program product includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a computer, CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium or computer program product to implement the related functions of the display driver 320, timing controller 321, source driver circuit 322, gate clock generation circuit 323, line counting circuit 710, charge sharing circuit 720, clock generator 730, and / or touch driver 350. Alternatively, the programming code or computer program product can be provided to the electronic device via any transmission medium (e.g., a communication network or broadcast radio waves). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

[0036] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0013] Figure 1 is a waveform diagram of the gate clock when the charge sharing function is not enabled during the entire frame. Figure 2 is a waveform diagram of the gate clock when the charge sharing function is enabled during the entire frame. Figure 3 is a circuit block diagram of a display device according to an embodiment of the present invention. Figure 4 is a waveform diagram of the gate clock when the charge sharing function is enabled during the entire frame, according to an embodiment of the present invention. Figure 5 is a flowchart of an operation method of a display driving device according to an embodiment of the present invention. Figure 6 is a waveform diagram of the gate clock when the charge sharing function is dynamically disabled / enabled during different scan sub-periods of the same frame, according to an embodiment of the present invention. Figure 7 is a circuit block diagram of a gate clock generation circuit according to an embodiment of the present invention. Figure 8 is a flowchart of an operation method of a display driving device according to another embodiment of the present invention.

Claims

1. A display device, comprising: A display panel; A touch driver is coupled to the display panel, wherein the touch driver drives the display panel to detect a touch event; The display driver also includes a display driving device for driving the display panel. The display driving device generates multiple gate clocks to a gate driving circuit of the display panel. The gate driving circuit scans multiple scan lines of the display panel based on the gate clocks. A frame period includes a first scan sub-period and a second scan sub-period. The display driving device generates the gate clocks during the first scan sub-period of the same frame with a charge sharing function disabled, and during the second scan sub-period of the same frame with the charge sharing function enabled. When the charge sharing function is disabled, the display driving device directly transitions a target gate clock from a first voltage level to a second voltage level. When the charge sharing function is enabled, the display driving device first transitions the target gate clock from the first voltage level to a charge sharing level during a charge sharing period, and then transitions the target gate clock from the charge sharing level to the second voltage level after the charge sharing period ends.

2. The display device as claimed in claim 1, wherein the charge sharing level is a ground voltage level.

3. The display device as claimed in claim 1, wherein when the charge sharing function is enabled, the display driving device, during a charge sharing period, raises a first gate clock of the gate clocks from a low gate voltage level to a charge sharing level, and lowers a second gate clock of the gate clocks from a high gate voltage level to the charge sharing level; and at the same point after the end of the charge sharing period, the display driving device raises the first gate clock from the charge sharing level to the high gate voltage level, and lowers the second gate clock from the charge sharing level to the low gate voltage level.

4. The display device as claimed in claim 1, wherein the same frame period further includes a third scan sub-period, the second scan sub-period being located between the first scan sub-period and the third scan sub-period, and the display driving device generates the gate clocks during the third scan sub-period of the same frame period with the charge sharing function disabled.

5. The display device as claimed in claim 1, wherein the display driving device comprises: A timing controller; A source drive circuit coupled to the timing controller, wherein the source drive circuit drives multiple data lines of the display panel based on the control of the timing controller; and a gate clock generation circuit coupled to the timing controller, wherein the gate clock generation circuit generates gate clocks to the gate drive circuit based on the control of the timing controller, wherein the gate clock generation circuit generates the gate clocks in the first scan sub-period of the same frame with the charge sharing function disabled, and the gate clock generation circuit generates the gate clocks in the second scan sub-period of the same frame with the charge sharing function enabled.

6. The display device as claimed in claim 5, wherein the gate clock generating circuit comprises: A line counting circuit, wherein the line counting circuit counts the currently driven scan line during the same frame period using a scan line count value; A clock generator, coupled to the line counting circuit, wherein the line counting circuit controls the clock generator to generate the gate clocks based on the scan line count value, and the clock generator outputs the gate clocks to the gate drive circuit through multiple gate clock transmission lines; and a charge sharing circuit, coupled to the gate clock transmission lines, wherein the line counting circuit controls the charge sharing circuit based on the scan line count value, the charge sharing circuit being disabled during the first scan sub-period of the same frame to disable the charge sharing function for the gate clock transmission lines, and the charge sharing circuit being enabled during the second scan sub-period of the same frame to enable the charge sharing function for the gate clock transmission lines.

7. The display device as claimed in claim 6, wherein, In response to the scan line count value being less than a first threshold, the line counting circuit disables the charge sharing circuit; and in response to the scan line count value being greater than the first threshold and less than a second threshold, the line counting circuit enables the charge sharing circuit.

8. The display device as claimed in claim 7, wherein, In response to the scan line count value being greater than the second threshold and less than a third threshold, the line counting circuit disables the charge sharing circuit; and in response to the scan line count value being equal to or greater than the third threshold, the line counting circuit resets the scan line count value.

9. A display driving device for driving a display panel, the display driving device comprising: A timing controller; A source drive circuit, coupled to the timing controller, drives multiple data lines of the display panel under the control of the timing controller; and a gate clock generation circuit, coupled to the timing controller, generates multiple gate clocks for a gate drive circuit of the display panel under the control of the timing controller. The gate drive circuit scans multiple scan lines of the display panel based on these gate clocks. A frame period includes a first scan sub-period and a second scan sub-period. The gate clock generation circuit generates the gate clocks during the first scan sub-period of the same frame period with a charge sharing function disabled, and during the second scan sub-period of the same frame period with the charge sharing function enabled. When the charge sharing function is disabled, the gate clock generation circuit directly transitions a target gate clock from a first voltage level to a second voltage level; and when the charge sharing function is enabled, the gate clock generation circuit first transitions the target gate clock from the first voltage level to a charge sharing level during a charge sharing period, and then transitions the target gate clock from the charge sharing level to the second voltage level after the charge sharing period ends.

10. The display driving device as claimed in claim 9, wherein the charge sharing level is a ground voltage level.

11. The display driving device as claimed in claim 9, wherein, when the charge sharing function is enabled, the display driving device, during a charge sharing period, raises a first gate clock of the gate clocks from a low gate voltage level to a charge sharing level, and lowers a second gate clock of the gate clocks from a high gate voltage level to the charge sharing level; and at the same point after the end of the charge sharing period, the display driving device raises the first gate clock from the charge sharing level to the high gate voltage level, and lowers the second gate clock from the charge sharing level to the low gate voltage level.

12. The display driving device as claimed in claim 9, wherein the same frame period further includes a third scan sub-period, the second scan sub-period being located between the first scan sub-period and the third scan sub-period, and the gate clock generation circuit generates the gate clocks in the third scan sub-period of the same frame period with the charge sharing function disabled.

13. The display driving device as claimed in claim 9, wherein the gate clock generating circuit comprises: A line counting circuit, wherein the line counting circuit counts the currently driven scan line during the same frame period using a scan line count value; A clock generator, coupled to the line counting circuit, wherein the line counting circuit controls the clock generator to generate the gate clocks based on the scan line count value, and the clock generator outputs the gate clocks to the gate drive circuit through multiple gate clock transmission lines; and a charge sharing circuit, coupled to the gate clock transmission lines, wherein the line counting circuit controls the charge sharing circuit based on the scan line count value, the charge sharing circuit being disabled during the first scan sub-period of the same frame to disable the charge sharing function for the gate clock transmission lines, and the charge sharing circuit being enabled during the second scan sub-period of the same frame to enable the charge sharing function for the gate clock transmission lines.

14. The display driving device as claimed in claim 13, wherein, In response to the scan line count value being less than a first threshold, the line counting circuit disables the charge sharing circuit; and in response to the scan line count value being greater than the first threshold and less than a second threshold, the line counting circuit enables the charge sharing circuit.

15. The display driving device as claimed in claim 14, wherein, In response to the scan line count value being greater than the second threshold and less than a third threshold, the line counting circuit disables the charge sharing circuit; and in response to the scan line count value being equal to or greater than the third threshold, the line counting circuit resets the scan line count value.

16. A method of operating a display driving device, comprising: Multiple data lines of a display panel are driven by a source drive circuit of the display driving device; A gate clock generation circuit of the display driving device generates multiple gate clocks to a gate driving circuit of the display panel. The gate driving circuit scans multiple scan lines of the display panel based on the gate clocks. The same frame period includes a first scan sub-period and a second scan sub-period. The gate clock generation circuit generates the gate clocks in the first scan sub-period of the same frame period with a charge sharing function disabled, and generates the gate clocks in the second scan sub-period of the same frame period with the charge sharing function enabled. When the charge sharing function is disabled, the gate clock generation circuit directly transitions a target gate clock from a first voltage level to a second voltage level. When the charge sharing function is enabled, the gate clock generation circuit first transitions the target gate clock from the first voltage level to a charge sharing level during a charge sharing period, and then transitions the target gate clock from the charge sharing level to the second voltage level after the charge sharing period ends.

17. The method of operation as described in claim 16, wherein the charge sharing level is a ground voltage level.

18. The operating method as described in claim 16, further comprising: When the charge sharing function is enabled, during a charge sharing period, a first gate clock among the gate clocks is raised from a low gate voltage level to a charge sharing level, and a second gate clock among the gate clocks is lowered from a high gate voltage level to the charge sharing level; and when the charge sharing function is enabled, at the same point in time after the end of the charge sharing period, the first gate clock is raised from the charge sharing level to the high gate voltage level, and the second gate clock is lowered from the charge sharing level to the low gate voltage level.

19. The operation method as described in claim 16, wherein the same frame period further includes a third scan sub-period, the second scan sub-period being located between the first scan sub-period and the third scan sub-period, and the operation method further includes: The gate clock generation circuit generates these gate clocks during the third scan sub-period of the same frame period with the charge sharing function disabled.

20. The operating method as described in claim 16 further includes: The one-line counting circuit of the gate clock generation circuit counts the currently driven scan line during the same frame period with a scan line count value; The line counting circuit controls a clock generator of the gate clock generation circuit to generate the gate clocks based on the scan line count value; the clock generator outputs the gate clocks to the gate drive circuit through multiple gate clock transmission lines; and the line counting circuit controls a charge sharing circuit of the gate clock generation circuit based on the scan line count value, wherein the charge sharing circuit is disabled in the first scan sub-period of the same frame to disable the charge sharing function for the gate clock transmission lines, and the charge sharing circuit is enabled in the second scan sub-period of the same frame to enable the charge sharing function for the gate clock transmission lines.

21. The operating method as described in claim 20, further comprising: The charge sharing circuit is disabled in response to the scan line count value being less than a first threshold. And in response to the scan line count value being greater than the first threshold and less than a second threshold, the charge sharing circuit is enabled.

22. The operating method as described in claim 21 further includes: In response to the scan line count value being greater than the second threshold and less than a third threshold, the charge sharing circuit is disabled; And in response to the scan line count value being equal to or greater than the third threshold, the scan line count value is reset.

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