Semiconductor device spacer and semiconductor device assembly

Abstract

This disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, the embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein can be used to form stacked semiconductor package elements, stacked PCB elements, and so on.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to stacked miniaturized electronic devices and methods of forming the same. More specifically, the embodiments described herein relate to PCBs and package spacers and methods of forming the same. Prior Technology

[0002] Driven by the ever-growing demand for miniaturized electronic devices with reduced footprints, electronic devices have evolved into complex 2.5D and 3D stacked devices. The development of stacked electronic device designs has led to greater circuit density in an effort to improve speed and processing power, and has also placed corresponding demands on the materials, components, and processes used to manufacture such electronic devices.

[0003] Conventionally, components of miniaturized electronic devices are vertically stacked with spacers positioned between them to provide physical separation. These spacers are typically formed from molding compounds (e.g., epoxy molding compounds, FR-4 and FR-5 grade woven fiberglass cloth with epoxy adhesive, etc.) and patterned via mechanical processes to achieve electrical connectivity between the device components. However, the materials used for the molding compounds and the patterning processes for the spacers present several limitations that hinder the scaling of electronic devices and overall device performance.

[0004] In particular, due to the thermal properties of current molding compound materials, a mismatch in the coefficient of thermal expansion (CTE) can occur between device components and adjacent spacers. Therefore, larger solder bumps with greater spacing are required to mitigate any warpage of device components or spacers caused by CTE mismatch. Furthermore, the inherent properties of these molding compound materials also make it difficult to pattern fine (e.g., less than 50 μm) features in the spacers, amplified by the resolution limitations of the mechanical structuring process itself. Thus, spacers using conventional molding compound materials can create a bottleneck in the fabrication of miniaturized electronic devices with reduced footprint stacks.

[0005] Therefore, there is a need in the art for improved spacers and structures for stacked miniaturized electronic devices, as well as methods for their formation. Summary of the Invention

[0006] This disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, the embodiments described herein relate to semiconductor device spacers and methods of forming the same.

[0007] In one embodiment, a semiconductor device spacer is provided. The semiconductor device spacer includes: a frame having a first surface opposite a second surface; a frame material comprising a polymer-based dielectric material having spherical ceramic fillers; and a via including a via surface defining an opening extending through the frame from the first surface to the second surface. The via has a diameter between about 10 μm and about 150 μm. Electrical interconnects are further disposed within the via on the via surface.

[0008] In one embodiment, a semiconductor device element is provided. The semiconductor device element includes a first printed circuit board (PCB) having a first glass fiber reinforced epoxy resin material and a first electrical distribution layer formed on the first glass fiber reinforced epoxy resin material. The semiconductor device element further includes a second PCB having a second glass fiber reinforced epoxy resin material and a second electrical distribution layer formed on the second glass fiber reinforced epoxy resin material. The semiconductor device element also includes a device spacer interposed between the first PCB and the second PCB to facilitate physical space between the first PCB and the second PCB. The device spacer includes: a frame having a first surface opposite a second surface; a frame material comprising a polymer-based dielectric material having spherical ceramic fillers; and a via including a via surface defining an opening extending through the frame from the first surface to the second surface. The via has a diameter between about 10 μm and about 150 μm. Electrical interconnects are further disposed within the via on the via surface to form at least a portion of a conductive path extending between at least a portion of the first electrical distribution layer and the second electrical distribution layer.

[0009] In one embodiment, a semiconductor device element is provided. The semiconductor device element includes a printed circuit board (PCB) having a first glass fiber reinforced epoxy resin material and a first electrical distribution layer formed on the first glass fiber reinforced epoxy resin material. The semiconductor device element further includes a silicon substrate having a silicon-cured structure with a thickness of less than about 1000 μm and a second electrical distribution layer formed on the silicon core structure. The semiconductor device element also includes a device spacer interposed between the PCB and the silicon substrate to facilitate physical space between the PCB and the silicon substrate. The device spacer includes: a frame having a first surface opposite a second surface and a thickness between about 400 μm and about 1600 μm; a frame material comprising a polymer-based dielectric material having spherical ceramic fillers; and a via including a via surface defining an opening extending through the frame from the first surface to the second surface. The thickness of the frame is substantially similar to the height of the physical space, and the via has a diameter between about 10 μm and about 150 μm. Electrical interconnects are further disposed within the vias on the via surface to form at least a portion of a conductive path extending between at least a portion of the first and second electrical distribution layers. The ratio of the area of ​​the device spacer to the surface area of ​​the PCB or silicon substrate is between about 0.15 and about 0.85. Simple Explanation of the Diagram

[0010] Therefore, in order to understand in detail the manner in which the features of this disclosure are described above, a more specific description of the disclosure briefly outlined above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate exemplary embodiments only and are not intended to limit its scope, and other equivalent embodiments may be permitted.

[0011] Figures 1A and 1B schematically show cross-sectional views of semiconductor device spacers according to embodiments described herein.

[0012] Figure 1C shows an enlarged cross-sectional view of a portion of a semiconductor device spacer according to an embodiment described herein.

[0013] Figures 2A and 2B schematically show cross-sectional views of semiconductor device spacers according to embodiments described herein.

[0014] Figures 3A and 3B schematically illustrate top-down views of a semiconductor device spacer according to an embodiment described herein.

[0015] Figure 4 is a flowchart illustrating the process for manufacturing the semiconductor device spacers of Figures 1 to 3B according to embodiments described herein.

[0016] Figures 5A to 5J schematically illustrate cross-sectional views of semiconductor device spacers at different stages of the process depicted in Figure 4, according to embodiments described herein.

[0017] Figure 6 is a flowchart illustrating a process for manufacturing a frame used in a semiconductor device spacer according to an embodiment described herein.

[0018] Figures 7A through 7E schematically show cross-sectional views of the frames at different stages of the process depicted in Figure 6 according to the embodiments described herein.

[0019] Figure 8 schematically shows a cross-sectional view of a stacked semiconductor device according to an embodiment described herein.

[0020] Figure 9 schematically shows a cross-sectional view of a stacked semiconductor device according to an embodiment described herein.

[0021] Figure 10 schematically shows a cross-sectional view of a stacked semiconductor device according to an embodiment described herein.

[0022] Figures 11A to 11E schematically illustrate top views of the arrangement of spacers in a semiconductor device according to embodiments described herein.

[0023] For ease of understanding, the same reference numerals have been used to denote common elements in the figures where possible. It is contemplated that elements and features of one embodiment may be advantageously combined in other embodiments without further description. Implementation

[0024] This disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, the embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein can be used to form stacked semiconductor package elements, stacked PCB elements, and so on.

[0025] The stacked semiconductor devices and semiconductor device spacers disclosed herein are intended to replace more conventional semiconductor PCBs and package components that use spacers made of molding compound materials, such as epoxy molding compounds, FR-4 and FR-5 grade woven fiberglass cloth with epoxy adhesive, etc. Typically, the scalability of stacked PCBs and package components is limited in part by the inherent properties of the molding compound materials used to form these spacers. For example, the rigidity of these materials makes it difficult to pattern fine (e.g., micrometer-scale) features in the spacers for interconnection of individual device components within the stacked components. Furthermore, due to the thermal properties of the molding compound materials currently used, a coefficient of thermal expansion (CTE) mismatch can occur between the spacers and any device components positioned adjacent to the spacers. Consequently, current PCBs and package components require large solder bumps with large spacing to mitigate any warpage effects caused by CTE mismatch. Therefore, conventional semiconductor PCBs and package assemblies are characterized by low through-structure electrical bandwidths that result in reduced overall power and efficiency. The methods and apparatus disclosed herein provide semiconductor device spacers that overcome many of the drawbacks associated with conventional PCBs and packaged components described above.

[0026] Figures 1A to 1C, 2A, and 2B illustrate cross-sectional views of a semiconductor device spacer 100 according to some embodiments. The semiconductor device spacer 100 can be used for physical separation, structural support, and electrical interconnection of semiconductor devices and components mounted to them. The semiconductor device spacer 100 can also be used to stack semiconductor package substrates, thus achieving economical space utilization and / or enhanced I / O connectivity and bandwidth between multiple package substrates in small electronic products. The semiconductor device spacer 100 also minimizes trace lengths between different interoperable portions to shorten wiring for interconnections between substrates.

[0027] Semiconductor device spacer 100 typically includes a frame 102 having one or more holes or through-holes 103 formed through the frame 102. In one embodiment, the frame 102 is formed of a polymer-based dielectric material. For example, the frame 102 is formed of a flowable stacking material. In a further embodiment, the frame 102 is formed of an epoxy resin material having ceramic filler 130 (shown in FIG. 1C), such as silicon dioxide (SiO2) particles. Other examples of ceramic fillers 130 that can be used to form frame 102 include aluminum nitride (AlN), alumina (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and so on.

[0028] As depicted in the enlarged cross-sectional view of frame 102 in Figure 1C, the ceramic filler 130 is generally spherical in shape or morphology. As used herein, the term "spherical" refers to any circular, elliptical, or spherical shape. For example, in some embodiments, the ceramic filler 130 may have an elliptical shape, an elongated elliptical shape, or other similar circular shape. However, other morphologies are also contemplated. In some examples, the ceramic filler 130 used to form frame 102 comprises particles with diameters ranging from about 40 nm to about 150 nm, such as those between about 80 nm and about 100 nm. For example, the ceramic filler 130 comprises particles with diameters ranging from about 200 nm to about 800 nm, such as those between about 300 nm and about 600 nm. In some examples, the ceramic filler 130 comprises particles having a substantially uniform diameter. In other examples, the ceramic filler 130 comprises particles with varying diameters. The particles of ceramic filler 130 have a packing density between about 0.02 and about 0.99 (e.g., the fraction of the solid volume of frame 102 formed by the volume of ceramic filler 130), such as a packing density between about 0.1 and about 0.98. For example, the ceramic filler 130 in frame 102 may have a packing density between about 0.2 and about 0.96, such as a packing density between about 0.5 and about 0.95.

[0029] Frame 102 can have any desired shape and size. In some embodiments, frame 102 has a polygonal shape. For example, frame 102 has a substantially rectangular shape, wherein the lateral dimension is between about 5 mm and about 100 mm, such as between about 10 mm and about 80 mm, such as between about 15 mm and about 50 mm. Typically, the thickness T0 of frame 102 is between about 45 μm and about 5000 μm, such as between about 100 μm and about 3000 μm. For example, the thickness T0 of frame 102 is between about 200 μm and about 2000 μm, such as between about 400 μm and about 1600 μm.

[0030] In some embodiments, frame 102 is formed of one or more layers 110 of a polymer-based dielectric material, which are laminated and cured together to form a single integral body (e.g., a block) of frame 102. For example, frame 102 is formed of stacked individual layers 110a-c, which are laminated and cured together to form a single integral body. In such an example, the thickness T0 of frame 102 is the sum of the thickness TA of individual layer 110a, the thickness TB of individual layer 110b, and the thickness TC of individual layer 110c. The thicknesses TA-B of each individual layer 110a-110c for frame 102 are between about 10 μm and about 150 μm, such as between about 25 μm and about 125 μm, for example, between about 50 μm and about 100 μm.

[0031] Holes or vias 103 (hereinafter referred to as "vias") are formed in frame 102 to allow conductive electrical interconnects 104 to be wired through frame 102. For example, a via 103 extends from a first surface 105 of frame 102 to an opposing second surface 107. Typically, one or more vias 103 are substantially cylindrical. However, other suitable forms for vias 103 are also contemplated. A via 103 may be formed as a single, isolated via 103 through frame 102, or as one or more groups or arrays. In one embodiment, the minimum spacing P0 of the vias 103 is less than about 1200 μm, such as a minimum spacing P0 between about 50 μm and about 1000 μm, such as between about 100 μm and about 800 μm. For example, the minimum spacing P0 is between about 150 μm and about 600 μm. For clarity, "spacing" refers to the distance between the centers of adjacent vias 103.

[0032] In the embodiment depicted in FIG1A, each of the one or more through-holes 103 has a substantially uniform diameter extending through the frame 102. For example, each of the one or more through-holes 103 has a uniform diameter Vl that is less than about 500 μm throughout, such as a uniform diameter Vl that is between about 10 μm and about 200 μm throughout. In a further example, each of the through-holes 103 has a uniform diameter Vl that is between about 10 μm and about 180 μm throughout, such as a uniform diameter Vl that is between about 10 μm and about 150 μm throughout.

[0033] Alternatively, in the embodiment depicted in FIG1B, each of the one or more through-holes 103 has a tapering diameter passing through the frame 102. For example, each of the one or more through-holes 103 has a first diameter V1A at a first surface 105, the first diameter V1A widening or expanding to a second diameter V1B at a second surface 107. Thus, it can be said that each through-hole 103 tapers from diameter V1B to diameter V1A. In one example, diameter V1B is less than about 500 μm, such as between about 10 μm and about 200 μm, such as between about 10 μm and about 180 μm, such as between about 10 μm and about 150 μm. In one example, diameter V1A is less than about 400 μm, such as between about 10 μm and about 130 μm, such as between about 10 μm and about 120 μm, such as between about 10 μm and about 100 μm.

[0034] Via 103 provides a channel through which one or more electrical interconnects 104 are formed in the semiconductor device spacer 100. In one embodiment, via 103 and electrical interconnects 104 are formed across the entire thickness T0 of the semiconductor device spacer 100 (i.e., from the first surface 105 to the second surface 107 of the semiconductor device spacer 100). For example, electrical interconnects 104 have a longitudinal length L corresponding to a thickness T0 of the semiconductor device spacer 100 between about 45 μm and about 5000 μm, such as a longitudinal length L between about 100 μm and about 3000 μm. In one example, the longitudinal length L of electrical interconnects 104 is between about 200 μm and about 2000 μm, such as a longitudinal length L between about 400 μm and about 1600 μm. In another embodiment, via 103 and / or electrical interconnects 104 are formed only through a portion of the thickness T0 of the semiconductor device spacer 100. In a further embodiment, the electrical interconnect 104 protrudes from one or more surfaces of the semiconductor device spacer 100 (such as surfaces 105, 107 depicted in Figures 1A and 1B). The electrical interconnect 104 is formed of any conductive material used in the fields of microelectronic devices, integrated circuits, circuit boards, etc. For example, the electrical interconnect 104 is formed of metallic materials such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.

[0035] In the embodiments depicted in Figures 1A to 2B, the electrical interconnect 104 fills the via 103. However, in some embodiments, the electrical interconnect 104 only lining the surface of the sidewall 113 of the via 103 and not fully filling (e.g., completely occupying) the via 103. Therefore, the electrical interconnect 104 may have a hollow core extending through it.

[0036] Furthermore, in Figures 1A and 1B, the diameter of the electrical interconnect 104 is equal to the diameter of the via 103 in which the electrical interconnect 104 is formed. In a further embodiment, as depicted in Figures 2A and 2B, the semiconductor device spacer 100 further includes an adhesive layer 112 and / or a seed layer 114 formed on the semiconductor device spacer 100 for electrical isolation of the electrical interconnect 104. In one embodiment, the adhesive layer 112 is formed on the surface of the semiconductor device spacer 100 adjacent to the electrical interconnect 104 (including the sidewall 113 of the via 103). Therefore, as depicted in Figures 2A and 2B, the diameter of the electrical interconnect 104 is smaller than the diameter of the via 103 in which the electrical interconnect 104 is formed. For example, in Figure 2A, the uniform diameter V2 of the electrical interconnect is smaller than the diameter V1 of the via 103. In Figure 2B, the first diameter V2A of the electrical interconnect is smaller than the diameter V1A, and the diameter V1A tapers to a second diameter V2B that is smaller than the diameter V1B.

[0037] The adhesive layer 112 is formed of any suitable material, including but not limited to titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, silicon nitride, etc. In one embodiment, the thickness of the adhesive layer 112 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness of the adhesive layer 112 is between about 75 nm and about 125 nm, such as about 100 nm.

[0038] The optional seed layer 114 comprises a conductive material, including but not limited to copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. The seed layer 114 is formed on the adhesive layer 112 or directly on the sidewall 113 of the via 103 (on the frame 102). In one embodiment, the thickness of the seed layer 114 is between about 50 nm and about 2000 nm, such as between about 100 nm and about 1000 nm. For example, the thickness of the seed layer 114 is between about 150 nm and about 800 nm, such as about 500 nm.

[0039] Figures 3A and 3B show schematic top-down views of a semiconductor device spacer 100, with an exemplary arrangement of vias 103 formed in the semiconductor device spacer 100. As mentioned above, the vias 103 are generally cylindrical and are therefore presented as circular in Figures 3A and 3B. However, other forms of vias 103 are also contemplated. Figures 3A and 3B further depict an adhesive layer 112 and a seed layer 114 formed within each via 103. The adhesive layer 112 is formed on the sidewall 113 of each via 103, while the seed layer 114 is formed on the adhesive layer 112. However, in some embodiments, electrical interconnects 104 can be formed through the vias 103 without using the adhesive layer 112 and / or the seed layer 114. In other embodiments, the seed layer 114 can be formed on the sidewall 113 of the via 103 without using the adhesive layer 112 before forming the electrical interconnects 104.

[0040] Through-holes 103 are formed through frame 102 in any suitable arrangement and number. As depicted in Figure 3A, six through-holes 103 are formed through frame 102 in a linear arrangement with two columns and three rows, wherein the through-holes 103 in each column and each row are aligned with each other. A first spacing P1 is drawn between adjacent aligned through-holes 103 in each row, a second spacing P2 is drawn between adjacent aligned through-holes 103 in each column, and a third spacing P3 is drawn between adjacent and diagonally opposite through-holes 103 spanning two columns. At least two of the spacings P1, P2, or P3 may be different from each other in length.

[0041] Figure 3B shows alternative arrangements also having two columns and three rows of vias 103, where only the vias 103 in each column are aligned. Thus, the spacing between all adjacent vias 103 is substantially the same in length, represented by spacing P1 in Figure 3B. As mentioned above, "spacing" refers to the distance between the centers of adjacent vias 103. Although two arrangements of vias 103 are depicted, Figures 3A and 3B are merely exemplary, and any suitable number and arrangement of vias 103 can be formed in the frame 102 of the semiconductor device spacer 100.

[0042] Figure 4 shows a flowchart of a representative method 400 for forming a semiconductor device spacer 500. Method 400 has multiple operations 402-416. (Except for cases where context excludes possibilities) the method may include one or more additional operations performed before any defined operation, between two defined operations, or after all defined operations. Figures 5A to 5J schematically show cross-sectional views of the semiconductor device spacer 500 at various stages of the method 400 represented in Figure 4. Therefore, for clarity, Figures 4 and 5A to 5J are described together herein.

[0043] Method 400 begins with optional operation 402 and the corresponding FIG. 5A, wherein one or more protective films 501 are removed from each of two or more device spacer precursor layers 510a, 510b. Precursor layers 510a, 510b serve as building blocks for forming frame 102 of the semiconductor device spacer 500, and therefore are formed of polymer-based dielectric materials as described above with reference to frame 102. For example, precursor layers 510a, 510b are formed of a flowable stacking material. In one embodiment, precursor layers 510a, 510b are formed of an epoxy resin containing ceramic fillers (such as an epoxy resin filled with (e.g., containing) silicon dioxide (SiO2) particles). Other examples of ceramic fillers 130 that can be used in precursor layers 510a and 510b include aluminum nitride (AlN), alumina (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and so on. Typically, the thickness TL of each precursor layer 510a and 510b is less than about 150 μm, such as between about 10 μm and about 150 μm, such as between about 25 μm and about 125 μm, for example between about 50 μm and about 100 μm. During method 400, any suitable amount of precursor layers 510a, 510b can be used to form semiconductor device spacers 100 having any desired size.

[0044] In some embodiments, each precursor layer 510a, 510b is coupled to one or more protective films 501, which are configured to protect the precursor layers 510a, 510b during processing and storage. Therefore, at operation 402, one or more protective films 501 are removed from each precursor layer 510a, 510b to expose one or more main surfaces of each precursor layer 510. As depicted in FIG5A, a single protective film 501 is removed from each of the two precursor layers 510a, 510b to expose surfaces 505, 507 of the precursor layers 510a, 510b for coupling the precursor layers 510a, 510b at operation 404.

[0045] At operation 404, one or more precursor layers 510 are coupled together (e.g., placed abutting each other) and laminated at their exposed surfaces. The coupling and lamination of surfaces 505, 507 of precursor layers 510a, 510b are depicted in Figures 5B and 5C. After the precursor layers 510a, 510b are placed together, as shown in Figure 5B, a vacuum pressure is applied to extract any air trapped between the main surfaces 505, 507 during the coupling of the main surfaces 505, 507. Thus, at least a portion of operation 404 can be performed in a vacuum laminator or vacuum adhesive or any other suitable container for applying vacuum pressure. In one embodiment, the vacuum pressure is ramped up to about 1 hPa or lower during intervals between about 10 seconds and about 90 seconds (e.g., time periods), such as intervals between about 30 seconds and about 60 seconds, such as intervals of about 45 seconds. After reaching the desired vacuum pressure level, the vacuum pressure can be maintained for intervals between approximately 50 and 300 seconds, such as intervals between approximately 100 and 200 seconds. In one example, the vacuum pressure is maintained at approximately 1 hPa or less for intervals of approximately 150 seconds to ensure the removal of any air gaps between the precursor layers 510. During the application of vacuum pressure, the temperature is maintained in the range between approximately 60°C and approximately 100°C, such as between approximately 70°C and approximately 90°C. For example, during the application of vacuum pressure at operation 404, the temperature is maintained at approximately 80°C.

[0046] In Figure 5C, the coupled precursor layers 510a, 510b are fused (e.g., laminated) together by applying pressure to one or more outer surfaces of the precursor layers 510a, 510b. In one embodiment, unilateral pressure is applied to the coupled precursor layers 510a, 510b when they are supported on a support diaphragm or pressure plate (e.g., a platform) (not shown). For example, pressure may be applied to a single side 517 of the coupled precursor layers 510a, 510b when they are supported by pressure plates on opposite sides 515. In other embodiments, bilateral pressure is applied to the coupled precursor layers 510a, 510b. For example, pressure is applied to both sides 515, 517 by means of mechanical means (such as a mechanical press or vice) or by means of pneumatic means (such as a pneumatic device using compressed air). In some embodiments, the lamination of precursor layers 510a, 510b is performed in the same container as the container for which the vacuum is applied, as depicted in FIG. 5B. For example, lamination is performed in a vacuum laminator or a vacuum adhesive machine.

[0047] During the lamination of precursor layers 510a and 510b, the temperature is maintained in the range of about 50°C to about 150°C, such as between about 75°C and about 125°C, such as about 100°C. Exposing precursor layers 510a and 510b to the elevated temperature can soften the precursor layers 510a and 510b and promote adhesion between the precursor layers 510a and 510b. In some embodiments, the pressure applied to the precursor layers 510a and 510b during lamination is between about 0.3 kg / cm² and about 1 kg / cm², such as between about 0.4 kg / cm² and about 0.8 kg / cm², such as about 0.5 kg / cm² or about 0.6 kg / cm².

[0048] After operation 404 is completed, operations 402 and 404 can be repeated to couple and fuse additional precursor layers 510 to the already fused precursor layers 510a, 510b, or the fused precursor layers 510a, 510b can be exposed to a curing process at operation 406 to form frame 502 in preparation for further structuring. For example, one or more additional precursor layers 510 can be coupled and fused to the sides 515 and / or sides 517 of the fused precursor layers 510a, 510b until a desired thickness of precursor material is obtained (corresponding to the final thickness of frame 102). Therefore, except for any protective film 501 coupled to the additional precursor layers 510 themselves, one or more remaining protective films 501 coupled to the fused precursor layers 510a, 510b are removed from the fused precursor layers 510a, 510b to prepare for the attachment of additional precursor layers 510. As depicted in Figure 5D, a single protective film 501 is removed from the side surface 517 of the fused precursor layers 510a and 510b in preparation for coupling the third precursor layer 510c to the side surface 517.

[0049] In other examples, protective film 501 is removed from each side 515, 517 of the fused precursor layers 510a, 510b to prepare for coupling additional third and fourth precursor layers (not shown) to the sides 515, 517 of the fused precursor layers 510a, 510b. Therefore, the amount of protective film 501 removed from the fused precursor layers 510a, 510b can depend on the number of additional precursor layers 510 to be added to the fused precursor layers 510a, 510b. If it is not desired to add additional precursor layers 510 to the fused precursor layers 510a, 510b and the fused precursor layers 510a, 510b are ready for curing, one or more protective films 501 coupled to the two sides 515, 517 can be removed at operation 406 depicted in FIG. 5E before the fused precursor layers 510a, 510b are exposed to the curing process.

[0050] At operation 406, the fused precursor layers 510a, 510b are exposed to a curing process to partially or completely cure (i.e., harden by chemical reaction and crosslinking) the polymer-based dielectric material of the fused precursor layers 510a, 510b and form a frame 502. In some embodiments, the curing process is performed at a high temperature to fully cure the frame 502. In a further embodiment, the curing process is performed at or near ambient (e.g., atmospheric) pressure conditions. During the curing process, the fused precursor layers 510a, 510b are placed on a first pressure plate 520a within a vacuum oven, vacuum bonding machine, vacuum laminator, or any other suitable container for applying vacuum pressure. The first pressure plate 520a includes an anti-stick layer 522 disposed on one side of the first pressure plate 520a, the anti-stick layer 522 being configured to contact and support the fused precursor layers 510a, 510b during curing. The non-stick layer 522 is formed of any suitable non-stick material with a low roughness value (such as Teflon, PDMS, polyimide, fluorinated ethylene propylene, etc.).

[0051] After the fused precursor layers 510a and 510b are placed on the first pressure plate 520a, the temperature and pressure within the vacuum chamber are ramped up to a first curing pressure of approximately 0.001 hPa and a first curing temperature of approximately 110°C. For example, the first curing pressure within the vacuum chamber is ramped up to between approximately 0.001 hPa and approximately 10 hPa, such as between approximately 0.001 hPa and approximately 1 hPa. In one example, the first curing temperature within the vacuum chamber is ramped up to between approximately 60°C and approximately 110°C, such as between approximately 100°C and approximately 110°C. The ramping up of temperature and / or pressure within the vacuum chamber can be performed at intervals between approximately 15 minutes and approximately 45 minutes, such as at intervals between approximately 20 minutes and approximately 40 minutes. In one example, after the fused precursor layers 510a and 510b are placed on the first pressure plate 520a, the temperature and / or pressure are ramped up at intervals of approximately 30 minutes.

[0052] After the desired first curing temperature and / or first curing pressure are reached in the vacuum chamber, the second pressure plate 520b is pressed against the side of the fused precursor layers 510a, 510b opposite to the first pressure plate 520a to clamp or fix the fused precursor layers 510a, 510b in place. Similar to the first pressure plate 520a, the second pressure plate 520b also includes an anti-stick layer 522 disposed on one side of the second pressure plate 520b, the anti-stick layer 522 being configured to contact the fused precursor layers 510a, 510b. Once the fused precursor layers 510a, 510b are fixed between the two pressure plates 520a, 520b, the fused precursor layers 510a, 510b are held in place at the first curing temperature and first curing pressure for an interval between approximately 45 minutes and approximately 75 minutes. For example, the fused precursor layers 510a and 510b can be held between two pressure plates 520a and 520b for a period of about 60 minutes at a temperature of about 110°C and a pressure of about 0.01 MPa.

[0053] In some embodiments, after the fused precursor layers 510a, 510b are held between the two pressure plates 520a, 520b for a desired amount of time at a first curing temperature and a first curing pressure, the first curing temperature is again ramped up to a second curing temperature while maintaining the first curing pressure. For example, the first curing temperature is ramped up again to a second curing temperature between about 150°C and about 180°C, such as between about 170°C and about 180°C. In one example, the second curing temperature is about 180°C. The fused precursor layers 510a, 510b can then be held between the two pressure plates 520a, 520b at the second curing temperature and the first curing pressure for an interval between about 15 minutes and about 45 minutes, such as between 20 minutes and about 40 minutes, such as an interval of about 30 minutes. After exposing the fused precursor layers 510a, 510b to the second curing temperature, the curing process can be completed, and the cured frame 502 is cooled and removed from the pressure plates 520a, 520b.

[0054] In operation 408 and Figure 5F, the cured frame 502 is exposed to a laser ablation process (e.g., direct laser patterning) to form one or more vias 503 in the cured frame 502. Any suitable laser ablation system can be used to form the one or more vias 503. In some examples, the laser ablation system uses an infrared (IR) laser source. In some examples, the laser source is a nanosecond or picosecond ultraviolet (UV) laser. In other examples, the laser is a femtosecond UV laser. In still other examples, the laser source is a femtosecond green laser.

[0055] The laser source of the laser ablation system generates a continuous or pulsed laser beam for patterning the frame 502. For example, the laser source generates a pulsed laser beam with a frequency between 5 kHz and 1000 kHz, such as between 10 kHz and about 200 kHz, such as between 15 kHz and about 100 kHz. In one embodiment, the laser source is configured to deliver the pulsed laser beam with an output power between about 10 watts and about 100 watts, a wavelength between about 200 nm and about 1200 nm, and a pulse duration between about 10 ns and about 5000 ns. In one embodiment, the laser source is configured to deliver the pulsed laser beam at fluctuating time intervals. For example, the laser source delivers one or more pulses with a time delay between about 1 pulse and about 20 pulses. Pulse timing fluctuations can reduce the overall thermal impact of the laser beam on the formation of the via 503 and any other features in the frame 502. Typically, the laser source is configured to form vias 503 in the frame 502 with any desired pattern, such as individual vias 503 or an array of vias 503.

[0056] In some embodiments, the through-hole 503 is formed to have a substantially uniform diameter over its entire length (e.g., between the first surface 525 and the second surface 527 of the frame 502). A through-hole 503 of uniform diameter can be formed by first drilling / perforating the frame 502 with a laser beam generated by a laser source, and then moving the laser beam in a helical (e.g., circular, spiral) motion relative to the central axis of each through-hole 503. A motion system can also be used to angle the laser beam to form a uniform through-hole 503. In other embodiments, the through-hole 503 is formed to have a tapered diameter over its entire length. The tapering of the through-hole 503 can be formed by using the same method described above, or by continuously pulsed laser beams generated by a laser source at a single location within the frame 502.

[0057] After the via 503 is formed, the cured and patterned frame 502 is exposed to a de-smear process. During the de-smear process, any unwanted residues and / or debris caused by laser ablation during the formation of the via 503 are removed. The de-smear process thus cleans the via 503 for subsequent metallization. In one embodiment, the de-smear process is a wet de-smear process. Any suitable solvent, etchant, and / or combination thereof is used in the wet de-smear process. In one example, methanol is used as the solvent and copper(II) chloride dihydrate (CuCl2·H2O) is used as the etchant. The duration of exposure of the frame 502 to the wet de-smear process varies depending on the thickness of the residue. In another embodiment, the de-smear process is a dry de-smear process. For example, the de-smear process is a plasma de-smear process using an O2 / CF4 gas mixture. The plasma decontamination process may include generating plasma by applying approximately 700 W of electricity and causing O2:CF4 to flow at a ratio of approximately 10:1 (e.g., 100:10 sccm) for a time period between approximately 60 seconds and approximately 120 seconds. In a further embodiment, the decontamination process is a combination of a wet process and a dry process.

[0058] Following the decontamination process, frame 502 is prepared for the formation of conductive interconnects. In optional operation 410 and corresponding FIG. 5G, an adhesive layer 512 and / or a seed layer 514 are formed on frame 502. The adhesive layer 512 is formed on desired surfaces of frame 502 (such as the first surface 525 and the second surface 527, and the sidewall 513 of the via 503) to help promote adhesion and prevent the diffusion of the subsequently formed seed layer 514 and electrical interconnects 504. Thus, in one embodiment, the adhesive layer 512 serves as an adhesive layer; in another embodiment, the adhesive layer 512 serves as a barrier layer. However, in both embodiments, the adhesive layer 512 will be described as an "adhesive layer".

[0059] In one embodiment, the adhesive layer 512 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, silicon nitride, or any other suitable material or combination thereof. In one embodiment, the thickness of the adhesive layer 512 is between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the thickness of the adhesive layer 512 is between about 75 nm and about 125 nm, such as about 100 nm. The adhesive layer 512 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0060] The seed layer 514 may be formed on the adhesive layer 512 or directly on the frame 502 (e.g., without forming the adhesive layer 512). In some embodiments, the seed layer 514 is formed on all surfaces of the frame 502, while the adhesive layer 512 is formed only on desired surfaces or portions of the frame 502. For example, the adhesive layer 512 is formed on the first surface 525 and the second surface 527 but not on the sidewall 513 of the via 503, while the seed layer 514 is formed on the first surface 525, the second surface 527, and the sidewall 513 of the via 503. The seed layer 514 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the thickness of the seed layer 514 is between about 0.05 µm and about 0.5 µm, such as between about 0.1 µm and about 0.3 µm. For example, the thickness of the seed layer 514 is between about 0.15 µm and about 0.25 µm, such as about 0.2 µm. In one embodiment, the thickness of the seed layer 514 is between about 0.1 µm and about 1.5 µm.

[0061] Similar to the adhesive layer 512, the seed layer 514 is formed by any suitable deposition process (such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc.). In one embodiment, the copper seed layer 514 is formed on the molybdenum adhesive layer 512 on the frame 502. The combination of the molybdenum adhesive layer and the copper seed layer enables improved adhesion to the surface of the frame 502 and reduces undercut of conductive interconnects during subsequent seed layer etching processes.

[0062] At operation 412, corresponding to FIG. 5H, a spin-coated / spray-coated or dry resist film 550 (such as photoresist) is applied over the first surface 525 and the second surface 527 of frame 502, and subsequently patterned. In one embodiment, the resist film 550 is patterned by selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to frame 502 prior to the formation of the resist film 550. The adhesion promoter improves the adhesion of the resist film 550 to frame 502 by creating an interfacial adhesive layer for the resist film 550 and by removing any moisture from the surface of frame 502. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0063] After the resist film 550 is applied, the frame 502 is exposed to a resist film development process. Development of the resist film 550 results in the exposure of vias 503 (shown in FIG. 5H), which may now have an adhesion layer 512 and / or a seed layer 514 formed on the vias 503. In one embodiment, the film development process is a wet process, such as a wet process that includes exposing the resist film 550 to a solvent. In one embodiment, the film development process is a wet etching process using an aqueous etching process. For example, the film development process is a wet etching process using a buffered etching process that is selective for the desired material. Any suitable combination of wet solvents or wet etchants is used in the resist film development process.

[0064] In operation 414 and FIG. 5I, an electrical interconnect 504 is formed through the exposed via 503, and subsequently the resist film 550 is removed. The electrical interconnect 504 is formed by any suitable method, including electroplating and electroless plating. In one embodiment, the resist film 550 is removed via a wet process. As depicted in FIG. 5I, after the removal of the resist film 550, the electrical interconnect 504 completely fills the via 503 and protrudes from the first surface 525 and the second surface 527 of the frame 502. In some embodiments, the electrical interconnect 504 only lining the sidewalls 513 of the via 503, without completely filling the via 503. In one embodiment, the electrical interconnect 504 is formed of copper. In other embodiments, the electrical interconnect 504 is formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0065] In operation 416 and FIG. 5J, the frame 502 in which the electrical interconnects 504 are formed is exposed to a seed layer etching process to remove the adhesive layer 512 and / or seed layer 514 exposed on the outer surfaces of the frame 502 (e.g., the first surface 525 and the second surface 527). After the seed layer etching process is completed in operation 416, the frame 502 is ready to be used as a semiconductor device spacer 500. In some embodiments, the adhesive layer 512 and / or seed layer 514 formed between the electrical interconnects 504 and the sidewalls 513 of the via 503 are retained after the seed layer etching process. In one embodiment, the seed layer etching is a wet etching process including rinsing and drying the frame 502. In one embodiment, the seed layer etching process is a buffered etching process selective for a desired material (such as copper, tungsten, aluminum, silver, or gold). In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants is used for the seed layer etching process.

[0066] As discussed above, Figures 4 and 5A through 5J illustrate a representative method 400 for forming a spacer 500 in a semiconductor device. Figures 6 and 7A through 7E illustrate an alternative method 600 for forming a block 502 at operation 406. Method 600 typically includes five operations 602-610, and an optional operation 602 (corresponding to Figure 7A) is substantially similar to operation 402 of method 400. Therefore, for clarity, method 600 will be described starting with operation 604.

[0067] Thus, after the protective film 501 is peeled off from the precursor layers 510a and 510b, the precursor layers 510a and 510b are laminated together in operation 604 and FIG. 7B. Similar to operation 404, the precursor layers 510a and 510b are placed abutting each other at their exposed surfaces 505 and 507, and then a vacuum pressure is applied to extract any air trapped between the coupling surfaces 505 and 507. In one embodiment, the precursor films 510a and 510b are exposed to a vacuum pressure between about 0.001 hPa and about 100 hPa. For example, the precursor films 510a and 510b are exposed to a vacuum pressure between about 0.001 hPa and about 10 hPa, such as a vacuum pressure between about 0.001 hPa and about 1 hPa. Vacuum pressure is applied at intervals of approximately 10 seconds to approximately 60 seconds, such as at intervals of approximately 15 seconds to approximately 45 seconds, such as at approximately 30 seconds. During the application of vacuum pressure, the temperature is maintained in the range of approximately 60°C to approximately 100°C, such as between approximately 70°C and approximately 90°C, such as at approximately 80°C.

[0068] After exposing precursor films 510a and 510b to vacuum pressure, the precursor films 510a and 510b are laminated together by applying positive pressure to one or more outer surfaces of the precursor layers 510a and 510b. As described above, the applied pressure can be unilateral or bilateral and is applied by a mechanical or pneumatic process. In one embodiment, a pressure between about 0.3 kg / cm² and about 1 kg / cm² is applied to one or more outer surfaces of the precursor layers 510a and 510b. For example, the precursor films 510a and 510b are exposed to a positive pressure between about 0.3 kg / cm² and about 0.8 kg / cm², such as a pressure of about 0.5 kg / cm². The positive pressure is applied at intervals between about 10 seconds and about 60 seconds, such as at intervals between about 15 seconds and about 45 seconds, such as about 30 seconds. During the application of positive pressure, the temperature is maintained in the range of approximately 60°C to approximately 100°C, such as between approximately 70°C and approximately 90°C, such as approximately 80°C.

[0069] After the precursor layers 510a and 510b are fused together, they are then laminated to the substrate 620 in operation 606 and FIG. 7C. The substrate 620 is any suitable type of substrate with an anti-adhesion layer 622 disposed on its side surface, the anti-adhesion layer 622 being configured to contact and support the fused precursor layers 510a and 510b. In some embodiments, the substrate 620 comprises a metallic or ceramic material and has a thickness between about 0.5 mm and about 1 mm. For example, the substrate 620 has a thickness between about 0.6 mm and about 0.8 mm, such as about 0.7 mm or about 0.75 mm. In some embodiments, the lateral dimension of the substrate 620 exceeds the dimensions of the precursor layers 510a and 510b, such that the entire lateral region of the precursor layers 510a and 510b is supported on the substrate 620. The non-stick layer 622 is formed of any suitable non-stick material with a low roughness value (such as Teflon, PDMS, polyimide, fluorinated ethylene propylene, etc.).

[0070] Similar to operation 604, laminating the fused precursor layers 510a, 510b to the substrate 620 includes: coupling the fused precursor layers 510a, 510b to the anti-adhesion layer 622, and exposing the precursor layers 510a, 510b and the substrate 620 to a vacuum, followed by positive pressure. In one embodiment, the vacuum pressure is between about 0.001 hPa and about 100 hPa. For example, exposing the coupled precursor films 510a, 510b and the substrate 620 to a vacuum pressure between about 0.001 hPa and about 10 hPa, such as a vacuum pressure between about 0.001 hPa and about 1 hPa. The vacuum pressure is applied for intervals between about 10 seconds and about 60 seconds, such as intervals between about 15 seconds and about 45 seconds, such as about 30 seconds. During the application of vacuum pressure, the temperature is maintained in the range of about 60°C to about 120°C, such as between about 70°C and about 110°C, such as about 80°C.

[0071] Following the vacuum, positive pressure is applied to one or more outer surfaces of the coupled precursor layers 510a, 510b and / or substrate 620. In one embodiment, the positive pressure is between about 0.3 kg / cm² and about 1 kg / cm², such as between about 0.4 kg / cm² and about 0.8 kg / cm², such as a pressure of about 0.5 kg / cm². The positive pressure is applied for intervals between about 10 seconds and about 60 seconds, such as between about 15 seconds and about 45 seconds, such as about 30 seconds. During the application of positive pressure, the temperature is maintained in the range between about 60°C and about 120°C, such as between about 70°C and about 110°C, such as about 80°C.

[0072] After operation 606 is completed, operations 602 and 604 can be repeated to couple and fuse additional precursor layers 510 to the precursor layers 510a and 510b already fused to the substrate 620, or the precursor layers 510a and 510b can be exposed to a curing process in operation 608 and FIG. 7D to form frame 502. Prior to the curing process, any residual protective film 501 on the fused precursor layers 510a and 510b is removed. In one embodiment, the curing process in operation 608 includes exposing the fused precursor layers 510a and 510b and the substrate 620 to a constant temperature between about 150°C and about 200°C for intervals between about 15 minutes and about 90 minutes. For example, exposing the fused precursor layers 510a and 510b and the substrate 620 to a temperature of about 180°C for intervals of about 30 minutes.

[0073] In another embodiment, the curing process includes exposing the fused precursor layers 510a, 510b and substrate 620 to a variable temperature. For example, exposing the fused precursor layers 510a, 510b and substrate 620 to a first temperature between about 80°C and about 120°C for an interval between about 45 minutes and about 75 minutes, followed by exposure to a second temperature between about 160°C and about 200°C for an interval between about 15 minutes and about 45 minutes. For example, exposing the fused precursor layers 510a, 510b and substrate 620 to a first temperature of about 100°C for an interval of about 60 minutes, followed by exposure to a second temperature of about 180°C for an interval of about 30 minutes. After curing, in operation 610 and FIG. 7E, the cured precursor frame 502 is removed from substrate 620 for further structuring.

[0074] Semiconductor device spacers 100 and 500 can be used in any suitable stacked PCB components, stacked package components, or other suitable stacked electronic devices. In an exemplary embodiment depicted in FIG8, two semiconductor device spacers 100 are used within a PCB component 800. As shown, the semiconductor device spacers 100 are disposed between two PCBs 850a and 850b and are configured to position the first PCB 850a relative to the second PCB 850b such that physical space 820 is maintained between the first PCBs 850a and 850b, while they are electrically connected through the semiconductor device spacers 100. Thus, the semiconductor device spacers 100 prevent the PCBs 850a and 850b from contacting each other, and therefore reduce the risk of short circuits between the PCBs 850a and 850b. Furthermore, inserting the semiconductor device spacer 100 between PCBs 850a and 850b ensures proper and easy placement of PCBs 850a and 850b relative to each other, thereby achieving proper alignment of contacts and holes between PCBs 850a and 850b. In addition, the convenience of the physical space 820 reduces heat trapped between adjacent PCBs 850a and 850b, thus reducing the risk of overheating and combustion of PCBs 850a and 850b. Although only two PCBs 850a and 850b are shown in Figure 8, it is envisioned that the semiconductor device spacer 100 can be used to stack and interconnect two or more PCBs in parallel.

[0075] PCBs 850a and 850b are formed of any suitable dielectric material. For example, PCBs 850a and 850b are formed of glass fiber reinforced epoxy resin (e.g., FR-1, FR-2, FR-4, halogen-free FR-4, high Tg FR-4, and FR-5). Other suitable examples of dielectric materials include resin-coated copper (RCC), polyimide, polytetrafluoroethylene (PTFE), CEM-3, etc. PCBs 850a and 850b can be single-sided or double-sided circuit boards. In some embodiments, at least one of PCBs 850a and 850b includes an electrical distribution layer 870 formed on PCBs 850a and 850b and conductively connected to the electrical interconnects 104 of the semiconductor device spacer 100. For example, as depicted in FIG8, both PCBs 850a and 850b include electrical distribution layers 870a and 870b respectively formed on PCBs 850a and 850b and adjacent to physical space 820. Electrical distribution layers 870a and 870b are formed of any suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. The thickness of each electrical distribution layer 870a and 870b is between about 40 μm and about 100 μm, such as between about 60 μm and about 80 μm. For example, each electrical distribution layer 870a and 870b has a thickness of about 70 μm. The electrical distribution layers 870a and 870b may have similar or different thicknesses relative to each other. Furthermore, although two electrical distribution layers 870a and 870b are depicted, each PCB 850a and 850b may have more or fewer electrical distribution layers formed on its surface. In other embodiments, PCBs 850a and 850b include conductive pads or other suitable electrical contacts for interconnection through the semiconductor device spacer 100.

[0076] PCBs 850a and 850b are electrically coupled to the semiconductor device spacer 100 via one or more solder bumps 840 disposed between electrical contacts (e.g., electrical distribution layers 870a and 870b) on PCBs 850a and 850b and electrical interconnects 104 on the semiconductor device spacer 100. In one embodiment, the solder bumps 840 are formed of a material substantially similar to the electrical interconnects 104 and / or electrical distribution layers 870a and 870b. For example, the solder bumps 840 are formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. Typically, the height B of the solder bumps 840 is less than about 50 μm, such as between about 5 μm and about 45 μm, such as between about 10 μm and about 30 μm. For example, the solder bumps 840 have a height B of about 20 μm. In summary, the semiconductor device spacer 100 with solder bumps 840 creates a physical space 820 with a height S between approximately 95 μm and approximately 5040 μm. Typically, the height S of the physical space 820 is substantially similar to the thickness of the frame 102 of the semiconductor device spacer 100.

[0077] In one embodiment, solder bump 840 includes a C4 solder bump. In a further embodiment, solder bump 840 includes a C2 (Cu pillar with solder cap) solder bump. Using C2 solder bumps allows for smaller pitch lengths and improved thermal and / or electrical properties of the PCB component 800. Solder bump 840 is formed by any suitable bump forming process, including but not limited to electrochemical deposition (ECD) plating and metal diffusion bonding (e.g., gold to gold).

[0078] In one embodiment, an encapsulating material 848 is used to fill the voids between the semiconductor device spacer 100 and the PCBs 850a, 850b to enhance the reliability of the solder bumps 840 disposed in the voids. The encapsulating material 848 is any suitable type of encapsulant or underfill material and substantially surrounds the solder bumps 840. In one example, the encapsulating material 848 includes pre-assembled underfill materials such as non-flowing underfill (NUF) material, non-conductive paste (NCP) material, and non-conductive film (NCF) material. In one example, the encapsulating material 848 includes post-assembled underfill materials such as capillary underfill (CUF) material and molded underfill (MUF) material. In one embodiment, the encapsulating material 848 comprises a resin containing low-expansion fillers, such as epoxy resins filled with (e.g., containing) SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O16, ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O12, MgO, TiO2, ZnO, etc.

[0079] In another exemplary embodiment depicted in FIG. 9, a semiconductor device spacer 100 is used in PCB element 900. PCB element 900 is substantially similar to PCB assembly 800, but includes substrate 950 in place of one of the PCBs 850a and 850b described above. Therefore, semiconductor device spacer 100 can be used to interconnect and stack individual PCBs 850 with substrates 950. Although only a single PCB 850 and a single substrate 950 are shown in FIG. 9, it is contemplated that semiconductor device spacer 100 can be used to stack and interconnect any number and combination of PCBs 850 and / or substrates 950 in parallel. In some embodiments, two or more substrates 950 may be stacked and interconnected without excluding PCBs 850.

[0080] Substrate 950 is any suitable type of substrate for electronic devices. In one embodiment, substrate 950 is configured as a core structure for semiconductor packaging, interposers, intermediate bridging connectors, PCB spacers, wafer carriers, etc. Thus, substrate 950 is formed of any suitable substrate material, including but not limited to III-V compound semiconductor materials, silicon, and crystalline silicon (e.g., Si). <100> or Si <111> The substrate 950 can be made of silicon oxide, germanium silicon, doped or undoped silicon, doped or undoped polycrystalline silicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, the substrate 950 is a monocrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 950 is a p-type or n-type silicon solar cell substrate.

[0081] In a further embodiment, the substrate 950 further includes an optional passivation layer 905, such as an oxide passivation layer 905, formed on a desired surface of the substrate 950. For example, the substrate 950 may include a silicon oxide passivation layer 905 formed on substantially all surfaces of the substrate 950, and thus the passivation layer 905 substantially surrounds the substrate 950. The passivation layer 905 provides a protective external barrier layer for the substrate 950 against corrosion and other forms of damage. In some examples, the thickness of the passivation layer 905 is between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. In one example, the thickness of the passivation layer 905 is between about 300 nm and about 2 μm, such as about 1.5 μm.

[0082] The substrate 950 may further have a polygonal or circular shape. For example, the substrate 950 comprises a substantially square silicon substrate with or without beveled edges, having a lateral dimension between about 140 mm and about 180 mm. In another example, the substrate 950 comprises a circular silicon-containing wafer with a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example, about 300 mm. Unless otherwise specified, the embodiments and examples described herein are carried out on a substrate 950 with a thickness between about 50 μm and about 1000 μm, such as between about 90 μm and about 780 μm. For example, the thickness of the substrate 950 is between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm.

[0083] In some embodiments, substrate 950 is a patterned substrate and includes one or more vias 903 formed in substrate 950 to allow conductive electrical interconnects 904 to be wired through the one or more vias 903. As depicted in FIG9, the vias 903 are formed as single and isolated vias 903 through substrate 950, or as one or more groups or arrays. In one embodiment, the minimum spacing between each via 903 is less than about 1000 μm, such as between about 25 μm and about 200 μm. For example, the spacing between vias 903 is between about 40 μm and about 150 μm.

[0084] Typically, one or more vias 903 are substantially cylindrical. However, other suitable forms for vias 903 are also contemplated. In one embodiment, the diameter of the via 903 and any electrical interconnects 904 thus formed in the via 903 is less than about 500 μm, such as a diameter less than about 250 μm. For example, the diameter of the via 903 and / or the electrical interconnect 904 is between about 25 μm and about 100 μm, such as a diameter between about 30 μm and about 60 μm. In one embodiment, the diameter of the via 903 and / or the electrical interconnect 904 is about 40 μm.

[0085] In one embodiment, the via 903 and / or the electrical interconnect 904 are formed through the entire thickness of the substrate 950. For example, the longitudinal length of the via 903 and / or the electrical interconnect 904 corresponds to the total thickness of the substrate 950 between about 50 μm and about 1000 μm, such as a longitudinal length between about 200 μm and about 800 μm. In one example, the longitudinal length of the via 903 and / or the electrical interconnect 904 is between about 400 μm and about 600 μm, such as a longitudinal length of about 500 μm. In another embodiment, the via 903 and / or the electrical interconnect 904 are formed through only a portion of the thickness of the substrate 950. In a further embodiment, as depicted in FIG. 9, the electrical interconnect 904 protrudes from one or more surfaces of the substrate 950. Similar to the electrical interconnect 104, the electrical interconnect 904 is formed of any conductive material used in the fields of microelectronic devices, integrated circuits, circuit boards, etc. For example, the electrical interconnect 904 is formed of metallic materials such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.

[0086] In some embodiments, the substrate 950 further includes an adhesive layer 912 and / or a seed layer 914 formed on a desired surface of the substrate 950, and an electrical interconnect 904 is formed on the adhesive layer 912 and / or the seed layer 914. For example, the adhesive layer 912 and / or the seed layer 914 is formed on the sidewall 913 of the via 903. Typically, the adhesive layer 912 and / or the seed layer 914 are substantially similar in material and morphology to the adhesive layers 112, 512 and the seed layers 114, 514. In some embodiments, the adhesive layer 912 and / or the seed layer 914 is formed on a passivation layer 905, which is formed on the sidewall 913 of the via 903.

[0087] In some embodiments, substrate 950 further includes one or more optional electrical distribution layers 970 disposed on a desired surface of substrate 950. In FIG. 9, electrical distribution layer 970 is disposed on a surface adjacent to physical space 820, opposite to optional electrical distribution layer 870, and in contact with electrical interconnect 904. Electrical distribution layer 970 is formed of any suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In a further embodiment, substrate 950 may include conductive pads or other suitable electrical contacts for interconnection with PCB 850 through semiconductor device spacer 100.

[0088] In another exemplary embodiment depicted in FIG. 10, a semiconductor device spacer 100 is used in PCB element 1000. PCB element 1000 is substantially similar to PCB element 900, but includes a semiconductor core element 1050 instead of the aforementioned substrate 950. Therefore, the semiconductor device spacer 100 can be used to interconnect and stack a single PCB 850 with the semiconductor core element 1050. Although only a single PCB 850 and a single semiconductor core element 1050 are shown in FIG. 10, it is contemplated that the semiconductor device spacer 100 can be used to stack and interconnect any number and combination of PCBs 850 and / or semiconductor core elements 1050 in parallel. In some embodiments, two or more semiconductor core elements 1050 may be stacked and interconnected without excluding PCB 850.

[0089] Semiconductor core element 1050 can be used for structural support and electrical interconnection in semiconductor packages. In other examples, semiconductor core element 1050 can be used as a carrier structure for surface mount devices such as wafers or graphics cards. Semiconductor core element 1050 typically includes a core structure 1002, an optional passivation layer 1005, and an insulating layer 1016.

[0090] In one embodiment, core structure 1002 includes a patterned (e.g., structured) substrate formed of any suitable substrate material. For example, core structure 1002 includes a substrate formed of any material described above with reference to substrate 950. The substrate used to form core structure 1002 may further have a polygonal or circular shape. For example, core structure 1002 includes a substantially square silicon substrate with or without beveled edges, having a lateral dimension between about 120 mm and about 180 mm. In another example, core structure 1002 includes a circular silicon-containing wafer with a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 50 mm, for example, about 300 mm. Unless otherwise specified, the embodiments and examples described herein are carried out on a substrate with a thickness between about 50 μm and about 1000 μm, such as between about 90 μm and about 780 μm. For example, the thickness of the substrate used for the core structure 1002 is between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm.

[0091] Similar to substrate 950, core structure 1002 further includes one or more core vias 1003 formed in core structure 1002 to allow conductive interconnects to be wired through core structure 1002. The core vias 1003 are formed as single, isolated core vias 1003 through core structure 1002 or as one or more groups or arrays. In one embodiment, the minimum spacing between each core via 1003 is less than about 1000 μm, such as between about 25 μm and about 200 μm. For example, the spacing is between about 40 μm and about 150 μm. In one embodiment, the diameter of one or more core vias 1003 is less than about 500 μm, such as a diameter less than about 250 μm. For example, the diameter of the core via 1003 is between about 25 μm and about 100 μm, such as a diameter between about 30 μm and about 60 μm. In one embodiment, the diameter of the core via 1003 is about 40 μm.

[0092] Optional passivation layer 1005 is similar to passivation layer 905 and is formed on one or more surfaces of core structure 1002, including one or more sidewalls 1013 of core via 1003. In one embodiment, passivation layer 1005 is formed on substantially all outer surfaces of core structure 1002 such that passivation layer 1005 substantially surrounds core structure 1002. In one embodiment, passivation layer 1005 is formed of an oxide film or oxide layer (such as a thermal oxide layer). For example, passivation layer 1005 may be a silicon oxide layer. In some examples, the thickness of passivation layer 1005 is between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. In one example, the thickness of passivation layer 1005 is between about 300 nm and about 2 μm, such as about 1.5 μm.

[0093] An insulating layer 1016 is formed on one or more surfaces of the core structure 1002 or the passivation layer 1005, and substantially surrounds the passivation layer 1005 and / or the core structure 1002. Therefore, the insulating layer 1016 extends into the core via 1003 and coats the passivation layer 1005 formed on the sidewall 1013 of the core via 1003 or directly coats the core structure 1002. In one embodiment, the insulating layer 1016 has a thickness of less than about 50 μm, such as less than about 20 μm, from the outer surface of the core structure 1002 or the passivation layer 1005 to the adjacent outer surface of the insulating layer 1016. For example, the thickness of the insulating layer 1016 is between about 5 μm and about 10 μm.

[0094] In one embodiment, similar to frame 102 of semiconductor device spacer 100, insulating layer 1016 is formed of a polymer-based dielectric material. For example, insulating layer 1016 is formed of a flowable stacking material. Thus, although insulating layer 1016 is referred to as "insulating layer" hereinafter, insulating layer 1016 may also be described as a dielectric layer. In a further embodiment, insulating layer 1016 is formed of an epoxy resin material having ceramic filler (such as silicon dioxide (SiO2) particles). Other examples of ceramic fillers that can be used to form the insulating layer 1016 include aluminum nitride (AlN), alumina (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and so on. In some examples, the ceramic fillers used to form the insulating layer 1016 have particles with diameters ranging from about 40 nm to about 1.5 μm, such as particles between about 80 nm and about 1 μm. For example, the ceramic fillers have particles with diameters between about 200 nm and about 800 nm, such as particles between about 300 nm and about 600 nm. In some embodiments, the ceramic filler includes particles with a diameter less than about 10% of the width or diameter of the adjacent core through-hole 1003 in the core structure 1002, such as particles with a diameter less than about 5% of the width or diameter of the core through-hole 1003.

[0095] One or more through-element vias 1023 are formed through the insulating layer 1016 at locations where the insulating layer 1016 extends into the core via 1003, allowing electrical interconnects 1004 to be wired through the one or more through-element vias 1023. For example, the through-element via 1023 is centrally formed within the core via 1003, in which the insulating layer 1016 is disposed. Thus, the insulating layer 1016 forms one or more sidewalls of the through-element via 1023, wherein the diameter of the through-element via 1023 is smaller than the diameter of the core via 1003. In one embodiment, the diameter of the through-element via 1023 is less than about 100 μm, such as less than about 75 μm. For example, the diameter of the through-element via 1023 is less than about 50 μm, such as less than about 35 μm. In one embodiment, the diameter of the through-element via 1023 is between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm.

[0096] In one embodiment, an electrical interconnect 1004 is formed through the entire thickness of the semiconductor core element 1050, and thus through-element vias 1023 and core vias 1003 are formed. For example, the longitudinal length of the electrical interconnect 1004 and / or through-element vias 1023 and / or core vias 1003 corresponds to the total thickness of the semiconductor core element 1050 between about 50 μm and about 1000 μm, such as a longitudinal length between about 200 μm and about 800 μm. In one example, the longitudinal length of the electrical interconnect 1004 and / or through-element vias 1023 and / or core vias 1003 is between about 400 μm and about 600 μm, such as a longitudinal length of about 500 μm. In another embodiment, the electrical interconnect 1004 and / or through-element vias 1023 and / or core vias 1003 are formed only through a portion of the thickness of the semiconductor core element 1050. In a further embodiment, as depicted in FIG10, electrical interconnect 1004 protrudes from one or more surfaces of semiconductor core element 1050. Similar to the interconnects described above, electrical interconnect 1004 is formed of any conductive material used in the fields of integrated circuits, circuit boards, wafer carriers, etc. For example, electrical interconnect 1004 is formed of metallic materials such as copper, aluminum, gold, nickel, silver, palladium, tin, etc.

[0097] In some embodiments, the semiconductor core element 1050 further includes an adhesive layer 1012 and / or a seed layer 1014 formed on a desired surface of the insulating layer 1016, with electrical interconnects 1004 formed on the adhesive layer 1012 and / or the seed layer 1014. For example, the adhesive layer 1012 and / or the seed layer 1014 are formed on the sidewalls of the through-hole 1023. Typically, the adhesive layer 1012 and / or the seed layer 1014 are substantially similar in material and morphology to the adhesive layers 112, 512 and the seed layers 114, 514.

[0098] In some embodiments, the semiconductor core element 1050 further includes one or more optional electrical distribution layers 1070 disposed on a desired surface of the semiconductor core element 1050. In FIG. 10, the electrical distribution layer 1070 is disposed on a surface adjacent to the physical space 820, opposite to the optional electrical distribution layer 870, and in contact with the electrical interconnect 1004 and solder bump 840. The electrical distribution layer 1070 is formed of any suitable conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In a further embodiment, the semiconductor core element 1050 may include conductive pads or other suitable electrical contacts for interconnection with the PCB 850 through the semiconductor device spacer 100.

[0099] Figures 11A to 11E schematically illustrate top views of possible arrangements of semiconductor device spacers 100 when coupled to at least a single device (such as PCB 850), as described above with reference to Figures 8 to 10. Typically, semiconductor device spacers 100 can be arranged in any suitable number and arrangement between adjacent PCBs or other devices. As depicted in Figure 11A, two semiconductor device spacers 100 are disposed along the edges of opposite ends of PCB 850 on the top surface of PCB 850. Figure 11B shows three semiconductor device spacers 100 disposed along three edges of the top surface of PCB 850, and Figure 11C shows four semiconductor device spacers 100 disposed along all four edges of the top surface of PCB 850. In an alternative example, Figure 11D shows a single semiconductor device spacer 100 disposed centrally along the top surface of PCB 850 and extending from one edge to its opposite edge.

[0100] Figures 11A to 11D depict exemplary arrangements in which one or more semiconductor device spacers 100 have a lateral dimension spanning one or more edges (e.g., sides) of adjacent devices. Figure 11E depicts an alternative exemplary arrangement in which one or more semiconductor device spacers 100 are smaller than the length of the side of the adjacent device. As shown in Figure 11E, two semiconductor device spacers 100 are centrally disposed along the top surface of PCB 850, each semiconductor device spacer 100 having a lateral dimension substantially smaller than the length of the side of PCB 850. In some embodiments, the ratio of the area of ​​the semiconductor device spacer 100 to the area of ​​PCB 850 is between about 0.01 and about 0.99, such as between about 0.05 and about 0.95. For example, the ratio of the area of ​​the semiconductor device spacer 100 to the area of ​​PCB 850 is between about 0.1 and about 0.9, such as between about 0.15 and about 0.85.

[0101] Compared to spacers used in conventional stacked packages, PCBs, and wafer carrier structures, the use of semiconductor device spacers 100 in the embodiments shown above offers several advantages. These benefits include improved thermal management for enhanced electrical efficiency and reliability of the stacked device architecture. The improved thermal conductivity of these spacers, and the ability to pattern fine features within them, further enable thin form factor structures with greater I / O scaling to meet the increasing bandwidth and power efficiency requirements of artificial intelligence (AI) and high-performance computing (HPC). Furthermore, the fabrication method of the semiconductor device spacers described herein offers high efficiency and flexibility for 3D integration at a relatively low manufacturing cost compared to conventional spacers and stacking techniques.

[0102] While the foregoing describes embodiments of this disclosure, other and further embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, and the scope of this disclosure is determined by the appended claims.

[0103] 100: Semiconductor device spacers 102: Box 103: Hole or through hole 104: Electrical interconnection 105: First Surface 107: Second Surface 110: Floor 110a-110c: Single layer 112: Adhesive layer 113: Sidewall 114: Seed Crystal Layer 130: Ceramic filler 400: Method 402: Operation 404: Operation 406: Operation 408: Operation 410: Operation 412: Operation 414: Operation 416: Operation 424: First Surface 500: Semiconductor device spacers 501: Protective film 502: Cured frame 503: Through hole 504: Electrical interconnection 505: Exposed Surface 507: Exposed Surface 510: Precursor layer 510a: Precursor layer 510b: Precursor layer 510c: Third precursor layer 512: Adhesive layer 513: Sidewall 514: Seed layer 515: Opposite side 517: Single side 520a: First pressure plate 520b: Second pressure plate 522: Anti-stick layer 525: First Surface 527: Second Surface 550: Resist film 600: Method 602-610: Operation 620:Substrate 622: Anti-stick layer 800: PCB components 820: Physical Space 840: Solder bump 848: Packaging Material 850:PCB 850a:PCB 850b:PCB 870: Electric distribution layer 870a: Electric distribution layer 870b: Electricity distribution layer 900: PCB components 903: Through hole 904: Electrical Interconnection 905: Passivation layer 912: Adhesive layer 913: Sidewall 914: Seed Crystal Layer 950:Substrate 970: Electricity Distribution Layer 1000: PCB components 1002: Core Structure 1003: Core through hole 1004: Electrical Interconnection 1005: Passivation layer 1012: Adhesive layer 1013: Sidewall 1014: Seed layer 1016: Insulation layer 1023: Through-hole for components 1050: Semiconductor core component 1070: Electricity distribution layer B: Height P0: Minimum spacing P1: First spacing P2: Second spacing P3: Third spacing S: Height T0: Thickness Ta: Thickness Tb: Thickness Tc: Thickness TL: Thickness V1: Diameter V1A: Diameter V1B: Diameter V2: Diameter V2A: Diameter V2B: Diameter

[0104] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device spacer, comprising: A frame having a first surface opposite a second surface, the frame further comprising: a frame material comprising a polymer-based dielectric material having a ceramic filler; and a via comprising a via surface defining an opening extending through the frame from the first surface to the second surface; an electrical interconnect disposed within the via and on the via surface; and a barrier layer lining the via surface and disposed between the via surface and the electrical interconnect, the barrier layer comprising molybdenum.

2. The semiconductor device spacer as claimed in claim 1, wherein the semiconductor device spacer is disposed between two semiconductor devices.

3. The semiconductor device spacer as claimed in claim 2, wherein the frame has a lateral dimension smaller than one of the lateral dimensions of each of the two semiconductor devices.

4. The semiconductor device spacer as claimed in claim 1, wherein the ceramic filler comprises particles formed from at least one of the following: silicon dioxide, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, or zinc oxide.

5. The semiconductor device spacer as claimed in claim 4, wherein a packing density of the particles is between about 0.02 and about 0.

99.

6. A semiconductor device element, comprising: The first printed circuit board (PCB); First, second PCB; The device spacer is inserted between the first PCB and the second PCB to create a physical space between the first PCB and the second PCB. The device spacer further includes: a frame having a first surface opposite a second surface, the frame further including: a frame material comprising a polymer-based dielectric material having ceramic filler particles; a through-hole comprising a through-hole surface defining an opening extending through the frame from the first surface to the second surface; an electrical interconnect disposed within the through-hole on the through-hole surface to form at least a portion of a conductive path extending between at least a portion of the first PCB and the second PCB; and a barrier layer lining the through-hole surface and disposed between the through-hole surface and the electrical interconnect, the barrier layer comprising molybdenum.

7. The semiconductor device element as claimed in claim 6, wherein the ceramic filler particles comprise particles formed from at least one of the following: silicon dioxide, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, or zinc oxide.

8. The semiconductor device element as claimed in claim 7, wherein the packing density of the particles is between about 0.02 and about 0.99 by volume.

9. The semiconductor device element as claimed in claim 6, wherein the thickness of the frame is between about 400 μm and about 1600 μm.

10. The semiconductor device element as claimed in claim 9, wherein a height of the physical space is substantially similar to the thickness of the frame.

11. The semiconductor device element as claimed in claim 6, further comprising: Solder bumps conductively couple the electrical interconnects to the electrical distribution layers of the first PCB and the second PCB, and the solder bumps have a maximum height of about 50 μm.

12. The semiconductor device element as claimed in claim 11, further comprising: An encapsulating material that substantially surrounds the solder bump.

13. The semiconductor device element of claim 6, wherein the ratio of an area of ​​the device spacer to an area of ​​a surface of the first PCB or the second PCB is between about 0.15 and about 0.

85.

14. A semiconductor device element, comprising: A semiconductor core structure includes: a silicon or glass core including a first through-hole formed therein; and a first electrical interconnect formed within the first through-hole; and a device spacer including: a frame having a first frame surface opposite to a second frame surface, the frame further including: a frame material comprising a polymer-based dielectric material having ceramic filler particles; and a second through-hole extending through the frame from the first frame surface to the second frame surface; a second electrical interconnect disposed within the second through-hole and electrically coupled to the first electrical interconnect; and a barrier layer lining the second through-hole, wherein the barrier layer comprises molybdenum.

15. The semiconductor device element of claim 14, wherein the ceramic filler particles comprise particles formed from at least one of the following: silicon dioxide, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, or zinc oxide.

16. The semiconductor device element as claimed in claim 15, wherein a maximum diameter of the particle is about 0.6 μm.

17. The semiconductor device element of claim 15, wherein a packing density of the particle is between about 0.02 and about 0.99 by volume.

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