Semiconductor structure and method of forming the same

Abstract

The semiconductor structure of the present invention includes a back-side dielectric layer; a back-side etch-stop layer located on the back-side dielectric layer; a first source / drain structure and a second source / drain structure located on the back-side etch-stop layer and separated from each other along a first direction; a front-side source / drain contact located on the first source / drain structure and the second source / drain structure; a back-side contact structure passing through the back-side dielectric layer and the back-side etch-stop layer to couple to the first source / drain structure; a via extending through the back-side dielectric layer and the back-side etch-stop layer; a substrate fin located between the back-side etch-stop layer and the second source / drain structure; and an isolation structure including a portion extending along the sidewall of the substrate fin. The back-side contact structure intersects with the via in the back-side dielectric layer, and the isolation structure comprises an oxide-based material.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and particularly to the configuration of back-side contact structures and vias. Prior Technology

[0002] The electronics industry continues to demand smaller, faster electronic devices that simultaneously support a large number of complex functions. In summary, the ongoing trend in the semiconductor industry is to manufacture low-cost, high-efficiency, and low-power integrated circuits. Therefore, to achieve these goals, the main approach is to shrink the size of semiconductor integrated circuits (such as minimum structural dimensions), thereby improving production capacity and reducing related costs. However, size reduction also increases the complexity of semiconductor manufacturing processes. Therefore, for the continued advancement of semiconductor integrated circuits and devices, semiconductor manufacturing processes and technologies also need to advance in a similar way.

[0003] As integrated circuit devices become smaller, it becomes increasingly challenging to tightly package front-side metal wiring without excessively increasing undesirable parasitic resistance (R) and capacitance (C). Back-side metal wiring has been introduced to reduce the metal wiring density on the front side of integrated circuit devices. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a back-side dielectric layer; a back-side etch-stop layer located on the back-side dielectric layer; a first source / drain structure and a second source / drain structure located on the back-side etch-stop layer and separated from each other along a first direction; a front-side source / drain contact located on the first source / drain structure and the second source / drain structure; a back-side contact structure extending through the back-side dielectric layer and the back-side etch-stop layer to couple to the first source / drain structure; a via extending through the back-side dielectric layer and the back-side etch-stop layer to couple to the front-side source / drain contact; a substrate fin located between the back-side etch-stop layer and the second source / drain structure; and an isolation structure including a portion extending along the sidewall of the substrate fin. The back-side contact structure intersects with the via in the back-side dielectric layer, and the isolation structure comprises an oxide-based material.

[0005] Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a back-side dielectric layer; a back-side etch stop layer located on the back-side dielectric layer; a first gate structure located on the back-side etch stop layer; a second gate structure located on the back-side etch stop layer and aligned with the first gate structure along a first direction; a third gate structure located on the back-side etch stop layer; a fourth gate structure located on the back-side etch stop layer and aligned with the third gate structure along the first direction; and a first source / drain structure located on the back-side etch stop layer and positioned between the first and third gate structures along a second direction. Between, and the second direction is perpendicular to the first direction; the second source / drain structure is located on the back side etch stop layer and along the second direction between the second gate structure and the fourth gate structure; the front source / drain contact is located on the first source / drain structure and the second source / drain structure; the back side contact structure extends through the back side dielectric layer and the back side etch stop layer to couple to the first source / drain structure; and the via extends through the back side dielectric layer and the back side etch stop layer to couple to the front source / drain contact. The back side contact structure intersects with the via in the back side dielectric layer. The first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure. The method includes providing a precursor structure, which includes a first source / drain structure and a second source / drain structure located on a front source / drain junction; a first substrate fin located on the first source / drain structure; a second substrate fin located on the second source / drain structure; an isolation structure located between the first substrate fin and the second substrate fin, and extending along the sidewalls of the first substrate fin and the second substrate fin; and a gate isolation structure located between the first substrate fin and the second substrate fin, with a portion of the gate isolation structure extending into the isolation structure; and depositing a backside... An etch stop layer is deposited on the first substrate fin, the second substrate fin, the isolation structure, and the gate isolation structure; a back-side dielectric layer is deposited on the back-side etch stop layer; a via opening is formed to pass through the back-side dielectric layer, the back-side etch stop layer, and the gate isolation structure to expose the front source / drain contacts; a via is formed in the via opening; a back-side opening is formed to pass through the first substrate fin to expose the first source / drain structure, such that a portion of the via is exposed through the back-side opening; and a back-side contact structure is formed in the back-side opening, such that the back-side contact structure intersects with the via. Simple Explanation of the Diagram

[0007] Figure 1 is a flowchart of a method 100A for forming a back contact structure and a through hole in one or more embodiments of the present invention. Figures 2 to 8 are partial cross-sectional views of the precursor structure for performing various steps of method 100A in Figure 1 in various embodiments of the present invention. Figure 9 is a top view of the precursor structure in Figure 8 in various embodiments of the present invention. Figure 10 is a flowchart of a method 100B for forming a back contact structure and a through hole in one or more embodiments of the present invention. Figures 11 to 13 are partial cross-sectional views of the precursor structure for performing various steps of method 100B in Figure 10 in various embodiments of the present invention. Figure 14 is a top view of the precursor structure in Figure 13 in various embodiments of the present invention. Figure 15 is a partial cross-sectional view of a semiconductor structure containing through holes on both sides of the back-side contact in various embodiments of the present invention. Figure 16 is a top view of the semiconductor structure in Figure 15 in various embodiments of the present invention. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are for simplification and not for limiting the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being separated by other additional components rather than in direct contact. Furthermore, various embodiments of the invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used to simplify the description of the relative relationship between one element and another in a diagram. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the diagram. When the device is turned in different directions (rotated 90 degrees or other directions), the spatial relative adjectives used will also be interpreted according to the direction after the turn.

[0011] Furthermore, when numerical values ​​or ranges are described using terms such as "about," "approximately," or similar expressions, they are intended to cover values ​​within a reasonable range, such as those inherent to the manufacturing process that are considered by those skilled in the art. For example, based on known manufacturing tolerances related to the numerical value, the numerical value or range covers a reasonable range including the stated number, such as within + / - 20% of the stated number. For example, when the thickness of the material layer is about 5 nm and the manufacturing tolerance for deposited material layers is known to those skilled in the art to be 15%, the included size range is 4.25 nm to 5.75 nm. When describing transistors, the source / drain regions may be considered individually or together as the source or drain, depending on the context.

[0012] As integrated circuit technology advances to smaller technology nodes, multi-gate devices are being introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects. Multi-gate devices generally refer to devices with a gate structure or a portion thereof located on multiple sides of the channel region. Fin field-effect transistors (FETs) and fully wound gate transistors (WWTs) are examples of multi-gate devices, which are becoming increasingly popular and are strong candidates for high-efficiency and low-leakage-current applications. The gate of a FET can cover multiple sides of a raised channel. For example, the gate covers the top and sidewalls of a "fin" of semiconductor material extending from the substrate. The gate structure of a WWT can extend around the channel region (partially or completely) to contact both sides or more of the channel region. Because the gate structure surrounds the channel region, a WWT can also be considered a gate-around transistor or a multi-bridge channel transistor. The channel region of a WWT can be micro-nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives full-wound gate transistors other names, such as nanosheet transistors or nanowire transistors. As the semiconductor industry progresses to the next 10-nanometer technology process node in pursuit of higher device density, higher efficiency, and lower cost, challenges from manufacturing and design issues have led to stacked device structure configurations such as complementary field-effect transistors, such as vertically stacked n-type multi-gate transistors and p-type multi-gate transistors.

[0013] Smaller device sizes and stacking arrangements put significant pressure on front-side-only electrical wiring and have spurred the development of device structures with wiring structures both above and below the device structure. For example, back-side power rails or super-power rails have been proposed, where back-side source / drain contacts penetrate the substrate to contact the source / drain structure, and power rails are formed on the back side of the substrate to contact the back-side source / drain contacts. The industry continues to seek methods to reduce resistance in wiring structures, including resistance between front-side and back-side wiring structures.

[0014] This invention provides a method for forming a back-side contact structure and a through-hole adjacent to the back-side contact structure. The through-hole extends between the source / drain structures to connect to the front-side source / drain contacts. This connection provides a low-resistance conductive path between the back-side contact structure and the front-side source / drain contacts. In the method of this invention, the opening used to form the through-hole and the opening used to form the back-side contact structure are separated. The metal filler used for the through-hole and the back-side contact structure can be deposited separately or simultaneously.

[0015] Figures 1 and 10 are flowcharts of methods 100A and 100B for forming a back-side contact structure and a through-hole adjacent to the back-side contact structure. Methods 100A and 100B are for illustrative purposes only and are not intended to limit the specific content of the embodiments of the present invention to methods 100A and 100B. Additional steps may be provided before, during, and after methods 100A or 100B, and additional embodiments of the methods may substitute, omit, or interchange some of the steps. All steps are not detailed here for simplicity. Method 100A will be described below with reference to Figures 2 to 8, which are partial cross-sectional views of the precursor structure 200 at different manufacturing stages in various embodiments of method 100A. Method 100B will be described below with reference to Figures 2 to 4 and Figures 11 to 13, which are partial cross-sectional views of the precursor structure 200 at different manufacturing stages in various embodiments of method 100B. Since the precursor structure 200 will be fabricated as a semiconductor structure, the precursor structure 200 may be considered as a semiconductor structure here as needed. For the avoidance of doubt, the X, Y, and Z directions in the drawings of this embodiment are perpendicular to each other. In the following description, unless otherwise stated, similar reference numerals are used to denote similar structures.

[0016] As shown in Figures 1, 2, and 3, step 102 of method 100A forms a precursor structure 200. As shown in Figures 2 and 3, the precursor structure 200 includes a front section structure, a middle section structure, and a rear section structure on the front side of the substrate 201 (shown as dashed lines). In one embodiment, the substrate 201 may include silicon. The substrate 201 may alternatively or additionally include another semiconductor element (such as germanium), a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or a combination thereof. The substrate 201 may be replaced with a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate.

[0017] Step 102 forms an epitaxial stack containing interleaved semiconductor layers on substrate 201. In some examples, the epitaxial stack may include multiple interleaved first semiconductor layers and multiple second semiconductor layers. The first semiconductor layers may include silicon, and the second semiconductor layers may include silicon germanium. As shown in FIG3, the precursor structure 200 includes a channel assembly 2080 released from the first semiconductor layer when the second semiconductor layer in the channel region is selectively removed. Gate structures are formed as shown in FIG3, a first gate structure 268 and a second gate structure 270 to cover each channel assembly 2080. The gate structure includes a gate dielectric layer 282 and a gate 284 located on the gate dielectric layer 282. The gate dielectric layer 282 includes a high dielectric constant dielectric material such as hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, zirconium oxide, lanthanum oxide, yttrium oxide, or hafnium lanthanum oxide. In one embodiment, the gate dielectric layer 282 includes hafnium oxide. Gate 284 may include a multilayer structure such as a metal layer (work function metal layer) having a selected work function to improve device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, gate 284 may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, other metallic materials, or combinations thereof.

[0018] In the embodiment described, the transistor is a fully wound gate transistor, which can be patterned with an epitaxial stack and a portion of the substrate 201 to form fin-shaped active regions. Each fin-shaped active region may include a base fin 202B formed from the substrate 201 and a top formed from the epitaxial stack. An isolation structure 204 is deposited on the substrate 201, and a portion of the isolation structure 204 extends along the sidewalls of the base fin 202B. The isolation structure 204 may comprise an oxide-based material, such as silicon oxide, silicon oxynitride, fluorosilicate glass, or a low-dielectric-constant dielectric material. The dielectric constant of the isolation structure 204 is significantly lower than that of the gate dielectric layer 282. In some examples, the dielectric constant of the gate dielectric layer 282 is at least three times that of the isolation structure 204. Gate spacers 210 are located along the sidewalls of a dummy gate stack, which is subsequently replaced by a gate structure. As shown in Figure 2A (a cross-sectional view through the first source / drain structure 226 and the second source / drain structure 227), a portion of the gate spacer 210 is located on the isolation structure 204. As shown in Figure 2, a buffer epitaxial layer 222 is located on the upper surface of the substrate fin 202B, and a bottom nitride layer 224 is located on the buffer epitaxial layer 222. In some embodiments, the buffer epitaxial layer 222 comprises undoped silicon, undoped germanium, or undoped silicon-germanium, and can be used to prevent leakage current into the substrate 201. The bottom nitride layer 224 comprises silicon nitride and is used to control the growth and stress of the first source / drain structure 226 and the second source / drain structure 227. A portion of the gate spacer 210 runs along the sidewalls of the buffer epitaxial layer 222 and the bottom nitride layer 224. In some embodiments, the gate spacer 210 may include a nitride-based material, such as silicon nitride, silicon carbonitride, or silicon carbonitride.

[0019] A first source / drain structure 226 and a second source / drain structure 227 can be epitaxially grown from the exposed end sidewalls of the channel assembly 2080 (as shown in FIG. 3). In some embodiments, the first source / drain structure 226 and the second source / drain structure 227 may include silicon germanium doped with a p-type dopant such as boron. In some other embodiments, the first source / drain structure 226 and the second source / drain structure 227 may include silicon doped with an n-type dopant such as phosphorus or arsenic. After forming the first source / drain structure 226 and the second source / drain structure 227, a contact etch stop layer 206 is deposited on the isolation structure 204, the gate spacer 210, the first source / drain structure 226, and the second source / drain structure 227. Then, a first interlayer dielectric layer 208 is formed on the contact etch stop layer 206. After the planarization step, a first etch stop layer 212 is formed on the planar upper surface of the first interlayer dielectric layer 208, and a second interlayer dielectric layer 214 is formed on the first etch stop layer 212. Since the first interlayer dielectric layer 208 needs to accommodate the height of the source / drain structure, the thickness of the first interlayer dielectric layer 208 along the Z direction is greater than the thickness of the second interlayer dielectric layer 214. The first interlayer dielectric layer 208 and the second interlayer dielectric layer 214 may comprise oxide-based materials, such as oxides of tetraethoxysilane, undoped silicate glass, or doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, or borosilicate glass). The contact etch stop layer 206 and the first etch stop layer 212 may comprise nitride-based materials, such as silicon nitride or aluminum nitride.

[0020] The precursor structure 200 includes a front contact 230 extending through the second interlayer dielectric layer 214, the first etch stop layer 212, and the first interlayer dielectric layer 208, to be electrically coupled to the first source / drain structure 226 and the second source / drain structure 227 via a silicon structure 228. The front contact 230 includes a lower portion located between the first source / drain structure 226 and the second source / drain structure 227, and an upper portion extending beyond the first source / drain structure 226 and the second source / drain structure 227. The front contact 230 may include cobalt, nickel, ruthenium, tungsten, or a combination thereof. The front contact 230 is separated from the first interlayer dielectric layer 208, the first etch stop layer 212, and the second interlayer dielectric layer 214 by a barrier layer. The barrier layer may include titanium nitride or tantalum nitride. The silicate structure 228 may include titanium silicate or cobalt silicate.

[0021] A gate isolation structure 220 is formed to separate the first gate structure 268 and the second gate structure 270, as shown in FIG3. As shown in FIG2 and 3, the gate isolation structure 220 also extends along the X direction between the substrate fins 202B, and the first gate structure 268 and the second gate structure 270 are insulated by the gate isolation structure 220. A portion of the gate isolation structure 220 extends into the isolation structure 204. Although not shown, the gate isolation structure 220 may include a gasket to interface with the gate structure, and a low-dielectric-constant filler layer is spaced from the gate structure by the gasket. In some embodiments, the gasket may include an oxygen-free dielectric material such as silicon nitride, and the low-dielectric-constant filler layer may include an oxide-based material.

[0022] As shown in Figure 2, the precursor structure 200 represents a structure on the front side 200F of the precursor structure 200. For example, the precursor structure 200 includes a first intermetallic dielectric layer 232, a second intermetallic dielectric layer 234, a third intermetallic dielectric layer 238, a second etch stop layer 242, and a fourth intermetallic dielectric layer 244 located on the second intermetallic dielectric layer 214. In some embodiments, the second etch stop layer 242 and the first etch stop layer 212 may have similar compositions. The first intermetallic dielectric layer 232, the second intermetallic dielectric layer 234, the third intermetallic dielectric layer 238, and the fourth intermetallic dielectric layer 244 may include oxide-based materials, such as oxides of tetraethoxysilane, undoped silicate glass, or doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, or borosilicate glass). The first front-side metal line 236 is located in the first intermetallic dielectric layer 232. The first front-side contact via 240 is located in the third intermetallic dielectric layer 238. The contact structure 246 is located in the second etch stop layer 242 and the fourth intermetallic dielectric layer 244. The first front-side metal line 236, the first front-side contact via 240, and the contact structure 246 may include titanium nitride, tantalum nitride, copper, or a combination thereof. Metal nitrides are the composition of the barrier layers used in these conductive structures.

[0023] After forming the front interconnect structure, the precursor structure 200 can be flipped and the substrate 201 thinned. A combination of grinding and planarization processes is then performed to thin the substrate 201, exposing the isolation structure 204 and the substrate fins 202B. In some embodiments, the thinning step also exposes the gate isolation structure 220 and the first interlayer dielectric layer 208.

[0024] As shown in Figures 1 and 4, step 104 of method 100A deposits a back-side etch stop layer 247 and a back-side dielectric layer 248 on the back-side surface of the precursor structure 200. In some embodiments, the back-side etch stop layer 247 may include silicon nitride, silicon carbonitride, aluminum nitride, or aluminum oxide, and its deposition method may be chemical vapor deposition. In one embodiment, the back-side etch stop layer 247 includes silicon nitride. The deposition method of the back-side dielectric layer 248 may be chemical vapor deposition, flowable chemical vapor deposition, or spin coating, and may include oxide-based dielectric materials such as oxides of tetraethoxysilane, undoped silicate glass, or doped silicon oxide (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, or borosilicate glass). In other embodiments, the back-side dielectric layer 248 includes silicon oxide.

[0025] As shown in Figures 1 and 5, step 106 of method 100A forms a via opening 250 to pass through the back-side etch stop layer 247 and the back-side dielectric layer 248. As shown in Figure 5, the via opening 250 can pass through the back-side dielectric layer 248, the back-side etch stop layer 247, the gate isolation structure 220, and the first interlayer dielectric layer 208 to expose the lower portion of the front contact 230. As described above, the low-dielectric-constant filling layer in the back-side dielectric layer 248 and the gate isolation structure 220 is composed of an oxide-based dielectric material, while the back-side etch stop layer 247 and the pad of the gate isolation structure 220 are composed of a nitride-based material. Since the back-side etch stop layer 247 and the pad are thinner than the back-side dielectric layer 248 and the low-dielectric-constant filling layer, the method for forming the via opening 250 mainly etches the oxide-based material. Photolithography and etching processes can be used to form the via opening 250. In this example of the process, a patterned mask (not shown in FIG. 5) is formed on the back-side dielectric layer 248. The patterned mask is then used as an etching mask for a first etching process 300 to etch the precursor structure 200. The first etching process 300 is configured to etch silicon oxide at a rate greater than that etching silicon or silicon nitride. In some embodiments, the first etching process 300 may include a dry etching process using a fluorine-containing gas (such as carbon tetrafluoride, octafluorocyclobutane, nitrogen trifluoride, chlorine trifluoride, or sulfur hexafluoride), a chlorine-containing gas (such as chlorine), oxygen, or hydrogen. Because the via opening 250 is relatively large and does not require alignment with the source / drain structure, the photolithography process required to form the via opening 250 may include immersion lithography using a deep ultraviolet light source with a wavelength between approximately 100 nm and approximately 300 nm, such as 193 nm. This means that the photolithography process used to form the via opening 250 does not employ extreme ultraviolet lithography.

[0026] As shown in Figures 1 and 6, step 108 of method 100A forms a through-hole 252 in the through-hole opening 250. In some embodiments, the through-hole 252 may include cobalt, nickel, ruthenium, tungsten, copper, or a combination thereof. In some embodiments, the through-hole 252 may be formed by depositing the aforementioned metal to fill the through-hole opening 250, and the deposition method may be physical vapor deposition, metal-organic chemical vapor deposition, electroplating, or electroless plating. After depositing the metal filler, a planarization process such as chemical mechanical polishing may be performed to remove excess metal on the back-side dielectric layer 248 to form the through-hole 252.

[0027] As shown in Figures 1 and 7, step 110 of method 100A forms a back-side contact opening 254 adjacent to the through-hole 252. As shown in Figure 7, the back-side contact opening 254 exposes the first source / drain structure 226 and is used to pass through the back-side dielectric layer 248, the back-side etch stop layer 247, the substrate fin 202B, the buffer epitaxial layer 222, and the bottom nitride layer 224 to expose the lower surface of the first source / drain structure 226. As described above, the substrate fin 202B and the buffer epitaxial layer 222 are composed of semiconductor materials such as silicon or germanium. Thus, the method for forming the back-side contact opening 254 mainly involves etching the semiconductor material. Photolithography and etching processes can be used to form the back-side contact opening 254. In this example of the process, a patterned mask (not shown in FIG. 7) is formed on the back-side dielectric layer 248. The patterned mask is then used as an etching mask for a second etching process 400 to etch the precursor structure 200. The second etching process 400 is configured to etch silicon at a rate greater than that etching silicon oxide or silicon nitride. Notably, the openings in the patterned mask partially overlap with the via 252 to ensure that the formed back-side contact 260 is adjacent to and physically intersected with the via 252. In some embodiments, the second etching process 400 may include a dry etching process using a fluorine-containing gas (such as carbon tetrafluoride, octafluorocyclobutane, nitrogen trifluoride, chlorine trifluoride, or sulfur hexafluoride), oxygen, or hydrogen. Because the back contact opening 254 is small and needs to be satisfactorily aligned with the first source / drain structure 226, extreme ultraviolet (EUV) photolithography is used to form the back contact opening 254. The wavelength of the UV source used in this process can be between about 10 nm and about 100 nm, for example, about 13.5 nm. Since the lower portion of the front contact 230 extends below the lower surface of the first source / drain structure 226, the back contact opening 254 extends below the lower surface of the through-hole 252.

[0028] As shown in Figures 1 and 8, step 112 of method 100A forms a back-side contact 260 in the back-side contact opening 254, such that the back-side contact 260 is adjacent to the through-hole 252. In some embodiments, the back-side contact 260 may include cobalt, nickel, ruthenium, tungsten, copper, or a combination thereof. In some embodiments, the back-side contact 260 may be formed by depositing the aforementioned metal to fill the back-side contact opening 254, and the deposition method may be physical vapor deposition, metal-organic chemical vapor deposition, electroplating, or electroless plating. After depositing the metal filler, a planarization process such as chemical mechanical polishing may be performed to remove excess metal on the back-side dielectric layer 248 to form the back-side contact 260. As shown in Figure 8, due to the planarization process, the back-side dielectric layer 248, the back-side contact 260, and the upper surface of the through-hole 252 are coplanar (note that the precursor structure 200 is flipped upside down).

[0029] Figure 9 is a top view of the back side 200B of the precursor structure 200 in Figure 8 (see Figure 8). As shown in Figure 9, Figure 8 is a partial cross-sectional view along section AA in Figure 9. As shown in Figure 9, the base fins 202B extend longitudinally along the Y direction and are parallel to each other. The first gate structure 268 and the second gate structure 270 extend longitudinally along the X direction. The third gate structure 272 and the fourth gate structure 274 also extend longitudinally along the X direction. The gate isolation structure 220 extends longitudinally along the Y direction between the first gate structure 268 and the second gate structure 270, and between the third gate structure 272 and the fourth gate structure 274. The gate isolation structure 220 isolates the first gate structure 268 and the second gate structure 270, so as to longitudinally align and isolate the first gate structure 268 and the second gate structure 270 along the X direction. Similarly, gate isolation structure 220 isolates third gate structure 272 and fourth gate structure 274 in a longitudinally aligned manner along the X direction. First gate structure 268, second gate structure 270, third gate structure 272, and fourth gate structure 274 each cover each channel assembly 2080 located on the base fin 202B (as shown in FIG3). Gate spacer 210 runs along the sidewalls of first gate structure 268, second gate structure 270, third gate structure 272, and fourth gate structure 274. As shown in FIG9, gate isolation structure 220 intersects with the sidewall of gate spacer 210 running along the sidewalls of first gate structure 268, second gate structure 270, third gate structure 272, and fourth gate structure 274. In some embodiments, the first etching process 300 used to form the through-hole opening 250 etches the gate spacer 210 at a slower rate, so that the gate spacer 210 defines the boundary of the through-hole 252 along the Y direction. In some embodiments shown in FIG9, the through-hole 252 is adjacent to and intersects with the gate spacer 210. As shown in FIG9, the first source / drain structure 226 and the second source / drain structure 227 are each located on the substrate fin 202B. Since the back side 200B faces upward, the front contact 230 is located below the first source / drain structure 226 and the second source / drain structure 227, and is electrically coupled to the first source / drain structure 226 and the second source / drain structure 227 (not shown in FIG9) via the silicon structure 228.

[0030] In the embodiment described, the through-hole 252 includes a first width W1 along the X direction and a first length L1 along the Y direction. The first width W1 is different from the first length L1. In some embodiments, the first length L1 is greater than the first width W1. In one embodiment, the ratio of the first length L1 to the first width W1 is between about 1.5 and about 2.5. In some examples, the first length L1 is between about 24 nm and about 72 nm, while the first width W1 is between about 12 nm and about 36 nm. The back-side contact 260 includes a second width W2 along the X direction and a second length L2 along the Y direction. The second width W2 is different from the second length L2. In some embodiments, the second width W2 is greater than the second length L2 because the width of the back-side contact 260 is intentionally increased to overlap and intersect with the through-hole 252. In one embodiment, the ratio of the second width W2 to the second length L2 is between about 1.1 and about 1.5. Due to differences in the formation method, the pin size of the through-hole 252 is larger than the pin size of the back-side contact 260. This means that the first length L1 is greater than the second length L2, and the first width W1 is greater than the second width W2.

[0031] In method 100A described above, the openings used to form the back contact 260 and the through hole 252 are formed separately, and the back contact 260 and the through hole 252 are formed separately in individual openings. In method 100B, the openings used to form the back contact 260 and the through hole 252 are formed separately, but the back contact 260 and the through hole 252 are formed simultaneously.

[0032] As shown in Figures 10, 2, and 3, step 102 of method 100B forms the precursor structure 200. Step 102 has been described in detail above in conjunction with method 100A. Detailed explanations of step 102 are omitted here for simplicity.

[0033] As shown in Figures 10 and 4, step 104 of method 100B deposits a back-side etch stop layer 247 and a back-side dielectric layer 248 on the back-side surface of the precursor structure 200. Step 104 has been described in detail above in conjunction with method 100A. Detailed descriptions of step 104 are omitted here for simplicity.

[0034] As shown in Figures 10 and 11, step 106 of method 100B forms a via opening 250 to pass through the back-side etch stop layer 247 and the back-side dielectric layer 248. As shown in Figure 11, the via opening 250 must pass through the back-side dielectric layer 248, the back-side etch stop layer 247, the gate isolation structure 220, and the first interlayer dielectric layer 208 to expose the lower portion of the front contact 230. As described above, the low-dielectric-constant filling layer in the back-side dielectric layer 248 and the gate isolation structure 220 is composed of an oxide-based dielectric material, while the back-side etch stop layer 247 and the pad of the gate isolation structure 220 are composed of a nitride-based material. Since the back-side etch stop layer 247 and the pad are thinner than the back-side dielectric layer 248 and the low-dielectric-constant filling layer, the method for forming the via opening 250 mainly etches the oxide-based material. Photolithography and etching processes can be used to form the via opening 250. In one example of the process, a patterned mask (not shown in FIG11) is formed on the back-side dielectric layer 248, and then the patterned mask is used as an etching mask for a first etching process 300 to etch the precursor structure 200. In some embodiments, the first etching process 300 may include a dry etching process, which may use a fluorine-containing gas (such as carbon tetrafluoride, octafluorocyclobutane, nitrogen trifluoride, chlorine trifluoride, or sulfur hexafluoride), a chlorine-containing gas (such as chlorine), oxygen, or hydrogen. Since the via opening 250 has a large size and does not need to be aligned with the source / drain structure, the photolithography process required to form the via opening 250 may include immersion lithography, in which the wavelength of the deep ultraviolet radiation source is between about 100 nm and about 300 nm, such as 193 nm. That is, the photolithography process used to form the via opening 250 may not use extreme ultraviolet photolithography.

[0035] As shown in Figures 10 and 12, step 109 of method 100B forms a back-side contact opening 254 to merge with the through-hole opening 250. The back-side contact opening 254 exposes the first source / drain structure 226, which can pass through the back-side dielectric layer 248, the back-side etch stop layer 247, the substrate fin 202B, the buffer epitaxial layer 222, and the bottom nitride layer 224 to expose the lower surface of the first source / drain structure 226. The substrate fin 202B and the buffer epitaxial layer 222 are composed of semiconductor materials such as silicon or germanium. Thus, the method for forming the back-side contact opening 254 primarily involves etching the semiconductor material. Photolithography and etching processes can be used to form the back-side contact opening 254. Since the through-hole opening 250 is not filled with any metal filler when forming the back-side contact opening 254, a bottom anti-reflective layer can be deposited to temporarily fill the through-hole opening 250. Next, a patterned mask (not shown in FIG. 12) is formed on the back-side dielectric layer 248. The patterned mask is then used as an etching mask for a second etching process 400 to etch the precursor structure 200. Notably, the openings in the patterned mask may partially overlap with the via openings 250 to ensure that fluid in the back-side contact openings 254 and via openings 250 can communicate with each other. In some embodiments, the dielectric separation structure between the via openings 250 and the back-side contact openings 254 is below the upper surface of the back-side dielectric layer 248. For ease of reference, the combined back-side contact opening 254 and via opening 250 shown in FIG. 12 can be considered as a combined opening 258. In some embodiments, the second etching process 400 may include a dry etching process using a fluorine-containing gas (such as carbon tetrafluoride, octafluorocyclobutane, nitrogen trifluoride, chlorine trifluoride, or sulfur hexafluoride), oxygen, or hydrogen. Because the back contact opening 254 is small and needs to be satisfactorily aligned with the first source / drain structure 226, a photolithography process such as extreme ultraviolet (EUV) photolithography is required to form the back contact opening. The wavelength of the X-ray source is between approximately 10 nm and approximately 100 nm, for example, approximately 13.5 nm. Since the lower portion of the front contact 230 extends below the lower surface of the first source / drain structure 226, the back contact opening 254 extends below the lower surface of the through-hole 252.

[0036] As shown in Figures 10 and 13, step 111 of method 100B forms a combined conductive structure 266 in the combined opening 258. In some embodiments, the combined conductive structure 266 may include cobalt, nickel, ruthenium, tungsten, copper, or a combination thereof. In some embodiments, the back-side contact 260 may be formed by depositing the aforementioned metal in the combined opening 258, and the deposition method may be physical vapor deposition, metal-organic chemical vapor deposition, electroplating, or electroless plating. After depositing the metal filler, a planarization process such as chemical mechanical polishing may be performed to remove excess metal on the back-side dielectric layer 248 to form the combined conductive structure 266. As shown in Figure 13, due to the planarization process, the back-side dielectric layer 248 and the upper surface of the combined conductive structure 266 (note that the precursor structure 200 is flipped upside down) are coplanar. Since the merged opening 258 includes a back contact opening 254 and a through-hole opening 250, the merged conductive structure 266 includes a through-hole pin 256 located in the through-hole opening 250 and a back contact pin 264 located in the back contact opening 254. The through-hole pin 256 and the back contact pin 264 are partially merged in the back dielectric layer 248 and branch as they extend toward the first source / drain structure 226 and the front contact 230.

[0037] Figure 14 is a top view of the dorsal side 200B of the precursor structure 200 in Figure 13 (see Figure 13). As shown in Figure 14, the base fins 202B extend longitudinally along the Y direction and are parallel to each other. The first gate structure 268 and the second gate structure 270 extend longitudinally along the X direction. The third gate structure 272 and the fourth gate structure 274 also extend longitudinally along the X direction. The gate isolation structure 220 extends longitudinally along the Y direction between the first gate structure 268 and the second gate structure 270, and between the third gate structure 272 and the fourth gate structure 274. The gate isolation structure 220 isolates the first gate structure 268 and the second gate structure 270 in a longitudinally aligned manner along the X direction. Similarly, the gate isolation structure 220 isolates the third gate structure 272 and the fourth gate structure 274 in a longitudinally aligned manner along the X direction. The first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274 each cover each channel assembly 2080 located on the substrate fin 202B (as shown in FIG3). Gate spacers 210 run along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. As shown in FIG14, the gate isolation structure 220 intersects with the sidewalls of the gate spacers 210 along the sidewalls of the first gate structure 268, the second gate structure 270, the third gate structure 272, and the fourth gate structure 274. In some embodiments, the first etching process 300 for forming the through-hole opening 250 etches the gate spacers 210 at a slower rate, such that the gate spacers 210 define the boundary of the through-hole foot 256 along the Y direction. In some embodiments shown in FIG14, the through-hole pin 256 of the combined conductive structure 266 is adjacent to and intersects with the gate spacer 210. As shown in FIG14, the first source / drain structure 226 and the second source / drain structure 227 are each located on the substrate fin 202B. Since the back side 200B (as shown in FIG13) faces upward, the front contact 230 is located below the first source / drain structure 226 and the second source / drain structure 227, and is coupled to the first source / drain structure 226 and the second source / drain structure 227 (not shown in FIG13) via the silicon structure 228.

[0038] In the embodiment described, the through-hole pin 256 and the back contact pin 264 of the combined conductive structure 266 are T-shaped in the top view. The through-hole pin 256 includes a first width W1 along the X direction and a first length L1 along the Y direction. The first width W1 is different from the first length L1. In some embodiments, the first length L1 is greater than the first width W1. In one embodiment, the ratio of the first length L1 to the first width W1 is between about 1.5 and about 2.5. In some examples, the first length L1 is between about 24 nm and about 72 nm, while the first width W1 is between about 12 nm and about 36 nm. The back contact pin 264 includes a third width W3 along the X direction and a second length L2 along the Y direction. The second length L2 may be similar to the third width W3. In one embodiment, the ratio of the second width W2 to the second length is between about 0.9 and about 1.1. Due to differences in the formation method, the pin size of the through-hole pin 256 is larger than that of the back contact pin 264. This means that the first length L1 is greater than the second length L2, and the first width W1 is greater than the third width W3. The through-hole pin 256 and the back contact pin 264 are continuous and have no interface, as they are formed simultaneously. However, the back contact 260 is different from the through-hole 252. Because the back contact 260 and the through-hole 252 are formed separately, there is a visible interface between them.

[0039] In the precursor structure 200 shown in Figure 2, the front contact 230 does not extend onto the third source / drain structure 229. In some other embodiments shown in Figure 15, the long front contact 2300 extends continuously onto the first source / drain structure 226, the second source / drain structure 227, and the third source / drain structure 229, and intersects with the first source / drain structure 226, the second source / drain structure 227, and the third source / drain structure 229 via the silicon structure 228. This configuration may form another through-hole 2520 to intersect with the long front contact 2300. In some embodiments, the through-holes 252 and 2520 are composed and formed in a similar manner. In other embodiments, the through-holes 252 and 2520 partially overlap with the back contact 260, and the back contact 260 is sandwiched between the through-holes 252 and 2520. Adding via 2520 can further reduce the contact resistance. Figure 16 is a top view of the semiconductor structure in Figure 15, such as the precursor structure 200. As shown in Figure 16, Figure 15 is a partial cross-sectional view along section AA in Figure 16. Through-holes 252 and 2520 can be symmetrical with respect to the back contact 260. Through-holes 252 and 2520 can intersect with the gate spacer 210 along the length direction (i.e., the Y direction).

[0040] An embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a back-side dielectric layer; a back-side etch-stop layer located on the back-side dielectric layer; a first source / drain structure and a second source / drain structure located on the back-side etch-stop layer and separated from each other along a first direction; a front-side source / drain contact located on the first source / drain structure and the second source / drain structure; a back-side contact structure extending through the back-side dielectric layer and the back-side etch-stop layer to couple to the first source / drain structure; a via extending through the back-side dielectric layer and the back-side etch-stop layer to couple to the front-side source / drain contact; a substrate fin located between the back-side etch-stop layer and the second source / drain structure; and an isolation structure including a portion extending along the sidewall of the substrate fin. The back-side contact structure intersects with the via in the back-side dielectric layer, and the isolation structure comprises an oxide-based material.

[0041] In some embodiments, the front source / drain contact includes a portion extending along a first direction between the first source / drain structure and the second source / drain structure. In some embodiments, the first source / drain structure is located along a second direction between the first gate structure and the second gate structure, and the second direction is perpendicular to the first direction; the second source / drain structure is located along the second direction between the third gate structure and the fourth gate structure. In some embodiments, the back contact structure includes a first width along the second direction, and the via includes a second width along the second direction, and the second width is greater than the first width. In some examples, the via is adjacent to the first gate structure and the second gate structure. In some embodiments, the semiconductor structure further includes a plurality of nanostructures at the sidewall junctions of the first source / drain structure. The first gate structure covers each nanostructure. In some embodiments, the semiconductor structure further includes a buffer semiconductor layer on a substrate fin; and a bottom isolation layer on the buffer semiconductor layer. In some embodiments, the buffer semiconductor layer includes undoped silicon, undoped germanium, or undoped silicon-germanium, and the bottom isolation layer includes silicon nitride.

[0042] Another embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a back-side dielectric layer; a back-side etch stop layer located on the back-side dielectric layer; a first gate structure located on the back-side etch stop layer; a second gate structure located on the back-side etch stop layer and aligned with the first gate structure along a first direction; a third gate structure located on the back-side etch stop layer; a fourth gate structure located on the back-side etch stop layer and aligned with the third gate structure along the first direction; and a first source / drain structure located on the back-side etch stop layer and positioned between the first and third gate structures along a second direction. Between, and the second direction is perpendicular to the first direction; the second source / drain structure is located on the back side etch stop layer and along the second direction between the second gate structure and the fourth gate structure; the front source / drain contact is located on the first source / drain structure and the second source / drain structure; the back side contact structure extends through the back side dielectric layer and the back side etch stop layer to couple to the first source / drain structure; and the via extends through the back side dielectric layer and the back side etch stop layer to couple to the front source / drain contact. The back side contact structure intersects with the via in the back side dielectric layer. The first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

[0043] In some embodiments, the back-side contact structure includes a first width along a second direction. The via includes a second width along the second direction, and the second width is greater than the first width. In some embodiments, the via is adjacent to the first gate structure and the third gate structure. In some embodiments, the semiconductor structure further includes a plurality of nanostructures at the sidewall junctions of the first source / drain structure. The first gate structure covers each nanostructure. In some embodiments, the semiconductor structure further includes a substrate fin located between the back-side etch stop layer and the second source / drain structure; and an isolation structure including a portion extending along the sidewall of the substrate fin. In some embodiments, portions of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are located on and at the junction of the isolation structure. In some embodiments, the front-side contact structure includes a portion extending along a first direction between the first source / drain structure and the second source / drain structure. In some embodiments, the back-side contact structure and the via are continuous structures.

[0044] An embodiment of the present invention provides a method for forming a semiconductor structure. The method includes providing a precursor structure, which includes a first source / drain structure and a second source / drain structure located on a front source / drain junction; a first substrate fin located on the first source / drain structure; a second substrate fin located on the second source / drain structure; an isolation structure located between the first substrate fin and the second substrate fin, and extending along the sidewalls of the first substrate fin and the second substrate fin; and a gate isolation structure located between the first substrate fin and the second substrate fin, with a portion of the gate isolation structure extending into the isolation structure; and depositing a backside... An etch stop layer is deposited on the first substrate fin, the second substrate fin, the isolation structure, and the gate isolation structure; a back-side dielectric layer is deposited on the back-side etch stop layer; a via opening is formed to pass through the back-side dielectric layer, the back-side etch stop layer, and the gate isolation structure to expose the front source / drain contacts; a via is formed in the via opening; a back-side opening is formed to pass through the first substrate fin to expose the first source / drain structure, such that a portion of the via is exposed through the back-side opening; and a back-side contact structure is formed in the back-side opening, such that the back-side contact structure intersects with the via.

[0045] In some embodiments, the lower surface of the back-side contact structure is lower than the lower surface of the through-hole. In some embodiments, the step of forming the through-hole includes employing a first etching process, and the step of forming the back-side opening includes employing a second etching process, wherein the second etching process is different from the first etching process. In some embodiments, the first etching process etches silicon oxide at a rate greater than the etching rate of silicon and silicon nitride, and the second etching process etches silicon at a rate greater than the etching rate of silicon oxide and silicon nitride.

[0046] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0047] AA: Section line L1: First Length L2: Second Length W1: First width W2: Second width W3: Third width 100A, 100B: Methods 102, 104, 106, 108, 109, 110, 111, 112: Steps 200: Front-wheel drive structure 200B: Backside 200F: Front 201:Substrate 202B: Basal fins 204: Isolation Structure 206: Contact Etching Stop Layer 208: First interlayer dielectric layer 210: Gate spacer 212: First etch stop layer 214: Second interlayer dielectric layer 220: Gate isolation structure 222: Buffer epitaxial layer 224: Bottom nitride layer 226: First source / drain structure 227: Second source / drain structure 228: Silicon structure 229: Third source / drain structure 230: Front contact 232: First intermetallic dielectric layer 234: Second intermetallic dielectric layer 236: First front metal circuit 238: Third intermetallic dielectric layer 240: First front contact through hole 242: Second etch stop layer 244: Fourth intermetallic dielectric layer 246: Contact Structure 247: Backside Etching Stop Layer 248: Backside dielectric layer 250: Through hole opening 252, 2520: Through holes 254: Backside contact opening 256: Through-hole foot 258: Merged opening 260: Backside contact 264: Backside contact point foot 266: Merged conductive structure 268: First gate structure 270: Second gate structure 272: Third gate structure 274: Fourth gate structure 282: Gate dielectric layer 284: Gate 300: First Etching Process 400: Second Etching Process 2080: Channel Component 2300: Long front contact

Claims

1. A semiconductor structure, comprising: One back-side dielectric layer; A back-side etch stop layer is located on the back-side dielectric layer; a first source / drain structure and a second source / drain structure are located on the back-side etch stop layer and separated from each other along a first direction; a front-side source / drain contact is located on the first source / drain structure and the second source / drain structure; a back-side contact structure extends through the back-side dielectric layer and the back-side etch stop layer to couple to the first source / drain structure; a via extends through the back-side dielectric layer and the back-side etch stop layer to couple to the front-side source / drain contact; a base fin is located between the back-side etch stop layer and the second source / drain structure; and an isolation structure includes a portion extending along the sidewall of the base fin, wherein the back-side contact structure intersects with the via in the back-side dielectric layer, wherein the isolation structure comprises an oxide-based material.

2. The semiconductor structure as claimed in claim 1, wherein the front-side source / drain contact includes a portion extending along the first direction between the first source / drain structure and the second source / drain structure.

3. The semiconductor structure as claimed in claim 1 or 2, wherein the first source / drain structure is located between a first gate structure and a second gate structure along a second direction, and the second direction is perpendicular to the first direction, wherein the second source / drain structure is located between a third gate structure and a fourth gate structure along the second direction.

4. The semiconductor structure as claimed in claim 3, wherein the back-side contact structure includes a first width along the second direction, wherein the via includes a second width along the second direction, wherein the second width is greater than the first width.

5. A semiconductor structure, comprising: One back-side dielectric layer; A back-side etch stop layer is located on the back-side dielectric layer; A first gate structure is located on the back-side etch stop layer; A second gate structure is located on the back-side etch stop layer and aligned with the first gate structure along a first direction; a third gate structure is located on the back-side etch stop layer; a fourth gate structure is located on the back-side etch stop layer and aligned with the third gate structure along the first direction; a first source / drain structure is located on the back-side etch stop layer and positioned between the first gate structure and the third gate structure along a second direction, wherein the second direction is perpendicular to the first direction; a second source / drain structure is located on the back-side etch stop layer and positioned between the second gate structure and the fourth gate structure along the second direction; a front-side source / drain contact is located on the first source / drain structure and the second source / drain structure; A back-side contact structure extends through the back-side dielectric layer and the back-side etch stop layer to couple to the first source / drain structure; and a via extends through the back-side dielectric layer and the back-side etch stop layer to couple to the front-side source / drain contact, wherein the back-side contact structure intersects with the via in the back-side dielectric layer, wherein the first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of an isolation structure.

6. The semiconductor structure as claimed in claim 5, wherein the back-side contact structure includes a first width along the second direction, wherein the via includes a second width along the second direction, wherein the second width is greater than the first width.

7. The semiconductor structure as described in claim 5 or 6, wherein the via is adjacent to the first gate structure and the third gate structure.

8. A method for forming a semiconductor structure, comprising: A precursor structure is provided, comprising: a first source / drain structure and a second source / drain structure located on a front source / drain junction; a first base fin located on the first source / drain structure; a second base fin located on the second source / drain structure; an isolation structure located between the first base fin and the second base fin, extending along the sidewalls of the first base fin and the second base fin; and a gate isolation structure located between the first base fin and the second base fin, with a portion of the gate isolation structure extending into the isolation structure; a back-side etch stop layer is deposited on the first base fin, the second base fin, the isolation structure, and the gate isolation structure; and a back-side dielectric layer is deposited on the back-side etch stop layer. A through-hole opening is formed to pass through the back-side dielectric layer, the back-side etch stop layer, and the gate isolation structure to expose the front-side source / drain contact; a through-hole is formed in the through-hole opening; a back-side opening is formed to pass through the first substrate fin to expose the first source / drain structure, such that a portion of the through-hole is exposed in the back-side opening; and a back-side contact structure is formed in the back-side opening, such that the back-side contact structure intersects with the through-hole.

9. A method for forming a semiconductor structure as described in claim 8, wherein the lower surface of the back-side contact structure is lower than the lower surface of the through-hole.

10. A method for forming a semiconductor structure as claimed in claim 8 or 9, wherein the step of forming the through-hole includes employing a first etching process, wherein the step of forming the back-side opening includes employing a second etching process, and the second etching process is different from the first etching process.

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