Substrate structure

Abstract

A substrate structure includes a substrate and at least one add-on structure layer. The substrate includes a dielectric core and at least one first conductive via penetrating the dielectric core. The at least one add-on structure layer is disposed on the substrate and includes a dielectric layer and at least one second conductive via penetrating the dielectric layer. The coefficient of thermal expansion of the dielectric layer is less than that of the dielectric core. The at least one second conductive via is electrically connected to the at least one first conductive via.

Description

Technical Field

[0001] This invention relates to a substrate structure, and more particularly to a substrate structure with better structural reliability. Prior Technology

[0002] High-end integrated circuit (IC) substrates and circuit boards are becoming larger and thicker, resulting in lower manufacturing yields and more severe board bending. To address the bending issue, the inner core board needs to be thickened to increase support strength. However, this approach increases the diameter and spacing of conductive vias, leading to low via density, which is detrimental to high-end product applications. Furthermore, if a glass substrate is used as the core layer, the core board thickness is typically greater than 0.5 mm, while the diameter of the conductive vias is less than 0.1 mm, resulting in lower electroplating fill yield. In addition, the added-layer structure on the core layer, due to its higher coefficient of thermal expansion than the core layer, generates tensile stress after heating processes (such as curing), which can easily cause the glass core layer to tear in the middle, reducing the product's structural reliability. Summary of the Invention

[0003] The present invention provides a substrate structure with better structural reliability.

[0004] The substrate structure of the present invention includes a substrate and at least one add-on structure layer. The substrate includes a dielectric core plate and at least one first conductive via penetrating the dielectric core plate. The at least one add-on structure layer is disposed on the substrate and includes a dielectric layer and at least one second conductive via penetrating the dielectric layer. The coefficient of thermal expansion of the dielectric layer is less than that of the dielectric core plate. The at least one second conductive via is electrically connected to the at least one first conductive via.

[0005] In one embodiment of the present invention, the substrate structure further includes at least one bonding layer and at least one third conductive via. The at least one bonding layer is disposed between the substrate and at least one add-on structure layer. The at least one third conductive via penetrates the at least one bonding layer and electrically connects at least one first conductive via and at least one second conductive via.

[0006] In one embodiment of the present invention, the material of the at least one third conductive via includes conductive paste, metal paste or nanowires.

[0007] In one embodiment of the present invention, as shown in cross-section, at least one first conductive via, at least one second conductive via, and at least one third conductive via have the same diameter.

[0008] In one embodiment of the present invention, as shown in cross-section, at least one first conductive via, at least one second conductive via, and at least one third conductive via are aligned and arranged with each other.

[0009] In one embodiment of the present invention, the dielectric core plate of the substrate is made of organic materials, inorganic materials or non-conductive composite materials.

[0010] In one embodiment of the present invention, the dielectric layer of the at least one added layer structure is made of organic materials, inorganic materials or non-conductive composite materials.

[0011] In one embodiment of the present invention, the dielectric core plate of the substrate is made of the same material as the dielectric layer of at least one add-on structure layer.

[0012] In one embodiment of the present invention, the Young's coefficient of at least one of the above-mentioned added-layer structures is greater than the Young's coefficient of the substrate.

[0013] In one embodiment of the present invention, the thickness of the substrate is between 80 micrometers and 800 micrometers.

[0014] In one embodiment of the present invention, the thickness of the at least one added layer is between 80 micrometers and 800 micrometers.

[0015] In one embodiment of the present invention, the substrate further includes at least one first circuit pattern, and the at least one add-on structure layer further includes at least one second circuit pattern. The at least one first circuit pattern is electrically connected to at least one first conductive via. The at least one second circuit pattern is electrically connected to at least one second conductive via.

[0016] Based on the above, in the substrate structure of the present invention, since the coefficient of thermal expansion of the dielectric layer of the added structure layer is less than the coefficient of thermal expansion of the dielectric core plate of the substrate, compressive stress can be formed to suppress the warping of the substrate structure, thereby enabling the substrate structure of the present invention to have better structural reliability.

[0017] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0018] Figure 1 is a cross-sectional schematic diagram of a substrate structure according to an embodiment of the present invention. Figure 2 is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention. Figure 3 is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention. Implementation

[0019] The embodiments of this invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings are not drawn to scale; in fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the invention.

[0020] Figure 1 is a schematic cross-sectional view of a substrate structure according to an embodiment of the present invention. Referring to Figure 1, in this embodiment, the substrate structure 100a includes a substrate 110 and at least one add-on structure layer (schematically shown as one add-on structure layer 120). The substrate 110 includes a dielectric core plate 112 and at least one first conductive via penetrating the dielectric core plate 112 (schematically shown as a plurality of first conductive vias 114). The add-on structure layer 120 is disposed on the substrate 110 and includes a dielectric layer 122 and at least one second conductive via penetrating the dielectric layer 122 (schematically shown as a plurality of second conductive vias 124). The coefficient of thermal expansion of the dielectric layer 122 is less than the coefficient of thermal expansion of the dielectric core plate 112. The second conductive via 124 is electrically connected to the first conductive via 114.

[0021] In detail, in this embodiment, the dielectric core plate 112 of the substrate 110 has a first surface 111 and a second surface 113 opposite to the first surface 111. A first conductive via 114 penetrates the dielectric core plate 112, that is, the first conductive via 114 is surrounded by the dielectric core plate 112. In one embodiment, a first end 114a and a second end 114b of the first conductive via 114, which are opposite each other, can be flush with the first surface 111 and the second surface 113 of the dielectric core plate 112, respectively. In one embodiment, the first end 114a and the second end 114b of the first conductive via 114, which are opposite each other, can be slightly higher than the first surface 111 and the second surface 113 of the dielectric core plate 112, respectively. In one embodiment, the thickness T1 of the substrate 110 is, for example, between 80 micrometers and 800 micrometers. In one embodiment, the material of the dielectric core plate 112 of the substrate 110 is, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the aforementioned organic material is, for example, glass fiber resin (e.g., FR4), prepreg (PP), or inorganic filler mixed in the photoresist resin, but is not limited thereto. In one embodiment, the aforementioned inorganic material is, for example, glass, ceramic, or glass-ceramic. In one embodiment, the first conductive via 114 may be formed in the dielectric core plate 112 by electroplating, electroplating with a filler metal paste, or electroplating with a filler non-conductive resin, but is not limited thereto.

[0022] Referring again to Figure 1, in this embodiment, the dielectric layer 122 of the add-on structure layer 120 has an outer surface 121 and an inner surface 123 opposite to the outer surface 121, wherein the inner surface 123 is located between the outer surface 121 and the substrate 110. A second conductive via 124 penetrates the dielectric layer 122, meaning the second conductive via 124 is surrounded by the dielectric layer 122. In one embodiment, a first end 124a and a second end 124b of the second conductive via 124, facing each other, may be flush with the outer surface 121 and the inner surface 123 of the add-on structure layer 120, respectively. In one embodiment, the first end 124a and the second end 124b of the second conductive via 124, facing each other, may be slightly higher than the outer surface 121 and the inner surface 123 of the dielectric layer 122, respectively. In one embodiment, the thickness T2 of the add-on structure layer 120 is, for example, between 80 micrometers and 800 micrometers. In one embodiment, the dielectric layer 122 of the add-on structure layer 120 is made of, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the organic material is, for example, glass fiber resin (e.g., FR4), prepreg (PP), or an inorganic filler mixed with a photoresist resin, but is not limited thereto. In one embodiment, the inorganic material is, for example, glass, ceramic, or glass-ceramic. In one embodiment, the second conductive via 124 can be formed within the dielectric layer 122 by electroplating, electroplating with a filler metal paste, or electroplating with a filler non-conductive resin, but is not limited thereto.

[0023] In one embodiment, the Young's coefficient of the add-on structure layer 120 may be greater than that of the substrate 110. That is, the add-on structure layer 120 has the lowest coefficient of thermal expansion and the highest Young's coefficient compared to the substrate 110. In one embodiment, the material of the dielectric core plate 112 of the substrate 110 may be the same as the material of the dielectric layer 122 of the add-on structure layer 120, for example, both being organic materials. In one embodiment, the material of the dielectric core plate 112 of the substrate 110 may be the same as that of the dielectric layer 122 of the add-on structure layer 120, for example, both being inorganic materials. In one embodiment, the material of the dielectric core plate 112 of the substrate 110 may be an organic material, while the material of the dielectric layer 122 of the add-on structure layer 120 may be an inorganic material. In one embodiment, the material of the dielectric core plate 112 of the substrate 110 may be an inorganic material, while the material of the dielectric layer 122 of the add-on structure layer 120 may be an organic material. In one embodiment, when the dielectric core plate 112 of the substrate 110 and / or the dielectric layer 122 of the add-on structure layer 120 are made of glass, the density of the first conductive via 114 and / or the second conductive via 124 can be increased, and because the glass surface is flat, it is also very suitable for fabricating high-density circuits on it.

[0024] Furthermore, referring again to FIG1, the substrate structure 100a of this embodiment further includes at least one bonding layer (schematically shown as a bonding layer 130) and at least one third conductive via (schematically shown as a plurality of third conductive vias 135). The bonding layer 130 is disposed between the substrate 110 and the add-on structure layer 120, wherein the add-on structure layer 120 is fixed to the substrate 110 through the bonding layer 130. The third conductive via 135 penetrates the bonding layer 130 and electrically connects the first conductive via 114 of the substrate 110 and the second conductive via 124 of the add-on structure layer 120. In one embodiment, in cross-sectional view, the first conductive via 114, the second conductive via 124, and the third conductive via 135 may have the same diameter and be aligned with each other in a straight line. In other words, the orthographic projections of the first conductive via 114, the second conductive via 124, and the third conductive via 135 on a plane may completely overlap.

[0025] In one embodiment, the bonding layer 130 may be made of, for example, a thermosetting or thermoplastic polymer. In one embodiment, the bonding layer 130 may be made of, for example, polyimide (PI), Ajinomoto build-up film (ABF), bismaleimide-triazine (BT), or other polymers. In one embodiment, the thickness T3 of the bonding layer 130 is, for example, 8 micrometers to 100 micrometers. In one embodiment, the bonding layer 130 has a low modulus and can serve as a stress-reducing layer. In one embodiment, the material of the third conductive via 135 formed within the bonding layer 130 may be, for example, conductive paste (such as TLPS), metal paste (such as copper or silver paste), or nanowires, but is not limited thereto.

[0026] In short, since the coefficient of thermal expansion of the dielectric layer 122 of the added structure layer 120 is less than that of the dielectric core plate 112 of the substrate 110, compressive stress can be formed to suppress the warping of the substrate structure 100a, thereby enabling the substrate structure 100a of this embodiment to have better structural reliability.

[0027] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0028] Figure 2 is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention. Referring to Figures 1 and 2 simultaneously, the substrate structure 100b of this embodiment is similar to the substrate structure 100a described above, except that the main difference is that in this embodiment, the substrate structure 100b further includes a build-up layer 140, a bonding layer 150, and a third conductive via 155. That is, the substrate structure 100b of this embodiment is composed of a substrate 110, two build-up layers 120 and 140, and two bonding layers 130 and 150.

[0029] In detail, the add-on structure layer 140 is disposed on the second surface 113 of the substrate 110. The add-on structure layer 140 includes a dielectric layer 142 and at least one second conductive via (a plurality of second conductive vias 144 are schematically shown) penetrating the dielectric layer 142. The coefficient of thermal expansion of the dielectric layer 142 is less than that of the dielectric core plate 112. In this embodiment, the dielectric layer 142 of the add-on structure layer 140 has an outer surface 141 and an inner surface 143 opposite to the outer surface 141, wherein the inner surface 143 is located between the outer surface 141 and the substrate 110. The second conductive via 144 penetrates the dielectric layer 142, that is, the second conductive via 144 is surrounded by the dielectric layer 142. In one embodiment, a first end 144a and a second end 144b of the second conductive via 144, which are opposite to each other, can be flush with the outer surface 141 and the inner surface 143 of the add-on structure layer 140, respectively. In one embodiment, the first end 144a and the second end 144b of the second conductive via 144, which are opposite each other, may be slightly higher than the outer surface 141 and the inner surface 143 of the dielectric layer 142, respectively. In one embodiment, the thickness T4 of the add-on structure layer 140 is, for example, between 80 micrometers and 800 micrometers. In one embodiment, the dielectric layer 142 of the add-on structure layer 140 is made of, for example, an organic material, an inorganic material, or a non-conductive composite material. In one embodiment, the organic material is, for example, glass fiber resin (e.g., FR4), prepreg (PP), or an inorganic filler mixed in a photoresist resin, but is not limited thereto. In one embodiment, the inorganic material is, for example, glass, ceramic, or glass-ceramic. In one embodiment, the second conductive via 144 may be formed in the dielectric layer 142 by electroplating, electroplating with a filler metal paste, or electroplating with a filler non-conductive resin, but is not limited thereto.

[0030] In one embodiment, the materials of the dielectric layer 122 of the add-on structure layer 120, the dielectric core plate 112 of the substrate 110, and the dielectric layer 142 of the add-on structure layer 140 may be, in sequence, a combination of glass, organic materials, and glass (GOG). In one embodiment, the materials of the dielectric layer 122 of the add-on structure layer 120, the dielectric core plate 112 of the substrate 110, and the dielectric layer 142 of the add-on structure layer 140 may be, in sequence, a combination of ceramic, organic materials, and ceramic (COC). In one embodiment, the materials of the dielectric layer 122 of the add-on structure layer 120, the dielectric core plate 112 of the substrate 110, and the dielectric layer 142 of the add-on structure layer 140 may be, in sequence, a combination of ceramic, organic materials, and glass (COG). In one embodiment, the substrate structure 100b can be considered as a hybrid core structure.

[0031] It is worth mentioning that by covering two pieces of glass (such as dielectric layers 122 and 142 of the add-on structure layers 120 and 140) on both sides of the organic material (such as the dielectric core plate 112 of the substrate 110), the thickness of the organic material can be effectively reduced and the rigidity can be improved. In addition, since the thickness of the organic material can be reduced, smaller vias can be used, the spacing can be reduced, and the density of conductive vias can be increased accordingly.

[0032] Furthermore, referring to Figure 2, the bonding layer 150 is disposed between the second surface 113 of the substrate 110 and the add-on structure layer 140, wherein the add-on structure layer 140 is fixed to the substrate 110 through the bonding layer 150. A third conductive via 155 penetrates the bonding layer 150 and electrically connects the first conductive via 114 of the substrate 110 and the second conductive via 144 of the add-on structure layer 140. In one embodiment, viewed in cross-section, the first conductive via 114, the second conductive via 124, the second conductive via 144, the third conductive via 135, and the third conductive via 155 may have the same diameter and be aligned with each other in a straight line. In other words, the orthographic projections of the first conductive via 114, the second conductive via 124, the second conductive via 144, the third conductive via 135, and the third conductive via 155 on a plane may completely overlap.

[0033] In one embodiment, the bonding layer 150 may be made of, for example, a thermosetting or thermoplastic polymer. In one embodiment, the bonding layer 150 may be made of, for example, polyimide (PI), Ajinomoto build-up film (ABF), bismaleimide-triazine (BT), or other polymers. In one embodiment, the thickness T5 of the bonding layer 150 is, for example, 8 to 100 micrometers. In one embodiment, the bonding layer 150 has a low modulus and can serve as a stress-reducing layer. In one embodiment, the material of the third conductive via 155 formed within the bonding layer 150 may be, for example, conductive paste (such as TLPS), metal paste (such as copper or silver paste), or nanowires, but is not limited thereto.

[0034] In short, in this embodiment, the outermost add-on structural layers 120 and 140 have the lowest coefficient of thermal expansion and the highest Young's coefficient compared to the dielectric core plate 112 of the substrate 110. Since the coefficients of thermal expansion of the dielectric layers 122 and 142 of the add-on structural layers 120 and 140 are less than those of the dielectric core plate 112 of the substrate 110, compressive stress can be generated to suppress warping of the substrate structure 100b, thereby enabling the substrate structure 100b of this embodiment to have better structural reliability.

[0035] Figure 3 is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention. Referring simultaneously to Figures 2 and 3, the substrate structure 100c of this embodiment is similar to the substrate structure 100b described above, except that in this embodiment, the substrate 110' further includes at least one first circuit pattern 116, and the add-on structure layer 120' further includes at least one second circuit pattern 126, and the add-on structure layer 140' further includes at least one second circuit pattern 146. The first circuit pattern 116 is disposed on the first surface 111 and the second surface 113 of the dielectric core plate 112, wherein the first circuit pattern 116 is electrically connected to the first conductive via 114. In one embodiment, the first circuit pattern 116 may be, for example, a pad, a circuit, a conductive blind via, or a combination thereof. The second circuit pattern 126 is disposed on the outer surface 121 and the inner surface 123 of the dielectric layer 122, wherein the second circuit pattern 126 is electrically connected to the second conductive via 124. In one embodiment, the second wiring pattern 126 may be, for example, a pad, a line, a conductive blind via, or a combination thereof. The second wiring pattern 146 is disposed on the outer surface 141 and the inner surface 143 of the dielectric layer 142, wherein the second wiring pattern 146 is electrically connected to the second conductive via 144. In one embodiment, the second wiring pattern 146 may be, for example, a pad, a line, a conductive blind via, or a combination thereof.

[0036] Furthermore, the add-on structure layer 120' is fixed to the first surface 111 of the substrate 110 through the bonding layer 130', wherein the bonding layer 130' contacts and covers the inner surface 123 of the add-on structure layer 120', a portion of the second circuit pattern 126, a portion of the first circuit pattern 116, and the first surface 111 of the dielectric core plate 112. The add-on structure layer 140' is fixed to the second surface 113 of the substrate 110 through the bonding layer 150', wherein the bonding layer 150' contacts and covers the inner surface 143 of the add-on structure layer 140', a portion of the second circuit pattern 146, a portion of the first circuit pattern 116, and the second surface 113 of the dielectric core plate 112. The second conductive via 124 is electrically connected to the first conductive via 114 through the third conductive via 135', and the second conductive via 144 is electrically connected to the first conductive via 114 through the third conductive via 155'.

[0037] Since the substrate 110' is bonded to the add-on structural layers 120' and 140' through bonding layers 130' and 150', wiring can be performed separately on the substrate 110' and the add-on structural layers 120' and 140', thereby increasing the wiring density of the substrate structure 100c. Furthermore, in an embodiment not shown, multiple substrate structures can also be combined through adhesive layers and electrically connected to the substrate structure through conductive vias within the bonding layers.

[0038] In summary, in the substrate structure of the present invention, since the coefficient of thermal expansion of the dielectric layer of the added structure layer is less than that of the dielectric core plate of the substrate, compressive stress can be formed to suppress the warping of the substrate structure, thereby enabling the substrate structure of the present invention to have better structural reliability.

[0039] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0040] 100a, 100b, 100c: Substrate structure 110, 110': Base 111: First Surface 112: Dielectric core board 113: Second Surface 114: First conductive via 114a: First end 114b: Second end 116: First route pattern 120, 120', 140, 140': Add-on structural layers 121, 141: Outer surface 122, 142: Dielectric layer 123, 143: Inner surface 124, 144: Second conductive via 124a, 144a: First end 124b, 144b: Second end 126, 146: Second route pattern 130, 130', 150, 150': Bonding layer 135, 135', 155, 155': Third conductive via T1, T2, T3, T4, T5: Thickness

Claims

1. A substrate structure, comprising: A substrate includes a dielectric core plate and at least one first conductive via penetrating the dielectric core plate; at least one add-on structure layer disposed on the substrate and including a dielectric layer and at least one second conductive via penetrating the dielectric layer, wherein the coefficient of thermal expansion of the dielectric layer is less than the coefficient of thermal expansion of the dielectric core plate; at least one bonding layer disposed between the substrate and the at least one add-on structure layer, wherein the at least one add-on structure is bonded and fixed to the substrate through the at least one bonding layer; and at least one third conductive via penetrating the at least one bonding layer and electrically connecting the at least one first conductive via and the at least one second conductive via, wherein the orthographic projections of the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via on a plane completely overlap.

2. The substrate structure as claimed in claim 1, wherein the material of the at least one third conductive via includes conductive paste, metal paste, or nanowires.

3. The substrate structure as claimed in claim 1, wherein, in cross-sectional view, the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via have the same diameter.

4. The substrate structure as claimed in claim 1, wherein, in cross-sectional view, the at least one first conductive via, the at least one second conductive via, and the at least one third conductive via are aligned with each other.

5. The substrate structure as claimed in claim 1, wherein the dielectric core plate of the substrate is made of organic materials, inorganic materials, or non-conductive composite materials.

6. The substrate structure as claimed in claim 1, wherein the dielectric layer of the at least one addendum layer is made of organic materials, inorganic materials, or non-conductive composite materials.

7. The substrate structure as claimed in claim 1, wherein the dielectric core plate of the substrate is made of the same material as the dielectric layer of the at least one add-on structure layer.

8. The substrate structure as claimed in claim 1, wherein the Young's coefficient of the at least one added-layer structure is greater than the Young's coefficient of the substrate.

9. The substrate structure as claimed in claim 1, wherein the thickness of the substrate is between 80 micrometers and 800 micrometers.

10. The substrate structure as claimed in claim 1, wherein the thickness of the at least one add-on structure layer is between 80 micrometers and 800 micrometers.

11. The substrate structure as claimed in claim 1, wherein the substrate further includes at least one first circuit pattern, and the at least one add-in structure layer further includes at least one second circuit pattern, the at least one first circuit pattern being electrically connected to the at least one first conductive via, and the at least one second circuit pattern being electrically connected to the at least one second conductive via.

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