Integrated circuit device and method for forming integrated circuit device

Abstract

A process for forming an integrated circuit device includes forming semiconductor fins on a substrate of a wafer and covering the semiconductor fins to form a sacrificial gate structure. The process includes removing a byproduct layer from the sacrificial gate structure by performing a multi-step etching process including dry etching and wet etching processes.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have resulted in several generations of integrated circuits, each with smaller and more complex circuitry than the previous generation. In the development of integrated circuits, functional density (i.e., the number of interconnects per wafer area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. Such scaling down also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying drawings, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figures 1 through 24 are perspective and cross-sectional views of integrated circuits at various processing stages according to some embodiments. Figure 25A is an illustration of a dry etching tool according to some embodiments. Figure 25B is an illustration of a wet etching tool according to some embodiments. Figures 26A and 26B are graphs relating to transistor characteristics according to some embodiments. Figure 27 is a flowchart of a method for forming an integrated circuit according to some embodiments. Figure 28 is a flowchart of a method for forming an integrated circuit according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). The spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptions used herein can be interpreted similarly accordingly.

[0007] Terms indicating relative degree, such as “about,” “substantially,” and the like, should be interpreted as terms that a person of ordinary skill would understand based on current technical specifications.

[0008] This disclosure generally relates to semiconductor devices, and more specifically, to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the spacing between active regions in nanostructure devices is generally uniform, the source / drain epitaxial structure is symmetrical, and the metal gate surrounds the four sides of the nanostructure (e.g., a nanosheet). Due to the larger metal gate clamps and the increased source / drain epitaxial size, the gate-drain capacitance ("Cgd") increases.

[0009] The embodiments disclosed herein provide a method for forming a transistor that improves transistor characteristics. A plurality of semiconductor fins are formed on a substrate extending in a first direction. A plurality of sacrificial gate structures are formed extending in a second direction and overlying the semiconductor fins. Patterning of the sacrificial gate structures results in a byproduct layer covering the sacrificial gate structures within the semiconductor fins. More specifically, thick accumulations of byproducts can be collected at the bottom junction between the semiconductor fins and the sacrificial gate structures. The embodiments disclosed herein advantageously utilize a multi-step etching process including a combination of dry and wet etching to effectively remove the byproduct layer and thick accumulations. Furthermore, sacrificial dielectric nanostructures are used to release the gate-encircling transistor channel formed with the fins. The result of these processes is maintained uniform channel thickness, and the gate metal does not contain protrusions with leakage or short-circuit risk to the source / drain regions. Transistor performance is significantly improved, and wafer yield is also significantly increased. More specifically, channel resistance is reduced, and the AC / DC performance of the transistor is improved.

[0010] Transistors can be referred to as "nanostructure transistors," and channels can be referred to as "semiconductor nanostructures." Nanostructure transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure transistor structure.

[0011] Figures 1 through 24 are perspective views and side cross-sectional views of a portion of an integrated circuit 100 at different processing stages according to some embodiments. The manufacturing process produces a plurality of transistors 154, as will be described in further detail below. While the description herein focuses primarily on the formation of transistors including stacked channels, in practice, the principles disclosed herein extend to FinFET transistors, fork transistors, CFET transistors, VFET transistors, and CMOS transistors.

[0012] Figure 1 is a perspective view of an integrated circuit 100 in an intermediate processing state according to some embodiments. The integrated circuit 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In an exemplary embodiment, the substrate includes silicon. Alternatively, the substrate 102 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may be used.

[0013] The integrated circuit 100 includes a semiconductor stack 103 comprising alternating semiconductor layers 104 and sacrificial semiconductor layers 106. As will be further described in detail below, the semiconductor layers 104 are patterned to form stacked channels of a plurality of transistors. As will be described in more detail below, the sacrificial semiconductor layers 106 are eventually completely removed to allow gate metal and other structures to be formed around the channels. In Figure 1, three semiconductor layers 104 and three sacrificial semiconductor layers 106 are illustrated. In some embodiments, the multilayer stack 103 may include fewer or more layers than shown in Figure 1.

[0014] In some embodiments, semiconductor layer 104 may be formed of a suitable first semiconductor material (such as silicon, silicon carbide, or the like), and sacrificial semiconductor layer 106 may be formed of a second semiconductor material (such as silicon germanium or the like). In an exemplary embodiment, semiconductor layer 104 is silicon, and semiconductor layer 106 is silicon germanium. Each of the layers in the multilayer stack 103 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

[0015] Due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form a stacked channel region of transistors, as will be explained in more detail below.

[0016] In Figure 1, the stack 103 has been patterned to form a plurality of semiconductor fins 108. Figure 1 only illustrates a single semiconductor fin 108. However, in practice, a plurality of semiconductor fins 108 are formed, which extend parallel to each other in the X direction and are spaced apart from each other in the Y direction.

[0017] Semiconductor fins 108 can be formed by depositing a hard mask layer on stack 103. The hard mask layer may include a dielectric material. The dielectric material may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The hard mask layer may have a thickness between 3 nm and 20 nm. The hard mask layer is then patterned according to an optical lithography process to form stripes extending in the Y direction in the pattern of the semiconductor fins 108 to be formed. After the hard mask layer is patterned, trenches 110 are formed in stack 103 and in substrate 102. The trenches 110 can be formed using an anisotropic etching process that etchs in the down direction. The etching process defines the semiconductor fins 108 by forming the trenches 110 in the presence of the hard mask layer. The result of the etching process is the formation of a plurality of semiconductor fins 108 from stack 103. The semiconductor fins 108 extend in the X direction.

[0018] In Figure 1, shallow trench isolation regions 112 are formed by depositing dielectric material in trenches 110 between fins 108. The dielectric material can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material includes silicon oxide. However, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. A chemical mechanical planarization (CMP) process has been performed to remove excess material from the top surface of the hard mask layer in the shallow trench isolation regions 112.

[0019] After depositing the material in the trench isolation zone 112, the hard mask layer is removed. The hard mask layer can be removed using one or more etching processes. The etching processes may include wet etching, dry etching, or other suitable etching processes.

[0020] According to some embodiments, after removing the hard mask layer, an etch-back process is performed to recess the top of the shallow trench isolation region 112. The etch-back process completes the shallow trench isolation region 112. The top surface of the shallow trench isolation region 112 is below the lowest semiconductor layer 104 of the fin 108.

[0021] As shown in Figure 1, the integrated circuit 100 includes a dielectric layer 109 formed on the fin 108. The dielectric layer 109 is a contact etch stop layer (CESL). The dielectric layer 109 covers the top fin 108. The dielectric layer 109 may also cover the top surface of the trench isolation region 112. In some embodiments, the dielectric layer 109 includes SiCN, SiOCN, SiOC-SiO, SiN, or other suitable dielectric materials. The dielectric layer 109 may have a thickness between 1 nm and 10 nm. Other materials and thicknesses may be used for the dielectric layer 109 without departing from the scope of this disclosure.

[0022] In Figure 1, according to some embodiments, a sacrificial gate layer 114 has been deposited over the integrated circuit 100. The sacrificial gate layer 114 covers the fin 108. The sacrificial gate material may include a material with high etch selectivity relative to the trench isolation region 112. In an exemplary embodiment, the sacrificial gate layer 114 comprises polycrystalline silicon. However, the sacrificial gate layer 114 may be a conductive, semiconductor, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 114 may be deposited by PVD, CVD, sputtering deposition, or other techniques for depositing the selected material. As will be described in more detail below, the sacrificial gate layer 114 will ultimately be patterned to form a sacrificial gate structure.

[0023] Figure 2 is a cross-sectional view of an integrated circuit 100, taken along cut line 2 in Figure 1, at the same processing stage as shown in Figure 1, according to some embodiments. Figure 2 illustrates a semiconductor fin 108 extending in the X direction, comprising a stack 103 of a semiconductor layer 104 and a sacrificial semiconductor layer 106 formed over a substrate 102. As shown, a dielectric layer 109 is located on the top surface of the fin 108. A sacrificial gate layer 114 covers the dielectric layer 109.

[0024] Figure 3 is a perspective view of an integrated circuit 100 in an intermediate processing stage according to some embodiments. In Figure 3, a sacrificial gate structure 118 has been formed above the fin 108. The sacrificial gate structure 118 extends perpendicularly to the fin 108 in the Y direction. Each sacrificial gate structure 118 transversely intersects multiple fins 108. The sacrificial gate structure 118 is also formed in a trench 110. Figure 3 only illustrates a single sacrificial gate structure 118. However, in practice, a plurality of sacrificial gate structures 118 are formed extending parallel to each other in the Y direction.

[0025] The sacrificial gate structure 118 includes a sacrificial gate layer 114. Specifically, the sacrificial gate structure 118 is formed by patterning the sacrificial gate layer 114 to form parallel stripes or structures of the sacrificial gate layer 114 extending in the Y direction. As will be explained in more detail below, the sacrificial gate structure 118 corresponds to the location where the gate metal of the transistor is formed in a subsequent step. Specifically, the sacrificial gate layer 114 is removed and replaced with gate metal.

[0026] Although not shown in Figure 3, the sacrificial gate structure 118 may include one or more dielectric masking layers formed on the sacrificial gate layer 114. The dielectric masking layers may include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric masking layers may be deposited using CVD, ALD, PVD, or other suitable deposition processes. Other materials and deposition processes may be used for the dielectric layers without departing from the scope of this disclosure.

[0027] In Figure 3, byproduct layer 119 has been deposited on all exposed surfaces of integrated circuit 100. Specifically, byproduct layer 119 covers semiconductor fin 108, with dielectric layer 109 inserted between byproduct layer 119 and semiconductor fin 108. Byproduct layer 119 covers the side surface of sacrificial gate layer 114. Byproduct layer 119 is also on top of trench isolation region 112.

[0028] In some embodiments, the byproduct layer 119 is a byproduct of the patterning process that forms the sacrificial gate structure 118. As previously described, the sacrificial gate structure 118 is formed by patterning a sacrificial gate layer 114 and forming one or more dielectric masking layers on top of the sacrificial gate layer 114. The byproduct layer 119 may be generated from this patterning process. The byproduct layer 119 may include silicon, silicon oxide, SiO-Cl, SiO-HBr, SiO-N, SiO-Ar, or other materials.

[0029] In some embodiments, byproduct accumulation 120 may be formed at the corner or junction where the trench isolation region 112, fin 108, and sacrificial gate layer 114 intersect. Byproduct accumulation 120 corresponds to the material accumulation of byproduct layer 119, which is thicker than other portions of byproduct layer 119. Byproduct accumulation 120 may include the material underlying sacrificial gate layer 114. As will be explained in more detail below, the presence of byproduct accumulation 120 may cause significant problems to the final structure of the transistor formed by fin 108.

[0030] Advantageously, embodiments disclosed herein include using an enhanced etching process to reduce or completely remove byproduct accumulation 120. The enhanced etching process may include a multi-stage etching process that first removes or significantly reduces byproduct accumulation 120, and then completely removes byproduct layer 119, as shown in subsequent figures.

[0031] In some embodiments, the etching process includes a first plasma etching process to remove or reduce byproduct accumulation 120. The plasma etching process can be performed in a plasma etching tool including a plasma etching chamber. Thus, at the processing stage shown in Figure 3, the wafer forming the integrated circuit 100 is conveyed to the plasma etching chamber. Subsequently, a plasma etching process is performed on the wafer including the integrated circuit 100. The plasma etching process is an anisotropic etching process that selectively etches in a specific direction, as will be described in more detail below. Directional etching can remove or reduce byproduct accumulation 120.

[0032] During the plasma etching process, plasma is generated within the plasma etching chamber. The etching gas may include HF, NH3, or other suitable etching gases. The plasma causes one or more of ions, neutral atoms, and free radicals to travel from the glow region of the plasma in a selected direction relative to the wafer. In some embodiments, the direction is substantially perpendicular. In some embodiments, the wafer is tilted such that the etchant species impacts the wafer at an angle relative to perpendicularity. This is particularly advantageous in removing byproduct buildup.

[0033] In some embodiments, during the etching process, a passivation gas flows into the etching chamber along with the etching gas. The passivation gas may include N2, O2, CO2, or other suitable passivation gases. The passivation gas helps provide etching selectivity relative to the unetched integrated circuit material. In some embodiments, a dilution gas flows into the plasma etching chamber. The dilution gas may include non-reactive gases such as He, Ar, N2, or other suitable gases.

[0034] In some embodiments, plasma is generated by applying a voltage between a top electrode in the plasma etching chamber and a bottom electrode beneath the wafer in the plasma etching chamber. In some embodiments, the total power consumption for plasma generation can be between 10 W and 40,000 W. In some embodiments, the pressure within the plasma etching chamber during the plasma etching process is between 1 mTorr and 800 mTorr. In some embodiments, the flow rate of the gases (etching, passivation, and dilution) can be between 20 sccm and 3000 sccm. Other etching gases, passivation gases, dilution gases, power levels, pressures, and flow rates may be used without departing from the scope of this disclosure. Although the plasma etching process has been described in conjunction with Figure 3, in practice, other dry etching processes may be used to reduce or remove byproduct buildup 120 without departing from the scope of this disclosure.

[0035] In Figure 4, the initial portion of the etching process has been performed, as described with respect to Figure 3. As can be seen in Figure 4, byproduct accumulation 120 has been substantially removed. Byproduct accumulation 120 may be completely removed or only partially removed. The benefits and consequences of this removal will be further described below.

[0036] Figure 5 is a cross-sectional view of the integrated circuit 100 at the processing stage shown in Figure 4 according to some embodiments. Figure 5 illustrates two sacrificial gate structures 118 that cross-section the semiconductor fin 108. A portion of the byproduct layer 119 remains on the sidewall of the sacrificial gate structure 118. In practice, during the processing stage, there may be more or less byproduct layer 119 remaining than shown in Figure 5.

[0037] In Figure 6, the second part of the etching process has been performed. The second part of the etching process removes the remaining portion of the byproduct layer 119 from the exposed surface. The second etching process may include a wet etching process. The wet etching process may include an isotropic etching process that etches in all directions. The wet etching process selectively etches the byproduct material relative to other exposed materials.

[0038] In some embodiments, after performing a plasma etching process, the wafer including the integrated circuit 100 is transferred from the plasma etching chamber to a wet etching chamber. In the wet etching chamber, the wet etching performed includes exposing the integrated circuit 100 to liquid chemicals used to etch the byproduct layer 119.

[0039] In some embodiments, the wet etching process does not substantially etch the dielectric layer 109. The result is the structure shown in Figure 6. The byproduct layer 119 and the byproduct accumulation 120 have been removed. If only a wet etching process is performed, a thick byproduct accumulation 120 may remain even after all other portions of the byproduct layer 119 have been removed. In some embodiments, instead of the byproduct accumulation 120, a small accumulation of material in the sacrificial gate layer 114 may be retained.

[0040] Figure 7 is a cross-sectional view of the integrated circuit 100 taken along cut line 7 of Figure 6 according to some embodiments. In Figure 7, the third portion of the etching process has been performed. The third portion of the etching process removes the dielectric layer 109 (CESL) from all locations except directly below the sacrificial gate structure 118. This can be accomplished via a second wet etching process. In some embodiments, the dielectric layer 109 can be removed using the same wet etching process as for removing the remaining portion of the byproduct layer 119.

[0041] Figure 8 is a cross-sectional view of an integrated circuit 100 cut along the Y direction (along cut line 8 in Figure 6) at the same processing stage as in Figure 7, according to some embodiments. Two semiconductor fins 108 are shown in Figure 8. Figure 8 shows a small remaining portion of the byproduct accumulation 120. The byproduct accumulation 120 may correspond to the material of the byproduct layer 119 and / or the material of the sacrificial gate layer 114.

[0042] Figure 9 is a cross-sectional view of the integrated circuit 100 taken in a horizontal plane along the cutting line 9 in Figure 6 (but after the exposed portion of the dielectric layer 109 has been removed), according to some embodiments. The cross-sectional view of Figure 9 illustrates a portion corresponding to the integrated circuit 100 and a portion corresponding to the alternative integrated circuit 101.

[0043] In the alternative integrated circuit 101, the plasma etching process described with respect to Figures 3 and 4 is not performed. As a result, a large amount of byproduct accumulation 120 remains at the corner between the lowest sacrificial semiconductor layer 106 and the sacrificial gate structure 118. In addition, a portion of the dielectric layer 109 (CESL) remains outside the sacrificial gate structure 118. This can lead to problems described later.

[0044] In integrated circuit 100, byproduct accumulation 120 has been substantially removed due to the enhanced multi-step etching process. Therefore, the corner between the lowest sacrificial semiconductor layer 106 and the sacrificial gate structure 118 is sharp. In practice, a very small amount of byproduct accumulation 120 may remain, but the residue is significantly reduced compared to replacing integrated circuit 101.

[0045] Figure 10 is a top view of an integrated circuit 100 at the processing stage shown in Figure 6 according to some embodiments. The top view of Figure 6 illustrates a nearly residue of byproduct accumulation 120 after an enhanced etching process. In some embodiments, the remaining thickness of the byproduct accumulation 120 has a dimension D1 between 0 nm and 2 nm in the X direction. In some embodiments, the remaining thickness of the byproduct accumulation 120 has a dimension D2 between 0 nm and 2 nm in the Y direction. In an alternative integrated circuit 101, dimensions D1 and D2 may be between 4 nm and 9 nm. Dimension D2 is also shown in Figure 8.

[0046] Figure 11 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 11, gate spacer layers 126 and 127 are formed on the sidewalls of the sacrificial gate structure 118. Gate spacer layers 126 and 127 may also be formed on other exposed surfaces of the integrated circuit. For example, portions of gate spacer layer 126 are formed on the top surface of fin 108, the sidewalls of fin 108, and the top surface of shallow trench isolation region 112. Gate spacer layer 126 may include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. Gate spacer layer 126 may be formed by PVD, CVD, ALD, or other suitable deposition processes. Gate spacer layer 127 may include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The gate spacer layer 127 can be formed by PVD, CVD, ALD or other suitable deposition processes.

[0047] After depositing gate spacer layer 126 / gate spacer layer 127, a portion of gate spacer layer 126 / gate spacer layer 127 (e.g., in the XY plane) has been removed. In other words, portions of the gate spacer layer on the top surface of fin 108 and the top surface of shallow trench isolation region 112 are removed. The vertically thicker portions of gate spacer layer 126 / gate spacer layer 127 remain on the sidewalls of fin 108. The removal of portions of gate spacer layer 126 / gate spacer layer 127 can be accomplished by an anisotropic etching process, thereby exposing the upper surfaces of fin 108 and trench isolation region 112. After patterning of gate spacer layer 126 / gate spacer layer 127, the vertically thicker portions of gate spacer layer 126 / gate spacer layer 127 still exist, such as the portions shown in Figure 11.

[0048] After removing a portion of gate spacer 126 / gate spacer 127, a source / drain trench 130 is formed in the fin 108. The sacrificial gate structure 118 and gate spacer 126 / gate spacer 127 serve as a mask for forming the source / drain trench 130 in the fin 108. Specifically, one or more etching processes are performed to form the source / drain trench 130 in the fin 108. Forming the source / drain trench 130 includes etching through each of the semiconductor layer 104 and the sacrificial semiconductor layer 106, and a portion of the substrate 102. Therefore, the removal operation may include suitable etching operations for removing material from the semiconductor layer 104, the sacrificial semiconductor layer 106, and the substrate 102. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), or similar methods.

[0049] The formation of the source / drain trench 130 results in the formation of stacks 132 of channels 105. Each stack 132 of channels 105 corresponds to a stacked channel of a transistor. The formation of the source / drain trench 130 also results in the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106. After the formation of the source / drain trench 130, the channels 105 and the sacrificial semiconductor nanostructures 107 may have substantially similar lateral dimensions.

[0050] Figure 12 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 12, the sacrificial semiconductor nanostructure 107 has been removed. The sacrificial semiconductor nanostructure 107 can be removed by performing an etching process that selectively etches the material of the sacrificial semiconductor nanostructure 107 relative to the material of the channel 105. As previously described, in an exemplary embodiment, the channel 105 is silicon and the sacrificial semiconductor nanostructure 107 is silicon-germanium. The etching process selectively etches the silicon-germanium of the sacrificial semiconductor nanostructure 107 relative to the silicon of the channel 105. The result is that the sacrificial semiconductor nanostructure 107 is completely removed, while the channel 105 is retained. As previously described, other materials may be used for the channel 105 and the sacrificial semiconductor nanostructure 107 without departing from the scope of this disclosure.

[0051] The view in Figure 12 also illustrates that the source / drain trench 130 extends into the substrate 102. Specifically, the etching process that forms the source / drain trench 130 also forms a groove in the substrate 102. As shown in Figure 12, the groove can be concave.

[0052] Figure 13 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 13, a dielectric layer 131 has been conformally deposited on the integrated circuit 100. The dielectric layer 131 is formed on the sidewalls of the gate spacer layer 127, the exposed portions of the substrate 102, and the exposed portions of the channel 105. Furthermore, the dielectric layer 131 fills the gaps between channels left by removing the sacrificial semiconductor nanostructure 107. In an exemplary embodiment, the dielectric layer 131 comprises silicon oxide. Alternatively, the dielectric layer 131 may comprise SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 131 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0053] Figure 14 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 14, a sacrificial dielectric nanostructure 133 has been formed instead of a sacrificial semiconductor nanostructure 107. Therefore, the sacrificial dielectric nanostructure 133 is formed between adjacent channels 105. The lowest sacrificial dielectric nanostructure 133 of each stack 132 is located between the substrate 102 and the lowest channel 105 of each stack 132. The sacrificial dielectric nanostructure 133 is formed by an etching process of the dielectric layer 131 using a gate spacer layer 127 as a mask. The etching process also forms grooves 134 in the dielectric nanostructure 133. Specifically, an isotropic etching process is performed, selectively etching the material of the sacrificial dielectric nanostructure 133 relative to other exposed materials. The etching process is timed to remove the end portions of the sacrificial dielectric nanostructure 133 without completely removing the sacrificial dielectric nanostructure 133. The result is the formation of a groove 134 in the dielectric nanostructure 133 between adjacent channels 105. In other words, the end of the dielectric nanostructure 133 is recessed relative to the end of the channel 105.

[0054] Figure 15 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 15, a dielectric layer 135 has been conformally deposited using ALD, CVD, or PVD. The dielectric layer lined with a gate spacer layer 127, a channel 105, a substrate 102, and filled with a recess 134. The dielectric layer 135 may include SiOCN, SiON, SiN, SiOC, SiOCN, SiON, or other suitable dielectric materials.

[0055] Figure 16 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 16, an etching process is performed to remove a portion of the dielectric layer 135 outside the recess 134. The etching process may include an anisotropic etching process, which selectively etches in the down direction, such that the gate spacer layer 127 and the channel 105 act as a mask for etching the dielectric layer 135. The result is the formation of an internal spacer 136.

[0056] Figure 17 is a cross-sectional view of an integrated circuit 100 according to some embodiments. A semiconductor structure 137 has been formed at the end of channel 105. Specifically, an epitaxial growth process has been performed to grow the semiconductor structure 137 from channel 105. In an exemplary embodiment, the semiconductor structure 137 comprises silicon germanium. However, other semiconductor materials may be used without departing from the scope of this disclosure. In practice, after the epitaxial growth process forming the semiconductor structure 137, the semiconductor material extends into the source / drain trench 130.

[0057] A bottom semiconductor layer 141 has been formed in the bottom of a trench 130 formed in a recess in substrate 102. The bottom semiconductor layer 141 may comprise an intrinsically semiconductor material, such as undoped silicon, undoped silicon-germanium, or other semiconductor materials. In Figure 17, in some embodiments, the bottom semiconductor layer 141 may be replaced by a bottom dielectric structure that electrically isolates the subsequently formed source / drain regions from substrate 102. The bottom dielectric structure may comprise silicon oxide, silicon nitride, or other suitable dielectric materials.

[0058] In Figure 17, source / drain regions 140 have been formed. In the illustrated embodiment, source / drain regions 140 are epitaxially grown from semiconductor structure 137 and bottom semiconductor layer 141 (if present). Source / drain regions 140 fill source / drain trenches 130. There are two source / drain regions 140 for each stack 132 in channel 105. Each channel 105 in stack 132 extends between adjacent source / drain regions 140.

[0059] In some embodiments, some stacks 132 of channels 105 may share a source / drain region 140 with stacks 132 of channels 105 adjacent to each other in the X direction. The central source / drain region 140 in Figure 17 is such a case, which is shared by two stacks of channels 105 on both sides.

[0060] The source / drain region 140 may comprise any acceptable material, such as materials suitable for n-type or p-type devices. For an n-type device, in some embodiments, the source / drain region 140 includes a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, or the like. According to some embodiments, when forming a p-type device, the source / drain region 140 includes a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, or the like. The source / drain region 140 may have surfaces protruding from individual surfaces of the fins and may have facets.

[0061] The source / drain region 140 may be implanted with dopants, followed by an annealing process. The source / drain region 140 may have an impurity concentration between approximately 10¹⁹ cm⁻³ and approximately 10²¹ cm⁻³. The n-type and / or p-type impurities used in the source / drain region 140 may be any of the impurities discussed previously. In some embodiments, the source / drain region 140 is in-situ doped during growth.

[0062] In Figure 17, a CESL 144 and an interlevel dielectric (ILD) 146 are formed. The CESL layer 144 may comprise a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain region 140, the trench isolation region 112, the gate spacer layer 127, and other exposed surfaces. The CESL layer 144 may comprise SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The CESL 144 may be deposited using CVD, ALD, PVD, or other suitable deposition processes.

[0063] Dielectric layer 146 covers CESL 144. Dielectric layer 146 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Dielectric layer 146 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0064] According to some embodiments, Figure 18 includes a right-hand portion and a left-hand portion, the right-hand portion being a cross-sectional view of the integrated circuit 100 of Figure 17, and the left-hand portion being a cross-sectional view of an alternative integrated circuit 101. The right-hand portion of Figure 18 corresponds to a horizontal plane passing through the X and Y axes of the lowest sacrificial dielectric nanostructure 133. Figure 18 again shows a portion of the integrated circuit 100 and a portion of the alternative integrated circuit 101 in a manner similar to that described with respect to Figure 9.

[0065] As previously described, in the alternative integrated circuit 101, no enhancement etching process is performed; therefore, byproduct accumulation 120 protrudes and extends to the vicinity of the source / drain region 140. This could be dangerous because after replacing the sacrificial gate layer 114 with gate metal, the gate metal will be very close to the source / drain region 140, potentially even forming a short circuit. However, as can be seen in the integrated circuit 100, there is little or no byproduct accumulation, and the sacrificial gate layer 114 does not protrude significantly toward the source / drain region 140.

[0066] Figure 19 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 19, the sacrificial gate structure 118 has been removed from between the gate spacers 126. Specifically, the sacrificial gate layer 114 has been completely removed from between the gate spacers 126.

[0067] In some embodiments, the sacrificial gate layer 114 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 114 without etching the spacer layer 126. When the sacrificial gate layer 114 is etched, the dielectric layer 109 (if present) may be used as an etch stop layer. The dielectric layer 109 may then be removed after the sacrificial gate layer 114 has been removed.

[0068] Removing the sacrificial gate layer 114 results in the formation of a void 149 between the gate spacer layers 126 above the channel 105. As will be explained in more detail below, the upper portion of the gate metal or gate electrode will be formed in the void 149. Therefore, the sacrificial gate layer 114 is sacrificed because the upper portion of the gate metal will ultimately be formed in its place.

[0069] Figure 20 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 20, channels 105 are released by removing the sacrificial dielectric nanostructure 133. The sacrificial dielectric nanostructure 133 can be removed by a selective etching process using an etchant selective to the material of the sacrificial dielectric nanostructure 133, such that the sacrificial dielectric nanostructure 133 is removed without substantially etching the channels 105 or the semiconductor structure 137. Removing the sacrificial dielectric nanostructure 133 results in the formation of voids 148 between the channels 105.

[0070] Figure 21 is an enlarged cross-sectional view of a portion of an integrated circuit 100 at the processing stage of Figure 20 according to some embodiments. The enlarged view illustrates channel 105, void 148, internal spacer 136, and source / drain region 140. One advantage of the process shown herein is that each of the channels 105 has a substantially constant vertical thickness. For example, the thickness dimension D3 near the center of channel 105 is substantially the same as the thickness dimension D4 near the lateral ends of channel 105. In other possible solutions, channel 105 may be substantially etched during release. However, because the release of channel 105 involves the removal of sacrificial dielectric nanostructure 133, which has a very high etch selectivity relative to channel 105, channel 105 is substantially unetched. As a result, the difference between thickness D3 and thickness D4 is less than 0.5 nm. As a result, the total resistance of the stacked channels 105 is relatively low during transistor operation, thereby reducing losses. This improves the DC performance of the transistor. In some embodiments, dimension D3 is between 9 nm and 10 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0071] In some embodiments, all channels 105 have the same thickness. In other words, the lower channels 105, the central channel 105, and the top channel 105 of each stack 132 all have substantially equal vertical thicknesses. Additionally, all gaps 148 have substantially equal vertical thicknesses. As a result, the gate metal subsequently formed will have the same thickness between the channels 105.

[0072] Figure 22 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 22, according to some embodiments, a high-k dielectric layer 150 and a gate metal 152 have been formed. Although not shown in Figure 22, an interface dielectric layer may be formed prior to the formation of the high-k dielectric layer 150. The interface dielectric layer and the high-k dielectric layer 150 correspond to the gate dielectric of the transistor.

[0073] An interface gate dielectric layer is deposited on all exposed surfaces of channel 105. The interface gate dielectric layer surrounds channel 105. The interface gate dielectric layer may include dielectric materials such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface gate dielectric layer may include a relatively low-k dielectric material relative to a high-k dielectric material (such as hafnium oxide or other high-k dielectric materials that can be used as gate dielectrics for transistors). High-k dielectric materials may include dielectric materials having a dielectric constant higher than that of silicon oxide. The interface gate dielectric layer may be formed by thermal oxidation processes, chemical vapor deposition (CVD) processes, or atomic layer deposition (ALD) processes. The interface gate dielectric layer may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interface gate dielectric layer without departing from the scope of this disclosure.

[0074] A high-k dielectric layer 150 is deposited using a conformal deposition process. The conformal deposition process deposits the high-k dielectric layer 150 on the interface gate dielectric layer, substrate 102, trench isolation region 112, and gate spacer layer 126. The high-k gate dielectric layer 150 surrounds the channel 105. The high-k gate dielectric layer 150 has a thickness between 1 nm and 3 nm. The high-k dielectric layer 150 includes one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k dielectric layer 150 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k dielectric layer 150 without departing from the scope of this disclosure. The high-k dielectric layer 150 is a gate dielectric layer.

[0075] Gate metal 152 is deposited on all exposed surfaces of the high-k dielectric layer 150. Gate metal 152 surrounds the channel 105. Although gate metal 152 is shown as a single layer in Figure 22, in practice, gate metal 152 may comprise one or more conductive liner layers, work function layers, and gate fill layers, which together constitute the gate metal. The gate metal may comprise one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. Gate metal 152 may be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes may be used for gate metal 152 without departing from the scope of this disclosure.

[0076] In the processing stage shown in Figure 22, transistor 154 is substantially completed. Each transistor 154 includes a stack 132 of channels 105 extending between source / drain regions 140 and serving as a stacked channel for the transistors 154. Gate metal 152 serves as a gate electrode surrounding the channels 105. Source / drain contacts may also be formed, although not shown in Figure 22. Trenches may be formed in dielectric layers 144 and 146 to expose the top surfaces of the source / drain regions 140. Silicon may be formed on the exposed portions of the source / drain regions 140. Conductive vias or sockets may be formed in contact with the silicon. Voltage may be applied to the source / drain regions 140, or current may be transmitted through the source / drain contacts.

[0077] Figure 23 is a perspective view of an integrated circuit 100 at the processing stage shown in Figure 22 according to some embodiments. The view in Figure 22 is taken along the cut line 22 in Figure 23.

[0078] According to some embodiments, Figure 24 includes a right-side portion and a left-side portion. The right-side portion is a cross-sectional view of the integrated circuit 100 of Figure 22, and the left-side portion is a cross-sectional view of the alternative integrated circuit 101. Figure 24 is a cut view of the gate metal 152 passing through the lowest channel 105, similar to the cut positions in Figures 9 and 18, but in Figure 24, the sacrificial gate layer 114 has been replaced by the gate metal 152 and the high-k dielectric layer 150. Figure 24 again illustrates the integrated circuit 100 according to some embodiments, namely the alternative integrated circuit 100 without utilizing the enhanced etching process.

[0079] In integrated circuit 101, byproduct accumulation 120 has caused a protrusion 153 of the gate metal 152 and the high-k dielectric layer 150 toward the source / drain region 140. The protrusion 153 is essentially nonexistent, and the corresponding bending angle in the high-k dielectric layer 150 at the edge of the internal spacer 136 is ϴ101. In some embodiments, for the bottom gate metal portion (the portion below the lowest channel 105), the angle ϴ101 is between 80° and 100°; for the middle gate metal portion (the portion between the lowest channel 105 and the middle channel 105), the angle ϴ101 is between 100° and 130°; and for the upper gate metal portion (between the middle channel 105 and the top channel 105), the angle ϴ101 is between 160° and 180°.

[0080] At protrusion 153, the high-k dielectric layer 150 intersects with the thin native oxide layer 156 and is separated from the source / drain region 140 by a relatively small distance D5, between 0.3 nm and 3 nm. The native oxide layer 156 has a dimension D6 in the Y direction between 3 nm and 5 nm. In some embodiments, dimension D7 is between 3 nm and 5 nm. Dimension D8 is between 8 nm and 13 nm. Although not shown in Figure 18, the native oxide layer 156 may also be present in Figure 18.

[0081] Conversely, in the integrated circuit 100, the gate metal 152 and the high-k dielectric layer 150 have little or no protrusion towards the source / drain region 140 at the edges of the internal spacers 136. In some embodiments, the high-k dielectric layer forms an angle ϴ100 at the edges of the internal spacers 136. For the lowest portion of the gate metal 152, ϴ100 has a value between 150° and 165°. For the middle portion of the gate metal, ϴ100 is between 165° and 170°. For the upper portion of the gate metal, ϴ100 is between 170° and 180°. These angle values ​​are highly advantageous because they result in the gate metal 152 not having sharp protrusions towards the source / drain region 140, which could lead to high leakage current or even short circuits. Therefore, the high angle values ​​result in improved electrical performance of the transistor.

[0082] Furthermore, dimension D9 corresponds to the separation between the high-k dielectric layer 150 and the source / drain region 140, and has a minimum value between 5 nm and 10 nm. This value is highly beneficial because it helps ensure virtually no leakage between the gate metal and the source / drain region. This also reduces parasitic capacitance. The overall result is improved transistor performance. Therefore, the integrated circuit 100 significantly reduces the likelihood of a short circuit between the source / drain region 140 and the gate metal 152, as well as the capacitance between the gate metal 152 and the source / drain region 140. Additionally, dimension D10 corresponds to the thickness of the native oxide layer 156, and is between 0.3 nm and 1 nm. Dimension D11 is between 0.3 nm and 1 nm. Dimension D12 is between 5 nm and 8 nm. This combination of values ​​gives the transistor improved electrical performance.

[0083] Figure 25A is an illustration of a plasma etching tool 170 according to some embodiments. Figure 25B is an illustration of a wet etching tool 171 according to some embodiments. In some embodiments, a wafer 172 (including integrated circuitry 100) is transferred to the plasma etching tool 170 at the processing stage shown in Figure 3. Then, as shown in Figures 3 and 4, a plasma etching process is performed to remove byproduct deposits 120. Next, the wafer 172 (including integrated circuitry 100) is transferred to the wet etching tool 171. Then, as previously described, a wet etching process is performed to remove the byproduct layer 119.

[0084] The plasma etching tool 170 includes a semiconductor process chamber 173, which includes a top electrode 174, a bottom electrode 175, and a wafer 172 positioned on the bottom electrode 175. An RF power supply 176 is coupled to the top electrode 174 and the bottom electrode 175. A control system 177 is coupled to the RF power supply 176. The bottom electrode 175 may also be a chuck for holding the wafer 172.

[0085] In one embodiment, the RF power supply 176 drives the top electrode 174 and the bottom electrode 175 to generate plasma in the plasma region 178 by applying an AC voltage in the RF range between the top electrode 174 and the bottom electrode 175. As previously described, the plasma can be generated from gas within the semiconductor process chamber 173.

[0086] Glow discharge is associated with plasma region 178. For example, etching processes, implantation processes, deposition processes, and other types of plasma-assisted semiconductor processes generate plasma, specifically optical and thermal properties. Glow discharge can also depend on various process parameters, such as DC voltage, RF power, pressure, and temperature.

[0087] In the example of Figure 25A, the plasma generation process results in an anodic glow region 179 adjacent to the top electrode 174. In this example, the top electrode 174 is the anode. The plasma generation process also results in a cathodic glow region 180 adjacent to the bottom electrode cathode. In this example, the bottom electrode 175 is the cathode. The main plasma region 178 is located between the anodic glow region 179 and the cathodic glow region 180. As previously described, the etch particles are driven vertically downward to selectively etch features of the wafer 172 in the downward direction. In some embodiments, the wafer 172 may be held on a chuck that may be tilted or rotated to allow the etch particles to impact the features of the wafer at a selected angle, as previously described. In these cases, the bottom electrode may be configured differently from that shown in Figure 25A.

[0088] Figure 25B is a simplified illustration of a wet etching tool 171 according to some embodiments. After performing a plasma etching process, a wafer 172 is transferred to the wet etching tool. The wet etching tool includes an internal etching chamber 183. The wafer 172 is placed on a wafer support 182 in an etching tank 184. Various etching apparatuses 185 can also be used to assist in performing the wet etching process. As previously mentioned, the wet etching process can be used in conjunction with the processes described in Figures 4 through 8. Other types of wet etching tools 171 can be used without departing from the scope of this disclosure.

[0089] Figure 26A is a graph 200 illustrating the relationship between the effective drain current minus the effective source current and Ceff1 of a transistor according to some embodiments. Curve 202 corresponds to a device in which a multi-step etching process has been performed and where the sacrificial dielectric nanostructure 133 has been used instead of the sacrificial semiconductor nanostructure 107. Curve 204 corresponds to a device without the sacrificial dielectric nanostructure 133. It can be seen that the DC / AC characteristics of the transistor are greatly improved in curve 202. The smaller Ceff is, the larger the current. Therefore, the effective drain current minus the source current (Sof1) is better. Better DC means a smaller resistance R. Better AC means a smaller Ceff.

[0090] Figure 26B is a graph 201 illustrating the relationship between the total channel resistance of a transistor and Ceff1 according to some embodiments. Curve 203 corresponds to a device in which a multi-step etching process has been performed and where a sacrificial dielectric nanostructure 133 has been used instead of a sacrificial semiconductor nanostructure 107. Curve 205 corresponds to a device that does not utilize the sacrificial dielectric nanostructure 133. As shown, in curve 203, the overall channel resistance of the transistor decreases.

[0091] Figure 27 is a flowchart of a method 2700 for forming an integrated circuit according to some embodiments. Method 2700 may utilize the structures, processes, and systems described in conjunction with other figures. At step 2702, method 2700 includes forming a semiconductor fin on a substrate of the integrated circuit. An example of a semiconductor fin is semiconductor fin 108 of Figure 1. An example of a substrate is substrate 102 of Figure 1. At step 2704, method 2700 includes depositing a sacrificial gate layer over the substrate and the semiconductor fin. An example of a sacrificial gate layer is sacrificial gate layer 114 of Figure 1. At step 2706, method 2700 includes forming a sacrificial gate structure on the semiconductor fin by patterning the sacrificial gate layer from the sacrificial gate layer. An example of a sacrificial gate structure is sacrificial gate structure 118 of Figure 3. At step 2708, method 2700 includes performing a plasma etching process on the integrated circuit after forming the sacrificial gate structure. At step 2710, method 2700 includes performing a wet etching process on the integrated circuit after performing a plasma etching process. At step 2712, method 2700 includes forming a gate spacer layer on the sidewall of the sacrificial gate layer after performing the wet etching process. An example of a gate spacer layer is gate spacer layer 126 / gate spacer layer 127 of Figure 11.

[0092] Figure 28 is a flowchart of a method 2800 for forming an integrated circuit according to some embodiments. Method 2800 may utilize the structures, processes, and systems described in conjunction with other figures. At step 2802, method 2800 includes forming a semiconductor fin on a substrate of a wafer and extending along a first direction. An example of a semiconductor fin is semiconductor fin 108 of Figure 1. An example of a substrate is substrate 102 of Figure 1. At step 2804, method 2800 includes forming a sacrificial gate structure overlying the semiconductor fin and extending in a second direction perpendicular to the first direction. An example of a sacrificial gate structure is sacrificial gate structure 118 of Figure 3. At step 2806, method 2800 includes removing a byproduct layer from the sacrificial gate structure by performing a multi-step etching process including dry etching and wet etching processes. An example of a byproduct layer is byproduct layer 119 of Figure 3. At step 2808, method 2800 includes forming a plurality of channels of a transistor from a semiconductor fin after a multi-step etching process. An example of a channel is channel 105 in Figure 11. At step 2810, method 2800 includes forming a plurality of sacrificial dielectric nanostructures between the channels. An example of a sacrificial dielectric nanostructure is sacrificial dielectric nanostructure 133 in Figure 14. At step 2812, method 2800 includes replacing the sacrificial gate structure and the sacrificial dielectric nanostructure with a gate metal of the transistor. An example of a gate metal is gate metal 152 in Figure 22.

[0093] The embodiments disclosed herein provide a method for forming a transistor that improves transistor characteristics. A plurality of semiconductor fins are formed on a substrate extending in a first direction. A plurality of sacrificial gate structures are formed extending in a second direction and overlying the semiconductor fins. Patterning of the sacrificial gate structures results in a byproduct layer covering the sacrificial gate structures within the semiconductor fins. More specifically, thick accumulations of byproducts can be collected at the bottom junction between the semiconductor fins and the sacrificial gate structures. The embodiments disclosed herein advantageously utilize a multi-step etching process including a combination of dry and wet etching to effectively remove the byproduct layer and thick accumulations. Furthermore, sacrificial dielectric nanostructures are used to release the gate-encircling transistor channel formed with the fins. The result of these processes is the maintenance of a uniform channel thickness, and the gate metal does not contain protrusions that pose a risk of leakage or short circuit to the source / drain regions. Transistor performance is significantly improved, and wafer yield is also significantly increased. More specifically, channel resistance is reduced, and the AC / DC performance of the transistor is improved.

[0094] In some embodiments, a method includes forming a semiconductor fin on a substrate of an integrated circuit and depositing a sacrificial gate layer over the substrate and the semiconductor fin. The method includes forming a sacrificial gate on the semiconductor fin from the sacrificial gate layer by patterning the sacrificial gate layer and performing a plasma etching process on the integrated circuit after forming the sacrificial gate structure. The method includes performing a wet etching process on the integrated circuit after performing the plasma etching process, and forming a gate spacer layer on the sidewalls of the sacrificial gate layer after performing the wet etching process.

[0095] In some embodiments, a method includes forming a semiconductor fin on a substrate of a wafer and extending in a first direction, and forming a sacrificial gate structure overlying the semiconductor fin and extending in a second direction perpendicular to the first direction. The method includes removing a byproduct layer from the sacrificial gate structure by performing a multi-step etching process including dry and wet etching processes, and forming a plurality of channels of a transistor from the semiconductor fin after the multi-step etching process. The method includes forming a plurality of sacrificial dielectric nanostructures between the channels and replacing the sacrificial gate structure and the sacrificial dielectric nanostructures with gate metal of the transistor.

[0096] In some embodiments, the device includes a substrate and a transistor. The transistor includes a plurality of stacked channels on the substrate, an internal spacer between the bottom channel of the stacked channels and the substrate, a gate spacer layer, and a gate dielectric layer that contacts the internal spacer layer and the gate spacer layer at the interface between the gate spacer layer and the internal spacer layer. The transistor includes a gate metal surrounding the channels and in contact with the gate dielectric between the substrate and the bottom channel. The internal spacer layer is bent at the interface at an angle between 150 degrees and 180 degrees in a lateral plane.

[0097] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0098] 2: Cutting line 7: Cutting line 8: Cutting line 9: Cutting line 22: Cutting line 100: Integrated circuits 101: Replacement for integrated circuits, integrated circuits 102:Substrate 103: Semiconductor stacking, stacking 104: Semiconductor layer 105: Channel 106: Sacrificial semiconductor layer, semiconductor layer 107: Sacrificial Semiconductor Nanostructures 108: Semiconductor fins, fins 109: Dielectric layer 110: Trench 112: Shallow trench isolation zone, trench isolation zone 114: Sacrificial Gate Layer 118: Sacrificial gate structure 119: By-product layer 120: Byproduct accumulation 126, 127: Gate spacer layer, spacer layer 130: Source / Drain trench, trench 131: Dielectric layer 132: Stacking 133: Sacrificial dielectric nanostructures, dielectric nanostructures 134: Groove 135: Dielectric layer 136: Internal spacers 137: Semiconductor Structure 140: Source / Drain Region 141: Bottom semiconductor layer 144: CESL layer, CESL, dielectric layer 146: Dielectric layer 148: Gap 149: Gap 150: High-K dielectric layer, high-K gate dielectric layer 152: Gate metal 153: Highlight 154: Transistor 156: Primary oxide layer 170: Plasma Etching Tools 171: Wet Etching Tools 172: Wafer 173: Semiconductor Process Chamber 174: Top Electrode 175: Bottom Electrode 176: Radio Frequency Power Supply 177: Control System 178: Plasma Zone 179: Anode glow region 180: Cathode glow region 182: Wafer support 183: Internal Etching Chamber 184: Etching tank 185: Etching Equipment 200, 201: Chart 202, 203, 204, 205: Curves 2700: Method 2702, 2704, 2706, 2708, 2710, 2712: Steps 2800: Method 2802, 2804, 2806, 2808, 2810, 2812: Steps D1, D2: Dimensions D3, D4: Thickness, Thickness Dimensions D5: Distance D6, D7, D8, D9, D10, D11, D12: Dimensions X, Y: Axis, Direction ϴ100, ϴ101: Angles

[0099] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming an integrated circuit device, the method comprising the steps of: forming a semiconductor fin on a substrate of the integrated circuit; depositing a sacrificial gate layer on the substrate and the semiconductor fin; forming a sacrificial gate structure on the semiconductor fin by patterning the sacrificial gate layer from the sacrificial gate layer; performing a plasma etching process on the integrated circuit after forming the sacrificial gate structure; performing a wet etching process on the integrated circuit after performing the plasma etching process to remove a secondary product layer from the sacrificial gate structure; forming a gate spacer layer on a sidewall of the sacrificial gate layer after performing the wet etching process; forming a plurality of stacked channels of a transistor from the semiconductor fin; and vertically forming an internal spacer between the substrate and the bottom channel of the stacked channels, wherein the internal spacer bends at an angle between 150 degrees and 180 degrees in a lateral plane at an interface between the gate spacer layer and the internal spacer.

2. The method as described in claim 1, wherein patterning the sacrificial gate layer results in the formation of the byproduct layer on a plurality of sidewalls of the sacrificial gate layer, a plurality of sidewalls of the semiconductor fin, and a trench isolation region adjacent to the semiconductor fin and the sacrificial gate structure.

3. The method as described in claim 2, wherein the step of performing the plasma etching process includes the following steps: at least partially removing a byproduct accumulation at a corner where the semiconductor fin, the sacrificial gate structure, and the trench isolation region intersect.

4. The method as described in claim 1 further comprises the following steps: after forming the gate spacer layer, forming a source / drain region of the transistor in the semiconductor fin; after forming the source / drain region, removing the sacrificial gate structure; and after removing the sacrificial gate structure, forming a gate metal of the transistor by forming a gate metal in place of the sacrificial gate structure.

5. A method for forming an integrated circuit device, the method comprising the steps of: forming a semiconductor fin on a substrate of a wafer and extending in a first direction; forming a sacrificial gate structure covering the semiconductor fin and extending in a second direction perpendicular to the first direction; removing a secondary product layer from the sacrificial gate structure by performing a multi-step etching process including a dry etching process and a wet etching process; forming a plurality of channels of a transistor from the semiconductor fin after the multi-step etching process; forming a plurality of sacrificial dielectric nanostructures between the channels; forming a gate spacer layer on a sidewall of the sacrificial gate structure; vertically forming an internal spacer between the substrate and the bottom channel of the channels, wherein the internal spacer bends at an angle between 150 degrees and 180 degrees in a lateral plane at an interface between the gate spacer layer and the internal spacer; and replacing the sacrificial gate structure and the sacrificial dielectric nanostructures with a gate metal of the transistor.

6. The method as described in claim 5, wherein the steps of performing the multi-step etching process include the following steps: after forming the sacrificial gate structure, transferring the wafer to a dry etching tool; and after transferring the wafer to the dry etching tool, transferring the wafer to a wet etching tool.

7. The method as described in claim 6, further comprising performing a plasma etching process on the wafer using the dry etching tool, comprising the steps of: allowing HF or NH3 to flow as an etching gas; and allowing a passivation gas including N2, O2, or CO2 to flow together with the etching gas.

8. An integrated circuit device comprising: a substrate; A transistor, comprising: A plurality of stacked channels on the substrate; an internal spacer between the bottom channel of one of the stacked channels and the substrate; A gate spacer layer; a gate dielectric layer at an interface between the gate spacer layer and the inner spacer and in contact with the inner spacer and the gate spacer layer; and a gate metal covering the stacked channels and in contact with the gate dielectric layer between the substrate and the bottom channel, wherein the inner spacer is bent at the interface at an angle between 150 degrees and 180 degrees in a lateral plane.

9. The apparatus as claimed in claim 8, wherein each of the stacked channels has a substantially uniform vertical thickness.

10. The apparatus of claim 8, wherein a distance between the gate dielectric layer and a source / drain region at the junction is greater than 5 nm.

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