Semiconductor package and methods for forming the same
Patent Information
- Application Number
- TW114116695
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2025-03-14
- Filing Date
- 2025-05-05
- Publication Date
- 2026-10-11
- Estimated Expiration
- 2045-05-04
Smart Images

Figure TWG2TB001915436_001 
Figure TWG2TB001915436_002 
Figure TWG2TB001915436_003
Abstract
Claims
1. A semiconductor package, comprising: Packaging substrate; A packaging structure, comprising at least one semiconductor die mounted to the packaging substrate; The cover layer includes: a sidewall portion attached to the packaging substrate and laterally surrounding the packaging structure; a central portion contacting the upper surface of the packaging structure; and a plurality of connecting arms extending between the sidewall portion and the central portion of the cover layer, wherein: the central portion of the cover layer is vertically recessed from the upper portion of the sidewall portion, the plurality of connecting arms are attached to the upper portion, and at least one of the plurality of connecting arms extends in an obliquely vertically downward direction between the sidewall portion and the central portion of the cover layer, wherein the plurality of connecting arms extends in an obliquely vertically downward direction between the sidewall portion and the central portion of the cover layer, and each of the plurality of connecting arms extending in the obliquely vertically downward direction includes a first end connected to the sidewall portion and a second end connected to the central portion, and the line segment between the first end and the second end of each of the plurality of connecting arms extending in the obliquely vertically downward direction has an angle between -5° and -25° relative to a horizontal plane.
2. The semiconductor package of claim 1, further comprising a thermal interface material located between the upper surface of the package structure and the central portion of the capping layer, wherein the thermal interface material comprises at least one of graphite and metal.
3. The semiconductor package of claim 1, wherein the package structure includes a plurality of semiconductor dies surrounded by a molding portion, wherein the upper surface of the package structure is formed by the plurality of semiconductor dies and the upper surface of the molding portion.
4. The semiconductor package as claimed in claim 3, wherein the central portion of the capping layer is located above a first group of semiconductor chips of the plurality of semiconductor chips and not above a second group of semiconductor chips of the plurality of semiconductor chips.
5. The semiconductor package as claimed in claim 1, wherein the capping layer includes an open region between adjacent connecting arms.
6. The semiconductor package of claim 1, wherein the central portion of the capping layer includes a cutout region in which the central portion of the capping layer does not cover the underlying package structure, and the plurality of connecting arms extend in pairs from the sidewall portions to opposite sides of each cutout region.
7. A capping layer for a semiconductor package, comprising: Side wall portion; The central portion located inside the sidewall portion; And a plurality of connecting arms extend between the sidewall portion and the central portion of the cover layer, wherein each of the plurality of connecting arms includes a first end connected to the sidewall portion and a second end connected to the central portion, and the line segment extending between the first end and the second end of each of the plurality of connecting arms has an angle between -5° and -25° relative to the horizontal plane.
8. The cover as claimed in claim 7, wherein each of the plurality of connecting arms includes a straight arm extending between the sidewall portion and the central portion.
9. A method for manufacturing a semiconductor package, comprising: A packaging structure comprising at least one semiconductor die is mounted onto a packaging substrate; The cover layer is attached to the package substrate, wherein the cover layer includes a sidewall portion that laterally surrounds the package structure, a central portion that contacts the upper surface of the package structure, and a plurality of connecting arms that extend in an inclined vertically downward direction between the sidewall portion and the central portion of the cover layer, wherein each of the plurality of connecting arms includes a first end connected to the sidewall portion and a second end connected to the central portion, and a line segment extending between the first end and the second end of each of the connecting arms has an angle between -5° and -25° relative to a horizontal plane.
10. The method as described in claim 9, further comprising: A thermal interface material is provided above the upper surface of the package structure, wherein the capping layer is attached to the package substrate such that the thermal interface material is located between the upper surface of the package structure and the central portion of the capping layer.
Citation Information
Patent Citations
Semiconductor package and method for manufacturing the same
CN107507823A
Package structure and forming method thereof
CN113451285A
