Package substrate and fabricating method thereof

Abstract

An encapsulation substrate is formed on wiring layers on opposite sides of a glass plate, with the glass plate serving as the core layer. By utilizing its high rigidity and low coefficient of thermal expansion, the encapsulation substrate can be effectively prevented from warping during large-size manufacturing processes.

Claims

1. A packaging substrate, comprising: A glass plate having two opposing surfaces and a plurality of conductive vias penetrating the two opposing surfaces of the glass plate; two wiring layers formed on the two opposing surfaces of the glass plate and electrically connected to the plurality of conductive vias; a first reinforcement structure disposed on one of the surfaces of the glass plate and electrically connected to the wiring layers; and a second reinforcement structure disposed on the other opposing surface of the glass plate and electrically connected to the wiring layers.

2. The packaging substrate as described in claim 1, wherein, The first add-in structure includes at least one insulating layer and a first wiring layer that is bonded to the insulating layer and electrically connected to the wiring layer.

3. The packaging substrate as described in claim 2, wherein, The material forming the insulating layer is selected from Ajinomoto laminate (ABF) or prepreg (PP).

4. The packaging substrate as described in claim 2, wherein, The second layer structure has at least one dielectric layer and a second wiring layer that is bonded to the dielectric layer and electrically connected to the wiring layer.

5. The packaging substrate as described in claim 4, wherein, The material used to form the dielectric layer is selected from polyimide (PI) or photosensitive polyimide (PSPI).

6. The packaging substrate as described in claim 4, wherein, The coefficient of thermal expansion of the insulating layer is less than that of the dielectric layer.

7. The packaging substrate as described in claim 1, wherein, The second layer structure is a circuit redistribution layer specification, which forms a bump-under metal layer directly on its surface.

8. The packaging substrate as described in claim 7, wherein, The thickness of the second layer is less than the thickness of the first layer.

9. The packaging substrate as described in claim 7, wherein, The linewidth / spacing of the second add-on structure is less than or equal to 5 micrometers.

10. A method for manufacturing a packaging substrate, comprising: A plurality of glass plates are provided, each having two opposing surfaces and a plurality of conductive through-holes directly penetrating the opposing surfaces of the glass plates. Two wiring layers electrically connected to the plurality of conductive through-holes are formed on the opposing surfaces of the glass plates. The glass plates are respectively attached to opposite sides of a carrier. A first reinforcement structure electrically connected to the wiring layers is formed on one surface of the glass plates. The carrier is removed. A second reinforcement structure electrically connected to the wiring layers is formed on the other opposing surface of the glass plates.

11. The method for manufacturing the packaging substrate as described in claim 10, wherein, The first add-in structure includes at least one insulating layer and a first wiring layer that is bonded to the insulating layer and electrically connected to the wiring layer.

12. The method for manufacturing the packaging substrate as described in claim 11, wherein, The material forming the insulating layer is selected from Ajinomoto laminate (ABF) or prepreg (PP).

13. The method for manufacturing the packaging substrate as described in claim 11, wherein, The second layer structure has at least one dielectric layer and a second wiring layer that is bonded to the dielectric layer and electrically connected to the wiring layer.

14. The method for manufacturing the packaging substrate as described in claim 13, wherein, The material used to form the dielectric layer is selected from polyimide (PI) or photosensitive polyimide (PSPI).

15. The method for manufacturing the packaging substrate as described in claim 13, wherein, The coefficient of thermal expansion of the insulating layer is less than that of the dielectric layer.

16. The method for manufacturing the packaging substrate as described in claim 10, wherein, The second layer structure employs a circuit redistribution process to directly form a bump under-metal layer on its surface.

17. The method for manufacturing the packaging substrate as described in claim 16, wherein, The thickness of the second layer is less than the thickness of the first layer.

18. The method for manufacturing the packaging substrate as described in claim 16, wherein, The linewidth / spacing of the second add-on structure is less than or equal to 5 micrometers.

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