Methods of forming semiconductor device

Abstract

A method includes forming a source / drain region, forming a contact etch stop layer over the source / drain region, forming an interlayer dielectric layer over the contact etch stop layer, forming a first contact plug in the interlayer dielectric layer and the contact etch stop layer, and performing an etching process to form a trench in the interlayer dielectric layer and the contact etch stop layer. The source / drain region and the first contact plug are exposed in the trench. The method further includes performing a silicon formation process to form a silicon region on the surface of the source / drain region, and etching a metal layer deposited on the dielectric region and in the trench. The dielectric region is exposed when the silicon formation process begins. A second contact plug is formed in the trench.

Description

Technical Field

[0001] none. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various parts are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various parts may be arbitrarily increased or decreased. Figures 1A and 1B are views of intermediate stages of the formation of complementary field-effect transistors and silicon regions according to some embodiments. Figures 2 through 14 are views of intermediate stages of the formation of complementary field-effect transistors and silicon regions according to some embodiments. Figures 15 to 19 are views of intermediate stages of the formation of complementary field-effect transistors and silicon regions according to some embodiments. Figures 20 and 21 show the zeta potentials of TiO2 and WO3 according to some embodiments. Figure 22 shows the distribution profile of an element in the passivation layer according to some embodiments. Figure 23 shows a flowchart of forming complementary field-effect transistors and silicon regions according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, this document uses spatial relative terms such as "below," "under," "lower part," "above," and "upper part" to describe the relationship between one element or feature and another, as shown in the figure. Spatial relative terms are intended to cover different orientations of the device in use or operation besides those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive symbols used herein can be interpreted accordingly.

[0008] This disclosure provides complementary field-effect transistors (CFETs), silicide regions, contact plugs, and methods for forming the same. According to some embodiments of this disclosure, silicide regions are formed by depositing metal, while the metal reacts with an epitaxial semiconductor to form the silicide regions. A dry etching process can be performed to remove unwanted metal deposits on the dielectric region surface. A nitriding process is then performed to form a metal nitride layer on the silicide regions, resulting in the formation of a metal nitride layer on the exposed metal regions. The metal nitride layer can then be removed using a wet etching process.

[0009] It should be understood that while CFETs (e.g., nanostructured transistors) including all-gate-ring field-effect transistors (GAA) have been discussed, the concepts disclosed herein can also be applied to forming contact plugs connected to other types of transistors (e.g., planar transistors, fin field-effect transistors (FinFETs), etc.). Throughout the description, the terms "FET" and "transistor" may be used interchangeably.

[0010] The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0011] Figures 1A and 1B, and Figures 2 through 14, show cross-sectional views of intermediate stages in the formation of complementary field-effect transistors and silicon regions according to some embodiments of this disclosure. The corresponding processes are also schematically illustrated in the process flow shown in Figure 23.

[0012] Figure 1A illustrates the formation of an exemplary C-transistor 10 (including transistors 10U and 10L) according to some embodiments. As shown in Figure 23, the corresponding process is illustrated as process 202 in process 200. The C-transistor 10 may include a lower nanostructure transistor 10L of a first element type (e.g., n-type / p-type) and an upper nanostructure transistor 10U of a second element type (e.g., p-type / n-type), opposite to the first element type. The nanostructure transistors 10U and 10L include semiconductor nanostructures 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' acts as a channel region of the nanostructure transistor. The lower semiconductor nanostructure 26'L is used for the lower nanostructure transistor 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure transistor 10U.

[0013] As shown in Figure 1A, a wafer 2 including a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., using p-type or n-type dopants) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, etc. The insulating layer is disposed on the substrate, such as a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0014] In the illustrated example, the upper transistor 10U and the lower transistor 10L each include two semiconductor layers 26'U and 26'L as channels. It should be understood that the upper transistor 10U and the lower transistor 10L may include any number of channel regions, such as 1, 2, 3, or more. The portion of the gate stack 90 located above and / or below the channel regions 26 forms a multilayer stack with the corresponding channel regions 26'U and 26'L.

[0015] Gate stacks 90 (including upper gate stack 90U and lower gate stack 90L) are formed between semiconductor layers 26. The upper gate stack 90U includes a gate dielectric 78 and an upper gate electrode 80U. The lower gate stack 90L includes a gate dielectric 78 and a lower gate electrode 80L. The gate dielectric 78 surrounds (in side view) the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including lower gate electrode 80L and upper gate electrode 80U) are located above the gate dielectric 78. A dielectric isolation layer 56 is formed to isolate the gate stack 90U of the upper transistor 10U from the gate stack 90L of the lower transistor 10L. A dummy semiconductor layer 26'M may be formed to contact the dielectric isolation layer 56.

[0016] The source / drain region 62 (including the lower source / drain region 62L and the upper source / drain region 62U) is located on the opposite side of the gate dielectric 78 and the corresponding gate electrode 80. The source / drain region may refer to the source or drain individually or collectively, depending on the context.

[0017] Internal spacers 54 are dielectric spacers formed on opposite sides of portions of the gate stack 90 located between semiconductor layers 26. Internal spacers 54 electrically insulate the source / drain regions 62L and 62U from corresponding portions of the gate stack 90 to prevent and reduce leakage.

[0018] Gate spacers 44 are formed over the multilayer stack and on the sidewalls of the gate stack 90. ​​Gate spacers 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0019] Source / drain regions 62L and 62U are laterally formed between a multilayer stack including channel region 26 and gate stack 90. ​​A lower source / drain region 62L is formed above and in contact with a substrate, which includes semiconductor substrate 20. The lower source / drain region 62L is also in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U.

[0020] The lower source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure transistor. When the lower source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon, doped with n-type dopants such as phosphorus or arsenic. When the lower source / drain region 62L is a p-type source / drain region, its material can include silicon or silicon-germanium, doped with p-type dopants such as boron or indium. The lower source / drain region 62L can be in-situ doped, with or without implantation of the corresponding p-type or n-type dopants.

[0021] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower source / drain region 62L. Suitable dielectric materials for the first ILD 68 may include phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), undoped silicate glass (USG), silicon oxide, etc. The first CESL 66 may be formed from a dielectric material with high etch selectivity relative to the first ILD 68. For example, the first CESL 66 may include silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed through any suitable deposition process, such as CVD, ALD, etc.

[0022] The upper source / drain region 62U is formed to overlap with the first CESL66 and the first ILD68, and also overlaps with the lower source / drain region 62L. The material of the upper source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the required conductivity type of the upper source / drain region 62U.

[0023] The conductivity type of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. In other words, the upper source / drain region 62U can be doped in the opposite way to the lower source / drain region 62L. The upper source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants.

[0024] The second CESL70 and the second ILD72 are formed above the upper source / drain region 62U. This material may be similar to, the same as, or different from the material and formation method of the first CESL66 and the first ILD68, which will not be discussed in detail here.

[0025] Figure 1B shows a cross-sectional view of the structure shown in Figure 1A. The illustrated cross-section can be cross-section 1B-1B as shown in Figure 1A. Dielectric isolation region 32 (sometimes also called shallow trench isolation (STI) region 32) is formed above substrate 20. Semiconductor strips 20' (also refer to Figure 1A) are formed between STI regions 32. Fin spacers 45 can be formed on the sidewalls at the top of semiconductor strips 20'. Lower source / drain region 62L, first CESL 66, first ILD 68, upper source / drain region 62U, second CESL 70, and second ILD 72 are shown.

[0026] Figure 1B further illustrates the formation of the contact plug 116. According to some embodiments, the formation of the contact plug 116 includes etching the second ILD72, the second CESL70, the first ILD68, and the first CESL66 to form a trench. The trench may extend to an intermediate level between the top and bottom surfaces of the isolation region 32.

[0027] A dielectric pad 114 is formed in the trench. As shown in FIG23, the corresponding process is shown as process 204 in process 200. According to some embodiments, the formation of the dielectric pad 114 includes a deposition process using a conformal deposition method (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.) to form a conformal dielectric layer. According to some embodiments, the material of the dielectric pad 114 may include silicon nitride, metal oxides of metals (e.g., Hf, Ti, Al, W, Nb, Re, etc.), metal nitrides of metals (e.g., Hf, Ti, Al, W, Nb, Re, etc.), or combinations thereof.

[0028] Contact plug 116 is then formed. As shown in FIG23, the corresponding process is shown as process 206 in process 200. Contact plug 116 may also be referred to as a vertical local interconnect. According to some embodiments, contact plug 116 comprises metals such as tungsten, molybdenum, ruthenium, and iridium or alloys thereof. According to some embodiments, contact plug 116 has a single-layer structure, and the entire contact plug 116 is formed of a homogeneous material as described above.

[0029] According to other embodiments, the formation of the contact plug 116 may include depositing a barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Next, a metallic material is deposited on the barrier layer and brought into contact with it. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, etc., or combinations thereof.

[0030] After depositing the material used to form the contact plug 116, a planarization process (e.g., CMP or mechanical polishing) is performed to remove excess material and leave the contact plug 116. The contact plug 116 is thus surrounded by a dielectric pad 114. Therefore, the top surfaces of the contact plug 116 and the dielectric pad 114 are coplanar, and when the second ILD 72 is the top layer in the structure, it can also be coplanar with the top surface of the second ILD 72.

[0031] As shown in Figure 1B, an etch stop layer (ESL) 118 is formed. As shown in Figure 23, the corresponding process is shown as process 208 in process 200. The etch stop layer 118 may include AlN, AlO, SiOC, or multiple layers thereof. A dielectric layer 120 is deposited over the etch stop layer 118. As shown in Figure 23, the corresponding process is shown as process 210 in process 200. The dielectric layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. A patterned etch mask 121, which may include photoresist, is formed on the dielectric layer 120.

[0032] As shown in Figure 2, the etch stop layer 118 and dielectric layer 120 are patterned by etching to form a contact opening (trench) 122, through which the second ILD 72 and contact plug 116 are exposed. As shown in Figure 23, the corresponding process is shown as process 212 in process 200. The contact opening 122 is formed by an etching process. In the etching process, the underlying second ILD 72, second CESL 70, contact plug 116, and dielectric pad 114 are exposed. The second ILD 72 and second CESL 70 are etched, exposing the upper source / drain region 62U. The etching stops at the top surface of the upper epitaxial source / drain region 62U. The dielectric pad 114 and contact plug 116 are also exposed. The patterned etch mask 121 is then removed (Figure 1B).

[0033] Referring to Figure 3, dielectric pad 124 is formed. As shown in Figure 23, the corresponding process is shown as process 214 in process 200. According to some embodiments, the formation of dielectric pad 124 includes depositing a conformal layer through a conformal deposition process (e.g., through ALD, CVD, PVD, etc.). Then, an anisotropic etching process is performed to remove the horizontal portion of the conformal layer, leaving the vertical portion as dielectric pad 124. In the anisotropic etching process, the exposed portion of dielectric pad 124 may also be recessed.

[0034] The material of dielectric pad 124 may be selected from the same set of candidate materials used to form dielectric pad 114, and may be the same as or different from the material of dielectric pad 114. For example, dielectric pad 124 may be formed of and / or include silicon nitride.

[0035] A vacuum destruction process can be performed to transfer the corresponding wafer 2 for subsequent formation of silicon regions. As shown in Figure 23, the corresponding process is shown as process 216 in process 200. Figure 4 shows the formation of a silicon oxide layer 126 on the exposed surface of the upper source / drain region 62U due to oxidation. A metal oxide layer 128 is also formed on the exposed surface of the contact plug 116 due to oxidation of the surface layer of the contact plug 116. Therefore, the metal oxide layer 128 comprises an oxide of the metal of the contact plug 116. For example, when the contact plug 116 comprises tungsten, the metal oxide layer 128 comprises tungsten oxide (including WO3).

[0036] A pre-cleaning process can be performed, for example, using a mixture of HF and NH3 gases. This removes the silicon oxide layer 126 and exposes the underlying upper source / drain region 62U. On the other hand, the metal oxide layer 128 may not be removed by the pre-cleaning process.

[0037] Referring to Figure 5, a silicate region (layer) 130 is formed. As shown in Figure 23, the corresponding process is shown as process 218 in process 200. According to some embodiments, the formation of the silicate region 130 may include introducing a process gas containing a metal precursor into a corresponding reaction chamber. The metal in the metal precursor is deposited on the upper source / drain region 62U and reacts with a portion of the surface of the upper source / drain region 62U to form the silicate region 130.

[0038] According to some embodiments, the metal-containing precursor is a titanium-containing precursor, such as TiCl4, titanium tetraisopropoxide (Ti[OCH(CH3)2]4(TTIP), titanium tetra(dimethylamino) (Ti[N(CH3)2]4(TDMAT)), etc. Therefore, according to some embodiments, the silicide region 130 may include titanium silicide (TiSi). Hydrogen (H2) may also be introduced into the reaction chamber. According to other embodiments, the metal-containing precursor may include other types of metals, such as V, Zn, Nb, Al, etc.

[0039] The process gas may be free of or substantially free of nitrogen-containing gases, such as N2, NH3, etc. (e.g., flow rate percentage less than 1%). This reaction is carried out with plasma on. For example, the individual wafers 2 can be heated to temperatures ranging from approximately 300˚C to approximately 600˚C. According to some embodiments, no additional annealing process is required after the siliconization process to form the siliconized region 130.

[0040] By using a metal-containing precursor (e.g., TiCl4), the formation of the silicate region 130 can have the effect of etching and removing the metal oxide layer 128.

[0041] According to some embodiments, a metal layer 132 is deposited on the surface of the exposed dielectric material (e.g., dielectric pad 124 and dielectric layer 120) concurrently with the formation of the metal silicate region 130. Therefore, the metal layer 132 comprises the same metal as the silicate region 130. The metal layer 132 may also be deposited on the contact plug 116. For example, the metal layer 132 may comprise titanium (Ti), which may be in the form of an elemental metal (not forming metal compounds with other elements).

[0042] Referring to Figure 6, etching process 134 is performed to selectively etch the metal layer 132 while leaving the silicon region 130 unetched and the subsequently exposed dielectric regions (e.g., dielectric pad 124). As shown in Figure 23, the corresponding process is shown as process 220 in process 200. After etching the metal layer 132, the contact plug 116 is exposed again. According to some embodiments, the selective etching process is performed by immersion using an etching gas comprising metal halides. The resulting structure is shown in Figure 6.

[0043] Metal halides can include titanium chloride (TiCl4), and other metal halides such as nickel halides, molybdenum halides, hafnium halides, tungsten halides, or combinations thereof can also be used. When TiCl4 is used, titanium chloride can react with elemental titanium to produce TiClx gas, where x can be 2, 3, etc. The reaction formula can be Ti(s) + TiCl4(g) -> TgiClx(g), where the letters "s" and "g" represent "solid" and "gas," respectively.

[0044] During etching process 134, no plasma is generated. Radio frequency power may not be applied, or if applied, the power may be insufficient to generate plasma. Additionally, Ar may not be introduced, and hydrogen (H2) may not be introduced. According to some embodiments, etching may be performed while wafer 2 is heated, for example, at a wafer temperature between approximately 300˚C and approximately 600˚C.

[0045] Next, as shown in Figure 7, a nitrogen treatment process 136 (also known as a nitriding process 136) is performed. As shown in Figure 23, the corresponding process is indicated as process 222 in process 200. The nitrogen treatment process 136 is performed simultaneously with the formation of the siliconized region 130 and the etching of the metal layer 132, without interruption of the vacuum. The nitrogen treatment process 136 can be performed using a nitrogen-containing gas (e.g., N2, NH3, etc.) as the process gas. The nitrogen treatment process 136 can be performed using plasma treatment and / or thermal treatment. When thermal treatment is used, the wafer temperature can be in the range of approximately 300˚C to approximately 600˚C.

[0046] The nitrogen treatment process 136 results in the formation of a metal silicon nitride layer 138 on the silicon region 130 due to the reaction of oxygen with the surface portion of the silicon region 130. The metal silicon nitride layer 138 serves to prevent oxygen from reaching the silicon region 130 during subsequent vacuum destruction. The metal silicon nitride layer 138 comprises the same metal as the silicon region 130. For example, when the silicon region 130 comprises titanium silicon (TiSi), the metal silicon nitride layer 138 comprises TiSiN.

[0047] In the aforementioned process (Figures 5 and 6), the metal layer 132 is removed before the nitrogen treatment process 136. It is understood that if the metal layer 132 is not removed, the nitrogen treatment process 136 will cause the metal layer 132 to transform into a metal nitride layer, such as a titanium nitride layer. Since the etching selectivity between the silicate region 130 and the titanium nitride layer is low, the titanium nitride layer is difficult to remove, and removing the titanium nitride layer may damage the silicate region 130. Therefore, according to the embodiment, the nitrogen treatment process 136 is performed after the removal of the metal layer 132, and the silicate region 130 is formed without nitrogen treatment to avoid the formation of metal nitrides.

[0048] The nitrogen treatment process 136 also results in the formation of a metal nitride layer 140 on the surface of the contact plug 116, as the surface portion of the contact plug 116 is nitrided. For example, when the contact plug 116 comprises tungsten, the metal nitride layer 140 may comprise tungsten nitride (WN).

[0049] Following nitrogen treatment process 136, a vacuum destruction process is performed. As shown in Figure 23, the corresponding process is represented as process 224 in process 200. The resulting structure is shown in Figure 8. The result of vacuum destruction is the formation of a metal oxide layer 142 above the metal silicon nitride layer 138. The metal oxide layer 142 may contain oxides of the same metal as the silicon nitride region 130 and the metal silicon nitride layer 138. For example, when the silicon nitride region 130 contains TiSi, the metal oxide layer 142 may contain TiOx, where the value "x" represents the relative atomic ratio of oxygen to titanium.

[0050] Due to the vacuum destruction process, the surface portion of the metal nitride layer 140 exposed to air is also oxidized, thereby forming a metal oxide layer 144 on the surface of the metal nitride layer 140. Therefore, the metal oxide layer 144 contains the same metal (e.g., tungsten) as the metal nitride layer 140. Thus, the metal oxide layer 144 may contain WOy, where the numerical value "y" represents the relative atomic ratio of oxygen to the metal (e.g., W) in the metal oxide layer 144. In addition to oxygen, the metal oxide layer 144 may also contain a small amount of nitrogen.

[0051] Figure 9 illustrates a selective passivation process 146 according to some embodiments. The corresponding process is shown as process 226 in process 200, as shown in Figure 23. A passivation layer 148 is selectively formed on the metal oxide layer 142, but not on the metal oxide layer 144 and exposed dielectric features (e.g., dielectric pad 124). The selective passivation process 146 can be performed using different zeta (ζ) potentials of the metal (e.g., Ti) in the metal oxide layer 142 and the metal (e.g., W) in the metal oxide layer 144. In the following discussion, it is assumed that the metal oxide layer 142 comprises titanium oxide and the metal oxide layer 144 comprises tungsten oxide.

[0052] Figure 20 shows the variation of the zeta potential of titanium dioxide (TiO2) with the pH of a chemical solution when exposed to it. At lower pH values ​​(acidic), such as in the range of approximately 2 to approximately 6, the zeta potential of titanium dioxide is positive. At higher pH values ​​(alkaline), the zeta potential of titanium dioxide is negative.

[0053] Figure 21 shows the variation of the zeta potential of tungsten oxide (WO3) with the pH of a chemical solution when the tungsten oxide is exposed to the solution. The zeta potential of tungsten oxide is negative at lower pH (acidic) values, for example, in the pH range of approximately 2 to approximately 6. The zeta potential of tungsten oxide is also negative at higher pH (alkaline) values.

[0054] Comparing Figures 20 and 21, it can be seen that when the solution is acidic, for example in the range of about 2 to about 6, there is a sufficient difference between the potential values ​​of titanium dioxide and tungsten oxide, where the potential value of titanium dioxide is positive and the potential value of tungsten oxide is negative. When certain chemicals are added to a chemical solution, these chemicals tend to adhere to surfaces with a positive potential, in this case the surface of titanium dioxide, rather than to surfaces with a negative potential (e.g., tungsten oxide). The adhered chemicals thus form a passivation layer 148 (Figure 10), which is selectively formed on the surface of titanium dioxide, but not on the surface of the metal oxide layer 144 (e.g., tungsten oxide) or on the surface of the exposed dielectric material.

[0055] According to some embodiments, the chemical solution used for selectively forming the passivation layer 148 may include acids such as HCl, H2SO4, and / or similar substances, wherein the pH of the chemical solution is adjusted to a range between about 2 and about 6. The chemical substance used for adhering to the surface of the metal oxide layer 142 (e.g., titanium dioxide) to form the passivation layer 148 may be selected from phosphoric acid, silane coupling agents, polyacrylic acid (molecular formula (C3H4O2)), and combinations thereof.

[0056] According to other embodiments, some fluorine compounds capable of effectively passivating titanium dioxide by forming a protective layer or strong chemical bonds with the titanium dioxide surface can also be used to form the passivation layer 148. Due to differences in surface chemistry and reactivity, these chemicals cannot provide the same passivation effect on WO3.

[0057] The wafer 2 shown in Figure 8 can be immersed in a chemical solution to form a passivation layer 148. The immersion process can last from about 10 seconds to about 600 seconds.

[0058] Depending on the chemical substances in the chemical solution, the passivation layer 148 may contain elements selected from a group consisting of phosphorus, carbon, fluorine, sulfur, and / or the like. Elements in the passivation layer 148 may (or may not) diffuse into the underlying metal oxide layer 142 and metal silicon nitride layer 138.

[0059] An etching process is then performed to remove the metal oxide layer 144 and the metal nitride layer 140. As shown in Figure 23, the corresponding process is shown as process 228 in process 200. The resulting structure is shown in Figure 10. According to some embodiments, the etching process can be performed via a wet etching process. The wet etching process can be performed using a mixture of ozonated deionized water (deionized water, DiO3) and hot deionized water. The temperature of the hot deionized water can be in the range of about room temperature (e.g., about 25˚C) to about 80˚C. The metal oxide layer 144 is soluble in the hot deionized water, and its pH value can be in the range of about 5.5 to 6.9. Therefore, the metal oxide layer 144 is removed first, exposing the metal nitride layer 140.

[0060] DiO3 has the function of oxidizing the metal silicon nitride layer 140 into a metal oxide. For example, tungsten nitride in the metal silicon nitride layer 140 can be oxidized into tungsten oxide (WO3), which is soluble in hot deionized water. Therefore, by using a mixture of DiO3 and hot deionized (DI) water, both the metal oxide layer 144 and the metal nitride layer 140 are removed.

[0061] According to some embodiments, after removing the metal oxide layer 144 and the metal nitride layer 140 through a wet etching process, the passivation layer 148 is removed. As shown in FIG23, the corresponding process is indicated as process 230 in process 200. The final structure is shown in FIG11. The removal of the passivation layer 148 can be achieved by rinsing with deionized water, followed by dissolving and removing the passivation layer with an organic solvent (e.g., ethanol, isopropanol, acetone, etc.).

[0062] The metal oxide layer 142 (e.g., titanium dioxide layer) is then removed. The resulting structure is shown in Figure 12. As shown in Figure 23, the corresponding process is shown as process 232 in process 200. According to some embodiments, plasma generated by a mixture of N2 and H2 can be used to remove the titanium dioxide. This exposes the metal silicon nitride layer 138 (e.g., TiSiN).

[0063] Next, referring to Figure 13, contact plug 150 is formed. Contact plug 150 may be referred to as upper source / drain contact plug. As shown in Figure 23, the corresponding process is shown as process 234 in process 200. According to some embodiments, contact plug 150 comprises metals such as tungsten, molybdenum, ruthenium, and iridium, or alloys thereof. According to some embodiments, contact plug 150 has a single-layer structure, and the entire contact plug 150 is formed of a homogeneous material as described above.

[0064] Referring further to Figure 13, after depositing the material used to form the contact plug 150, a planarization process (e.g., CMP or mechanical polishing) is performed to remove excess material, leaving the contact plug 150. The contact plug 150 is surrounded by a dielectric pad 124. Therefore, the top surfaces of the contact plug 150 and the dielectric pad 124 are coplanar, and may further be coplanar with the top surface of the dielectric layer 120.

[0065] Figure 14 shows the formation of a conductive feature on the back side, which is electrically connected to the lower source / drain region 62L and the contact plug 116. As shown in Figure 23, the corresponding process is shown as process 236 in process 200. According to some embodiments, a thinning process (e.g., through a CMP process and / or an etching process) is performed to remove the substrate 20, thereby exposing the contact plug 116.

[0066] A semiconductor strip 20' (FIG. 13) is etched to form a back opening, through which the bottom of the lower source / drain region 62L is exposed. A silicate region 158 is formed below the lower source / drain region 62L and contacts its bottom surface. A back contact plug 160 is formed to fill the remaining back contact opening. The back contact plug 160 contacts the silicate region 158. The back contact plug 160 may be formed of a homogeneous metallic material, which may include tungsten, cobalt, ruthenium, etc. A dielectric pad may or may not be formed around the back contact plug 160.

[0067] Then, a dielectric layer 164 is deposited. A back redistribution line 162 (conductive feature 162) is formed on the back side of the complementary field-effect transistor and in the dielectric layer 164. The back redistribution line 162 is electrically connected to the contact plug 116 and the lower source / drain region 62L.

[0068] Figure 22 shows the elemental distribution in passivation layer 148 according to some embodiments. This element may include elements in passivation layer 148, selected from the group consisting of carbon, fluorine, phosphorus, and combinations thereof. Although passivation layer 148 and the underlying metal oxide layer 142 (Figure 10) are removed in subsequent processes, elements in passivation layer 148 may diffuse into metal silicon nitride layer 138 and silicon region 130, and may diffuse into upper semiconductor region 62U. Moreover, because elements diffuse from metal silicon nitride layer 138 after removal of passivation layer 148 and the underlying metal oxide layer 142, the distribution in contact plug 150 has a more abrupt drop and lower concentration than the distribution in metal silicon nitride layer 138, silicon region 130, and upper source / drain region 62U. The peak of the device may be located at the interface between metal silicon nitride layer 138 and contact plug 150.

[0069] Figures 15 to 19 show cross-sectional views of intermediate stages in the formation of a complementary field-effect transistor according to an alternative embodiment of the present disclosure. According to these embodiments, the metal oxide layer 144 and the metal silicon nitride layer 140 are removed without forming a passivation layer to protect the metal oxide layer 142. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. The details regarding materials, structures, and formation processes provided throughout each embodiment of the specification can be applied to any other embodiment where applicable.

[0070] The initial steps of these embodiments are essentially the same as those shown in Figures 1A and 1B through 8. The resulting structure is also shown in Figure 15, and is the same as the structure shown in Figure 8.

[0071] A wet etching process was performed to remove the metal oxide layer 144 and the metal silicon nitride layer 140, resulting in the structure shown in Figure 15. The wet etching process can be substantially the same as the wet etching process discussed with reference to Figure 10. For example, a mixture of DiO3 and hot deionized water can be used to perform the wet etching process. Therefore, both the metal oxide layer 144 and the metal nitride layer 140 can be removed.

[0072] In the wet etching process, there is etching selectivity between the etching of the metal oxide layer 144 and the metal nitride layer 140 and the etching of the metal oxide layer 142. The metal oxide layer 142 has a lower etching rate than the metal oxide layer 144 and the metal nitride layer 140; therefore, in the embodiment shown in FIG. 16, the metal oxide layer 142 acts as a protective layer, protecting the underlying silicon nitride layer 138 from damage. Alternatively, in embodiments where the etching rate of the metal oxide layer 142 is not low enough, the embodiment shown in FIG. 10 can be used, and a passivation layer 148 (FIG. 10) can be further formed to provide sufficient protection.

[0073] Figure 17 illustrates the removal of the metal oxide layer 142. The process details are essentially the same as those shown and discussed in Figure 12, and will not be repeated here. Figure 18 illustrates the formation of the contact plug 150. Figure 19 illustrates the formation of the silicon layer 158, the back contact plug 160, the dielectric layer 164, and the conductive feature 162. The details of these processes are discussed with reference to Figures 13 and 14, and will not be repeated here.

[0074] The embodiments disclosed herein have several advantageous features. By removing the metal layer formed in the contact opening, no metal layer residue is converted into metal nitrides during the subsequent nitriding process, which are difficult to remove without damaging the silica. The wet etching process can effectively remove metal oxides and metal nitrides from the contact plug, potentially further reducing contact resistance.

[0075] According to some embodiments of the present disclosure, a method includes: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric on the contact etch stop layer; forming a first contact plug in the interlayer dielectric and the contact etch stop layer; performing an etching process to form a trench in the interlayer dielectric and the contact etch stop layer, wherein the source / drain region and the first contact plug are exposed in the trench; performing a silicon formation process to form a silicon region on the surface of the source / drain region; etching a metal layer deposited in the dielectric region and the trench, wherein the dielectric region is exposed at the start of the silicon formation process; and forming a second contact plug in the trench.

[0076] In one embodiment, the metal layer is etched in a plasma-free and hydrogen-free (H2-free) environment. In one embodiment, titanium chloride (TiCl4) is used as the process gas for both the silicate formation process and the etching of the metal layer, and hydrogen (H2) is used during the silicate formation process. In one embodiment, the method further includes: performing a nitrogen treatment process after the silicate formation process to form a metal nitride layer over the silicate region, wherein the metal nitride layer is formed on the first contact plug; and performing a wet etching process to remove the metal nitride layer. In one embodiment, the method further includes performing a vacuum destruction process to form a metal oxide layer over the metal nitride layer, wherein the metal oxide layer is also removed by a wet etching process.

[0077] In one embodiment, a chemical solution comprising ozonated deionized water and hot deionized water is used to perform a wet etching process. In one embodiment, the method further includes selectively forming a passivation layer over the silicate region and removing a metal compound layer from the first contact plug, wherein the metal compound layer is selected from metal nitride layers, metal oxide layers, and combinations thereof, wherein the passivation layer is located over the silicate region when the metal compound layer is removed.

[0078] In one embodiment, a passivation layer is formed by immersing a wafer comprising a siliconized region in a chemical solution, wherein chemicals in the chemical solution adhere to the siliconized region to form the passivation layer. In one embodiment, the pH of the chemical solution is in the range of about 2 to about 6. In one embodiment, after removing the metal compound layer, the process further includes: removing the passivation layer, wherein a second contact plug is formed after removing the passivation layer.

[0079] According to some embodiments of this disclosure, a method includes forming a lower source / drain region; forming a first contact etch stop layer above the lower source / drain region; forming a first interlayer dielectric on the first contact etch stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch stop layer above the upper source / drain region; forming a second interlayer dielectric on the second contact etch stop layer; forming a first contact plug with its top surface higher than the upper source / drain region and its bottom surface lower than the lower source / drain region; and performing an etching process to form contact openings in the second interlayer dielectric and the second contact etch stop layer, wherein the first contact plug is exposed in the contact openings.

[0080] In one embodiment, the method further includes forming a dielectric pad in the contact opening; forming and contacting a silicon region over and with the upper source / drain region, wherein a metal layer is simultaneously formed on the dielectric pad; performing a first etching process to remove the metal layer; performing a nitriding process to form a metal silicon nitride layer over the silicon region and a metal nitride layer over the first contact plug; performing a second etching process to etch the metal nitride layer and expose the first contact plug; and forming a second contact plug in the contact opening.

[0081] In one embodiment, the second etching process includes a wet etching process. In one embodiment, prior to the second etching process, the process further includes forming a passivation layer to protect the metal silicon nitride layer during etching of the metal nitride layer. In one embodiment, the metal silicon nitride layer is selectively formed by immersing it in a chemical solution to allow chemicals in the chemical solution to adhere to the metal silicon nitride layer.

[0082] In one embodiment, a passivation layer is selectively formed using the zeta potential difference between a metal nitride layer and a metal nitride layer. In one embodiment, the chemical solution comprises a chemical substance selected from phosphoric acid, silane coupling agents, polyacrylic acid, and combinations thereof.

[0083] According to some embodiments of the present disclosure, a method includes forming a silicon-containing region; forming a silicate region over the silicon-containing region; forming a metal nitride layer over the silicate region; and forming a metal feature on the metal nitride layer, wherein, after forming the metal feature, the metal nitride layer, and the silicate region contain an element selected from phosphorus, carbon, sulfur, fluorine, and combinations thereof.

[0084] In one embodiment, the element has a peak concentration at the interface between the metal silicon nitride layer and the metal feature. In one embodiment, prior to forming the metal feature, the method further includes: forming a passivation layer over the metal silicon nitride layer; performing an etching process to remove the metal nitride layer on an additional metal feature adjacent to the silicide region, wherein the passivation layer protects the metal silicon nitride layer during etching; and removing the passivation layer, wherein the metal feature is formed after the passivation layer is removed. In one embodiment, the silicon-containing region is contained within the source / drain region of the transistor, and wherein the silicide region is the source / drain silicide region of the transistor.

[0085] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the scope of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0086] 2: Wafer 10: Transistor 10U: Transistor 10L: Transistor 20:Substrate 20': Semiconductor strip 26: Channel Region / Semiconductor Layer / Nanostructure 26': Nanostructure 26'L: Nanostructure / Semiconductor Layer 26'U: Nanostructure / Semiconductor Layer 26'M: Semiconductor layer 32: Isolation Zone / STI Zone 44: Gate spacer 45: Fin spacers 54: Spacers 56: Dielectric isolation layer 62: Source / Drain Region 62L: Source / Drain Region (Semiconductor Region) 62U: Source / Drain Region (Semiconductor Region) 66: First CESL / First Contact Etching Stop Layer 68: First ILD 70: Second CESL 72: Second ILD 78: Gate Dielectric 80: Gate electrode 80L: Gate electrode 80U: Gate electrode 90: Gate Stacking 90U: Gate Stack 90L: Gate Stack 114: Dielectric Pad 116: Contact plug 118: Etching Stop Layer 120: Dielectric layer 121: Etching Mask 122: Contact opening (groove) 124: Dielectric Pad 126: Silicon oxide layer 128: Metal oxide layer 130: Silicon region / silicon layer 132: Metal layer 134: Etching Process 136: Nitrogen treatment process / Nitriding process 138: Metal nitride silicon layer 140: Metal nitride layer / Silicon nitride layer 142: Metal oxide layer 144: Metal oxide layer 146: Manufacturing Process 148: Passivation layer 150: Contact plug 158: Silicate Region / Silicide Layer 160: Contact plug 162: Backside redistribution lines (conductive characteristic) 164: Dielectric layer 200: Process 202: Process 204: Process 206: Manufacturing Process 208: Process 210: Manufacturing Process 212: Manufacturing Process 214: Manufacturing Process 216: Manufacturing Process 218: Manufacturing Process 220: Process 222: Manufacturing Process 224: Manufacturing Process 226: Manufacturing Process 228: Manufacturing Process 230: Process 232: Manufacturing Process 234: Manufacturing Process 236: Manufacturing Process 1B-1B: Cross-section

[0087] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: Forming a source / drain region; A contact etch stop layer is formed on the source / drain region; an interlayer dielectric is formed on the contact etch stop layer; a first contact plug is formed in the interlayer dielectric and the contact etch stop layer; an etching process is performed to form a trench in the interlayer dielectric and the contact etch stop layer, wherein the source / drain region and the first contact plug are exposed in the trench; a siliconization process is performed to form a siliconization region on the surface of the source / drain region; a metal layer deposited on a dielectric region and in the trench is etched, wherein the dielectric region is exposed at the start of the siliconization process; and a second contact plug is formed in the trench.

2. The method as described in claim 1, wherein, The metal layer was etched in a plasma-free and hydrogen-free environment.

3. The method as described in claim 1, further comprising: After the silicate formation process, a nitrogen treatment process is performed to form a metal nitride layer over the silicate region, wherein the metal nitride layer is formed on the first contact plug; and a wet etching process is performed to remove the metal nitride layer.

4. The method as described in claim 1, further comprising: A passivation layer is selectively formed on the silicate region; And remove a metal compound layer from the first contact plug, wherein the metal compound layer is selected from a metal nitride layer, a metal oxide layer, or a combination thereof, and wherein, when the metal compound layer is removed, the passivation layer is located above the silicate region.

5. A method of forming a semiconductor device, comprising: Forming a lower source / drain region; A first contact etch stop layer is formed on the lower source / drain region; a first interlayer dielectric is formed on the first contact etch stop layer; an upper source / drain region is formed above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; a second contact etch stop layer is formed above the upper source / drain region; a second interlayer dielectric is formed on the second contact etch stop layer; a first contact plug is formed, wherein one top surface is higher than the upper source / drain region and one bottom surface is lower than the lower source / drain region; an etching process is performed to form a contact opening in the second interlayer dielectric and the second contact etch stop layer, wherein the first contact plug is exposed in the contact opening; a dielectric pad is formed in the contact opening; a silicon region is formed above and in contact with the upper source / drain region, wherein a metal layer is simultaneously formed on the dielectric pad; A first etching process is performed to remove the metal layer; a nitriding process is performed to form a silicon nitride layer over the silicon region and a metal nitride layer over the first contact plug; a second etching process is performed to etch the metal nitride layer and expose the first contact plug; and a second contact plug is formed in the contact opening.

6. The method as described in claim 5, wherein the second etching process includes a wet etching process.

7. The method as described in claim 6 further includes: Prior to the second etching process, a passivation layer is formed to protect the silicon nitride layer during etching.

8. A method of forming a semiconductor device, comprising: Forming a source / drain region; A contact etch stop layer is formed on the source / drain region; an interlayer dielectric is formed on the contact etch stop layer; a first contact plug is formed in the interlayer dielectric and the contact etch stop layer; an etching process is performed to form a trench in the interlayer dielectric and the contact etch stop layer, wherein the source / drain region and the first contact plug are exposed in the trench; a silicon-containing region is formed on a surface of the source / drain region; a silicate region is formed on the silicon-containing region; a silicon nitride layer is formed on the silicate region; and a metal feature is formed on the silicon nitride layer, wherein, after the metal feature is formed, the silicon nitride layer and the silicate region contain an element selected from phosphorus, carbon, sulfur, fluorine and combinations thereof.

9. The method as described in claim 8, wherein, The element has a peak concentration at an interface between the silicon nitride layer and the metal feature.

10. The method as described in claim 8, further comprising: Before forming the metallic feature, a passivation layer is formed on the metallic silicon nitride layer; An etching process is performed to remove a metal nitride layer on an additional metal feature located on one side of the silicon region, wherein a passivation layer protects the metal silicon nitride layer during the etching process; and the passivation layer is removed, wherein the metal feature is formed after the passivation layer is removed.

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