Comparator with switched tail current

Abstract

This invention provides a comparator with a switchable tail current. The comparator includes a switchable tail current path circuit, a first input transistor, a second input transistor, and a latching load circuit. The switchable tail current path circuit generates the switchable tail current. The first input transistor generates a first input current based on a first input signal and the switchable tail current, and the second input transistor generates a second input current based on a second input signal and the switchable tail current. The latching load circuit generates a first output signal and a second output signal based on the first input current and the second input current, wherein the switchable tail current path circuit controls the switchable tail current based on the first output signal and the second output signal.

Claims

1. A comparator having a switchable tail current, comprising: a switchable tail current path circuit for generating the switchable tail current; a first input transistor coupled to the switchable tail current path circuit for generating a first input current based on a first input signal and the switchable tail current; a second input transistor coupled to the switchable tail current path circuit for generating a second input current based on a second input signal and the switchable tail current; a latching load circuit coupled to the switchable tail current path circuit for receiving the first input current and the second input current, and generating a first output signal and a second output signal based on the first input current and the second input current, wherein the switchable tail current path circuit controls the magnitude of the switchable tail current based on the first output signal and the second output signal; wherein when the comparator operates in a reset mode, the latching load circuit pulls both the first output signal and the second output signal to a first threshold, and the switchable tail current path circuit is turned off; When the comparator operates in the initial stage of a comparison mode, the switching tail current path circuit sets the switching tail current to a first current value because both the first output signal and the second output signal are at the first level; and when the comparator operates in the completion stage of the comparison mode, the latching load circuit pulls one of the first output signal and the second output signal to a second level and pulls the other of the first output signal and the second output signal to the first level, and the switching tail current path circuit sets the switching tail current to a second current value because one of the first output signal and the second output signal is at the second level.

2. The comparator as described in claim 1, wherein the switching tail current path circuit comprises: a first control transistor, wherein a drain terminal of the first control transistor is coupled to a first node of the switching tail current path circuit, and a source terminal of the first control transistor is coupled to a second node of the switching tail current path circuit; a second control transistor, wherein a drain terminal of the second control transistor is coupled to the first node of the switching tail current path circuit, and a source terminal of the second control transistor is coupled to the second node of the switching tail current path circuit; wherein a gate terminal of the first control transistor is used to receive the first output signal, and a gate terminal of the second control transistor is used to receive the second output signal.

3. The comparator as described in claim 1, wherein the switching tail current path circuit comprises: a first control transistor, wherein a drain terminal of the first control transistor is coupled to a first node of the switching tail current path circuit; and a second control transistor, wherein a drain terminal of the second control transistor is coupled to a source terminal of the first control transistor, and a source terminal of the second control transistor is coupled to a second node of the switching tail current path circuit; wherein a gate terminal of the first control transistor is used to receive the first output signal, and a gate terminal of the second control transistor is used to receive the second output signal.

4. The comparator as described in claim 1, wherein the switching tail current path circuit comprises: a first control transistor, wherein a drain terminal of the first control transistor is coupled to a first node of the switching tail current path circuit; a second control transistor, wherein a drain terminal of the second control transistor is coupled to a source terminal of the first control transistor, and a source terminal of the second control transistor is coupled to a second node of the switching tail current path circuit; A third control transistor, wherein a drain terminal of the third control transistor is coupled to the first node of the switched tail current path circuit; And a fourth control transistor, wherein a drain terminal of the fourth control transistor is coupled to a source terminal of the third control transistor, and a source terminal of the fourth control transistor is coupled to the second node of the switched tail current path circuit; wherein a gate terminal of the first control transistor is used to receive the first output signal, a gate terminal of the second control transistor is used to receive the second output signal, a gate terminal of the third control transistor is used to receive the second output signal, and a gate terminal of the fourth control transistor is used to receive the first output signal.

5. The comparator as described in claim 1, wherein the latching load circuit comprises: a first positive feedback (regeneration) transistor for receiving the first input current; a second positive feedback transistor for receiving the second input current; wherein a drain terminal of the first positive feedback transistor is coupled to a gate terminal of the second positive feedback transistor and is used to output the first output signal, and a drain terminal of the second positive feedback transistor is coupled to a gate terminal of the first positive feedback transistor and is used to output the second output signal.

6. The comparator as described in claim 5, wherein the latching load circuit further comprises: a first reset transistor coupled between the drain terminal of the first positive feedback transistor and a reference voltage, wherein a gate terminal of the first reset transistor is configured to receive a mode control signal; and a second reset transistor coupled between the drain terminal of the second positive feedback transistor and the reference voltage, wherein a gate terminal of the second reset transistor is configured to receive the mode control signal.

7. The comparator as described in claim 5, wherein the latching load circuit further includes: a reset transistor coupled between the drain terminal of the first positive feedback transistor and the drain terminal of the second positive feedback transistor, wherein a gate terminal of the reset transistor is used to receive a mode control signal.

8. The comparator as described in claim 5, wherein the latching load circuit further comprises: a third positive feedback transistor, wherein a gate terminal of the third positive feedback transistor is coupled to the drain terminal of the second positive feedback transistor, a drain terminal of the third positive feedback transistor is coupled to the drain terminal of the first positive feedback transistor, and a source terminal of the third positive feedback transistor is coupled to a drain terminal of the first input transistor; and a fourth positive feedback transistor, wherein a gate terminal of the fourth positive feedback transistor is coupled to the drain terminal of the first positive feedback transistor, a drain terminal of the fourth positive feedback transistor is coupled to the drain terminal of the second positive feedback transistor, and a source terminal of the fourth positive feedback transistor is coupled to a drain terminal of the second input transistor.

9. The comparator as described in claim 5, wherein the latching load circuit further comprises: a third positive feedback transistor, wherein a gate terminal of the third positive feedback transistor is coupled to the drain terminal of the second positive feedback transistor; a fourth positive feedback transistor, wherein a gate terminal of the fourth positive feedback transistor is coupled to the drain terminal of the first positive feedback transistor; a first reset transistor, wherein a gate terminal of the first reset transistor is used to receive a mode control signal; and a second reset transistor, wherein a gate terminal of the second reset transistor is used to receive the mode control signal; wherein the third positive feedback transistor and the first reset transistor are connected in series between the drain terminal of the first positive feedback transistor and the drain terminal of the first input transistor, and the fourth positive feedback transistor and the second reset transistor are connected in series between the drain terminal of the second positive feedback transistor and the drain terminal of the second input transistor.

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