Comparator circuit

Abstract

A comparator circuit includes a latch-up circuit and an input amplifier circuit. The latch-up circuit comprises two pairs of intercoupled transistors disposed between a pair of first voltage receivers and a pair of second voltage receivers, and electrically coupled through a pair of output terminals. The input amplifier circuit includes a pair of P-type input transistors and a pair of N-type input transistors. The P-type input transistors are electrically coupled between a pair of third voltage receivers and the output terminals and are controlled by the input voltage. The N-type input transistors are coupled between the output terminals and a pair of fourth voltage receivers and are controlled by the input voltage. The P-type and N-type input transistors provide voltage inputs to the output terminals according to the input voltage, thereby activating the latch-up circuit and generating a pair of output voltages at the output terminals.

Claims

1. A comparator circuit, comprising: a latching circuit including a first voltage receiver, a second voltage receiver, and a pair of output terminals, wherein the latching circuit includes two pairs of intercoupled transistors disposed between the first voltage receiver and the second voltage receiver and electrically coupled through the pair of output terminals, wherein the first voltage receiver is configured to receive a first power supply voltage, and the second voltage receiver is configured to receive a second power supply voltage; and an input amplifier circuit, comprising: a pair of P-type input transistors electrically coupled between a pair of third voltage receivers and the pair of output terminals and controlled by a pair of input voltages, wherein the pair of third voltage receivers is configured to receive a third power supply voltage; and a pair of N-type input transistors electrically coupled between the pair of output terminals and a pair of fourth voltage receivers and controlled by the pair of input voltages, wherein the pair of fourth voltage receivers is configured to receive a fourth power supply voltage; The pair of P-type input transistors and the pair of N-type input transistors input voltage to the pair of output terminals according to the pair of input voltages, so that the latching circuit operates and generates a pair of output voltages at the pair of output terminals.

2. The comparator circuit as claimed in claim 1, wherein the size of a first element of the pair of P-type input transistors is smaller than the size of a second element of the plurality of elements included in the latching circuit.

3. The comparator circuit as claimed in claim 1, wherein the input amplifier circuit further includes a pair of P-type load transistors electrically coupled between the pair of third voltage receiving terminals and a third voltage supply terminal for providing the third power supply voltage, such that the pair of P-type input transistors receives the third power supply voltage through the pair of P-type load transistors; the pair of P-type load transistors are controlled by the pair of input voltages.

4. The comparator circuit as claimed in claim 1, wherein the input amplifier circuit further includes a pair of P-type load transistors electrically coupled between the pair of third voltage receiving terminals and a third voltage supply terminal for providing the third power supply voltage, such that the pair of P-type input transistors receives the third power supply voltage through the pair of P-type load transistors; and the pair of P-type load transistors are controlled by a delayed clock signal to be turned on according to a first state of the delayed clock signal to operate the pair of P-type input transistors in an input state according to the pair of input voltages, and to be turned off according to a second state of the delayed clock signal to operate the pair of P-type input transistors in a closed state.

5. The comparator circuit as claimed in claim 4, wherein the pair of input voltages is generated by a voltage generating circuit, and the voltage generating circuit comprises: a pair of first switching transistors electrically coupled between a fifth voltage receiving terminal and a pair of generating terminals for generating the pair of input voltages, and controlled by a clock signal, wherein the fifth voltage receiving terminal is configured to receive a fifth power supply voltage, and the delayed clock signal is generated by delaying the clock signal by a preset time; a pair of voltage generating transistors electrically coupled between the pair of generating terminals and a sixth voltage receiving terminal, and controlled by a pair of original input voltages, wherein the sixth voltage receiving terminal is configured to receive a sixth power supply voltage; and a second switching transistor electrically coupled between the sixth voltage receiving terminal and a sixth voltage supply terminal for providing the sixth power supply voltage, and controlled by the clock signal; The first switching transistor is turned on according to the first state of the clock signal, and the second switching transistor is turned off according to the first state of the clock signal, so that the pair of voltage generating transistors operates in an initial state; and the first switching transistor is turned off according to the second state of the clock signal, and the second switching transistor is turned on according to the second state of the clock signal, so that the pair of voltage generating transistors operates in a voltage generating state.

6. The comparator circuit as claimed in claim 5, wherein the pair of input voltages is at the level of the fifth power supply voltage in the initial state, and gradually changes from the level of the fifth power supply voltage to the level of the sixth power supply voltage in the generated state.

7. The comparator circuit as claimed in claim 5, wherein the two pairs of intercoupled transistors include a first pair of intercoupled transistors electrically coupled to the first voltage receiving terminal and a second pair of intercoupled transistors electrically coupled to the second voltage receiving terminal, wherein the first pair of intercoupled transistors is a pair of P-type transistors and the second pair of intercoupled transistors is a pair of N-type transistors, the comparator circuit further comprising: a first reset circuit disposed between the first voltage receiving terminal and the pair of output terminals and controlled by the clock signal; and a second reset circuit disposed between the second voltage receiving terminal and a second voltage supply terminal for providing the second power supply voltage and controlled by the clock signal; The first reset circuit is turned on according to the first state of the clock signal and the second reset circuit is turned off according to the first state of the clock signal, so that the input amplifier circuit operates in a reset state; and the first reset circuit is turned off according to the second state of the clock signal and the second reset circuit is turned on according to the second state of the clock signal, so that the input amplifier circuit operates in a working state.

8. The comparator circuit as claimed in claim 5, wherein the two pairs of intercoupled transistors include a first pair of intercoupled transistors electrically coupled to the first voltage receiving terminal and a second pair of intercoupled transistors electrically coupled to the second voltage receiving terminal, wherein the first pair of intercoupled transistors is a pair of N-type transistors and the second pair of intercoupled transistors is a pair of P-type transistors, the comparator circuit further comprising: a first reset circuit disposed between the first voltage receiving terminal and the pair of output terminals and controlled by an inverted clock signal, wherein the inverted clock signal is generated by inverting the clock signal; and a second reset circuit disposed between the second voltage receiving terminal and a second voltage supply terminal for providing the second power supply voltage and controlled by the inverted clock signal; The first reset circuit is turned on according to the second state of the inverted clock signal and the second reset circuit is turned off according to the second state of the inverted clock signal, so that the latching circuit operates in a reset state; and the first reset circuit is turned off according to the first state of the inverted clock signal and the second reset circuit is turned on according to the first state of the inverted clock signal, so that the latching circuit operates in a working state.

9. A comparator circuit, comprising: a latching circuit including a first voltage receiver, a pair of second voltage receivers, and a pair of outputs, wherein the latching circuit includes two pairs of interleaved transistors disposed between the first voltage receiver and the pair of second voltage receivers and electrically coupled through the pair of outputs, wherein the first voltage receiver is configured to receive a first power supply voltage, and the pair of second voltage receivers is configured to receive a second power supply voltage; and an input amplifier circuit, comprising: a pair of P-type input transistors electrically coupled between a third voltage receiver and the pair of second voltage receivers and controlled by a pair of input voltages, wherein the third voltage receiver is configured to receive a third power supply voltage; and a pair of N-type input transistors electrically coupled between the pair of second voltage receivers and a fourth voltage receiver and controlled by the pair of input voltages, wherein the fourth voltage receiver is configured to receive a fourth power supply voltage; The pair of P-type input transistors and the pair of N-type input transistors input voltage to the pair of second voltage receivers according to the input voltage, so that the latching circuit operates and generates a pair of output voltages at the output terminals.

10. A comparator circuit, comprising: a latching circuit including a first voltage receiver, a pair of connection terminals, and a pair of output terminals, wherein the latching circuit includes two pairs of intercoupled transistors disposed between the first voltage receiver and the pair of connection terminals and electrically coupled through the pair of output terminals, wherein the first voltage receiver is configured to receive a first power supply voltage; and an input amplifier circuit including: a pair of P-type input transistors electrically coupled between a third voltage receiver and the pair of connection terminals and controlled by a pair of input voltages, wherein the third voltage receiver is configured to receive a third power supply voltage; and a pair of N-type input transistors electrically coupled between the pair of connection terminals and a fourth voltage receiver and controlled by the pair of input voltages, wherein the fourth voltage receiver is configured to receive a fourth power supply voltage; wherein the pair of P-type input transistors and the pair of N-type input transistors provide voltage inputs to the pair of connection terminals according to the pair of input voltages, so as to operate the latching circuit and generate a pair of output voltages at the pair of output terminals.

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