Comparator circuit

Abstract

A comparator circuit. A latching circuit operates based on a reset clock signal and an amplified voltage to generate an output voltage, having a reset level, a regenerated voltage value, and high and low levels during the reset phase, voltage regeneration phase, and voltage regeneration completion phase, respectively. An input amplifier circuit includes: an input pair circuit, and first and second load transistor circuits. The input pair circuit is coupled between a connection terminal and a first power supply and is controlled by the input voltage to generate an amplified voltage at the connection terminal. The first and second load transistor circuits are coupled between a second power supply and the connection terminal, each including two transistors connected in parallel and controlled by the output voltage. During the reset phase, they are both turned on or off; during the voltage regeneration phase, they are both turned on to form a load on the input pair circuit; and during the voltage regeneration completion phase, the first transistor is turned on and the second is turned off.

Claims

1. A comparator circuit comprising: a latch-up circuit configured to operate at least according to a pair of amplified voltages to generate a pair of output voltages such that the pair of output voltages share a reset level in a reset phase, have a first regenerated voltage value and a second regenerated voltage value in a voltage regeneration phase, and have a high level and a low level in a voltage regeneration completion phase, wherein the reset level is one of the high level and the low level, and the first regenerated voltage value and the second regenerated voltage value are located between the high level and the low level; and an input amplifier circuit comprising: an input pair circuit electrically coupled between a pair of terminals and a first power supply, and controlled by the pair of input voltages to generate the pair of amplified voltages at the pair of terminals; a first load transistor circuit electrically coupled between a second power supply and a first terminal of the pair of terminals; and a second load transistor circuit electrically coupled between the second power supply and a second terminal of the pair of terminals; Each of the first load transistor circuit and the second load transistor circuit includes two transistors connected in parallel. A first transistor is controlled by a first output voltage of the pair of output voltages, and a second transistor is controlled by a second output voltage of the pair of output voltages. The two transistors are configured to be turned on or off together during the reset phase, to be turned on together during the voltage regeneration phase to form a load of the input pair circuit, and to be turned on by the first transistor and off by the second transistor during the voltage regeneration completion phase.

2. The comparator circuit as described in claim 1, wherein the input pair circuit is an N-type transistor circuit and the two transistors are each a P-type transistor.

3. The comparator circuit as described in claim 2, wherein when the reset level is the high level, the two transistors are both turned off during the reset phase, and when the reset level is the low level, the two transistors are both turned on during the reset phase.

4. The comparator circuit as described in claim 1, wherein the input pair circuit is an N-type transistor circuit, and the two transistors are each an N-type transistor.

5. The comparator circuit as described in claim 4, wherein when the reset level is the high level, the two transistors are both turned on during the reset phase, and when the reset level is the low level, the two transistors are both turned off during the reset phase.

6. The comparator circuit as claimed in claim 1, wherein the input pair circuit is a P-type transistor circuit, and the two transistors are each a P-type transistor.

7. The comparator circuit as claimed in claim 6, wherein when the reset level is the high level, the two transistors are both turned off during the reset phase, and when the reset level is the low level, the two transistors are both turned on during the reset phase.

8. The comparator circuit as claimed in claim 1, wherein the input pair circuit is a P-type transistor circuit and the two transistors are each an N-type transistor.

9. The comparator circuit as claimed in claim 8, wherein when the reset level is the high level, the two transistors are both turned on during the reset phase, and when the reset level is the low level, the two transistors are both turned off during the reset phase.

10. The comparator circuit as claimed in claim 1, wherein the input amplifier circuit further includes a pair of load elements such that the input pair circuit is electrically coupled to the pair of terminals through the pair of load elements, wherein the pair of load elements is a pair of load transistors or a pair of resistors.

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