Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes a substrate having a first surface and a second surface on opposite sides. An etch stop layer is disposed within the substrate and adjacent to the first surface. A deep trench isolation structure is disposed within the substrate and extends vertically from the second surface to the etch stop layer. A patterned isolation layer is disposed below the second surface of the substrate and contacts the deep trench isolation structure, wherein the patterned isolation layer and the deep trench isolation structure surround a first region of the substrate, and a second surface of the second region of the substrate is exposed through an opening in the patterned isolation layer. Lateral elements are disposed within the first region of the substrate, and vertical elements are disposed within the second region of the substrate. A back metal layer is disposed below the patterned isolation layer, fills the opening in the patterned isolation layer, and contacts the second surface of the second region of the substrate.

Claims

1. A semiconductor device, comprising: A substrate having a first surface and a second surface on opposite sides; An etch stop layer is disposed within the substrate and close to the first surface; a deep trench isolation structure is disposed within the substrate and extends vertically from the second surface to the etch stop layer; a patterned isolation layer is disposed below the second surface of the substrate and contacts the deep trench isolation structure, wherein the patterned isolation layer and the deep trench isolation structure surround a first region of the substrate, and a second surface of a second region of the substrate is exposed through an opening in the patterned isolation layer; a lateral element is disposed within the first region of the substrate; a vertical element is disposed within the second region of the substrate; and a back metal layer is disposed below the patterned isolation layer, fills the opening in the patterned isolation layer, and contacts the second surface of the second region of the substrate.

2. The semiconductor device as claimed in claim 1, wherein the vertical projected area of ​​the etch stop layer is greater than the vertical projected area of ​​the deep trench isolation structure.

3. The semiconductor device as claimed in claim 1, wherein the lateral element comprises a bipolar transistor, a complementary metal-oxide-semiconductor transistor, a laterally diffused metal-oxide-semiconductor transistor, or a combination thereof.

4. The semiconductor device as claimed in claim 1 further includes a shallow trench isolation region disposed in the first region of the substrate, wherein, in a horizontal direction, the width of the etch stop layer is greater than the width of the shallow trench isolation region.

5. The semiconductor device as claimed in claim 4, wherein, in a vertical direction, the thickness of the etch stop layer is equal to or greater than the depth of the shallow trench isolation region.

6. The semiconductor device as claimed in claim 1, wherein the etch stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

7. The semiconductor device as claimed in claim 1, wherein the vertical element comprises a vertically doubly diffused metal-oxide-semiconductor transistor, an insulated-gate bipolar transistor, a trench metal-oxide-semiconductor transistor, or a combination thereof.

8. The semiconductor device as claimed in claim 1, wherein the deep trench isolation structure comprises: A deep trench; An insulating material is used to fill the deep trench, wherein the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

9. The semiconductor device as claimed in claim 1, wherein the deep trench isolation structure comprises: A deep trench; A dielectric liner is disposed on the sidewall of the deep trench, wherein the dielectric liner comprises silicon oxide; and a semiconductor material fills the remaining space of the deep trench, and the dielectric liner surrounds the semiconductor material, wherein the semiconductor material comprises polycrystalline silicon or silicon carbide.

10. The semiconductor device as claimed in claim 1, wherein the substrate comprises: A heavily doped N-type semiconductor substrate; An epitaxial layer is stacked on the N-type heavily doped semiconductor substrate, wherein the N-type heavily doped semiconductor substrate located in the second region constitutes a drain region of the vertical element, and the back metal layer located in the second region constitutes a drain electrode of the vertical element.

11. A method for manufacturing a semiconductor device, comprising: A substrate is formed having a first surface and a second surface on opposite sides; An etch stop layer is formed within the substrate and close to the first surface; a lateral element is formed in a first region of the substrate; a vertical element is formed in a second region of the substrate; after forming the lateral element and the vertical element, a deep trench isolation structure is formed within the substrate, the deep trench isolation structure extending vertically from the second surface to the etch stop layer; a patterned isolation layer is formed below the second surface of the substrate, and the patterned isolation layer contacts the deep trench isolation structure, wherein the patterned isolation layer and the deep trench isolation structure surround the lateral element; and a back metal layer is formed below the patterned isolation layer, and the back metal layer contacts the second surface of the second region of the substrate.

12. A method of manufacturing a semiconductor device as claimed in claim 11, wherein forming the deep trench isolation structure comprises: The substrate is etched from the second surface, and the etching stops at the etch stop layer to form a deep trench; The deep trench is filled with a filler material to form the deep trench isolation structure, wherein the vertical projected area of ​​the etch stop layer is larger than the vertical projected area of ​​the deep trench isolation structure.

13. A method for manufacturing a semiconductor device as described in claim 12, wherein the filler material comprises: An insulating material, comprising silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof; or a dielectric liner formed on the sidewalls of the deep trench, and a semiconductor material filling the remaining space of the deep trench, wherein the semiconductor material comprises polycrystalline silicon or silicon carbide.

14. A method for manufacturing a semiconductor device as claimed in claim 11, wherein forming the substrate comprises: An N-type heavily doped semiconductor substrate is provided, having a front side and a back side on opposite sides; an epitaxial layer is grown on the front side of the N-type heavily doped semiconductor substrate; and the back side of the N-type heavily doped semiconductor substrate is ground before forming the deep trench isolation structure to reduce the thickness of the N-type heavily doped semiconductor substrate.

15. A method of manufacturing a semiconductor device as claimed in claim 14, wherein forming the vertical element includes forming a vertical double-diffused metal-oxide-semiconductor transistor, an insulated-gate bipolar transistor, a trench metal-oxide-semiconductor transistor, or a combination thereof in the epitaxial layer of the second region, and the thinned N-type heavily doped semiconductor substrate located in the second region constitutes a drain region of the vertical element, and the back metal layer located in the second region constitutes a drain electrode of the vertical element.

16. A method of manufacturing a semiconductor device as claimed in claim 14, wherein forming the lateral element comprises: A bipolar transistor, a complementary metal-oxide-semiconductor transistor, a laterally diffused metal-oxide-semiconductor transistor, or a combination thereof are formed within the epitaxial layer of the first region; and a shallow trench isolation region is formed within the epitaxial layer of the first region.

17. A method of manufacturing a semiconductor device as claimed in claim 16, wherein the etch stop layer and the shallow trench isolation region are formed simultaneously, the composition of the etch stop layer is the same as that of the shallow trench isolation region, the thickness of the etch stop layer is the same as the depth of the shallow trench isolation region in a vertical direction, and the width of the etch stop layer is greater than the width of the shallow trench isolation region in a horizontal direction.

18. A method of manufacturing a semiconductor device as claimed in claim 16, wherein the etch stop layer and the shallow trench isolation region are formed separately, the composition of the etch stop layer and the composition of the shallow trench isolation region are different, the thickness of the etch stop layer is greater than the depth of the shallow trench isolation region in a vertical direction, and the width of the etch stop layer is greater than the width of the shallow trench isolation region in a horizontal direction.

19. A method of manufacturing a semiconductor device as claimed in claim 11, wherein forming the patterned isolation layer comprises: An isolation material layer is deposited on the second surface of the substrate to cover the second surface of the first region, the second surface of the second region, and the bottom surface of the deep trench isolation structure; And pattern the insulating material layer to form an opening that exposes the second surface of the second region of the substrate.

20. A method of manufacturing a semiconductor device as claimed in claim 19, wherein the back metal layer covers the bottom and side surfaces of the patterned isolation layer and fills the opening.

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