Memory system, controller, and control method

Abstract

Error correction is performed using a simpler configuration. The memory system includes: memory and a controller. The memory stores data encoded by error correction codes used to correct errors of t bits or less. The controller uses received characters read from the memory to calculate t checksums. By performing variable transformations on the checksums, it calculates (t-1) key information, which is used to obtain a first error pattern. This first error pattern includes a combination of multiple transformed positions obtained by performing variable transformations on multiple error positions when the number of error bits is (t+1). Using the corresponding information, it obtains the first error pattern corresponding to the key information. It performs inverse variable transformations on the transformed positions included in the first error pattern to calculate the error positions, and obtains a list containing a second error pattern, which includes combinations of error positions. It then performs list decoding using the list.

Description

Technical Field

[0001] The embodiments of the present invention relate to a memory system, a controller, and a control method. Prior Technology

[0002] In memory systems, error-corrected data is stored in memory to protect data stored in memory such as NAND flash memory. Therefore, when reading data stored in memory, the error-corrected data (hereinafter referred to as received characters) read from memory is decoded to restore the data before the error correction encoding. Summary of the Invention

[0003] The purpose of this invention is to provide a memory system, controller, and control method capable of error correction (decoding) with a simpler configuration.

[0004] The memory system of the embodiment includes: a memory and a controller. The memory stores data encoded by error correction codes used to correct errors of t bits or less. The controller uses received characters read from the memory to calculate t syndromes, and calculates (t-1) key information by variable transformation of the syndromes. This (t-1) key information is used to obtain a first error pattern containing a combination of multiple transformed positions obtained by variable transformation of a multiple number of error positions when the number of erroneous bits is (t+1). The first error pattern corresponding to the key information is obtained using corresponding information. The transformed positions contained in the first error pattern are inversely transformed to calculate the error positions. A list containing a second error pattern is obtained, which contains a combination of error positions, and list decoding is performed using the list. Simple Explanation of the Diagram

[0005] [Figure 1] is a block diagram of the memory system according to the embodiment. [Figure 2] is a block diagram of the decoding unit in the first embodiment. [Figure 3] is a flowchart of the decoding process in the implementation method. [Figure 4] is a flowchart of the decoding process in the variant example. [Figure 5] is a diagram showing an example of the configuration of the root calculation circuit of the first embodiment. [Figure 6] is a diagram illustrating an example of pseudocode used to determine the error pattern. [Figure 7] is a diagram illustrating an example of the configuration of the root calculation circuit in the second embodiment. [Figure 8] is a diagram showing an example of a lookup table. [Figure 9] is a diagram showing an example of a lookup table. [Figure 10] is a diagram showing an example of a lookup table. [Figure 11] is a diagram illustrating an example of pseudocode used to determine the error pattern. [Figure 12] is a diagram illustrating an example of pseudocode used to determine the error pattern. Implementation

[0006] Hereinafter, with reference to the attached drawings, a suitable embodiment of the memory system of the present invention will be described in detail.

[0007] (First Embodiment) First, the memory system of this embodiment will be described in detail with reference to the drawings. FIG1 is a block diagram showing a schematic configuration example of the memory system of this embodiment. As shown in FIG1, the memory system 1 includes: a memory controller 10 and a non-volatile memory 20. The memory system 1 is connectable to a host 30, and FIG1 shows the state of connection with the host 30. The host 30 may be an electronic device such as a personal computer or a portable terminal.

[0008] Non-volatile memory 20 is a non-volatile memory that stores data in a non-volatile manner, such as NAND flash memory (hereinafter, simply referred to as NAND memory). In the following description, although the case of using NAND memory as non-volatile memory 20 is illustrated, memory devices other than NAND memory such as three-dimensional flash memory, ReRAM (Resistive Random Access Memory), and FeRAM (Ferroelectric Random Access Memory) can also be used as non-volatile memory 20. Furthermore, non-volatile memory 20 does not necessarily have to be semiconductor memory, and this embodiment can also be applied to various memory media other than various semiconductor memory.

[0009] The memory system 1 may be a so-called SSD (Solid State Drive), a memory card that combines the memory controller 10 and the non-volatile memory 20 into a single package, or various memory systems that have the non-volatile memory 20.

[0010] The memory controller 10 controls the writing to the non-volatile memory 20 according to the write request from the host 30. Furthermore, the memory controller 10 controls the reading from the non-volatile memory 20 according to the read request from the host 30. The memory controller 10 is, for example, a semiconductor integrated circuit configured as a System-on-a-Chip (SoC). The memory controller 10 includes: a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (encoder / decoder) 14, and a data buffer 12. The host I / F 15, memory I / F 13, control unit 11, encoding / decoding unit 14, and data buffer 12 are interconnected by an internal bus 16. Part or all of the operation of each component of the memory controller 10 described below can be implemented by the CPU (Central Processing Unit) executing firmware, or it can be implemented through hardware.

[0011] The host I / F15 performs interface-specific processing with the host 30 and outputs commands received from the host 30, user data of the write target, etc., to the internal bus 16. In addition, the host I / F15 transmits user data read and restored from the non-volatile memory 20 and responses from the control unit 11 to the host 30.

[0012] The memory I / F13 is a circuit that performs write processing on the non-volatile memory 20 based on the instructions of the control unit 11. Furthermore, the memory I / F13 performs read processing from the non-volatile memory 20 based on the instructions of the control unit 11. Although the memory I / F13 can be an interface conforming to any specification, it is an interface conforming to, for example, Toggle DDR (Double Data Rate) or ONFI (Open NAND Flash Interface) specifications.

[0013] The control unit 11 comprehensively controls all components of the memory system 1. The control unit 11 can also be implemented using a processor such as a CPU or GPU (Graphics Processing Unit), i.e., software. The control unit 11 can also be implemented using a processor such as an integrated circuit (IC), i.e., hardware. The control unit 11 can also be implemented using both software and hardware. When the control unit 11 receives commands from the host 30 via the host I / F 15, it performs control according to those commands. For example, based on a command from the host 30, the control unit 11 sends a write instruction to the memory I / F 13 for user data and parity of the non-volatile memory 20. Furthermore, based on a command from the host 30, the control unit 11 sends a read instruction to the memory I / F 13 for user data and parity of the non-volatile memory 20.

[0014] Furthermore, when the control unit 11 receives a write request from the host 30, it determines the memory region (memory area) on the non-volatile memory 20 for the user data stored in the data buffer 12. In other words, the control unit 11 manages the write destination of the user data. The logical address of the user data received from the host 30 and the corresponding physical address of the memory region on the non-volatile memory 20 where the user data is stored are stored as an address translation table.

[0015] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address translation table mentioned above, and sends a read instruction from the physical address to the memory I / F13.

[0016] In NAND memory, data is typically written to and read from units called pages, and deleted from units called blocks. In this embodiment, multiple memory cells connected to the same word line are called a memory cell group. When the memory cell is a single-level cell (SLC), one memory cell group corresponds to one page. When the memory cell is a multiple-level cell (MLC), one memory cell group corresponds to multiple pages. However, in this specification, MLC includes: TLC (Triple-Level Cell), QLC (Quad-Level Cell), etc. Furthermore, each memory cell is connected to both the word line and the bit line. Therefore, each memory cell can be identified using the address of the word line and the address of the bit line.

[0017] The data buffer 12 temporarily stores user data received from the host 30 before the memory controller 10 stores it in the non-volatile memory 20. Similarly, the data buffer 12 temporarily stores user data read from the non-volatile memory 20 before transmitting it to the host 30. The data buffer 12 can utilize general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). However, the data buffer 12 may also be external to the memory controller 10 instead of being built into it.

[0018] User data transmitted from host 30 is transferred to internal bus 16 and temporarily stored in data buffer 12. Encoding / decoding unit 14 encodes the user data stored in non-volatile memory 20 to generate codewords. Furthermore, encoding / decoding unit 14 decodes received characters read from non-volatile memory 20 to recover user data. Therefore, encoding / decoding unit 14 includes an encoder 17 and a decoder 18. However, the data encoded by encoding / decoding unit 14 includes not only user data but also control data used internally by memory controller 10.

[0019] Next, the write process of this embodiment will be explained. When the controller 11 writes to the non-volatile memory 20, it instructs the encoding unit 17 to encode the user data. At this time, the controller 11 determines the memory location (memory address) of the codeword in the non-volatile memory 20 and also instructs the determined memory location to the memory I / F13.

[0020] The encoding unit 17 encodes user data on the data buffer 12 to generate codewords based on instructions from the control unit 11. Encoding methods can be employed, for example, using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) code and RS (Reed-Solomon) code, and using these codes as component codes in the row and column directions (product codes, etc.). The memory I / F 13 controls the storage of the codewords to the memory location on the non-volatile memory 20 indicated by the control unit 11. The following explanation uses BCH code with an error-correctable number of bits (correction capability) of t (t being an integer greater than or equal to 2) as an example.

[0021] Next, the process of reading from the non-volatile memory 20 in this embodiment will be explained. When reading from the non-volatile memory 20, the control unit 11 specifies an address on the non-volatile memory 20 to instruct the memory I / F 13 to read. Furthermore, the control unit 11 instructs the decoding unit 18 to begin decoding. According to the instruction from the control unit 11, the memory I / F 13 reads the received characters from the specified address of the non-volatile memory 20 and inputs the read received characters to the decoding unit 18. The decoding unit 18 decodes the received characters read from the non-volatile memory 20.

[0022] The decoding unit 18 decodes the received characters read from the non-volatile memory 20. The decoding unit 18 can perform error correction processing for errors exceeding the correction capability (number of erroneous bits) with a relatively simple configuration. In the case of using a BCH code with a correction capability of t, in this embodiment, errors at (t+1) erroneous positions when the number of erroneous bits is (t+1) can be corrected. Hereinafter, although the case where t is 2 is used as an example, the same steps can also be applied to cases where t is 3 or more.

[0023] Here, a technique for correcting errors exceeding the correction capability of the error correction code is described. In soft-decision decoding, such as Chase decoding, which utilizes reliability information for each bit, candidate patterns (hereinafter referred to as error patterns) are listed to display the error positions that satisfy a complex number of checksums calculated from the received characters, and the error pattern with the highest likelihood is selected from the complex patterns for error correction. In this technique, there may be cases where error patterns containing error positions exceeding the correction capability of the error correction code are listed. Each error pattern contains information comprising a combination of a complex number (e.g., 3) error positions.

[0024] In one technique for such situations, there exists a method to flip a portion of the bits to recalculate the checksum and obtain the error location (hereinafter referred to as the comparative example). When an error pattern containing three (3-bit) error locations is obtained from, for example, a BLH code with a correction capability of 2 bits, if the error at one of the three error locations is corrected by bit flipping, the remaining error count becomes two. Therefore, it is possible to calculate two error locations from the checksum.

[0025] As shown in the comparative example, in techniques that list error patterns using bit flipping, error correction is performed on the checksum recalculated after each bit flip. Therefore, error correction must be performed only on the number of bit flips being targeted, which may result in situations where high-speed decoding is not possible.

[0026] Therefore, in this embodiment, for BCH codes with a correction capability of 2 bits, instead of performing bit flipping as in the comparison example, the error patterns displaying 3 (3 bits) error positions are enumerated, and list decoding is performed using a list containing the enumerated error patterns. In this embodiment, by using a lookup table (LUT, an example of corresponding information) for obtaining error patterns, the error patterns can be enumerated in a single decoding process.

[0027] As a simple method of using a lookup table, one could consider directly using the checksum as key information and obtaining the error pattern corresponding to the key information. However, in such a method, the number of entries is too large, resulting in an excessively large lookup table size. Therefore, in this embodiment, by performing variable transformation on the checksum, the size of the lookup table can be further reduced. This allows for error correction (decoding) with a simpler configuration. The following describes the details of the decoding unit 18 in this embodiment.

[0028] Figure 2 is a block diagram showing an example of the configuration of the decoding unit 18 of this embodiment. Figure 2 is an example of the decoding unit 18 implemented as hardware circuitry. As shown in Figure 2, the decoding unit 18 includes: a checksum calculation circuit 201, a root calculation circuit 100, a selection circuit 210, a root calculation circuit 220, and a bit flipping circuit 230.

[0029] The received character R input to the decoding unit 18 includes, for example, the log-likelihood ratio (LLR) as an element, and is a vector of the same length as the code length n (n is an integer greater than or equal to 2). The receiver polynomial r(x) formed by the bits of the positive and negative codes of the LLR corresponding to the received character R is input to the checksum calculation circuit 201, and the reliability vector l of length n formed by the absolute values ​​of the LLR elements is input to the selection circuit 210.

[0030] The checksum calculation circuit 201 takes the receiving polynomial r(x) as input, calculates the checksum, and outputs it. The receiving polynomial r(x) is a polynomial with the bits corresponding to the positive and negative codes of the LLR as coefficients, and is represented by the following equation (1). For example, when the k-th LLE is positive, r￢k=0, and when it is negative, r￢k=1.

[0031] For example, the checksum calculation circuit 201 calculates the checksum si using si := r(αi). Due to the additive nature of errors, the receiving polynomial is r(x) = c(x) + e(x). However, c(x) is the polynomial representing the codeword, and e(x) is the polynomial representing the error. e(x) can be called the error polynomial. α represents the primitive 2m-1 root of GF(2m). When using a BCH code with a correction capability of 2 bits, the checksum calculation circuit 201 inputs the receiving polynomial r(x) and outputs checksums s1 and s3. Checksums s1 and s3 are respectively the sum of the first and third powers of the primitive element α corresponding to the Galois body GF.

[0032] The root calculation circuit 100 calculates candidate error patterns including error locations when the error count is 2 or 3. The method for calculating the error pattern when the error count is 2 can be any conventionally known method, but the method described in, for example, Japanese Patent Publication No. 2023-045450 is also applicable.

[0033] An error pattern can be represented, for example, as a binary vector e(v) of the same length as the code length n, where the v elements corresponding to the number of errors have a value of 1, and the other elements have a value of 0. However, the form of an error pattern is not limited to a binary vector. For example, an error pattern can also be represented as a tuple in which integers represent the index of the error location.

[0034] The following are cases where the error pattern represented by the binary vector e(v) is called error pattern e(v). Error pattern e(v) with 1 or 2 errors means there is one error pattern e(1) and one error pattern e(2). Error pattern e(v) with 3 errors means there is more than one error pattern e(3). The following are cases where the i-th error pattern e(v) (where i is an integer greater than or equal to 1) is represented by ei(v).

[0035] The calculation circuit 100 calculates one error pattern (e(2)) when the number of errors is 2, and includes the calculated error pattern in a list. When the number of errors is 2, the error pattern contains a combination of two error positions. Hereinafter, there is a case where the combination of two error positions is represented as (X1, X2).

[0036] The root calculation circuit 100 calculates, for example, one or more error patterns e(3) (the second error pattern) when the number of errors is 3 using the following steps.

[0037] The root calculation circuit 100, for example, calculates two key pieces of information for obtaining one or more error patterns eA (the first error pattern) by performing variable transformations on the calculated checksum. Error pattern eA is an error pattern that comprises a combination of multiple transformed positions obtained by applying variable transformations to three error positions X1, X2, and X3 respectively. The variable transformations are, for example, affine transformations, suitable for further reducing the amount of data in the lookup table. Details of the variable transformations will be described later.

[0038] However, there are cases where one of the three error positions can be calculated from the remaining two. For example, error position X3 can be calculated using operations on error positions X1 and X2. In such cases, error pattern eA can also be an error pattern containing a combination of two transformed positions. The following will primarily illustrate an example of error pattern eA using a combination of two transformed positions (X^1, X^2). However, X^ is equivalent to adding a hat to X.

[0039] The root calculation circuit 100 uses a lookup table to obtain one or more error patterns eA corresponding to the calculated key information. The lookup table is equivalent to matching the multiple values ​​of the key information that can be obtained with the corresponding error patterns eA.

[0040] The root calculation circuit 100 performs an inverse variable transformation (inverse variable transformation) on the transformed positions contained in each of the more than one error patterns eA to calculate the error position X. The root calculation circuit 100 calculates more than one error pattern e(3) that contains combinations of the calculated error positions X. When the number of errors is 3, the error pattern e(3) contains combinations of 3 error positions (X1, X2, X3). The root calculation circuit 100 obtains a list containing the calculated error patterns e(3).

[0041] The selection circuit 210 selects the maximum likelihood error style (hereinafter referred to as the maximum likelihood error style) from more than one error style contained in the list, and outputs the error positions contained in the selected maximum likelihood error style. When the error style e(2) with 2 errors is selected as the maximum likelihood error style, the selection circuit 210 outputs the error positions X1 and X2. When the error style e(3) with 3 errors is selected as the maximum likelihood error style, the selection circuit 210 outputs the error positions X1, X2, and X3.

[0042] For example, the selection circuit 210 uses the following equation (2) to select the maximum likelihood error pattern e*.

[0043] Here, L(ei (v)) represents the scoring function, which returns a real or integer score from the error pattern ei (v) and the reliability information of each element. The score indicates the reliability of the error location; for example, a smaller value indicates that it is closer to the true error. Equation (2) indicates that the error pattern with the smallest score is selected as the maximum likelihood error pattern e*. That is, the selection circuit 210 selects the error pattern with a higher reliability as the error location than other error patterns as the maximum likelihood error pattern e*.

[0044] However, equation (2) is an example, and any other evaluation value can be used. For example, a larger value can be used to indicate that the value is closer to the true error.

[0045] The reliability information for each element is a positive value, for example, greater than or equal to 0, with a higher value indicating higher reliability. The absolute value of the log-likelihood ratio can also be used as the reliability information. When the reliability information lj of the j-th element (j is an integer satisfying 1 ≤ j ≤ n) is taken as the reliability vector of the element, the scoring function L(ei (v)) is represented by the following equation (3). However, "·" denotes the inner product between vectors.

[0046] Furthermore, in systems where the code length changes dynamically (also known as shortened codes, where the length of the encoded data changes), the selection circuit 210 will discard the error pattern that indicates the error location that is longer than the code length of the received character.

[0047] The root calculation circuit 220 calculates the error location X1 when the error count is 1. For example, the root calculation circuit 220 calculates the error pattern e(1) when the error count is 1. The root calculation circuit 220 takes the error pattern e(1) as the maximum likelihood error pattern and outputs the error location X1 contained in the maximum likelihood error pattern. The method for calculating the error pattern when the error count is 1 can be any conventionally known method, such as the method described in Japanese Patent Publication No. 2023-045450.

[0048] However, the number of errors can be estimated using the value of the checksum as follows. The number of errors and the value of the checksum have the following relationship. When the error count is 0 or 1, s1 3 = s3 When the number of errors is 2 or 3, s1 3 ≠ s3

[0049] Therefore, if we assume the error count is less than 3 (s1 3=s3), the error count is 0 or 1.

[0050] Here, if β:=s1 3+s3, β=0 is equivalent to s1 3=s3. Therefore, if β is used, the following relationship can be obtained regarding the number of errors. If we assume the error count is less than 3, then when β=0, the error count is 0 or 1. Also, when β=0 and s1=0, the error count is 0.

[0051] The bit-flipping circuit 230 takes the received polynomial r(x) as input and the error position output by the selection circuit 210 or the root calculation circuit 220 as input, and outputs the received character with the error position reversed. However, although the received character is used as the output of the decoding unit 18, the output of the decoding unit 18 is not limited to the received character. The output form of the decoding unit 18 can be changed according to the configured system. For example, after reversing the error position, the error polynomial, or the bits of the error position, it can output payload data that has excluded redundant data used for error correction.

[0052] The process of using the list of error patterns obtained by the root calculation circuit 100, selecting the maximum likelihood error pattern by the selection circuit 210, and reversing the bits of the error positions contained in the maximum likelihood error pattern by the bit flipping circuit 230 is equivalent to list decoding.

[0053] Next, the decoding process of memory system 1 will be described. Figure 3 is a flowchart showing an example of the decoding process in this embodiment.

[0054] The control unit 11 reads the error correction code from the non-volatile memory 20 and obtains the received characters (step S101). Then, the control unit 11 instructs the decoding unit 18 to begin decoding.

[0055] The checksum calculation circuit 201 of the decoding unit 18 calculates the checksum from the received character (received polynomial r(x)) (step S102). For example, the checksum calculation circuit 201 calculates checksums s1 and s3.

[0056] The decoding unit 18 determines whether the values ​​of all checksums (checksums s1, s3) are 0 (step S103). When all checksums are 0 (step S103: Yes), the decoding process ends. This is because when all checksums are 0, it can be determined that there are no errors in the received characters.

[0057] When all checksums are not 0 (step S103: No), the decoding unit 18 determines whether s13 = s3 is satisfied (step S104). As mentioned above, determining whether s13 = s3 is satisfied is equivalent to determining whether the error count is 1. Furthermore, if s13 = s3 is not satisfied, it means that the error count is 2 or 3.

[0058] When s1 3 = s3 (error count is 1) (step S104: yes), the root calculation circuit 220 calculates the error position X1 when the error count is 1 (step S105).

[0059] When s1 3 = s3 (error count is 2 or 3) is not satisfied (step S104: No), the root calculation circuit 100 calculates one error pattern when the error count is 2 (step S106). Also, the root calculation circuit 100 calculates more than one error pattern when the error count is 3 (step S107). The root calculation circuit 100 generates a list containing error patterns when the error count is 2 and error patterns when the error count is 3 (step S108). However, steps S106 and S107 can be performed in reverse order or in parallel.

[0060] The selection circuit 210 selects the maximum likelihood error style from more than one error style contained in the generated list (step S109).

[0061] Bit-flipping circuit 230 corrects the bits at the error location (step S110). For example, when the error number is 2 or 3, bit-flipping circuit 230 corrects the error by flipping the bits at the error location included in the maximum likelihood error pattern selected by selection circuit 210. When the error number is 1, bit-flipping circuit 230 corrects the error by flipping the bits at the error location X1 calculated by root calculation circuit 220.

[0062] Figure 3 shows an example of generating lists containing error patterns for a count of 2 and error patterns for a count of 3 for list decoding. This example is applicable when it is impossible to determine whether the error count is 2 or 3.

[0063] (Modified Example) This section describes a variation where the error count can be determined to be 2 or 3. For example, in extended BCH codes, in addition to checksums s1 and s3, checksum s0 can also be calculated. Checksum s0 is 0 when the error count is even and 1 when the error count is odd. In this variation, the checksum calculation circuit 201 receives the receiving polynomial r(x), calculates the checksums s0, s1, and s3, and outputs them.

[0064] Figure 4 is a flowchart showing an example of the decoding process in the modified example. Steps S201, S203 to S205 are the same as steps S101, S103 to S105 in Figure 3, so the explanation is omitted.

[0065] In step S202, the checksum calculation circuit 201 receives the polynomial r(x) as input, calculates the checksums s0, s1, and s3, and outputs them (step S202).

[0066] In a variant example, when s1 3 = s3 is not satisfied (error count is 2 or 3) (step S204: No), the decoding unit 18 will further determine whether s0 = 0 is satisfied (step S206). Determining whether s0 = 0 is satisfied is equivalent to determining whether the error count is 2 (even number).

[0067] When s0=0 (error count is 2) (step S206: Yes), the root calculation circuit 100 calculates one error pattern when the error count is 2 (step S207). At this time, since the error count is known to be 2, this error pattern can be used as the maximum likelihood error pattern.

[0068] When s0=0 (error count is 3) is not satisfied (step S206: No), the root calculation circuit 100 calculates more than one error pattern when the error count is 3 (step S208). In a variant example, the root calculation circuit 100 generates a list containing error patterns when the error count is 3.

[0069] The selection circuit 210 selects the maximum likelihood error style from more than one error style contained in the generated list (step S209).

[0070] Bit-flipping circuit 230 corrects the bits at the error locations (step S210). For example, when the error count is 3, bit-flipping circuit 230 corrects the error by flipping the bits at the error locations included in the maximum likelihood error pattern selected by selection circuit 210. When the error count is 1, bit-flipping circuit 230 corrects the error by flipping the bits at the error location X1 calculated by root calculation circuit 220. When the error count is 2, bit-flipping circuit 230 corrects the error by flipping the bits at the two error locations included in one error pattern when the error count is 2, calculated by root calculation circuit 100 in step S207.

[0071] Next, an example of the configuration of the root calculation circuit 100 will be described. Figure 5 is a diagram showing an example of the configuration of the root calculation circuit 100.

[0072] The root calculation circuit 100 includes: arithmetic circuits 111, 112, 113, 114, 115, 116, LUT (lookup table) 121, 122, and arithmetic circuits 131, 132.

[0073] Each part within the root calculation circuit 100 performs the following operations individually. • Operational circuit 111: Outputs the cube power of the parity checker s1. • Operational circuit 112: Adds the output value of operational circuit 111 to the check s3, and outputs β (=s1 3+s3) as the result of the addition. ·LUT121: Use β as the key information and output r and αq corresponding to β. • LUT122: Takes the output r from LUT121 as the key information and outputs one or more error patterns eA corresponding to r. Each of the one or more error patterns eA contains a combination of transformed positions (X^1, X^2). • Operational circuit 131: Multiplies the transformed position X^1 contained in the error pattern eA output from LUT122 by αq output from LUT121, and outputs αqX^1 as the result of the multiplication. • Operational circuit 132: Multiplies the transformed position X^2 contained in the error pattern eA output from LUT122 by αq output from LUT121, and outputs αqX^2 as the result of the multiplication. • Operational circuit 113: Adds the output value of operational circuit 131 to the check s1, and outputs the result as the error position X1 (=αqX^1+s1). • Operational circuit 114: Adds the output value of operational circuit 132 to the check s1, and outputs the result as the error position X2 (=αqX^2+s1). • Operational circuit 115: Adds the output value of operational circuit 113 to the check s1 and outputs the sum X1+s1. • Operational circuit 116: Adds the output value X1+s1 of operational circuit 115 to the output value X2 of operational circuit 114, and outputs the result as the error position X3 (=X1+X2+s1).

[0074] LUT121 and LUT122 are equivalent to corresponding information that maps the multiple values ​​of the key information β and one or more error patterns eA to each other. Hereinafter, LUT121 will be referred to as table θ and LUT122 as table ψ.

[0075] αq and r are elements on the Galois body GF and integers from 0 to 2, respectively, and are pre-calculated as β = α³q + r. Based on the value of β, αq and r are each assigned one value. Furthermore, a combination of αq and r corresponds to a list of error patterns. A list of error patterns is a list containing more than one error pattern.

[0076] As described above, in this embodiment, variable transformations that reduce the amount of data in the lookup table are used. For example, variable transformations with three values ​​of r, from 0 to 2, are used. Examples of variable transformations will be described below.

[0077] If the elements on the Galois body GF of size 2m corresponding to the three error positions are taken as X1, X2, and X3, then the checkers s1 and s3 are represented by the following equation (4).

[0078] If the error location is found using a lookup table from these checksums s1 and s3, then the number of key information entries in the lookup table used as arguments is 2^2m-1. That is, a lookup table with a huge number of entries is required.

[0079] Therefore, in this embodiment, the variable transformation (affine transformation) shown in the following equation (5) is applied to the error position Xi (i=1, 2, 3). If this variable transformation is applied, the checksums s1 and s3 are transformed into s^1 and s^3 shown in the following equation (6).

[0080] Here, if B = As1, then equation (6) can be rewritten as equation (7).

[0081] As shown in equation (7), since s^1 is 0, the error position x^i after variable transformation can be represented by s^3 alone. That is, the key information of the lookup table can be made based solely on the value of s^3. Furthermore, when s1 3+s3=α3q+r is expressed, by making A=α-q, the checksum s^3 can be expressed as s^3=αr. In other words, the error position x^i after variable transformation can be represented solely by the exponent r.

[0082] That is, by using the exponent r, which is the value of s^3=αr that can be specifically transformed as A=α-q and B=As1, as the key information, the error pattern eA, which is the pattern of the error position x^i, can be listed by referring to the lookup table of the corresponding error position x^i.

[0083] Figure 6 is a diagram illustrating an example of the pseudocode corresponding to the function of obtaining the error pattern (X1,X2) containing the error positions X1 and X2 from the checkers s1 and s3 in the root calculation circuit 100.

[0084] The θ(β) in the second row is used to calculate the functions representing αq and r when β=s1 3+s3=α3q+r, which is equivalent to LUT121 (table θ).

[0085] The ψ(r) in the third line is a function that outputs one or more error patterns eA (a list of error patterns eA) for input r, containing the combination of transformed positions (X^1, X^2), and is equivalent to LUT122 (table ψ).

[0086] In lines 5 through 9, for each of more than one error pattern eA, an inverse variable transformation is performed relative to the transformed positions X^1 and X^2 to restore the error positions X1 and X2. Furthermore, the error pattern containing the combination (X1, X2) of the restored error positions X1 and X2 is appended to the pseudocode output (a list of error patterns). As shown in lines 6 and 7, the inverse variable transformation is represented by Xi = (Xi^+B) / A = αq × Xi^+s1.

[0087] Each entry in table θ contains αq∈GF(2m) and r∈{0,1,2}. Therefore, each entry contains m+2 bits of data, and even if the number of entries increases, the data volume of table θ will not be too large.

[0088] On the other hand, each entry in table ψ contains combinations of more than one error location (error patterns). Therefore, there is a possibility that the number of entries becomes C(2m-1,3) of combinations of 3 selected from 2m-1. Furthermore, the data volume of one error pattern is simply 3m bits. If the number of entries or the data volume of each entry can be reduced, the overall data volume of table ψ can be further reduced. Details regarding the function of reducing data volume will be explained after the second embodiment.

[0089] (Second Implementation) A second implementation method using a different variable transformation than described above is explained. In this implementation method, the affine transformation X^=X+s1 is used as the variable transformation. This variable transformation is equivalent to the variable transformation in equation (5) where A=1 and B=s1.

[0090] In this embodiment, the root calculation circuit 100 of the first embodiment is replaced by the root calculation circuit 100-2. Since other configurations are the same as in the first embodiment, the description is omitted.

[0091] Figure 7 shows a schematic diagram of a configuration example of the root calculation circuit 100-2. The root calculation circuit 100-2 includes: arithmetic circuits 111, 112, 113-2, 114-2, 115, 116, and LUT 121-2.

[0092] The root calculation circuit 100-2 differs from the root calculation circuit 100 in the functions of the arithmetic circuits 113-2, 114-2, and LUT 121-2, as well as the deletion arithmetic circuits 131 and 132. For configurations identical to those in the first embodiment, the same reference numerals are used and descriptions are omitted.

[0093] The operational circuits 113-2, 114-2, and LUT121-2 perform the following operations. • LUT121-2: Using β as the key information, output one or more error patterns eA corresponding to β. Each of the one or more error patterns eA contains a combination of transformed positions (X^1, X^2). • Operational circuit 113-2: Adds the converted position X^1 in the output of LUT121-2 to the check s1, and outputs the result as the error position X1 (=X^1+s1). • Operational circuit 114-2: Adds the converted position X^2 in the output of LUT121-2 to the check s1, and outputs the result as the error position X2 (=X^2+s1).

[0094] The following is a summary of the processing flow of the root calculation circuit 100-2. Calculate β = s1 3 + s3. Using β as the key information, from LUT121-2 that outputs more than one error pattern eA (the combination of transformed positions (X^1,X^2)), the error pattern eA corresponding to the calculated β is obtained. Adding s1 to X^1 and X^2 contained in the error pattern eA yields the error positions X1 and X2. The operation X = X^ + s1, which adds s1 to the transformed position X^, is equivalent to the inverse variable transformation. • The third error position X3 is obtained through X3=X1+X2+s1.

[0095] LUT121-2 also utilizes a key information β obtained through variable transformation. Therefore, compared to the simple method of directly using the checksum as the key information, the amount of data in the lookup table can be reduced. Furthermore, although a larger LUT121-2 is used in this embodiment, circuitry for multiplication operations in the later stages of the LUT (in the first embodiment, arithmetic circuits 131 and 132) is not required. That is, in the later stages of the LUT, since only circuitry for addition operations (arithmetic circuits 113-2, 114-2, 115, and 116) is used, a simpler configuration can be achieved.

[0096] The following details the methods for reducing the amount of data in table ψ. Examples of methods for reducing the amount of data include (DM1) to (DM3). (DM1) Calculate the error patterns of the remaining entries from the error patterns contained in one of the multiple entries. (DM2) Of the three error locations, one is calculated from the remaining two error locations. For example, as described above, the error location X3 is calculated by using the operations of error locations X1 and X2. This reduces the data size of one error pattern (a pattern containing a combination of two error locations) to 2m bits. Furthermore, by creating only one error location X1, the data size of one error pattern can also be m bits. In this case, X2 and X3 can be obtained using the following algorithm, which calculates the error pattern with error number 2 by using the contribution of the error location X1 contained in the error pattern to the checksum from the checksums s1 and s3, resulting in checksums s'1 = s1 - X1 and s'3 = s3 - X1 (e.g., the processing in step S106 of Figure 3). (DM3) For each entry, calculate the remaining error patterns from one of the multiple error patterns contained in the entry.

[0097] The following examples, using tables of BCH codes with correction capabilities of GF(24), GF(25), and GF(210) relative to 2 (t=2), illustrate methods for reducing data volume.

[0098] First, an example of obtaining a lookup table with reduced data on GF(24) using method (DM1) will be explained. Figure 8 is a diagram showing an example table when the original polynomial is transformed into p(x) = 1 + x + x⁴. Figure 8 corresponds to the table before reducing the data. However, this table is the same as the table in the second embodiment, which corresponds to the table when using the affine transformation X^ = X + s1.

[0099] In Figure 8, although two types of key information s^3 and exponent i are shown, either one can be used as key information. The value of s^3 in Figure 8 is equivalent to the integer value of the binary series of s^3. An error pattern is equivalent to one or more error patterns containing the combination (X^1, X^2, X^3) of the transformed positions. However, for ease of explanation, Figure 8 shows an error pattern containing the combination of three transformed positions. Furthermore, the value of the transformed positions in Figure 8 is represented by the exponent when the transformed positions (X^1, X^2, X^3) are expressed as powers of α.

[0100] The intervals of the three indices, which correspond to the three transformed positions, are regular. For example, the three intervals of the three indices for the entry in the first row of Figure 8 are shown below. • The first and second indices: the interval between 0 and 5 is 5. • The second and third indices: the interval between 5 and 10 is 5. • The third index and the first index: the interval from 10 to 0 is 5.

[0101] However, the interval from 10 to 0 is calculated by adding the value 15 of 0 to the entry number 15 in Figure 8, and using this as the value from 10 to 15. This is because the elements on GF(24) cycle with α15=α0=1.

[0102] The combination of index intervals mentioned above is represented as (5,5,5). In the table of Figure 8, there are three combinations of index intervals: (5,5,5), (2,6,7), and (1,3,11). These combinations are categorized as types TA, TB, and TC. The types TA, TB, and TC, and the index i representing the key information, are as follows. • Type TA=(5,5,5): Index i=0, 3, 6, 9, 12 • Category TB=(2,6,7): Index i=1,4,7,10,13 • Category TC=(1,3,11): Index i=2,5,8,11,14

[0103] It can be seen that when the index i is 3q, q=0, 1, 2, 3, 4, it is category TA; when the index i is 3q+1, q=0, 1, 2, 3, 4, it is category TB; and when i is 3q+2, q=0, 1, 2, 3, 4, it is category TC. Further referring to Figure 8, the error patterns for each category are obtained by adding q to the elements of the pattern where q=0. For example, the error pattern [1,6,11] with index i=3 is obtained by adding q=1 to the elements of the error pattern [0,5,10] with index i=0. Thus, since the pattern after q=1 is obtained using the value of q=0, the number of entries in the table can be reduced to 3 (15÷5=3, corresponding to r=0, 1, 2). Figure 9 is a diagram showing an example of the table ψ after reducing the number of entries. In the first embodiment, such a reduction in the amount of data (number of entries) can be achieved by making A=α-q.

[0104] Types TB and TC correspond to the exponent i for the three error patterns. Furthermore, the remaining error patterns can be calculated from one of these three error patterns. This calculation is equivalent to the method described above (DM3).

[0105] For example, index i=1 (category TB) corresponds to the following 3 error patterns. ·[12,14,5] ·[2,4,10] ·[7,9,0]

[0106] The first element (12, 2, 7) of the three error patterns is spaced 5 times. Therefore, the other two error patterns can be calculated from one error pattern using the rule of 5-times intervals. In this case, for example, a table ψ can be constructed using information about the display type (e.g., 2 bits) and an exponent r corresponding to one error pattern, instead of three error patterns. That is, the amount of data in table ψ can be reduced.

[0107] The method (DM3) is further explained. Consider the error polynomial e(x) where the checksum s^1 after variable transformation is 0. However, the error polynomial e(x) represents the error vector, not the error position polynomial. The checksum s^1 substitutes α into the value e(α) of the error polynomial. Therefore, if s^1 = e(α) = 0, e(x) takes the minimal polynomial M1(x) = p(x) of α as its factor. That is, it can be expressed as e(x) = M1(x) × q(x) mod x15 + 1. With such an error polynomial, the error pattern of ψ can be rewritten in the following way, for example. However, the following shows examples of rewriting the error patterns corresponding to exponents r = 0, 1, and 2. • Exponent r=0: M1(x)(1+x+x2)(1+x3+x4) • Exponent r = 1: (M1(x))²x¹², (M1(x))²x², (M1(x))²x⁷ • Exponent r=2: M1(x)x4, M1(x)x14, M1(x)x9

[0108] Thus, each error pattern contains a factor of M1(x). Furthermore, entries with exponents r=1 and 2 each contain three error polynomials. Also, by multiplying the first of the three error polynomials by a fixed number, the remaining two error polynomials can be calculated.

[0109] For example, in the case of exponent r=1, if we make... e1(x)=((M1(x))2x12, Then x5e1(x) = ((M1(x))2x2 mod x15+1 x10e1(x)=((M1(x))7x7 mod x15+1 Therefore, it is sufficient to store only one erroneous polynomial as a representative in table ψ. This reduces the amount of data in table ψ.

[0110] Next, the table ψ over GF(25) will be explained. Figure 10 is a diagram showing an example of the table ψ when the original polynomial is converted to p(x) = 1 + x² + x⁵. In Figure 10, only the exponent r is shown as key information. The exponent r can be any of 0, 1, or 2.

[0111] The five error patterns of exponent r=0 can be represented by error polynomials as follows. M1(x)x4q1(x), M1(x)x8, ((M1(x))2x16, M1(x)x2q2(x), ((M1(x))4x

[0112] However, M1(x) = p(x), q1(x), and q2(x) are represented as follows. q1(x)=1+x+x2+x3+x4+x7+x8+x10+x13 q2(x) = 1 + x2 + x4 + x5 + x6 + x8 + x11

[0113] Here, the five polynomials corresponding to the exponent r=0 are sequentially represented as e1(x), e2(x), e3(x), e4(x), and e5(x). If this polynomial is used, the error patterns of exponents r=0, 1, and 2 are represented as follows. • Exponent r=0: e1(x), e2(x), e3(x), e4(x), e5(x) • Exponent r=1: e1(x)x21、e2(x)x21、e3(x)x21、e4(x)x21、e5(x)x21 • Exponent r=2: e1(x)x11, e2(x)x11, e3(x)x11, e4(x)x11, e5(x)x11

[0114] In other words, error patterns with exponents r=1 and 2 can be generated as a fixed multiple of the error patterns with exponent r=0. Therefore, table ψ only needs to record the error patterns with exponent r=0. Thus, for table ψ on GF(25), the amount of data in table ψ can be reduced by the above method (DM1).

[0115] However, for GF(25) and beyond, the same regularity exists, so this regularity can be used to reduce the amount of data in table ψ. For example, when m in GF(2m) is even, since the cube root of 1 is included in the element, there exists the following erroneous polynomial. However, the "^" in the following expression indicates the power of the value within the parentheses on the right. 1+x^((2m-1) / 3)+x^(2(2m-1) / 3)

[0116] Furthermore, for a complex number of entries, polynomials multiplied by α^((2m-1) / 3) and α^(2(2m-1) / 3) are presented. Therefore, it is possible to compute other error patterns from one error pattern.

[0117] Next, let's explain the table ψ on GF(210). The original polynomial is p(x) = 1 + x + x² + x³ + x⁵ + x⁶ + x¹⁰. The number of error patterns corresponding to exponents r = 0, 1, and 2 are 181, 165, and 165 respectively. Since the multiplication of the cubic root can generate three different error polynomials, the number of error patterns recorded in table ψ can be reduced to one-third of the above. Specifically, the number of error patterns is 61, 55, and 55. The reason for 61 for r = 0 is that the original 181 error patterns include those where the error position remains unchanged even after multiplying α³⁴¹ and α⁶⁸², and the error positions are spaced 341 apart. Therefore, removing that 180 results in one-third, which is (180 ÷ 3 + 1 = 61). Furthermore, since the square power of the error patterns in the table with r=2 is equivalent to that in the table with r=1, the table ψ only needs r=0 and r=1. The pseudocode of the specific algorithm using the table with r=0 and r=1 is shown in Figure 11. Moreover, it is also possible to generate 61 and 51 error patterns respectively from 13 and 11 error patterns through computation. The pseudocode of such an algorithm is shown in Figure 12. In Figure 12, Φj0 and Φj1 are Φj0(x)=x^(2j) and Φj1(x)=α^((1-4j) / 3)x^(4j), respectively. By generating 5 patterns from each of the 12 patterns out of the 13 patterns using Φj0, 12×5+1=61 patterns are created. Also, by generating 5 patterns from each of the 11 patterns using Φj1, 11×5=55 patterns are created. Subsequently, by multiplying 1, α^341, and α^682, 181 patterns or 165 patterns are generated. Thus, by using the operations Φj 0 and Φj 1, the number of error patterns recorded in table ψ can be made 13 and 11, respectively. However, the operations Φj 0 and Φj 1 shown here are an example on GF(210), and different operations are performed on other sizes of GF.

[0118] Thus, in this embodiment, by utilizing variable transformation, a (specific) error location can be represented using only one key piece of information. That is, the number of entries in the lookup table can be reduced, and the amount of data in the lookup table can be reduced. Furthermore, in this embodiment, when representing the error pattern using an error polynomial, utilizing items with common factors in the error polynomial can further reduce the amount of data in the lookup table.

[0119] As explained above, based on the first and second embodiments, error correction (decoding) can be performed with a simpler configuration.

[0120] While several embodiments of the invention have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are all included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and their equivalents.

[0121] 1: Memory System 10: Memory controller 11: Control Department 12: Data Buffer 13: Memory I / F 14: Encoding / Decoding Section 15: Host I / F 16: Internal bus 17: Coding Department 18: Decoding Department 20: Non-volatile memory 30: Host 100,100-2,220: Root calculation circuit 201: Verification circuit 210: Selection Circuit 230: Bit Flip Circuit

Claims

1. A memory system comprising: a memory and a controller, the memory storing data encoded by an error correction code for correcting errors of t bits or less (t being an integer greater than or equal to 2), the controller reading received characters from the memory, calculating at least t checksums using the read received characters, calculating (t-1) key information by performing variable transformations on the calculated checksums, the (t-1) key information being used to obtain one or more first error patterns, each of the one or more first error patterns comprising a combination of a plurality of transformed positions obtained by applying the aforementioned variable transformations to a plurality of error positions when the number of error bits is (t+1), and obtaining one or more of the aforementioned first error patterns corresponding to the calculated key information by using the plurality of values ​​obtainable from the aforementioned key information and the corresponding information of the one or more aforementioned first error patterns. Perform inverse variable transformation on the transformed positions contained in each of the more than one first error patterns to calculate the aforementioned error positions, obtain a list containing more than one second error pattern, each of the more than one second error pattern containing a combination of the calculated aforementioned error positions, and perform list decoding using the aforementioned list.

2. The memory system as described in claim 1, wherein, t is 2, and there are t aforementioned checksums, including: checksum s1 corresponding to the first power sum of the primitive elements of the Galois body, and checksum s3 corresponding to the third power sum of the primitive elements. By performing the aforementioned variable transformations on the aforementioned checksums s1 and s3, one key information for obtaining one or more of the aforementioned first error patterns is calculated, and each of the one or more of the aforementioned first error patterns contains three error positions.

3. The memory system as described in claim 2, wherein, The aforementioned variables are converted into affine transformations.

4. The memory system as described in claim 3, wherein, The aforementioned affine transformation, when representing the aforementioned error position as X, the aforementioned transformed position as X^, and representing β=s13+s3=α3q+r (q and r are integers above 0), is represented by X^=AX+B, A=α-q, B=As1, the aforementioned key information is r, and the aforementioned controller obtains the aforementioned error position X by the aforementioned variable inverse transformation represented by X=(X^+B) / A=αq×X^+s1.

5. The memory system as described in claim 3, wherein, The aforementioned affine transformation, when representing the aforementioned error position as X and the aforementioned transformed position as X^, is represented by X^=X+s1. The aforementioned key information is β=s13+s3. The aforementioned controller obtains the aforementioned error position X by the aforementioned variable inverse transformation represented by X=X^+s1.

6. The memory system as described in claim 2, wherein, The aforementioned controller, when the number of errors is 2 or 3, in addition to the aforementioned first error pattern which includes a combination of 3 error positions, also obtains the aforementioned list which includes a single error pattern, the single error pattern including a combination of the aforementioned error positions when the number of errors is 2.

7. The memory system as described in claim 2, wherein, t is 2, and there are t aforementioned checkers, including: checker s1 corresponding to the sum of the first power of the primitive elements of the Galois body, checker s3 corresponding to the sum of the third power of the primitive elements, and checker s0 which is 0 when the number of errors is even. The aforementioned controller uses the aforementioned checker s0 to determine whether the number of errors is 2. When the number of errors is not 2, it obtains the aforementioned list containing one or more of the aforementioned first error patterns, each of which contains a combination of 3 error positions.

8. The memory system as described in claim 1, wherein, The controller, among the aforementioned second error patterns included in the aforementioned list, selects the aforementioned second error pattern whose reliability as the error location is greater than that of the other aforementioned second error patterns, and corrects the error at the error location included in the selected aforementioned second error pattern.

9. The memory system as described in claim 1, wherein, The aforementioned memory and controller are connected via an interface conforming to the Toggle DDR (Double Data Rate) specification.

10. The memory system as described in claim 1, wherein, The aforementioned memory and controller are connected via an interface conforming to the ONFI (Open NAND Flash Interface) specification.

11. A controller reads received characters from memory storing data encoded by an error correction code for correcting errors of t bits or less (t being an integer greater than or equal to 2); calculates at least t checksums using the read received characters; calculates (t-1) key information by performing variable transformations on the calculated checksums, the (t-1) key information being used to obtain one or more first error patterns, each of the one or more first error patterns comprising a combination of multiple transformed positions obtained by applying the aforementioned variable transformations to multiple error positions when the number of error bits is (t+1); obtains one or more of the aforementioned first error patterns corresponding to the calculated key information using correspondence information that corresponds to multiple values ​​obtainable from the aforementioned key information and the one or more aforementioned first error patterns; and performs inverse variable transformations on the transformed positions contained in each of the one or more aforementioned first error patterns to calculate the aforementioned error positions. Find a list containing one or more second error patterns, each of which contains a combination of the calculated error positions, and perform list decoding using the aforementioned list.

12. A control method for controlling memory, comprising: storing data encoded by an error correction code in memory, the error correction code being used to correct errors of t bits or less (t being an integer greater than 2); reading received characters from the memory; calculating at least t checksums using the read received characters; calculating (t-1) key information by performing variable transformations on the calculated checksums, the (t-1) key information being used to obtain one or more first error patterns, each of the one or more first error patterns comprising a combination of a plurality of transformed positions obtained by applying the aforementioned variable transformations to a plurality of error positions when the number of error bits is (t+1); and obtaining one or more of the aforementioned first error patterns corresponding to the calculated key information by using the plurality of values ​​obtainable from the aforementioned key information and the corresponding information of the one or more aforementioned first error patterns. Perform inverse variable transformation on the transformed positions contained in each of the more than one first error patterns to calculate the aforementioned error positions, obtain a list containing more than one second error pattern, each of the more than one second error pattern containing a combination of the calculated aforementioned error positions, and perform list decoding using the aforementioned list.

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