COT step-down converter

Abstract

This invention provides a Constant-On-Time (COT) buck converter, comprising: an inductor current detection circuit configured to detect the inductor current flowing through an inductor connected to the system output terminal of the COT buck converter output system output voltage, and to generate a current zero-crossing detection signal indicating whether the inductor current has crossed zero, wherein the inductor current crossing zero means that the inductor current changes from a positive current to a negative current; and a sleep mode control circuit configured to generate a sleep mode control signal for controlling one or more circuit modules in the COT buck converter to change from an operating state to a closed state based on the current zero-crossing detection signal, an output feedback voltage characterizing the system output voltage of the COT buck converter, and a predetermined reference voltage.

Claims

1. A COT buck converter, comprising: An inductor current detection circuit is configured to detect the inductor current flowing through an inductor connected to the system output terminal of the COT buck converter output system output voltage, and generate a zero-crossing current detection signal indicating whether the inductor current has crossed zero, wherein the inductor current crossing zero means that the inductor current changes from a positive current to a negative current; and a sleep mode control circuit is configured to generate a sleep mode control signal for controlling one or more circuit modules in the COT buck converter to change from an operating state to a closed state based on the zero-crossing current detection signal, an output feedback voltage characterizing the system output voltage of the COT buck converter, and a predetermined reference voltage.

2. The COT buck converter as described in claim 1, wherein, When the current zero-crossing detection signal indicates that the inductor current has crossed zero and a first predetermined time has elapsed, the sleep mode control signal switches from the first quasi-state to the second quasi-state to control one or more circuit modules in the COT buck converter to change from the working state to the off state.

3. The COT buck converter as described in claim 2, wherein, When the output feedback voltage is lower than the predetermined reference voltage, the sleep mode control signal switches from the second level state to the first level state to control one or more circuit modules in the COT buck converter to change from the off state to the working state.

4. The COT buck converter as described in claim 1, wherein, The sleep mode control circuit is also configured to generate a sleep mode indication signal based on the current zero-crossing detection signal, the output feedback voltage, and the predetermined reference voltage, for instructing the COT buck converter to enter or exit sleep mode.

5. The COT buck converter as described in claim 4, wherein, When the current zero-crossing detection signal indicates that the inductor current has crossed zero and a first predetermined time has elapsed, the sleep mode indication signal switches from the first quasi-state to the second quasi-state to indicate that the COT buck converter enters sleep mode.

6. The COT buck converter as described in claim 5, wherein, When the output feedback voltage is lower than the predetermined reference voltage for a second predetermined duration, the sleep mode indication signal switches from the second level state to the first level state to indicate that the COT buck converter exits the sleep mode.

7. The COT buck converter as described in claim 5, wherein, The first predetermined duration is longer than the operating clock cycle of the COT buck converter in continuous current mode.

8. The COT buck converter as described in claim 6, wherein, The second predetermined duration is related to the internal circuit setup time of the COT buck converter.

9. The COT buck converter as described in claim 4, further comprising: The on-time generation circuit is configured to generate a second pulse signal with a fixed pulse width based on a first pulse signal from the sleep mode control circuit. The logic control circuit is configured to generate a pulse width modulation signal for controlling the on / off state of the high-side power transistor and the low-side power transistor in the COT buck converter based on the second pulse signal and the current zero-crossing detection signal, wherein the high-side power transistor and the low-side power transistor are connected between the input line voltage and ground of the COT buck converter, the inductor is connected between the midpoint between the high-side power transistor and the low-side power transistor and the system output of the COT buck converter, and the sleep mode control circuit is further configured to generate the first pulse signal based on the sleep mode indication signal.

10. The COT buck converter as claimed in claim 5, wherein, The sleep mode control circuit is also configured to generate the first pulse signal when the sleep mode indication signal switches from the second level state to the first level state.

11. The COT buck converter as claimed in claim 9, further comprising: A ripple compensation generating circuit is configured to generate a first ripple compensation voltage and a second ripple compensation voltage; a comparator is configured to generate a comparison result signal based on the first ripple compensation voltage, the second ripple compensation voltage, the output feedback voltage, and the predetermined reference voltage; and a first logic OR gate is configured to generate a first logic OR result signal based on the comparison result signal and the first pulse signal, wherein the on-time generating circuit is further configured to generate the second pulse signal based on the first logic OR result signal.

12. The COT buck converter as claimed in claim 11, further comprising: The second logic OR gate is configured to generate a second logic OR result signal based on the second pulse signal and the comparison result signal, wherein the logic control circuit is further configured to generate the pulse width modulation signal based on the second logic OR result signal and the current zero-crossing detection signal.

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