One-time programmable memory cell and one-time programmable memory array

Abstract

This disclosure discloses a one-time programmable (OTP) memory cell including an antifuse element and a selection circuit. The antifuse element includes a first terminal, a second terminal coupled to a programming line, and a gate terminal. The selection circuit is coupled to the first terminal of the antifuse element, a word line, and a bit line. The selection circuit controls the electrical connection between the bit line and the first terminal of the antifuse element based on the voltage of the word line. The one-time programmable memory cell is programmed through a programming operation, and the channel between the first and second terminals of the antifuse element is damaged due to the programming operation.

Description

[Technical Field]

[0001] This disclosure relates to a one-time programmable memory device, and more particularly to a one-time programmable memory device with a low programming voltage. [Previous Technology]

[0002] With the continuous advancement of semiconductor manufacturing processes, the size of transistors has also shrunk significantly. Smaller transistors not only reduce circuit area but also allow for lower operating voltages, thereby improving power efficiency. However, the continued reduction in transistor size also brings new challenges, particularly the issue of decreased voltage tolerance.

[0003] For example, when manufacturing one-time programmable (OTP) memory cells using advanced nodes, the programming process may face some challenges. Traditional programming operations typically require applying high voltages to the transistor gates on the channel. However, in advanced nodes, these voltages may exceed the junction breakdown voltage of the transistor, resulting in poor programming efficiency or even failure. Therefore, how to develop one-time programmable memory cells that utilize advanced nodes and operate efficiently at lower voltages has become a key issue in this field.

[0004] This “Background Discussion” section provides background information only. The statements in this “Background Discussion” section are not an admission that the subject matter disclosed in this section constitutes prior art to this disclosure, and no part of this background discussion section should be used as an admission of any part of this specification, including the discussion in the background section, which constitutes prior art to this disclosure. [Summary of the Invention]

[0005] One embodiment of this disclosure provides a one-time programmable memory (OTP) cell. The OTP cell includes an antifuse element and a selection circuit. The antifuse element includes a first terminal, a second terminal coupled to a programming line, and a gate terminal. The selection circuit is coupled to the first terminal of the antifuse element, a word line, and a bit line. The selection circuit controls the electrical connection between the bit line and the first terminal of the antifuse element based on the voltage of the word line. When the OTP memory is programmed via a programming operation, the channel between the first and second terminals of the antifuse element is damaged.

[0006] Another embodiment of this disclosure provides an one-time programmable memory array. The one-time programmable memory array includes a first one-time programmable memory cell and a second one-time programmable memory cell. The first one-time programmable memory cell includes a first antifuse element and a first selection circuit. The first antifuse element includes a first terminal, a second terminal coupled to a first programming line, and a gate terminal. The first selection circuit is coupled to the first terminal of the first antifuse element, a first word line, and a first bit line. The first selection circuit controls the electrical connection between the first bit line and the first terminal of the first antifuse element based on the voltage of the first word line. The second one-time programmable memory cell includes a second antifuse element and a second selection circuit. The second antifuse element includes a first terminal, a second terminal coupled to the first programming line, and a gate terminal. The second selection circuit is coupled to the first terminal of the second antifuse element, the first word line, and a second bit line. The second selection circuit controls the electrical connection between the second bit line and the first terminal of the second antifuse element based on the voltage of the first word line. When the first one-time programmable memory unit is programmed through a programming operation, the channel between the first and second terminals of the first antifuse element will be damaged due to the programming operation.

Implementation Method

[0018] FIG1 shows an one-time programmable (OTP) memory cell 100 according to one embodiment of the present disclosure. The one-time programmable memory cell 100 includes an antifuse element 110 and a selection circuit 120. The antifuse element 110 includes a first terminal 110a, a second terminal 110b coupled to a programming line PL, and a gate terminal 110c. The selection circuit 120 is coupled to the first terminal 110a of the antifuse element 110, a word line WL, and a bit line BL. The selection circuit 120 controls the electrical connection between the bit line BL and the first terminal 110a of the antifuse element 110 based on the voltage of the word line WL.

[0019] In the embodiment shown in FIG1, the selection circuit 120 may include a selection transistor 122, which includes a first end 122a coupled to the bit line BL, a second end 122b coupled to the first end 110a of the antifuse element 110, and a gate end 122c coupled to the bit line WL.

[0020] In the initial stage, the one-time programmable memory unit 100 may have a first state (i.e., an initial state), which may, for example but not limited to, correspond to the bit value "0". After a programming operation of the one-time programmable memory unit 100, the one-time programmable memory unit 100 may be programmed to have a second state, which may, for example but not limited to, correspond to the bit value "1". In some embodiments, the programming operation may damage the channel between the first terminal 110a and the second terminal 110b of the antifuse element 110, resulting in a short-channel effect and causing a change in the resistance of the channel. Therefore, during a read operation of the one-time programmable memory unit 100, the second terminal 110b may be a drain receiving a high voltage, and the damaged channel may cause a high-order critical leakage current from the second terminal 110b to the first terminal 110a. If the one-time programmable memory unit 100 has not been programmed, no leakage current will be generated, so during a read operation, the bit value stored in the one-time programmable memory unit 100 can be read by sensing the read current.

[0021] Figure 2 shows the voltage supplied to the one-time programmable memory unit 100 during the programming operation according to one embodiment of the present disclosure. During the programming operation, the bit line BL may receive voltage VSS, the word line WL may receive voltage VDD, the programming line PL may receive voltage VPP, and the gate terminal of the antifuse element 110 may receive voltage VAF or be floating. Voltage VPP may be greater than voltage VDD, and voltage VDD may be greater than voltage VSS and voltage VAF. In some embodiments, voltage VSS may be ground voltage, such as 0V, and voltage VDD may be the power supply voltage of the one-time programmable memory unit 100, and may be in the range of 0.3V to 1.2V. In some embodiments, voltage VPP may be in the range of 2V to 6V, and voltage VAF may be in the range of -0.5V to 0.5V, such as 0V.

[0022] In this case, during programming operations, the select transistor 122 can be turned on, allowing the first terminal 110a of the antifuse element 110 to receive voltage VSS through the select transistor 122 and bit line BL. Therefore, when a high voltage VPP is applied to the second terminal 110b of the antifuse element 110, it may cause high-density defects in the channel between the first terminal 110a and the second terminal 110b, or damage to the gate oxide at the gate terminal 110c. In some embodiments, both density defects in the channel and damage to the gate oxide can cause leakage during read operations, thereby allowing the programmed one-time programmable memory unit 100 to be distinguished from the unprogrammed one-time programmable memory unit 100.

[0023] Figure 3 shows the voltage supplied to the one-time programmable memory unit 100 during the read operation according to one embodiment of the present disclosure. During the read operation, the bit line BL receives a first voltage VSS, the word line WL receives a voltage VDD, the programming line PL receives a voltage VR, and the gate terminal 110c of the antifuse element 110 may be floating. The voltage VR is greater than or equal to the voltage VDD and may be in the range of 0.3V to 2V. For example, the voltage VDD may be 0.4V and the voltage VR may be 0.8V.

[0024] During the read operation, the select transistor 122 can be turned on, allowing the first terminal 110a of the antifuse element 110 to receive voltage VSS through the select transistor 122 and the bit line BL. At this time, if the channel between the first terminal 110a and the second terminal 110b of the antifuse element 110 has been damaged during the programming operation, the voltage VR applied to the second terminal 110b of the antifuse element 110 will cause a subcritical leakage current (or tunneling current), which will flow from the second terminal 110b of the antifuse element 110 to the first terminal 110a. In this way, a significant current can be sensed from the bit line BL.

[0025] In addition, in some embodiments, if the gate oxide at the gate end 110c of the antifuse element 110 is damaged during programming operation, the gate end 110c may be charged to a higher voltage, thereby turning on the antifuse element 110 and contributing a significant current on the bit line BL.

[0026] In other words, during programming operations, two different programming mechanisms may occur, both of which can contribute to the read current during read operations: one is channel damage, and the other is gate oxide damage. In this embodiment, the gate terminal 110c of the antifuse element 110 may float during read operations, so the read current caused by both programming mechanisms can contribute to the final read current. However, this disclosure is not limited to this. In some cases, special care may be required in circuit design to ensure that the gate terminal 110c is floating and unaffected by other signals, which may not always be desirable. Therefore, in some embodiments, the gate terminal 110c of the antifuse element 110 may receive a voltage VAF during read operations. In this case, since the gate terminal 110c is coupled to a voltage VAF close to 0V, the gate oxide damage programming mechanism may not affect the final read current. However, the channel damage programming mechanism can still cause a significant read current during read operations, sufficient to identify the bit value of the one-time programmable memory cell 100.

[0027] Figure 4 shows the relationship between the programming time and read current of the one-time programmable memory unit 100 according to one embodiment of the present disclosure. As shown in Figure 4, if the one-time programmable memory unit 100 has not yet been programmed, no read current can be observed or only a negligible read current can be observed. However, when the programming time of the programming operation reaches 2 μs, a read current of 50 μA can be observed.

[0028] Furthermore, it can be noted that when the programming time of the programming operation reaches 3 seconds, the read current further increases to a saturation value of approximately 280A. This significant increase in read current is mainly due to the subcritical leakage current caused by defects in the channel of the antifuse element 100 during the programming operation. In some embodiments, in order to utilize the high read current to assist in identifying the bit values ​​stored in the one-time programmable memory unit 100, the programming operation can be extended to more than 3 μs or long enough to ensure that the channel of the antifuse element 110 is damaged. However, this disclosure is not limited to this. In some embodiments, the read current caused by gate oxide damage is also large enough for bit value identification, so the programming operation time can be reduced to, for example, 1 or 2 μs.

[0029] Figure 5 shows the relationship between the gate voltage applied to the gate terminal 110c of the antifuse element 110 and the read current of the one-time programmable memory cell 100 during a read operation according to one embodiment of the present disclosure. In Figure 5, the solid line L1 indicates that the one-time programmable memory cell 100 has been programmed for more than 3 μs, while the dashed line L2 indicates that the one-time programmable memory cell 100 has not been programmed.

[0030] As shown in Figure 5, if the one-time programmable memory cell 100 is not yet programmed, the read current will not become significant until the gate voltage reaches the critical voltage (e.g., 0.3 V) of the antifuse element 110. However, if the one-time programmable memory cell 100 has been previously programmed, the current density can reach 10⁻⁴ A / μm even with a gate voltage of 0 V. Therefore, in some embodiments, the gate voltage applied to the gate terminal 110c of the antifuse element 110 can be set to 0 V for read operations because the difference between the read current generated by the programmed one-time programmable memory cell and the read current generated by the unprogrammed one-time programmable memory cell is significant enough to be perceived.

[0031] In this embodiment, since channel damage is the main programming mechanism causing the read current in the read operation, and the voltage applied to the antifuse element 110 to damage the channel of the antifuse element 110 in the programming operation can be relatively low (e.g., 2V to 6V), the programming operation can still be effectively performed on the antifuse element 110 which is small in size and has a low junction collapse voltage.

[0032] In this case, the antifuse element 110 may be a transistor manufactured using an advanced process node. Figure 6 shows a three-dimensional architecture diagram of a one-time programmable memory cell 100 according to one embodiment of the present disclosure. In the embodiment shown in Figure 6, both the antifuse element 110 and the transistor 122 are implemented using a gate all around (GAA) field-effect transistor (FET).

[0033] As shown in Figure 6, the first end 110a can be the source of the antifuse element 110, and the second end 110b can be the drain of the antifuse element 110. The source and drain of the antifuse element 110 are located at the two ends of the gate end 110c of the gate structure G1, and the gate structure G1 surrounds the channel CH1, which is connected between the source and drain of the antifuse element 110.

[0034] Additionally, the first end 122a of the selector transistor 122 can be the source of the selector transistor 122, and the second end 122b can be the drain of the selector transistor 122. The source and drain of the selector transistor 122 are located at both ends of the gate end 122c of the gate structure G2, and the gate structure G2 surrounds the channel (not shown), which connects the source and drain of the selector transistor 122. In this embodiment, the source of the antifuse element 110 and the drain of the selector transistor 122 can be formed in a combined region; however, this disclosure is not limited thereto. In some embodiments, the source of the antifuse element 110 and the drain of the selector transistor 122 can also be separate from each other.

[0035] Figure 7 shows a cross-sectional view of the antifuse element 110 cut along line AA' in Figure 6. In this embodiment, the antifuse element 110 can be an N-channel metal oxide silicon (NMOS) transistor. In this case, the first terminal 110a (i.e., the source) and the second terminal 110b (i.e., the drain) can be doped with N-type carriers, while the channel CH1 is lightly doped with P-type carriers. Both the source and drain can be disposed on the substrate 140.

[0036] The gate structure G1 includes a dielectric layer 112 and a gate layer 114 surrounded by the dielectric layer 112. The dielectric layer 112 may include silicon oxide, silicon nitride, or a high-k dielectric material. The gate layer 114 may include polysilicon or a metal gate electrode. The gate structure G1 is disposed between a first end 110a (i.e., the source) and a second end 110b (i.e., the drain), a spacer wall 116 is disposed between the gate structure G1 and the first end 110a, and a spacer wall 118 is disposed between the gate structure G1 and the second end 110b.

[0037] Furthermore, in Figure 7, the one-time programmable memory cell 100 is in a read operation, so the second terminal 110b receives voltage VR, while the first terminal 110a receives voltage VSS. At this time, the depletion region DP1 in the channel CH1 can extend from the second terminal 110b to a region close to the first terminal 110a. This is caused by the short channel length of the antifuse element 110, for example, less than 20 nm, so the programming operation during the programming operation can damage the channel CH1. As a result, a high subcritical leakage current (or tunneling current) will be generated during the read operation.

[0038] Although the antifuse element 110 and the select transistor 122 are implemented using a GAAFET in the embodiment shown in FIG. 6, this disclosure is not limited thereto. In some embodiments, the antifuse element may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a diode. Furthermore, in some embodiments, the antifuse element 110 may also be implemented using other advanced processes. For example, the antifuse element 110 may be a FinFET, a junctionless FET, or a nanosheet FET. Additionally, in some embodiments, while advanced nodes may be used to fabricate the antifuse element, the select circuit 120 of the select transistor 122 may be fabricated using mature nodes.

[0039] FIG8 shows a one-time programmable memory unit 200 according to another embodiment of the present disclosure. The one-time programmable memory unit 200 differs from the one-time programmable memory unit 100 in that the selection circuit 220 of the one-time programmable memory unit 200 includes a selection transistor 222 and a follower transistor 224. Specifically, the selection transistor 222 includes a first terminal 222a and a second terminal 222b coupled to the bit line BL, and a control terminal 222c coupled to the word line WL. The follower transistor 224 includes a first terminal 224a coupled to the second terminal 222b of the selection transistor 222, a second terminal 224b coupled to the first terminal 110a of the antifuse element 110, and a gate terminal 224c coupled to the follower line FL.

[0040] In this embodiment, the follower transistor 224 can reduce the cross voltage applied to the select transistor 222, thereby reducing gate-induced drain leakage (GIDL) and preventing breakdown current. In some embodiments, the one-time programmable memory unit 200 can receive the same voltage as shown in FIG. 2 to perform a programming operation, and the follower line FL can receive a voltage VDD2 between voltage VDD and voltage VPP. Additionally, the one-time programmable memory unit 200 can receive the same voltage as shown in FIG. 3 to perform a read operation, and the follower line FL can receive voltage VDD.

[0041] In some embodiments, to further reduce GIDL, the channels of the follower transistor 224 may employ lighter doping. On the other hand, the channel doping concentration of the antifuse element 110 may be higher, making the channels more susceptible to damage during programming operations. In some embodiments, the channel doping concentration of the antifuse element 110 may be higher than the channel doping concentration of the follower transistor 224 and the channel doping concentration of the select transistor 222. However, this disclosure is not limited thereto.

[0042] FIG9 shows a one-time programmable memory array 20 according to one embodiment of the present disclosure. The one-time programmable memory array 20 includes a plurality of one-time programmable memory cells 200_1_1 to 200_M_N arranged in an MxN array, where M and N are integers greater than 1. In this embodiment, each one-time programmable memory cell 200_1_1 to 200_M_N may have the same structure as the one-time programmable memory cell 200 shown in FIG8.

[0043] As shown in Figure 9, one-time programmable memory units arranged in the same column can be connected to the same bit line, and one-time programmable memory units arranged in the same column can be connected to the same word line, the same follow line, the same antifuse line and the same programming line.

[0044] For example, one-time programmable memory units 200_1_1, 200_1_2, and 200_1_N are arranged in the same column. In this case, the antifuse element 210_1_1 in the one-time programmable memory unit 200_1_1 includes a first terminal, a second terminal coupled to the programming line PL1, and a gate terminal coupled to the antifuse line AF1. In addition, a selection circuit 220_1_1 including a select transistor 222 and a follower transistor 224 is connected to the first terminal of the antifuse element 210_1_1, the word line WL1, the follower line FL1, and the bit line BL1. The selection circuit 220_1_1 controls the electrical connection between the bit line BL1 and the first terminal of the antifuse element 210_1_1 according to the voltage of the word line WL1.

[0045] Furthermore, the antifuse element 210_1_2 in the one-time programmable memory unit 200_1_2 includes a first terminal, a second terminal coupled to the programming line PL1, and a gate terminal coupled to the antifuse line AF1. Additionally, the selection circuit 220_1_2 is coupled to the first terminal of the antifuse element 210_1_2, the word line WL1, the follower line FL1, and the bit line BL2. The selection circuit 220_1_2 controls the electrical connection between the bit line BL2 and the first terminal of the antifuse element 210_1_2 based on the voltage of the word line WL1. Similarly, the antifuse element 210_1_N is coupled to the bit line BLN, the word line WL1, the follower line FL1, the antifuse line AF1, and the programming line PL1.

[0046] Furthermore, the one-time programmable memory units 200_1_1, 200_2_1, and 200_M_1 are arranged in the same column. In this case, the antifuse element 210_2_1 in the one-time programmable memory unit 200_2_1 includes a first terminal, a second terminal coupled to the programming line PL2, and a gate terminal coupled to the antifuse line AF2. In addition, the selection circuit 220_2_1 is coupled to the first terminal of the antifuse element 210_2_1, the word line WL2, the follower line FL2, and the bit line BL1. The selection circuit 220_2_1 controls the electrical connection between the bit line BL1 and the first terminal of the antifuse element 210_2_1 according to the voltage of the word line WL2. Similarly, the antifuse element 210_M_1 is coupled to the bit line BL1, the word line WLM, the follower line FLM, the antifuse line AFM, and the programming line PLM.

[0047] Through the arrangement of the one-time programmable memory array 200, each one-time programmable memory cell 200_1_1 to 200_M_N can be independently programmed and read. For example, when programming the one-time programmable memory cell 200_1_1, a voltage VSS can be applied to the bit line BL1, a voltage VDD can be applied to the word line WL1, a voltage VDD2 can be applied to the follower line FL1, and a programming voltage VPP can be applied to the programming line PL1. In addition, a voltage VAF can be applied to the antifuse line AFL1. In this case, the select transistor 222 and its follower transistor 224 in the select circuit 220_1_1 will be turned on, and a high voltage will be applied between the first and second terminals of the antifuse element 210_1_1, thereby creating a high-density defect in the channel, thereby programming the one-time programmable memory cell 200_1_1.

[0048] Furthermore, during the programming operation of the one-time programmable memory unit 200_1_1, a voltage VDD can be applied to the bit lines BL2 to BLN, thereby reducing the voltage applied to the antifuse elements 200_1_2 to 200_1_N, and thus preventing the programming of the one-time programmable memory units 200_1_2 to 200_1_N. Moreover, during the programming operation of the one-time programmable memory unit 200_1_1, a voltage VSS can be applied to the word lines WL2 to WLM and the programming lines PL2 to PLM. In this way, the antifuse elements 200_2_1 to 200_2_M will not receive a high voltage, therefore, during the programming operation of the one-time programmable memory unit 200_1_1, the one-time programmable memory units 200_2_1 to 200_2_M will not be programmed.

[0049] In this embodiment, follower lines FL1 to FLM can all be coupled to each other, but this disclosure is not limited thereto. In some embodiments, follower lines FL1 to FLM can also be controlled individually. Furthermore, in this embodiment, the gate terminals of antifuse elements 210_1_1 to 210_M_N can be correspondingly coupled to antifuse lines AF1 to AFM to receive voltage VAF. However, in some other embodiments, the gate terminals of antifuse elements 210_1_1 to 210_M_N can be physically kept floating and not interconnected with other gate terminals.

[0050] Furthermore, in some embodiments, each of the one-time programmable memory units 200_1_1 to 200_M_N can be replaced by the one-time programmable memory unit 100 by omitting the follower transistor 224 and follower lines FL1 to FLM.

[0051] Furthermore, in some embodiments, one-time programmable memory units 100 and 200 may also be used to form physically unclonable function (PUF) units. FIG10 shows a PUF unit 30 according to one embodiment of the present disclosure. The PUF unit 30 includes two one-time programmable memory units 300A and 300B.

[0052] For example, a one-time programmable memory unit 300A includes an antifuse element 310A and a selection circuit 320A. The antifuse element 310A includes a first terminal, a second terminal coupled to the programming line PL, and a gate terminal. The selection circuit 320A is coupled to the first terminal of the antifuse element 310A, the word line WL1, and the bit line BL1. The selection circuit 320A controls the electrical connection between the bit line BL1 and the first terminal of the antifuse element 310A according to the voltage of the word line WL1. The antifuse element 310B includes a first terminal, a second terminal coupled to the programming line PL, and a gate terminal. The selection circuit 320B is coupled to the first terminal of the antifuse element 310B, the word line WL2, and the bit line BL2. The selection circuit 320B controls the electrical connection between the bit line BL2 and the first terminal of the antifuse element 310B according to the voltage of the word line WL2.

[0053] In this embodiment, selection circuits 320A and 320B may have the same structure as selection circuit 220. That is, selection circuit 320A may include selection transistor 322A and follower transistor 324A, and selection circuit 320B may include selection transistor 322B and follower transistor 324B. In some embodiments, the gate terminals of follower transistor 324A and follower transistor 324B may be coupled to the same follower line FL.

[0054] The PUF unit 30 can be registered through a registration operation, such that one of the one-time programmable memory units 300A and 300B will be programmed due to a damaged channel, while the other one-time programmable memory unit 300A and 300B will not be programmed. Specifically, during the registration operation, bit lines BL1 and BL2 can both receive VSS, word lines WL1 and WL2 can both receive voltage VDD, programming line PL can receive voltage VPP, and follower line FL can receive voltage VDD2. In addition, the gate terminals of antifuse element 310A and antifuse element 310B can both receive voltage VAF or be in a floating state.

[0055] In this case, both one-time programmable memory units 300A and 300B may be programmed. However, due to inherent characteristic differences caused by manufacturing variations in one-time programmable memory units 300A and 300B, one of them will be programmed first. Furthermore, the one-time programmable memory unit programmed first will conduct current from the programming line PL to the corresponding bit line BL1 or BL2, thereby reducing the voltage applied to the other one-time programmable memory unit and preventing that other one-time programmable memory unit from being programmed. Therefore, after registration is completed, one-time programmable memory units 300A and 300B will have different bit values, and reading one-time programmable memory unit 300A through bit line BL1 or one-time programmable memory unit 300B through bit line BL2 will yield unpredictable bit values. Alternatively, in some embodiments, the unpredictable bit values ​​can also be read by sensing bit lines BL1 and BL2 as a differential pair.

[0056] Since the PUF unit 30 allows programming of one of the one-time programmable memory units 300A or 300B at a relatively low programming voltage VPP by damaging the channel of the anti-fuse element therein, the PUF unit 30 can be implemented by using a transistor with an advanced node process that has a smaller size and operates at a lower voltage.

[0057] In summary, the one-time programmable memory unit, one-time programmable memory array and PUF unit provided in this disclosure embodiment enable the one-time programmable memory unit to be programmed with a lower programming voltage by disrupting the anti-fuse element channel therein, and the above-mentioned one-time programmable memory unit, one-time programmable memory array and PUF unit can be implemented using transistors with advanced node processes, thereby having a smaller size and a lower operating voltage. [Simplified Explanation of the Diagram]

[0007] This disclosure will be more fully understood by referring to the detailed description and the claims, as well as the drawings, in which the same reference numerals in all the drawings may represent the same elements.

[0008] FIG1 shows a one-time programmable (OTP) memory cell according to one embodiment of the present disclosure.

[0009] Figure 2 shows the voltage supplied to the one-time programmable memory cell in Figure 1 during the programming operation according to one embodiment of the present disclosure.

[0010] Figure 3 shows the voltage supplied to the one-time programmable memory cell in Figure 1 during the read operation according to one embodiment of the present disclosure.

[0011] Figure 4 shows the relationship between programming time and read current of the one-time programmable memory cell in Figure 1 according to one embodiment of the present disclosure.

[0012] Figure 5 shows the relationship between the gate voltage applied to the gate terminal of the antifuse element during a read operation and the read current of the one-time programmable memory cell in Figure 1, according to one embodiment of the present disclosure.

[0013] Figure 6 shows a three-dimensional architecture diagram of the one-time programmable memory unit in Figure 1 according to one embodiment of the present disclosure.

[0014] Figure 7 shows a cross-sectional view of the antifuse element of the one-time programmable memory unit.

[0015] Figure 8 shows a one-time programmable memory unit according to another embodiment of the present disclosure.

[0016] Figure 9 shows a one-time programmable memory array according to one embodiment of the present disclosure.

[0017] FIG10 shows a PUF unit according to one embodiment of the present disclosure.

Claims

1. A one-time programmable (OTP) memory unit, comprising: An antifuse element includes a first terminal, a second terminal coupled to a programming line, and a gate terminal; And a selection circuit coupled to the first terminal of the antifuse element, a word line and a bit line, and configured to control an electrical connection between the bit line and the first terminal of the antifuse element according to the voltage of the word line. When the one-time programmable memory unit is programmed through a programming operation, one of the channels between the first and second terminals of the antifuse element is damaged; the selection circuit includes a selection transistor, which includes a first terminal coupled to the bit line, a second terminal coupled to one of the first terminals of the antifuse element, and a gate terminal coupled to the word line; during the programming operation, the bit line is configured to receive a first voltage, the word line is configured to receive a second voltage, the programming line is configured to receive a third voltage, and the gate terminal of the antifuse element is configured to receive a fourth voltage or be floating, wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage and the fourth voltage.

2. The one-time programmable memory cell as claimed in claim 1, wherein the antifuse element is a metal-oxide-semiconductor field-effect transistor (MOSFET), a gate all around (GAA) field-effect transistor (FET), a fin field-effect transistor, a junctionless field-effect transistor, a nanosheet field-effect transistor, or a diode.

3. The one-time programmable memory cell as claimed in claim 1, wherein the channel length of the antifuse element is less than 20 nm.

4. As in request item 1, a one-time programmable memory unit, wherein: During a read operation, the bit line is configured to receive the first voltage, the word line is configured to receive the second voltage, the programming line is configured to receive a fifth voltage, and the gate terminal of the antifuse element is configured to receive the fourth voltage or be floating, and the fifth voltage is greater than or equal to the second voltage.

5. A one-time programmable (OTP) memory cell, comprising: an antifuse element including a first terminal, a second terminal coupled to a programming line, and a gate terminal; and a selection circuit coupled to the first terminal of the antifuse element, a word line, and a bit line, and configured to control an electrical connection between the bit line and the first terminal of the antifuse element according to the voltage of the word line; When the one-time programmable memory unit is programmed through a programming operation, one of the channels between the first and second terminals of the antifuse element will be damaged; wherein the selection circuit includes: A selective transistor includes a first terminal, a second terminal coupled to the bit line, and a gate terminal coupled to the word line; And a follower transistor, which includes a first end of one of the second ends of the select transistor coupled to the select transistor, a second end of one of the first ends of the antifuse element coupled to the selecter transistor, and a gate end coupled to a follower line.

6. As in request item 5, a one-time programmable memory unit, wherein: During the programming operation, the bit line is configured to receive a first voltage, the word line is configured to receive a second voltage, the programming line is configured to receive a third voltage, the gate terminal of the antifuse element is configured to receive a fourth voltage or be floating, and the follower line is configured to receive a sixth voltage, wherein the third voltage is greater than the second voltage and the sixth voltage, the sixth voltage is greater than the second voltage, and the second voltage is greater than the first voltage and the fourth voltage.

7. As in request item 6, a one-time programmable memory unit, wherein: During a read operation, the bit line is configured to receive the first voltage, the word line and the follower line are configured to receive the second voltage, the programming line is configured to receive a fifth voltage, and the gate terminal of the antifuse element is configured to receive the fourth voltage or be floating, and the fifth voltage is greater than or equal to the second voltage.

8. The one-time programmable memory cell of claim 5, wherein the doping concentration of the channel of the antifuse element is higher than the doping concentration of the channel of the follower transistor.

9. The one-time programmable memory cell of claim 1, wherein the programming operation is maintained for more than a predetermined time to ensure that the channel between the first end and the second end of the antifuse element is damaged.

10. A One-Time Programmable (OTP) memory cell, comprising: an antifuse element including a first terminal, a second terminal coupled to a programming line, and a gate terminal; and a selection circuit coupled to the first terminal of the antifuse element, a word line, and a bit line, and configured to control an electrical connection between the bit line and the first terminal of the antifuse element based on the voltage of the word line; wherein when the one-time programmable memory cell is programmed through a programming operation, a channel between the first terminal and the second terminal of the antifuse element is damaged; wherein during a read operation, a high-order critical leakage current is generated from the second terminal of the antifuse element to the first terminal of the antifuse element.

11. A one-time programmable (OTP) memory array, comprising: A first one-time programmable memory cell includes: a first antifuse element having a first terminal, a second terminal coupled to a first programming line, and a gate terminal; and a first selection circuit coupled to the first terminal, a first word line, and a first bit line of the first antifuse element, and configured to control an electrical connection between the first bit line and the first terminal of the first antifuse element based on the voltage of the first word line; and a second one-time programmable memory cell includes: a second antifuse element having a first terminal, a second terminal coupled to the first programming line, and a gate terminal; and a second selection circuit coupled to the first terminal, the first word line, and a second bit line of the second antifuse element, and configured to control an electrical connection between the second bit line and the first terminal of the second antifuse element based on the voltage of the first word line; When the first one-time programmable memory unit is programmed through a programming operation, the channel between the first end and the second end of the first antifuse element will be damaged. During the read operation, a high-order critical leakage current will be generated from the second end of the first antifuse element to the first end of the first antifuse element.

12. As in claim 11, a one-time programmable memory array, further comprising: A third one-time programmable memory cell includes: a third antifuse element having a first terminal, a second terminal coupled to a second programming line, and a gate terminal; and a third selection circuit coupled to the first terminal, the second word line, and the first bit line of the third antifuse element, and configured to control the electrical connection between the first bit line and the first terminal of the third antifuse element according to the voltage of the second word line.

13. The one-time programmable memory array of claim 12, wherein the gate terminal of the first antifuse element, the gate terminal of the second antifuse element, and the gate terminal of the third antifuse element are all floating.

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