Memory circuit and memory device

Abstract

A memory circuit and a memory device are proposed. The memory circuit includes a pair of memory cell circuits and a first switch. The pair of memory cell circuits includes a first memory cell circuit and a second memory cell circuit. The first memory cell circuit is coupled to a bit line through the first switch, and the second memory cell circuit is also coupled to a bit line through the first switch. During a write operation, the first switch is turned off, and the first and second memory cell circuits are connected in series between a first source line and a second source line. During a read operation, the first switch is turned on, and the first and second memory cell circuits are coupled in parallel.

Claims

1. A memory circuit, comprising: A memory cell circuit pair includes a first memory cell circuit and a second memory cell circuit; The system includes a first switch, wherein the first memory cell circuit is coupled to a bit line through the first switch, and the second memory cell circuit is coupled to the bit line through the first switch. During a write operation, the first switch is turned off, and the first memory cell circuit and the second memory cell circuit are connected in series between a first source line and a second source line. During a read operation, the first switch is turned on, and the first memory cell circuit and the second memory cell circuit are connected in parallel.

2. The memory circuit as claimed in claim 1, wherein during the write operation, the first memory cell circuit and the second memory cell circuit receive a bias current, and the first memory cell circuit and the second memory cell circuit are respectively written with a first logic value and a second logic value according to the bias current.

3. The memory circuit as claimed in claim 1, wherein during the read operation, the first memory cell circuit and the second memory cell circuit receive a read bias voltage through the first switch, and provide a read voltage and a reference voltage to a sense amplifier through the first source line and the second source line, respectively.

4. The memory circuit as claimed in claim 1, wherein each of the first memory cell circuits and the second memory cell circuits comprises: A second switch; And a memory cell including a free layer, a reference layer and a tunneling layer, the tunneling layer being covered by the free layer and the reference layer, wherein one of the free layer and the reference layer is coupled to the bit line, and the other of the free layer and the reference layer is coupled to the second switch.

5. The memory circuit as claimed in claim 4, wherein the second switches of the first memory cell circuit and the second memory cell circuit are controlled by the same word line signal.

6. The memory circuit as claimed in claim 1, wherein the first memory cell circuit and the second memory cell circuit are respectively disposed in different memory banks of a memory device.

7. The memory circuit as claimed in claim 1, wherein a first memory cell of the first memory cell circuit and a second memory cell of the second memory cell circuit are disposed on the same horizontal plane, a first conductor forming the bit line is disposed on a first side of the first memory cell and the second memory cell; a second conductor and a third conductor are disposed on a second side of the first memory cell and the second memory cell, wherein the second conductor and the third conductor respectively form the first source line and the second source line.

8. The memory circuit of claim 7, wherein the first wire is coupled to a reference layer of the first memory cell and a reference layer of the second memory cell; the second wire is coupled to a free layer of the first memory cell; and the third wire is coupled to a free layer of the second memory cell.

9. The memory circuit as claimed in claim 1, wherein a first memory cell of the first memory cell circuit and a second memory cell of the second memory cell circuit are stacked alternately, a first source line formed by a first wire is coupled to the first memory cell; a bit line formed by a second wire is coupled to the first memory cell and the second memory cell; and a second source line formed by a third wire is coupled to the second memory cell.

10. The memory circuit of claim 1, wherein the first wire is coupled to a reference layer of the first memory cell; the second wire is coupled to a free layer of the first memory cell and a reference layer of the second memory cell; and the third wire is coupled to a free layer of the second memory cell.

11. A memory device, comprising: Multiple memory circuits are arranged in an array, each memory circuit including: a pair of memory cell circuits, including a first memory cell circuit and a second memory cell circuit; and a first switch, wherein the first memory cell circuit is coupled to a bit line through the first switch, and the second memory cell circuit is coupled to the bit line through the first switch; wherein in a write operation, the first switch is turned off, and the first memory cell circuit and the second memory cell circuit are connected in series between a first source line and a second source line; in a read operation, the first switch is turned on, and the first memory cell circuit and the second memory cell circuit are coupled in parallel.

12. The memory device as claimed in claim 11, wherein during the write operation, the first memory cell circuit and the second memory cell circuit receive a bias current, and the first memory cell circuit and the second memory cell circuit are respectively written with a first logic value and a second logic value according to the bias current.

13. The memory device of claim 11, wherein during the read operation, the first memory cell circuit and the second memory cell circuit receive a read bias through the first switch and provide a read voltage and a reference voltage to a sense amplifier through the first source line and the second source line, respectively.

14. The memory device as claimed in claim 11, wherein each of the first memory cell circuits and the second memory cell circuits comprises: A second switch; And a memory cell including a free layer, a reference layer and a tunneling layer, the tunneling layer being covered by the free layer and the reference layer, wherein one of the free layer and the reference layer is coupled to the bit line, and the other of the free layer and the reference layer is coupled to the second switch.

15. The memory device as claimed in claim 14, wherein the first memory cell circuit and the second memory cell circuit are respectively disposed in different memory banks of a memory device.

16. The memory device of claim 11, wherein a first memory cell of the first memory cell circuit and a second memory cell of the second memory cell circuit are disposed on the same horizontal plane, a first conductor forming the bit line is disposed on a first side of the first memory cell and the second memory cell; a second conductor and a third conductor are disposed on a second side of the first memory cell and the second memory cell, wherein the second conductor and the third conductor respectively form the first source line and the second source line.

17. The memory device of claim 11, wherein a first memory cell of the first memory cell circuit and a second memory cell of the second memory cell circuit are stacked alternately, a first source line formed by a first conductor is coupled to the first memory cell; a bit line formed by a second conductor is coupled to the first memory cell and the second memory cell; and a second source line formed by a third conductor is coupled to the second memory cell.

18. The memory device as claimed in claim 11, further comprising: A bit line controller is coupled to the bit line; And a source line controller, coupled to the first source line and the second source line.

19. The memory device of claim 18, wherein the source line controller includes a sensing amplifier to sense read data based on signals on the first source line and the second source line during a read operation.

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