Flash memory cell and three-dimensional flash memory device having the same

Abstract

A flash memory cell includes a channel structure, a first gate, a second gate, a storage structure, source posts, and bit posts. The channel structure is formed above a substrate. The first gate is adjacent to the channel structure. The second gate is spaced apart from the first gate and the channel structure. The storage structure is adjacent to the channel structure. The source posts and bit posts are respectively adjacent to opposite sidewalls of the channel structure. Furthermore, the first gate does not overlap perpendicularly with the channel structure.

Description

[Technical Field]

[0001] This invention relates to a memory structure and a three-dimensional memory device having the memory structure, and particularly to a flash memory unit and a three-dimensional flash memory device having the flash memory unit. [Previous Technology]

[0002] Currently, NOR flash memory devices with stacked gates have slow programming and erasing speeds. To improve the operating speed of flash memory, discrete gate flash memory with high-efficiency programming and erasing speeds has been developed. However, discrete gate flash memory has a larger cell size, thereby reducing the integration density of memory cells. Therefore, a trade-off needs to be made between the operating speed and integration density of flash memory. [Summary of the Invention]

[0003] Accordingly, this disclosure provides a flash memory cell and a three-dimensional flash memory device having the flash memory cell, in order to overcome the trade-off between operating speed and integration density in traditional flash memory devices.

[0004] The embodiments disclosed herein provide a flash memory cell including a channel structure, a first gate, a second gate, a storage structure, source terminals, and bit terminals. The channel structure is formed above a substrate. The first gate is disposed adjacent to the channel structure. The second gate is disposed spaced apart from the first gate and the channel structure. The storage structure is disposed adjacent to the channel structure. The source terminals and bit terminals are disposed adjacent to opposite sidewalls of the channel structure. Furthermore, the first gate does not overlap perpendicularly with the channel structure.

[0005] Furthermore, embodiments of the present invention also provide a three-dimensional flash memory device comprising a plurality of memory layers stacked on a substrate, spaced apart from each other by an insulating material. Each memory layer comprises a plurality of memory cells arranged in an array. Each memory cell comprises a channel structure, a first gate, a second gate, a storage structure, a source post, and a bit post. The channel structure is disposed in the memory layer. The first gate is disposed in the memory layer and adjacent to the channel structure. The second gate is disposed perpendicularly on the substrate and spaced apart from the first gate and the channel structure. The storage structure is adjacent to the channel structure. The source post and bit post are disposed perpendicularly on the substrate and are respectively adjacent to the opposite sidewalls of the channel structure. The first gate does not overlap perpendicularly with the channel structure.

[0006] According to the embodiments, the operating speed and component integration density of flash memory devices can be improved.

Implementation Method

[0008] Figure 1 is a perspective view of a three-dimensional flash memory device 10 according to some embodiments of the present disclosure. Figure 2 is a circuit diagram of the three-dimensional flash memory device 10 of Figure 1. The embodiments can be applied to flash memory devices, such as NOR flash memory devices. The following describes the three-dimensional flash memory device 10 of the embodiments using a three-dimensional split-gate flash memory device.

[0009] In some embodiments, the three-dimensional flash memory device 10 includes a plurality of memory layers LM stacked on a substrate 100 and separated by an insulating material. Each memory layer LM includes a plurality of memory cells arranged in an array. The memory layer LM may be a plane defined by a first direction D1 and a second direction D2. The memory layers LM are at different levels in a third direction D3.

[0010] To simplify the drawings, Figures 1 and 2 show two memory layers Mn and Mn-1 above the substrate 100, each memory layer having four memory cells 20, for illustrative purposes. Furthermore, to clearly show the relevant components of the memory cells 20 in the embodiment for ease of explanation, the insulating material located between the memory layers LM is not shown in Figure 1.

[0011] In some embodiments, each memory cell 20 of the three-dimensional flash memory device 10 is a discrete gate memory cell. The memory cell 20 includes a channel structure 21, a first gate 23, a second gate 25, a storage structure 26, a source line pillar 27, and a bit line pillar 29. The channel structure 21 is formed in the memory layer LM and serves as the channel region of the memory cell 20. When the memory cell 20 is operated, the generated current flows through the channel structure 21. The channel structure 21 may include polysilicon, indium gallium zinc oxide (IGZO), or other suitable channel materials.

[0012] In some embodiments, the first gate 23 is formed in the memory layer LM and can serve as the selection gate of the memory cell 20. The first gate 23 does not overlap with the channel structure 21 in the vertical direction. The first gate 23 is disposed adjacent to the channel structure 21 but does not contact it. For example, the sidewall 231 of the first gate 23 is separated from the channel structure 21 by an insulating material. The insulating material includes, for example, oxides. The first gate 23 can be considered as a word line of the memory cell 20. Furthermore, the first gate 23 may include doped polysilicon, a metallic material such as tungsten (W), other suitable conductive materials, or a combination of the foregoing materials.

[0013] In some embodiments, the second gate 25 is vertically disposed on the substrate 100 and can serve as the control gate of the memory cell 20. The first gate 23 and the second gate 25 are disposed on the same side of the channel structure 21. The second gate 25 is spaced apart from both the first gate 23 and the channel structure 21. The storage structure 26 surrounds the second gate 25 and provides data storage functionality.

[0014] The second gate 25 of the memory cell 20 and the storage structure 26 extend vertically through the memory layer LM and the insulating material. As shown in Figure 1, the second gate 25 may be a conductive post extending along a third direction D3, and the storage structure 26 may be a hollow tube surrounding the second gate 25. According to an embodiment, the second gate 25 is a common control gate for a group of memory cells stacked in a vertical direction relative to the substrate 100. For example, the second gate 25 is a common control gate for memory cells 20_11(n) and 20_11(n-1) in a vertical string, as shown in Figure 2.

[0015] In some embodiments, the storage structure 26 includes a charge-trapping layer surrounding the second gate 25 and trapping charge to store data. The charge-trapping layer may be a nitride layer or a high-dielectric-constant dielectric layer. As shown in Figure 1, the storage structure 26 may include a silicon oxide layer 26A in contact with the second gate 25, a silicon nitride layer 26B on the silicon oxide layer 26A, and another silicon oxide layer 26C on the silicon nitride layer 26B. When the memory cell 20 is programmed, the silicon nitride layer 26B of the storage structure 26 acts as a charge-trapping layer, trapping charge injected as hot electrons from the channel source side. Either of the two silicon oxide layers 26A and 26C may act as a tunneling insulating layer, while the other acts as a barrier insulating layer.

[0016] In some embodiments, the source posts 27 and bit posts 29 of the memory cell 20 are located on opposite sides of the channel structure 21. Furthermore, the source posts 27 and bit posts 29 are vertically disposed on the substrate 100 and penetrate, for example, layers of memory layer LM and insulating material.

[0017] According to some embodiments, source line post 27 is a common source line for a group of memory cells stacked vertically relative to the substrate 100. For example, source line post 27 is a common source line for memory cells 20_21(n) and 20_21(n-1) stacked vertically, as shown in Figure 2. Similarly, bit line post 29 is a common bit line for a group of memory cells stacked vertically relative to the substrate 100. For example, bit line post 29 is a common bit line for memory cells 20_12(n) and 20_12(n-1) stacked vertically, as shown in Figure 2.

[0018] The second gate 25, source pillar 27, and bit pillar 29 may comprise one or more metallic materials, such as tungsten, other suitable conductive materials, or combinations thereof. In one embodiment, the second gate 25, source pillar 27, and bit pillar 29 comprise the same material. For example, the second gate 25, source pillar 27, and bit pillar 29 are tungsten pillars. The second gate 25, source pillar 27, and bit pillar 29 can be formed by any known method, such as lithography using patterned masks, etching processes for forming deep trenches, material filling processes, planarization processes, and any suitable processes. The source pillar 27 and bit pillar 29 can be formed simultaneously by the same manufacturing steps.

[0019] According to an embodiment, each memory cell 20 includes a selection transistor Ts and a control transistor Tc coupled to the selection transistor Ts, as shown in Figure 2. The first gate 23 can be considered as the selection gate Ts of the selection transistor, and the second gate 25 can be considered as the control gate Tc of the control transistor. The stacking structure of the present invention can improve the aggregation density of the memory cells.

[0020] Furthermore, at least some of the first gates 23 of the memory cells 20 located in the same memory layer LM can be connected together to simplify word line decoding. In some embodiments, the memory cells 20 of each memory layer LM can be configured as an array comprising multiple rows and columns. The first gates 23 of a group of memory cells 20 in each row can be electrically connected to each other, for example, via an interconnect.

[0021] Figure 3 is a top view of adjacent memory cells 20_11(n) and 20_21(n) in the same row in the memory layer Mn of the three-dimensional flash memory device 10. Figure 3 illustrates the configuration and arrangement of related components of two adjacent memory cells in the same memory layer, wherein the first gate 23 of memory cells 20_11(n) and 20_21(n) are connected by interconnect 32. Please refer to Figures 1, 2, and 3.

[0022] In this exemplary embodiment, four memory cells in a memory layer can be configured as an array with two rows and two columns. As shown in Figure 2, the first gates 23 of memory cells 20_11(n-1) and 20_21(n-1) in the first row of memory layer Mn-1 are electrically connected to each other. More specifically, interconnects 31 extending in the row direction (e.g., the first direction D1) are electrically connected to the first gates 23 of memory cells 20_11(n-1) and 20_21(n-1), forming a common word line for memory cells 20_11(n-1) and 20_21(n-1). The interconnect 31 can be a single wire physically contacting one side of the first gate 23 of the corresponding memory cell in the first row, or the interconnect 31 can be a continuous portion extending from the corresponding first gate 23.

[0023] Similarly, in this exemplary embodiment, the first gates 23 of memory cells 20_11(n) and 20_21(n) in the first row of memory layer Mn are electrically connected to each other via interconnects 32 extending in the row direction, thus interconnects 32 form a common word line for memory cells 20_11(n) and 20_21(n). Furthermore, interconnects 33 are electrically connected to the first gates 23 of memory cells 20_12(n-1) and 20_22(n-1) located in memory layer Mn-1, thus interconnects 33 form a common word line for memory cells 20_12(n-1) and 20_22(n-1). Interconnect 34 electrically connects the first gate 23 of memory cells 20_12(n) and 20_22(n) located in memory layer Mn, thus forming a common word line for memory cells 20_12(n) and 20_22(n). These interconnects 31, 32, 33 and 34 are arranged in parallel to each other, for example.

[0024] In one embodiment, each of the interconnects 31, 32, 33, and 34 is formed simultaneously with the first gate 23 of the corresponding memory cell 20 in the same patterning process. That is, the first gate 23 and the interconnects 31, 32, 33, and 34 can be formed of the same conductive material.

[0025] Furthermore, in some embodiments, multiple interconnects extending in the row direction (e.g., the first direction D1) of each memory layer in the memory layer LM are further connected by another wire to simplify character line decoding. As shown in Figure 2, interconnects 31 and 33 in memory layer Mn-1 can also be electrically connected, for example, via wire 41. Interconnects 32 and 34 in memory layer Mn can also be electrically connected via wire 42. Wires 41 and 42 can be considered as shared character lines, such as WLn-1 and WLn, and can extend in the column direction (e.g., the second direction D2).

[0026] Specifically, referring to Figure 3, the channel structure 21 includes opposing sidewalls 211 and 213 and opposing sidewalls 212 and 214. The first gate 23 and the second gate 25 are, for example, adjacent to the sidewall 211 of the channel structure 21. The source post 27 is disposed adjacent to the sidewall 212 of the channel structure 21, while the bit post 29 is disposed adjacent to the sidewall 214 of the channel structure 21.

[0027] Furthermore, in one embodiment, each memory cell 20 further includes heavily doped regions 22S and 22D on opposite sides of the channel structure 21, for example, on sidewalls 212 and 214. The heavily doped regions 22S and 22D provide low contact resistance between the source post 27 and the bit post 29 and the channel structure 21, respectively. In one embodiment, the channel structure 21 and the heavily doped regions 22S and 22D have different conductivity types. For example, the channel structure 21 has a first conductivity type, such as p-type; the heavily doped regions 22S and 22D have a second conductivity type, such as n-type. Additionally, the channel structure 21 may be lightly doped, with a doping concentration lower than that of the heavily doped regions 22S and 22D. In this embodiment, the heavily doped regions 22S and 22D may be represented as n+ regions.

[0028] Preferably, the storage structure 26 is configured as close as possible to the channel structure 21, thereby facilitating charge injection from the channel structure 21 into the charge trapping layer (e.g., silicon nitride layer 26B) of the storage structure 26. It should be noted that the shape of the second gate 25 may be a square prism, a rectangular prism, a cylinder, or other suitable three-dimensional shape. In some preferred embodiments, the second gate 25 is a square or rectangular prism so that the storage structure 26 can be configured adjacent to the channel structure 21.

[0029] Furthermore, viewed from above the memory layer, the second gate 25 and the storage structure 26 are located near the corner defined by the first gate 23 and the channel structure 21. Specifically, in the example where the first gate 23 connects adjacent memory cells (e.g., memory cells 20_21(n) and 20_11(n)) with an interconnect (e.g., interconnect 32 in Figure 3), the second gate 25 and the storage structure 26 are configured in the region defined by the interconnect 32, the first gate 23, and the sidewall 211 of the channel structure 21. According to some embodiments, the storage structure 26 has a first portion 261 and a second portion 262 adjacent to the first portion 261, as shown in Figure 3. The first portion 261 is located between the channel structure 21 and the second gate 25. The second portion 262 is located between the first gate 23 and the second gate 25. Specifically, the first portion 261 of the storage structure 26 extends along the sidewall 211 of the channel structure 21, and the second portion 262 of the storage structure 26 extends along the sidewall of the first gate 23.

[0030] Furthermore, the dimensions of the first gate 23 and the storage structure 26 can be designed based on the dimensions of the channel structure 21. For example, the total width (in the first direction D1) of the first gate 23 and the storage structure 26 can be less than, close to, or slightly greater than the length (in the first direction D1) of the channel structure 21. Specifically, in this exemplary embodiment, as shown in Figure 3, the sidewall 211 or sidewall 213 has a length Lc in the first direction D1. The first gate 23 has a width W1 in the first direction D1. The storage structure 26 has a width Ws in the first direction D1. The length Lc is greater than the sum of the width W1 of the first gate 23 and the width Ws of the storage structure 26.

[0031] Figures 4A, 4B, and 4C-1 illustrate schematic diagrams of a memory cell during operation according to some embodiments of the present disclosure. Source post 27 and bit post 29 can be considered as the source and drain of the memory cell 20. The memory cell 20 can be programmed from the source end via hot carrier injection (also known as "hot electron injection"). A first gate 23 serves as the selection gate of the memory cell 20 and can be used to drive current flow.

[0032] In one embodiment, as shown in Figure 4A, when a positive bias is applied to the first gate 23 and the bit post 29 and the source post 27 is grounded, the memory cell 20 is in a conducting state. Current I1 flows in the channel structure 21 from the source end (i.e., the source post 27) to the drain end (i.e., the bit post 29).

[0033] In one embodiment, as shown in Figure 4B, when the source post 27 is grounded and the memory cell 20 is programmed using hot carrier injection, a positive bias is applied to the second gate 25, the first gate 23, and the bit post 29. Hot electrons e- are injected into the storage structure 26 and trapped in the silicon nitride layer 26B.

[0034] According to some embodiments, the memory cell 20 can be erased by thermoelectric hole injection for faster operation; or it can be erased by Fowler-Nordheim (FN) tunneling injection to avoid over-erasing.

[0035] In one embodiment, as shown in Figure 4C-1, when memory cell 20 is erased by thermoelectric hole injection, a negative bias is applied to the first gate 23, a larger negative bias is applied to the second gate 25, a larger positive bias is applied to the bit post 29 (drain), and the source post 27 is grounded. When a thermoelectric hole is injected into the charge trapping layer (e.g., silicon nitride layer 26B) of storage structure 26, it can neutralize electrons that have previously been trapped by the charge trapping layer.

[0036] In one embodiment, as shown in Figure 4C-2, when memory cell 20 is erased using FN tunneling injection, a large positive bias is applied to the second gate 25, while the other gates are floating. In other words, no bias is applied to the first gate 23, source post 27, and bit post 29. Electrons previously trapped by the charge trapping layer (e.g., silicon nitride layer 26B) are pulled out of the charge trapping layer and carried away into the second gate 25. As the charge decreases, the electric field also weakens. Therefore, this erasure operation is self-limiting to prevent memory cell 20 from being over-erased.

[0037] Figures 5A to 15 illustrate schematic diagrams of multiple intermediate stages of a method for forming a three-dimensional flash memory device 10 according to some embodiments of the present disclosure. Figure 5B is a cross-sectional view of one intermediate stage of the three-dimensional flash memory device taken along line C1-C1 of Figure 5A. Figure 13B is a cross-sectional view of one intermediate stage of the three-dimensional flash memory device taken along line C2-C2 of Figure 13A.

[0038] Referring to Figures 5A and 5B, a plurality of insulating layers 201 and conductive layers 203 are alternately stacked on a substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, or the like. The substrate 100 may be undoped or doped with p-type or n-type dopants. The insulating layer 201 may include oxide or other suitable insulating materials. The conductive layer 203 may include one or more semiconductor materials doped with p-type or n-type dopants, or other suitable conductive materials. In some embodiments, the insulating layer 201 is a silicon oxide layer, and the conductive layer 203 is p+ polycrystalline silicon.

[0039] In some embodiments, the insulating layer 201 can be formed by a chemical vapor deposition (CVD) process, such as a low-pressure CVD process, a plasma-assisted CVD process, or a combination of the foregoing processes. The conductive layer 203 can be formed by a CVD process, a physical vapor deposition (PVD) process, or a combination of the foregoing processes. The number of insulating layers 201 and conductive layers 203 can be adjusted according to the actual product requirements of the three-dimensional flash memory device 10.

[0040] Referring to Figure 6, in some embodiments, a trench 204 is formed to pass through the stacked insulating layer 201 and conductive layer 203, and the trench 204 exposes the top surface 100a of the substrate 100. The trench 204 can be formed by one or more etching processes. In some embodiments, the trench 204 can be formed by vertically removing a portion of the stacked insulating layer 201 and conductive layer 203 until the substrate 100 is exposed, and then laterally recessing the conductive layer 203 to form recesses 204R, each recess 204R being located on the remaining conductive layer 203' and between adjacent remaining insulating layers 201'.

[0041] Subsequently, referring to Figure 7, in some embodiments, a gate dielectric layer 206 is formed on the exposed sidewalls where the conductive layer 203' remains. The gate dielectric layer 206 can be formed using processes such as CVD or atomic layer deposition (ALD). The insulating layer 201 and the gate dielectric layer 206 may comprise the same insulating material, such as silicon oxide.

[0042] In some embodiments, after forming a gate dielectric layer 206 on the exposed sidewalls of the remaining conductive layer 203', channel material is deposited to fill the trench 204, including filling the recess 204R. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed to expose the top surface 201a of the insulating layer 201', thereby forming a channel material pillar 210 in the trench 204. The top surface 201a of the insulating layer 201' may be coplanar with the top surface 210a of the channel material pillar 210. The channel material pillar 210 may comprise a semiconductor material with dopants of a suitable conductivity type. In some embodiments, the channel material pillar 210 comprises polycrystalline silicon with p-type dopant. In some embodiments, the channel material pillar 210 and the conductive layer 203' comprise the same material. The doping concentration of the conductive layer 203' is greater than the doping concentration 210 of the channel material pillar. For example, the conductive layer 203' is a p+ polycrystalline silicon layer, and the channel material pillar 210 is a p-type polycrystalline silicon pillar.

[0043] Next, referring to Figure 8, in some embodiments, a portion of the channel material pillar 210 is removed, for example, by etching, to form a trench 215 exposing the top surface 100a of the substrate 100. The remaining portion 210' of the channel material pillar 210 fills the recess 204R, thereby forming the channel structure 21 of the three-dimensional flash memory device 10. That is, when viewed from the top of the substrate 100, the remaining portion 210' of the channel material pillar 210 in the same memory layer is a portion of a ring. After the trench 215 is formed, the vertical sidewalls 201s of the insulating layer 201' are generally aligned with the inner sidewalls 210s of the remaining portion 210' of the channel material pillar 210 (i.e., the channel structure 21).

[0044] Referring to Figure 9, backfill material 216 is formed to completely fill trench 215. In some embodiments, to improve process convenience, backfill material 216 may include an insulating material, such as an oxide. Thus, as shown in Figure 10, channel structure 21 may form a channel ring (i.e., the remaining portion 210' of the channel material pillar 210) to surround the backfill material 216 made of insulating material. The backfill material 216 described above can be formed using a CVD process, a PVD process, or an ALD process. In some embodiments, backfill material 216 and insulating layer 201 include the same insulating material, such as silicon oxide, such that there is no interface between the materials of backfill material 216 and insulating layer 201'. However, in an alternative embodiment, as shown in Figure 17, backfill material 216 may include channel material, and channel structure 21 may be formed as a channel sheet.

[0045] In some embodiments, after the channel structure 21 is formed in each horizontal plane, the first gate 23, the storage structure 26 and the second gate 25 are formed in sequence.

[0046] Referring to Figure 10, in some embodiments, after the backfill material 216 fills the trench 215, the upper part and a portion of the backfill material 216 of the insulating layer 201 are removed, for example by an etch-back process or a CMP process, to expose the underlying conductive layer 203' and channel structure 21. Figure 10 is a top view showing the backfill material 216 filling the internal space of the channel structure 21, with the gate dielectric layer 206 surrounding the channel structure 21. The channel structure 21, the gate dielectric layer 206, and the conductive layer 203' form a layer parallel to the top surface 100a of the substrate 100.

[0047] Referring to Figure 11, in some embodiments, a character line mask 213 is provided to define the location of the first gate 23 of each memory cell and the location of the interconnect 32, wherein the interconnect 32 connects to the first gate 23 of the memory cell. The character line mask 213 includes a first portion 2131 and a second portion 2132. The first portion 2131 masks the channel structure 21 and defines the location of the subsequently formed first gate 23. As shown in Figure 11, the first portion 2131 is T-shaped and connects to the second portion 2132. The second portion 2132 defines the location of the subsequently formed interconnect 32. The second portion 2132 extends in a first direction D1 and connects to other first portions 2131 used to define the first gates of adjacent memory cells in the same row of the memory cell array. Please also refer to Figures 1 through 3.

[0048] Referring to Figure 12, in some embodiments, a patterning process is performed to remove portions of the laminate (including the conductive layer 203' and the insulating layer 201') that are not covered by the character line mask 213. The remaining conductive layer 203' forms a first gate 23 and interconnects 32 stacked above the substrate 100. Therefore, the top surface of the first gate 23 and the top surface of the channel structure 21 are coplanar. After the patterning process is completed, the character line mask 213 is removed by a suitable method, such as etching, stripping, or ashing. Then, the remaining space formed by removing portions of the laminate is backfilled with an insulating filler material 2010, such as silicon oxide. The insulating filler material 2010 may be over-deposited to cover the underlying components, including the first gate 23, interconnects 32, and channel structure 21. The insulating filler material 2010 can be planarized, for example, by CMP, to form a flat top surface on the insulating filler material 2010. In this embodiment, the insulating filler material 2010 and the gate dielectric layer 206 may include the same insulating material, such as silicon oxide, so there is no interface between the insulating filler material 2010 and the gate dielectric layer 206. In some embodiments, the remaining insulating layer 201' and the insulating filler material 2010 may be collectively referred to as the insulating material.

[0049] Referring to Figures 13A and 13B, in some embodiments, the formed second gate 25 and storage structure 26 are disposed adjacent to the first gate 23 and channel structure 21. In an exemplary embodiment, an opening (not shown) is formed vertically to pass through the insulating filler material 2010 and expose the substrate 100. Then, a silicon oxide layer 26A, a silicon nitride layer 26B, and another silicon oxide layer 26C of the storage structure 26 are formed in the opening, and a conductive pillar is formed as the second gate 25. The silicon oxide layer 26C and the conductive pillar are formed by filling a space surrounded by the silicon nitride layer 26B with silicon oxide, then forming a vertical hole (not shown) having the same shape and size as the predetermined second gate 25 in the filled silicon oxide, and then filling the vertical hole with a conductive material to form the second gate 25. As shown in Figure 13B, the second gate 25 is a vertical conductive pillar extending in the third direction D3. The silicon oxide layer 26A and silicon nitride layer 26B of the storage structure 26 are hollow columns surrounding the second gate 25 on the substrate 100.

[0050] Furthermore, the insulating filler material 2010 and the silicon oxide layer 26C may include the same insulating material, such that there is no interface between the insulating filler material 2010 and the silicon oxide layer 26C.

[0051] Referring to Figure 14, in some embodiments, two heavily doped regions 22S and 22D are formed on opposite sides of the channel structure 21 in each memory cell.

[0052] Referring to Figure 15, in some embodiments, source posts 27 and bit posts 29 are formed perpendicularly on the substrate 100. The formed source posts 27 are in contact with a heavily doped region 22S of one of the memory cells in each memory layer LM (Figure 1). Similarly, the formed bit posts 29 are in contact with a heavily doped region 22D of one of the memory cells in each memory layer LM (Figure 1). The channel structure 21, the gate dielectric layer 206, the first gate 23, the second gate 25, the heavily doped regions 22S and 22D, the source posts 27 embedded in the insulating material, and the bit posts 29 constitute the memory cell 20.

[0053] Figures 16A to 16D illustrate schematic diagrams of multiple intermediate stages in one application method for forming heavily doped regions 22S and 22D, source pillars 27 and bit pillars 29 of a three-dimensional flash memory device 10 according to some embodiments of the present disclosure. Figures 16A to 16D are cross-sectional views of the intermediate stages of the three-dimensional flash memory device 10 taken along line C1-C1 of Figures 14 and 15.

[0054] Referring to Figure 16A, in some embodiments, two vertical trenches (not shown) are formed by removing portions of the insulating filler material 2010, and these two trenches are adjacent to the channel structure 21. The vertical trenches can be formed by one or more etching processes. In some embodiments, an isotropic etching process can selectively etch the channel structure 21 (e.g., a p+ polysilicon layer) at a higher etching rate than that used for the insulating filler material 2010. After the p+ polysilicon ring is recessed, an n+ polysilicon material 220 is deposited on the insulating filler material 2010 to fill the vertical trenches. The n+ polysilicon material 220 is then planarized, for example, by CMP, until the insulating filler material 2010 is exposed. Therefore, the sidewalls 212 of the channel structure 21 are laterally recessed from the interface 2201 between the n+ polysilicon material 220 and the insulating filler material 2010.

[0055] Subsequently, referring to Figure 16B, in some embodiments, excess portions of the n+ polycrystalline silicon material 220 are removed, for example, by etching. The remaining portions of the n+ polycrystalline silicon material 220 form heavily doped regions 22S and 22D at the sidewalls 212 and 214 of the channel structure 21. For example, portions of the insulating filler material 2010 are removed to form a trench 230. The inner sidewalls 230s of the trench 230 are substantially flush with the interface 2201 between the n+ polycrystalline silicon material 220 and the insulating filler material 2010.

[0056] Subsequently, referring to Figure 16C, in some embodiments, an insulating material 240 is filled in the trench 230. Furthermore, the insulating material 240 covers the exposed sidewalls of the heavily doped regions 22S and 22D in the trench 230. In some embodiments, the insulating material 240 and the insulating filler material 2010 comprise the same insulating material, such as silicon oxide, such that there is no interface between the insulating material 240 and the insulating filler material 2010.

[0057] Next, referring to Figure 16D, in some embodiments, for example by etching to remove a portion of the insulating filler material 2010, thereby forming two vertical holes (not shown) in the insulating filler material 2010 having the same shape and size as the source posts 27 and bit posts 29. Then, a conductive material, including one or more metallic materials (e.g., tungsten) or other suitable conductive materials, is deposited on the insulating filler material 2010 to fill these vertical holes. The conductive material can be deposited by a CVD process such as metal-organic CVD (MOCVD), a PVD process such as vacuum evaporation, or a sputtering process, or a combination of the foregoing processes. Then, excess portions of the conductive material are removed, thereby forming the source posts 27 and bit posts 29 in the vertical holes. The source posts 27 and bit posts 29 are positioned on two opposite sides of the channel structure to contact the heavily doped regions 22S and 22D (e.g., n+ regions).

[0058] In some embodiments of the three-dimensional flash memory device 10, the word lines of different memory layers LM are located at different levels, while the second gate 25, source pillar 27, and bit pillar 29 pass through layers vertically stacked above the substrate 100. According to embodiments, the structural configuration of these related components can increase the activity of the memory cells of the three-dimensional flash memory device 10, particularly the activity of the memory cells of the three-dimensional NOR flash memory device. For example, the first gate 23 and the second gate 25 are disposed on one side of the channel structure 21, making the gate components more densely arranged in the lateral region. Furthermore, multiple laminated layers can be etched simultaneously, meaning fewer etching steps can be used. A recessed process can be used to form a film layer for separating material layers. The word lines of the memory cells of the three-dimensional flash memory device 10 can be formed in the same process step. The source pillar 27 and bit pillar 29 of the three-dimensional flash memory device can be formed in the same process step. Furthermore, some embodiments of the 3D flash memory device 10 provide simpler character line decoding to simplify memory operations. Moreover, according to some embodiments, a 3D discrete gate flash memory device with higher component integration density and higher operating efficiency can be provided. For example, compared to conventional stacked gate memory devices, the 3D discrete gate flash memory device of the embodiments has more efficient programming, more efficient erasure, and better data retention capabilities.

[0059] Furthermore, the three-dimensional flash memory device of the embodiment has many advantages in terms of environmental friendliness. For example, compared with two-dimensional memory devices, the memory device of the embodiment is constructed as a three-dimensional structure with a higher component integration density and is suitable for applying larger components (e.g., about 100 nanometers) in the three-dimensional flash memory device of the embodiment. Therefore, it is not necessary to use advanced lithography processes, such as immersion lithography, to form the three-dimensional flash memory device of the embodiment. The three-dimensional flash memory device of the embodiment can be formed by typical lithography processes, which require less power than advanced lithography processes. Furthermore, as described above, fewer etching steps are required to form the three-dimensional flash memory device of the embodiment, so less etchant is used for etching during device manufacturing. This reduces the problem of global warming and other potential hazards caused by etchants containing fluorocarbons. Furthermore, the three-dimensional flash memory device of the embodiment can be erased by FN tunneling injection to avoid over-erasing of memory cells. Accordingly, the three-dimensional flash memory device of the embodiment has higher durability (number of programming and erasure repetitions) and longer service life, thereby reducing unnecessary waste of environmental resources.

[0060] Although the invention has been described by way of the foregoing examples and according to several preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, the embodiments disclosed above are intended to cover various modifications and similar configurations (as will be understood by one of skill in the art to which this disclosure pertains). Therefore, the scope defined in the appended claims should be given the broadest interpretation to cover all modifications and similar configurations. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a perspective view of a three-dimensional flash memory device according to some embodiments of the present disclosure. Figure 2 is a circuit diagram of the three-dimensional flash memory device of Figure 1. Figure 3 is a top view of adjacent memory cells in the same row in the memory layer of the three-dimensional flash memory device according to some embodiments of the present disclosure. Figures 4A, 4B, and 4C-1 show schematic diagrams of a memory cell during operation according to some embodiments of the present disclosure. Figure 4C-2 shows a schematic diagram of a memory cell during an FN erase operation according to some embodiments of the present disclosure. Figures 5A, 5B, 6, 7, 8, 9, 10, 11, 12, 13A, 13B, 14, and 15 illustrate schematic diagrams of multiple intermediate stages of a method for forming a three-dimensional flash memory device according to some embodiments of the present disclosure. Figures 16A to 16D show schematic diagrams of multiple intermediate stages of one application method for forming a heavily doped region, source pillar, and bit pillar of a three-dimensional flash memory device according to some embodiments of the present disclosure. Figure 17 shows a top view of some embodiments according to this disclosure, in which backfill material includes channel material and fills the internal space of the channel structure.

Claims

1. A flash memory cell, comprising: A channel structure is formed above a substrate; A first gate is disposed adjacent to the channel structure; A second gate is disposed separately from the first gate and the channel structure; a storage structure is disposed adjacent to the channel structure; and a source post and a bit post are disposed adjacent to opposite sidewalls of the channel structure, wherein the first gate does not overlap perpendicularly with the channel structure, the storage structure includes a charge trapping layer surrounding the second gate, and the channel structure forms a channel ring or a channel sheet.

2. The flash memory cell as claimed in claim 1, wherein the charge trapping layer is separated from the first gate and the second gate, and the first gate and the second gate are disposed on the same side of the channel structure.

3. The flash memory cell as claimed in claim 1 further includes an insulating material formed on the substrate, wherein the storage structure, the second gate, the source post and the bit post are disposed perpendicularly on the substrate and pass through the insulating material.

4. The flash memory cell as described in claim 1, wherein the first gate and the second gate serve as a selection gate and a control gate of a discrete gate memory cell, respectively, and the top surface of the first gate is coplanar with the top surface of the channel structure.

5. The flash memory cell as claimed in claim 1, wherein the first gate and the second gate are adjacent to a sidewall of the channel structure, the sidewall being adjacent to an opposite sidewall of the channel structure.

6. The flash memory cell as described in claim 5, wherein the storage structure includes: A first part extends along the sidewall of the channel structure; And a second portion extending between the first gate and the second gate.

7. The flash memory unit as described in claim 1, further comprising: The heavily doped regions are located at the opposite sidewalls of the channel structure, respectively. The source pillar and the bit pillar are connected to the channel structure through the heavily doped regions.

8. A three-dimensional flash memory device, comprising: Multiple memory layers are stacked on a substrate, spaced apart by an insulating material. Each memory layer includes multiple memory cells arranged in an array. Each memory cell includes: a channel structure disposed in the memory layer; a first gate disposed in the memory layer and adjacent to the channel structure; a second gate vertically disposed on the substrate and spaced apart from the first gate and the channel structure; a storage structure adjacent to the channel structure; and a source post and a bit post vertically disposed on the substrate and adjacent to opposite sidewalls of the channel structure, respectively. The first gate does not vertically overlap with the channel structure. The storage structure includes a charge trapping layer surrounding the second gate, and the channel structure forms a channel ring or a channel sheet.

9. The three-dimensional flash memory device as claimed in claim 8, wherein the second gate is a common control gate for one group of memory cells stacked in a vertical direction relative to the substrate, and the source line post and the bit line post are a common source line and a common bit line for one group of memory cells stacked in the vertical direction relative to the substrate, respectively.

10. The three-dimensional flash memory device as claimed in claim 8, wherein the memory cells of each of the memory layers are arranged in an array having multiple rows and columns, and the first gate systems of a group of the memory cells in each of the rows are electrically connected to each other.

11. The three-dimensional flash memory device as claimed in claim 10, wherein the first gates of the group of memory cells in each of the rows are electrically connected by an interconnect extending in a row direction, and in each of the memory layers, the interconnects extending in the row direction are parallel to each other, and the interconnects are connected to a wire.

12. The three-dimensional flash memory device as claimed in claim 8, wherein the charge trapping layer is separated from the first gate and the second gate, and the first gate and the second gate are disposed on the same side of the channel structure.

13. The three-dimensional flash memory device as claimed in claim 8, wherein the first gate and the channel structure of each memory cell in the memory cells are formed in one of the memory layers and extend parallel to the substrate.

14. The three-dimensional flash memory device as claimed in claim 8, wherein the storage structure, the second gate, the source post and the bit post are disposed vertically on the substrate and pass through the insulating material.

15. The three-dimensional flash memory device as claimed in claim 8, wherein each memory cell of the memory cells further comprises: Heavily doped regions are located at the opposite sidewalls of the channel structure, wherein the source post and the bit post are connected to the channel structure via the heavily doped regions.

16. The three-dimensional flash memory device as claimed in claim 8, wherein the first gate and the second gate serve as a selection gate and a control gate of a discrete gate memory unit, respectively, and the top surface of the first gate is coplanar with the top surface of the channel structure.

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