Programmable circuit board and method of use

Abstract

A programmable circuit board preferably includes: a base, a memory, and a working metal, wherein the base preferably includes a set of cells defined by a substrate stack and a set of driver elements. A method for dynamically programming a circuit board preferably includes: receiving a circuit board design; determining a cell positioning map; positioning the working metal; optionally assembling the remaining portion of the circuit board; optionally testing the assembled PCB emulator; and / or optionally updating the configuration of the physical PCB emulator.

Description

Technical Field

[0001] This application claims the benefits of U.S. Provisional Application No. 63 / 672,915, filed July 18, 2024, and U.S. Provisional Application No. 63 / 784,789, filed April 7, 2025, each of which is incorporated herein by reference in its entirety.

[0002] This invention relates generally to the field of electronic design, and more specifically to a novel and practical programmable circuit board and a method of using the same in the field of electronic design. Prior Technology

[0003] none. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic representation of a side cross-sectional view of one variant of a programmable circuit board.

[0006] Figure 2 is an illustrative embodiment of a side cross-sectional view of an exemplary printed circuit board (PCB) emulator formed using a programmable circuit board.

[0007] Figure 3 is a schematic top view representation of one variant of a substrate that defines multiple cells.

[0008] Figure 4 is a schematic representation of a top view of a second variant of a substrate that defines multiple cells.

[0009] Figure 5 is a schematic representation of one embodiment of a cell.

[0010] Figure 6 shows an illustrative embodiment of forming a PCB simulation.

[0011] Figure 7 is an illustrative embodiment of the drive circuit arrangement within the base.

[0012] Figure 8 is a schematic representation of one variant of a method for dynamic programming of a circuit board.

[0013] Figure 9 is a schematic representation of one variant of a programmable circuit board and its associated components. Implementation

[0014] The following description of preferred embodiments of the present invention is not intended to limit the invention to these preferred embodiments, but rather to enable those skilled in the art to make and use the invention.

[0015] 1. Overview.

[0016] As shown in Figure 1, in several variations, the programmable circuit board 10 may include: a rig 100 comprising a set of unit cells 101 co-defined by a substrate stack 110 and a set of driver elements 120; a reservoir 130 fluidly connected to the set of unit cells; and working metal 140 held within the reservoir. In operation, droplets 140' of the working metal are selectively drawn into a subset of the unit cells to co-define a set of circuit traces. The programmable circuit board (dynamically programmable circuit board, DPCB) may optionally be used with or include the following elements: conductive layer 201, electronic components 202, a set of one or more controllers 210, and / or other components (e.g., as exemplarily shown in Figures 2 and / or 9). The DPCB may optionally include one or more vias 103 (e.g., through-hole vias 103a and / or blind vias 103b) defined therein. Programmable circuit boards function to dynamically and reversibly define printed circuit board (PCB) analog components 300.

[0017] As shown in Figure 8, in several variations, the method 90 for dynamically programming a circuit board may include: receiving a circuit board design S910; determining a cell location map S920 (e.g., pixelating traces in the circuit board design to identify target cell locations); locating working metal S930 (e.g., locating based on the cell location map, preferably locating droplets of working metal within each target cell location); optionally assembling the remaining parts of the circuit board components S940; optionally testing the assembled PCB emulator S950; and / or optionally updating (e.g., dynamically updating) the configuration of the physical PCB emulator (e.g., by repeating any or all of the previous steps).

[0018] In one illustrative embodiment, the programmable circuit board includes a base comprising an array of cells (e.g., regular arrays, such as two-dimensional or three-dimensional matrices; regular or irregular stacks of regular two-dimensional arrays, such as stacks of identical or substantially identical two-dimensional arrays with alignment errors between stacked arrays, stacks of dissimilar two-dimensional arrays, etc.; irregular arrays, such as irregular two-dimensional or irregular three-dimensional arrays; etc.); a set of driver elements (e.g., FETs, TFTs, etc.), each driver element assigned to a different cell of the matrix; a set of drive lines extending through the body of the substrate and electrically connecting the driver elements to a set of controllers; a memory fluidly connected to the cells; and working metal housed within the memory. In some embodiments, the stacking of layers may exhibit some alignment errors (e.g., subpixel, single pixel, multipixel, etc.) between planar arrays of different layers; in such embodiments, the method preferably includes determining this alignment error (e.g., before performing S920 and / or S930) and / or compensating for this alignment error (e.g., during performing S920 and / or S930). The substrate stack may include an upper outer substrate, a lower outer substrate, and a set of intermediate substrates disposed therebetween. One or more intermediate substrates may define an array of vias extending therethrough. Each cell includes: an upper substrate segment, an intermediate substrate segment containing vias, a lower substrate segment, a pixel driver element configured to control the positioning of working metal along the wide face of the intermediate substrate segment, and a via driver element configured to control the flow of working metal within the vias. In several variations, the outer substrate (e.g., the uppermost or lowermost substrate in the stack) may optionally include a blind via mesh (e.g., where vias are capped along the outer face). In these variations, the DPCB may optionally include or be used with an anisotropic conductive layer, which may be used to attach other electronic components (such as surface mount components or through-hole components (e.g., using an interposer)) to conductive paths within the DPCB (e.g., defined by one or more trace emulators 301 and / or via emulators 302). An embodiment is shown in FIG2.

[0019] In one illustrative embodiment of DPCB operation, droplets of the working metal can be selectively moved to a target cell array location (e.g., by selectively applying an electric field to sequentially adjacent cells in a predetermined droplet path until the target location is reached, such as applying an electric field to control EWOD and / or other electrowetting of the droplets) to collectively form a simulant of the PCB trace. For example, this method and / or any suitable element thereof (e.g., S930) can be repeated until a series of adjacent droplets are formed in adjacent cells, wherein the series of adjacent droplets collectively define the trace, and droplets extending through vias define interlayer connections. In several variations, during PCB simulant setup, the DPCB and / or the working metal (or any suitable portion thereof) can be heated above the melting point of the working metal, and once the PCB trace simulant is formed, the DPCB can be frozen (e.g., cooled below the melting point of the working metal). Once the PCB simulant is formed (e.g., with or without cooling the DPCB), the electric field holding the droplets can be removed. The resulting circuit board simulator can then be tested (e.g., using conventional methods and / or equipment), wherein the circuit output can be obtained at the cell (e.g., by means of a driver element), at the surface (e.g., using a conductive layer), from a connector (e.g., USB, Ethernet, etc.; connected to the circuit board at the conductive layer, or connected to the filled cell by direct connection); from an installed component; or otherwise. One embodiment is shown in Figure 6.

[0020] The programmable circuit board is preferably operable to perform methods for dynamically programming the circuit board and / or to be used in the performance of such methods, but may additionally or alternatively be operable to perform any other suitable methods and / or to be used in the performance of any other suitable methods. The methods for dynamically programming the circuit board are preferably performed by and / or using the programmable circuit board, but may additionally or alternatively be performed by and / or using any other suitable system.

[0021] However, the programmable circuit board may additionally or alternatively include any other suitable elements in any suitable configuration, and / or the method may additionally or alternatively include any other suitable elements performed in any suitable manner.

[0022] As used herein, the term "dynamic" (such as in "dynamically programmable board" and / or "dynamic programming of a board") does not necessarily indicate reconfiguration (e.g., reprogramming) and / or reconfigurability of the board while it is in use (e.g., as a device-under-test (DUT), as one or more circuits in which it is configured, etc.). Rather, the term "dynamic" may additionally or alternatively indicate the ability to reconfigure the DPCB multiple times (e.g., any number of times; the number of times limited by DPCB degradation and / or maintenance considerations, such as but not limited by factors such as limited availability of reconfiguration resources and / or inability to cycle individual pixels between different states; etc.). However, in some variations, the DPCB may be reconfigurable while in use (e.g., as a DUT, etc.) and / or reconfigurable at any other suitable time.

[0023] 2. Technical advantages.

[0024] Variations of this technology may offer one or more advantages over conventional technologies.

[0025] First, variations of this technology can enable faster, cheaper, and / or less environmentally damaging PCB prototyping. Instead of static prototyping and shipping of new PCB designs (which can take weeks or months), dynamically programmable boards can be prototyped in minutes or hours by selectively moving droplets to different locations within a substrate. This avoids the need for multiple iterations of PCB design manufacturing, which can further increase overall design timelines (e.g., due to waiting for PCB manufacturing and shipping) and may also lead to higher costs and / or environmental impact (e.g., due to the manufacturing and shipping of multiple prototype PCBs).

[0026] Second, variations of this technology can additionally or alternatively enable PCB prototyping, testing, and design to be entirely remote. Since the DPCB is a direct emulation of the PCB, when tested using the same tests, the DPCB can produce the same or similar test results as the PCB. In a first embodiment, the PCB design can be transferred to a remote facility, where the remote facility can create a DPCB emulation of the PCB design and run tests on it, with the test results being fed back to the user. In another embodiment, physical connections (e.g., USB, Ethernet, etc.) and results can be simulated on the user's local device. In yet another embodiment, physical connectors (e.g., USB, Ethernet) can be physically connected to the DPCB emulation, where the user can connect to the DPCB emulation via physical connectors (e.g., indirect connections via a local device medium receiving connector signals, such as where the user can SSH into a local device).

[0027] However, variations of the systems and / or methods disclosed herein may additionally or alternatively provide further advantages.

[0028] 3. System.

[0029] As shown in Figure 1, in several variations, a programmable circuit board may include: a base comprising a set of cells defined by a substrate stack and a set of driver elements; a memory fluidly connected to the set of cells; and working metal held within the memory. The programmable circuit board functions to dynamically and reversibly model a printed circuit board emulator.

[0030] The base serves to provide a physical component that defines the PCB analog component. The base may comprise a set of cells defined by a substrate stack and a set of driver components, or otherwise configured. The system preferably includes a single base, but may additionally or alternatively include multiple bases (e.g., fluidly connected to the same reservoir, operatively connected to the same controller, etc.).

[0031] The substrate stack serves to define a set of cells between them, through which working metal can flow via manifold 102 to each of a set of target cell locations that together form a PCB trace. The substrate stack can also define working metal wetting behavior, anchor driver components, define physical boundaries between cells, and / or perform other functionalities.

[0032] A substrate stack may contain one or more substrates. The substrates of the base serve to define the portions of the cells, control the wetting behavior of the working metal, and provide other functionalities.

[0033] The substrates can be arranged in parallel (e.g., wide-face parallel), but can alternatively be arranged in series, or in any other suitable configuration. The different substrates in the stack can have the same or different dimensions (e.g., length, width, thickness, etc.). In several embodiments, the substrate may have a thickness of 0.1-2 mm (e.g., 0.1, 0.2, 0.3, 0.5, 0.7, 1, 1.5, 2, 0.1-0.2, 0.2-0.3, 0.3-0.5, 0.5-0.7, 0.7-1, 1-1.5, and / or 1.5-2 mm, etc.), but may additionally or alternatively have a thickness greater than 2 mm (e.g., 3, 5, 10, 2-3, 3-5, 5-10, and / or greater than 10 mm, etc.) and / or less than 0.1 mm (e.g., 10, 20, 35, 50, 70, 10-20, 20-35, 35-50, 50-70, 70-100, and / or less than 10 μm, etc.). The substrate may be coextensive, offset, and / or arranged in any other suitable manner.

[0034] The substrate can be: plastic (e.g., polyimide, polyethylene naphthalate, polyethylene terephthalate, polycarbonate, transparent polyamide, cyclic olefin polymers, etc.), glass (e.g., borosilicate glass, aluminosilicate glass, alkali-aluminosilicate glass, soda-lime glass, Corning Gorilla Glass, AGC Dragontrail Glass, etc.), ceramic (e.g., alumina, yttria-stabilized zirconia, magnesium aluminate spinel, alumina, silicon dioxide (such as fused silica or quartz), glass ceramics (such as CERAN or ZERODUR, etc.), silicon, and / or made of any other suitable material. Substrates can be manufactured using thin-film deposition, lamination, stacking processes, melt forming processes (e.g., float, fusion draw, slot draw, etc.) and / or other processes. Substrates within a stack can contain the same or different materials (e.g., a glass outer substrate and a plastic interlayer).

[0035] The substrate may be coated (e.g., the embodiments shown in Figures 1, 2, 3, and 4) or uncoated. The coating may comprise one or more layers (e.g., discrete layers, graded composition layers, etc.). The coating may comprise one or more conductive coatings 111, dielectric coatings 112, and / or any other suitable coating. The coating may extend above the driver element, below the driver element, and / or in any other configuration relative to the driver element. The substrate coating and / or its layers are preferably dielectric, but may alternatively be any other coating. Examples of substrate coatings may include: hafnium oxide (e.g., HfO₂), tantalum oxide (e.g., Ta₂O₅), barium strontium titanate, silicon nitride, LiF, NaF, Al₂O₃, SiO₂, Si₃N₄, MgO, other dielectrics used in LED or OLED displays, ITO, electroplated layers, filler layers, and / or any other suitable coating material.

[0036] The conductive coating 111 may comprise: one or more transparent conducting oxides (TCOs), such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), etc., and / or combinations thereof; other transparent conductive materials; metal nitrides, such as titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, vanadium nitride, etc., and / or combinations thereof; metals, such as titanium, copper, and / or titanium-copper alloys; and / or any other suitable conductive material. In some embodiments, the thin-film resistivity of the conductive material is preferably greater than a threshold value (e.g., less than 200, 200, 500, 1000, 1500, 2000, 3000, 4000, 5000, 10,000, 100-200, 200-500, 500-1000, 1000-1500, 1500-2500, 2000-3000, 3000-5000, 5000-10,000, or greater than 10,000 Ω / sq, etc.), such as to provide excellent radio frequency (RF) transparency. However, the conductive coating may additionally or alternatively contain any other suitable material with any suitable properties.

[0037] The dielectric coating 112 may comprise: hafnium oxide (e.g., HfO₂), tantalum oxide (e.g., Ta₂O₅), barium strontium titanate, silicon nitride, LiF, NaF, Al₂O₃, SiO₂, Si₃N₄, MgO, other dielectrics used in LED or OLED displays, and / or any other suitable dielectric material. One or more coatings may extend across the entire width of the substrate, extend only along a portion of the substrate surface (e.g., working metal region; cell region; etc.), and / or extend along any other portion of the substrate. The coating material may be selected based on the initial liquid metal droplet contact angle, liquid metal contact angle hysteresis, dielectric capacitance, and / or any other parameter. The dielectric may be deposited (and / or otherwise fabricated) using atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (such as sputtering), doping (e.g., using a doped dielectric), printing, spraying, and / or any other suitable deposition method. The dielectric can be configured in different ways to achieve the desired properties. For example, the thickness of the dielectric layer can be adjusted to modify the capacitance of the capacitor defined at the cell (e.g., defined by the dielectric layer, one or more conductive materials embedded under the dielectric layer, and optionally working metal droplets); in several embodiments, the dielectric layer can have a thickness of about: 10, 20, 30, 50, 75, 100, 125, 150, 200, 250, 300, 400, 500, 750, 1000, less than 10, 10-20, 20-50, 30-75, 75-125, 100-150, 150-200, 200-300, 300-500, 500-1000, and / or greater than 1000. Preferably, the leakage current across the dielectric layer is negligible (e.g., for manipulating the DPCB to position the working metal, for using the configured DPCB as a PCB emulator, etc.), such as the absence or minimal presence of pinholes penetrating the dielectric layer. The surface roughness of the dielectric can be controlled to affect the droplet contact angle and contact angle hysteresis. However, the dielectric can be configured in other ways.

[0038] In one specific embodiment, the substrate may include: glass coated with TCO (e.g., ITO), wherein driving elements (e.g., including one or more TFTs and / or other electrical devices) are disposed (e.g., defined on, deposited on, etc.) the glass substrate (e.g., such that the driving elements (such as one or more TFT terminals) are electrically connected to the TCO), and a dielectric is coated on the substrate, the driving elements and / or the TCO.

[0039] In some variations, the system may include two or more outer substrates (e.g., an upper outer substrate and a lower outer substrate). In some variations, the system may include zero, one, or more intermediate substrates. Alternatively, the system may include any other suitable number and / or arrangement of substrates.

[0040] The outer substrate serves to define the outer boundary of the base and can act as an interface between traces within the DPCB and the external environment. The outer substrate can form the top and bottom of the substrate stack, but can alternatively form any other suitable part of the system. In a first embodiment, the outer substrate may not include vias (e.g., it may be smooth or substantially smooth). In a second embodiment, the outer substrate may define a blind via 103b. The blind via preferably defines an inlet hole (e.g., at the surface of the substrate, such as the inner surface of the outer substrate), a terminal (e.g., within the substrate, preferably between the inner and outer surfaces of the substrate; preferably substantially parallel to the inlet hole and the surface of the substrate), and a sidewall extending from the inlet hole to the terminal (e.g., a cylindrical sidewall, a conical sidewall, a straight sidewall, a pyramidal sidewall, etc.), wherein the volume of the blind via is defined by the inlet hole, the terminal, and the sidewall. Blind vias are preferably capped along the outer surface (e.g., where the blind via is made by drilling through the substrate and subsequently capping the resulting via along the outer surface), wherein the via has an opening (entry hole) on the inner surface of the substrate and is sealed along the outer surface of the substrate (e.g., by a cap 103b', such as a conductive cap 103b'', wherein the cap defines a terminal pad that defines the via), but may be capped in other ways (or may not include such a cap, such as where the via terminates within the substrate at the location where it remains after the blind via is drilled). Blind vias can be capped with conductive materials (e.g., copper, gold, tantalum, etc.), with glass, with materials having anisotropic conductors (e.g., vertically aligned and laterally insulated), and / or with any other material. The capping material (and any other material that may come into contact with the working metal) is preferably compatible with the working metal (e.g., both solid and liquid) (e.g., does not react with it, is not dissolved by it, etc.), but may additionally or alternatively be any other suitable material. Blind vias are preferably arranged in a grid pattern, but can alternatively be arranged in any other suitable pattern (e.g., a regular or irregular array, such as a planar array). Blind vias are preferably aligned with other vias in the base (e.g., with vias defined in the intermediate substrate), but can alternatively be offset or otherwise arranged. The number of blind vias is preferably the same as the number of vias in the intermediate substrate layer, but can alternatively be more or fewer. However, the outer substrate can be configured in other ways.

[0041] In one illustrative embodiment, the upper outer substrate may be smooth and without vias, while the lower outer substrate has blind vias that are capped along their outer surfaces (e.g., the embodiment shown in FIG. 1). The via grid spacing of the lower substrate may be substantially the same as that of the vias in the intermediate substrate, but may alternatively have any other suitable grid spacing. In a second illustrative embodiment, both the upper and lower outer substrates may include blind vias, wherein the blind vias are capped on their respective outer surfaces.

[0042] However, the outer substrate can be configured in other ways.

[0043] Intermediate substrates are disposed between the outer substrates in a substrate stack and function to divide the volume between the outer substrates into several fluid manifolds. The substrate stack may include one or more intermediate substrates. The intermediate substrates preferably extend along the entire length and width of the outer substrates, but may alternatively extend only a portion thereof. Different intermediate substrates may have the same or different parameters (e.g., material, size, features, etc.). Intermediate substrates may have the same or different parameters as the outer substrates. In one embodiment, the substrate stack may include one or more intermediate substrates arranged in parallel, wherein the intermediate substrates have the same set of parameters as the outer substrates.

[0044] In a first variant, the intermediate substrate may define a set of vias 103a. The vias may be formed by drilling, patterning, and / or any other suitable method. The vias are preferably arranged in a regular grid along the intermediate substrate (e.g., the embodiments shown in Figures 1 and 3), but may alternatively be arranged in a predetermined pattern (e.g., spiral, concentric circles, etc.) or any other pattern. The vias may be coated with a dielectric (e.g., the same dielectric as the substrate, a different dielectric than the substrate, etc.), a conductive material (e.g., copper, gold, carbon nanotubes, etc.), and / or any other material.

[0045] In a second variant, the intermediate substrate may be smooth and undamaged (e.g., solid) and without vias or features.

[0046] However, the intermediate substrate can be configured in other ways.

[0047] In several variations, the substrate stack may include a set of holding mechanisms that function to retain working metal droplets within the cells. The holding mechanisms are preferably passive, holding the working metal when the actuator element is turned off, but can alternatively be active (e.g., by an applied voltage, etc.). The holding mechanisms can utilize: surface tension, intermolecular forces (e.g., hydrogen bonds, van der Waals forces, dipole-dipole interactions, etc.), physical holding (e.g., holding the droplet in a tank), and / or other holding methods. The holding mechanisms may include: a surface coating (e.g., a dielectric) controlling the surface tension of the working metal droplets (e.g., to prevent droplet wicking, to form a high contact angle, etc.); holding walls or pins (e.g., positioned along opposite cell sides, along cell corners, etc.); a phase change (e.g., solidifying the working metal droplets before turning off the actuator element); the actuator element; and / or other holding mechanisms. Physical holding mechanisms are preferably conductive (e.g., the same or similar conductivity as the working metal; alternatively, higher or lower), but can alternatively be electrically insulating.

[0048] The substrate stack can be hermetically sealed to control the environment within the substrate stack and to retain the working metal within a manifold defined between adjacent substrates in the stack. The hermetically sealed substrate stack is preferably completely sealed, isolating the interior of the substrate stack from ambient fluids, but alternatively, it may not be completely sealed. The hermetically sealed material may comprise: AMOLED or OLED hermetically sealed materials, such as plastics, glass (e.g., glass frit, bonded glass (e.g., where laser encapsulation is used to melt and / or bond the glass frit to form a hermetically sealed material), etc.), epoxy resins, metals (e.g., using metal-to-metal bonding), ceramics, and / or other materials. However, any other suitable material may be used. The hermetically sealed material is preferably disposed between each adjacent substrate layer, but may additionally or alternatively disposed between subsets of adjacent substrate layers, coated on the outer edges of the substrate stack, or otherwise disposed. The hermetically sealed material may maintain: a vacuum, reducing atmosphere, gas-filled portions, volumes filled with gas or other materials, and / or any other suitable environment within the substrate stack. Please note that the system (e.g., a reservoir and / or its manifold) is preferably operable to compensate for volume changes in the working metal (e.g., due to thermal expansion of solid and / or liquid metals, due to phase changes of metals, etc.), such as including one or more compressible fluids (e.g., gases, preferably inert gases (such as nitrogen and / or rare gases)), expansion tanks (e.g., including movable and / or deformable walls, such as membranes, which isolate the environment within the substrate stack from the surrounding environment but allow for volume changes, such as changes in response to the expansion and / or contraction of the working metal), and / or any other suitable components.

[0049] The substrate stack preferably defines the inter-substrate spacing. The inter-substrate spacing is preferably substantially constant along each inter-substrate gap, but may alternatively vary along the gap. The inter-substrate spacing is preferably substantially equal across different inter-substrate gaps in the substrate stack, but may alternatively vary between different gaps. In some embodiments, the inter-substrate spacing can be 10-200 μm (e.g., 15-150 μm, such as 17 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 65 μm, 80 μm, 100 μm, 120 μm, 140 μm, 15-20 μm, 17-35 μm, 30-40 μm, 35-50 μm, 50-90 μm, 90-150 μm, etc.); however, the spacing can additionally or alternatively be less than 10 μm (e.g., 0.1-10 μm, such as 0.1-0.3 μm, 0.3-0.1 μm, 1-2 μm, 2-5 μm, 5-10 μm, etc.; less than 0.1 μm; etc.), greater than 200 μm, and / or have any other suitable size.

[0050] The substrate stack may optionally include a set of spacers that control the inter-substrate spacing (e.g., control the gap height or gap width). The spacers may include: spheres (e.g., with a diameter substantially the same as the desired gap height, such as 17 μm, 35 μm, 40 μm, 45 μm, 50 μm, between 30 and 50 μm, less than 30 μm, greater than 50 μm, etc.), protrusions (e.g., pins, walls, etc.), slots (e.g., complementary to protrusions), and / or having any other suitable shape factor. The spacers may be: disposed within a hermetically sealed area, defined along the edge of one or more of the substrate faces, and / or otherwise disposed. The spacers may be disposed along two opposite sides of the substrate stack, along all edges of the substrate stack, and / or otherwise disposed. However, etched trenches, deposited structures, and / or other spacer mechanisms can be used to achieve the spacing between adjacent substrates.

[0051] A stack of substrates can define a set of manifolds that function to fluidly connect cell cells to a reservoir. The manifolds are preferably defined between two adjacent substrates, but may alternatively include conduits disposed within the inter-substrate gap, channels defined within the substrate or along the surface of the substrate, and / or otherwise defined. In a first variation, the manifold is formed by a series of adjacent cells (e.g., the manifold is subdivided into an array of cells). In a second variation, the manifold is a channel defined between columns of cells (e.g., defined by a set of walls extending along the edge of the cell). In a third variation, the manifold is a channel extending through the substrate body and fluidly connected to each cell. However, the manifold can be defined in other ways.

[0052] The manifold may be hermetically sealed or open to the surrounding environment. It may contain inert gases, air, etchants, or other fluids, and / or any other suitable substance.

[0053] However, substrate stacking can be configured in other ways.

[0054] The base may also include a set of actuator elements that drive a flow of working metal to an area adjacent to the actuator elements. The actuator elements may induce the flow of working metal using electrostatic, capillary, electromagnetic (e.g., by applying a moving electric field, etc.) and / or any other suitable mechanism. For example, the set of actuator elements may apply a voltage across a region of a cell, causing the working metal to move to that region. In an illustrative embodiment, a first actuator element may be held at ground potential while a voltage is applied to a second actuator element, which attracts and slides the working metal droplet. In a second embodiment, the set of actuator elements may selectively alter the surface charge of a substrate surface adjacent to the working metal droplet to selectively attract and / or repel the working metal droplet toward or away from a location. In a third embodiment, the set of actuator elements may apply a global non-uniform electromagnetic field to the substrate stack, wherein the electromagnetic field is patterned to form a trace pattern. In a fourth embodiment, the set of actuator elements applies a moving electromagnetic field (e.g., a global EM field) to the working metal droplet to move the droplet to a target location. However, the actuator elements may otherwise control the positioning of the working metal droplet. Additionally or alternatively, the driver element may function as a sensing element and may measure voltage, current, resistance, capacitance, signal, and / or other electrical signals.

[0055] The set of driver elements can be disposed along the wide face of one or more substrates within the substrate stack (e.g., the embodiment shown in FIG. 1). In several embodiments, the driver elements can be disposed along: the upper inner wide face of each substrate, the lower inner wide face of each substrate, the upper and lower surfaces of each substrate, adjacent to vias (e.g., along the upper and lower surfaces of the substrates defining the vias), and / or on any other suitable surface. The driver elements can be mounted to the substrate, manufactured from the substrate, and / or otherwise attached to the substrate. The driver elements can be configured in a regular pattern, an irregular pattern, and / or any other suitable pattern. A regular pattern is preferably a grid (e.g., having the same spacing as the cells), but can additionally or alternatively be configured as a spiral, concentric circles, and / or any other pattern.

[0056] Each driver element can be operatively connected to a controller (e.g., a driver controller) that controls the operation of the driver element. For example, the controller can control: when a voltage is applied to the driver element, the amount of voltage applied, the frequency of the applied voltage, and / or other control parameters. The base can include: a driver element for each cell (e.g., a pixel driver), multiple driver elements for each cell (e.g., positive and negative driver elements, etc.), a driver element for each via (e.g., a via driver), multiple driver elements for each via (e.g., positive and negative driver elements, etc.), and / or any number of driver elements.

[0057] The driver elements can be connected to the driver controller via a set of drive lines 204, or otherwise connected to the controller. Each driver element preferably has its own drive lines (e.g., these drive lines are electrically isolated), but alternatively, they can share drive lines. A subset of the driver elements can be connected in parallel or in series. In a first variant, the drive lines can extend through the body of the substrate (e.g., embedded within the substrate); an embodiment is shown in FIG. 7. In a second variant, the drive lines can extend along the surface of the substrate, such as in the space between pixels. However, the drive lines can be arranged in any other suitable manner.

[0058] A driver element may comprise one or more of the following: transistors; capacitors; transistors and capacitors; combinations of transistors and capacitors; field-effect transistors (FETs), such as thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs); electrodes; current-based drivers, such as micro LED drivers; and / or any other suitable driver element. A driver element may comprise (e.g., made therefrom) one or more of the following: semiconductor materials (e.g., silicon materials, such as amorphous silicon, polycrystalline silicon (such as low-temperature polycrystalline silicon, LTPS)), etc.); metal oxides, such as zinc oxide, indium gallium zinc oxide (IGZO), tin oxide, copper oxide, etc.; compound semiconductors, such as cadmium selenide, metal halide perovskite, etc. Perovskites, etc.; organic semiconductors; semiconductor carbon nanotubes, etc.); dielectric materials (e.g., silicon compounds, such as silicon dioxide, silicon nitride, silicon oxynitride, etc.; high K-value dielectrics, such as hafnium oxide, zirconium oxide, aluminum oxide, barium titanate and / or strontium titanate, etc.; polymer dielectrics, such as PMMA, PVA, parylene, etc.); etc.); conductive materials (e.g., metals; transparent conductive oxides, such as ITO, FTO, AZO, ITO, etc.; graphene; metal carbon nanotubes, etc.); and / or any other suitable materials.

[0059] However, the driver element can be configured in other ways.

[0060] The base may also include a set of sensing elements that function to measure electrical signals. These sensing elements can measure current, voltage, resistance, capacitance, and / or other electrical signals. The sensing elements can be configured to operate in different modes, such as continuous sensing, periodic sensing, or on-demand sensing, and / or any other mode. The sensing elements may include: driver elements, electrodes, resistors, capacitors, diodes, inductors, operational amplifiers, and can be semiconductor-based sensors, thin-film sensors, micro-electromechanical systems (MEMS), and / or otherwise constructed. The sensing elements can be made from a substrate, can be separate integrated components, or can be otherwise fabricated. The base may include: sensing elements for each: cell, cell column, cell group, cell sub-component (e.g., pixel, via, etc.), memory, and / or any other suitable area of ​​the base. The sensing elements are preferably connected to a controller (e.g., the same or different controller as the one driving the driver elements), but can be connected to any other output. The sensing element can be connected to the controller in the following ways: by drive lines (e.g., when the driver element acts as the sensing element, when the sensing element is separated from the driver element, etc.), by using auxiliary lines (e.g., extending within the substrate body, extending along the surface of the substrate, etc.), and / or by using any other connection method.

[0061] The components of the base work together to form a set of cells, each functioning to define a discrete, programmable volume of selectively retained working metal. In operation, a series of adjacent working metal droplets positioned in adjacent cells can work together to form simulants of PCB traces (trace simulants), wherein the base can simultaneously define multiple trace simulants to work together to form the PCB simulant. The components of the base (e.g., some or all of the base components) are preferably transparent (or substantially transparent) to radio frequency (RF) radiation (e.g., over a wide frequency band), which can serve to minimize the interaction (e.g., interference) between the components and RF signals; however, some or all of the base components may additionally or alternatively possess any other suitable RF characteristics.

[0062] The base can define: a two-dimensional array of cells (e.g., a single-layer cell formed by stacking two substrates), such as a square array, rectangular array, hexagonal array, triangular array, pentagonal array, etc.; a three-dimensional array of cells (e.g., having two or more cell layers formed by stacking three or more substrates), such as a simple cubic or tetragonal array, hexagonal prism array, pentagonal prism array, triangular prism array, etc.; and / or any other suitable cell array. Cells within the base can be heterogeneous or homogeneous (e.g., of the same size, type, dimension, etc.). Cells within a layer are preferably homogeneous (e.g., identical), but can alternatively be heterogeneous. The footprint defined by each cell on the substrate can be square, rectangular, hexagonal, triangular, and / or have any other suitable shape. In several embodiments, the lateral dimension of the cell (e.g., the size of the cell coverage area on the substrate) is preferably in the micrometer range (e.g., less than 10, 10, 20, 35, 50, 70, 100, 125, 150, 200, 300, 500, 10-20, 20-35, 35-50, 50-100, 100-150, 150-200, 200-300, 300-500, 500-1000, 10-35, 20-70, 70-150, and / or greater than 1000 μm, etc.), more preferably small enough to enable high-fidelity replication of typical circuit board traces (e.g., trace thickness greater than 35, 50, 70, 100, 125, 150, 200, 300, and / or 500 μm). μm, etc.; traces have arbitrary orientation within a layer; etc.); however, the lateral dimensions may additionally or alternatively be submicron (e.g., nanometer), millimeter (e.g., 1-10 mm, greater than 10 mm, etc.), and / or have any other suitable dimensions.

[0063] Cells are preferably physically and / or electrically separated from each other (e.g., by means of gaps 105 in the conductive substrate coating, such as ITO, embodiments shown in Figures 1, 2, 3 and 4; physical separation, etc.), but may alternatively be adjacent or connected. The gaps may be between 1 and 3 μm, or have any other size.

[0064] Cells may have a square or rectangular coverage area, but may alternatively have any other suitable shape. The coverage area may be the same for each cell, but may alternatively vary between cells. Cells may have a length and / or width of 150 micrometers (e.g., 150 micrometers x 150 micrometers), 100 micrometers, 50 micrometers, 1 millimeter, 200 micrometers, 500 micrometers, between 100 micrometers and 1 millimeter, and / or any other size.

[0065] A cell may include: a segment of a wide surface of a substrate, a volume adjacent to the substrate surface segment (e.g., above or below the substrate surface segment), optionally a segment of the substrate thickness, a subset of a set of driver elements, and / or other portions of a base member. The volume adjacent to the substrate may be part of a manifold or separate from it. In a first variation, the cell includes a wide surface of a smooth substrate and a volume adjacent to the wide surface. In a second variation, the cell includes a via of an intermediate substrate, a wide surface of the intermediate substrate surrounding the via (e.g., an upper surface, a lower surface, or both), and a volume adjacent to the wide surface of the intermediate substrate (e.g., an upper volume, a lower volume, or both, respectively). In a third variation, the cell includes a blind via of an outer substrate, a wide surface of the substrate surrounding the via, and a volume adjacent to the wide surface. However, cells may be defined in other ways.

[0066] In several variations, the cell preferably contains pixel 104 and may optionally contain via 103; embodiments are shown in Figures 1 and 5.

[0067] Pixels function to provide volume for a portion of a trace (e.g., a portion of a flat trace) that can be formed in a PCB simulation. A pixel (e.g., a voxel) comprises a portion of a broad facet of a substrate and the volume adjacent to the broad facet, but may be defined in other ways. In one embodiment, a pixel may comprise a segment of conductive material disposed along the broad facet of the substrate (e.g., a transparent conductive material, such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), etc., and / or combinations thereof; any suitable conductive material, such as those described above with respect to conductive coating 111; etc.), wherein the segment is discontinuous with conductive material segments used for adjacent pixels and / or vias (e.g., electrically isolated from adjacent pixels, adjacent vias, and / or the conductive material therein). The conductive material is preferably coated with one or more dielectric materials (e.g., hafnium oxide, tantalum oxide, barium strontium titanate, silicon nitride, LiF, NaF, Al2O3, SiO2, Si3N4, MgO, any suitable dielectric material, such as those described above with respect to dielectric coating 112, etc.) (partially or entirely), which can function to electrically isolate the conductive material from the manifold (e.g., prevent short circuits between the conductive material and the working metal), but may additionally or alternatively be coated, exposed, and / or otherwise configured by any other suitable material.

[0068] A cell preferably contains a single pixel (e.g., along the top, along the bottom, etc.), but may alternatively contain two pixels (e.g., top and bottom pixels). Each pixel may contain one or more driver elements (pixel driver element 120a) from the set of driver elements, which function to control the positioning of the working metal (e.g., drawing the working metal into the pixel, holding the working metal within the pixel, repelling the working metal from the pixel, etc.). Each pixel preferably contains a single driver element from the set of driver elements (e.g., positioned along a pixel corner, edge, center, or other area, etc.), but may alternatively contain two driver elements (e.g., positioned along opposite pixel corners, edges, etc.; positioned along adjacent corners or edges, etc.), four driver elements, or any number of driver elements. Driver elements are preferably located at the far end of the memory (e.g., on the side or corner of the pixel furthest from the memory), but may alternatively be located on the side or corner closest to the memory, on an orthogonal side or corner, and / or on any other side or corner.

[0069] Optional cell vias serve to provide volume for forming interlayer connections (e.g., vias) within the PCB simulation. A cell via includes vias defined by an intermediate substrate, but may be defined in other ways. A cell preferably contains a single via, but may alternatively contain multiple vias. Vias may be coated with a conductive material (e.g., transparent conductive materials such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), etc., and / or combinations thereof; metal nitrides such as titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, vanadium nitride, etc., and / or combinations thereof; metals such as titanium, copper, and / or titanium-copper alloys; any suitable conductive material, such as those described above with respect to conductive coating 111; etc.), or uncoated. The via coating is preferably discontinuous with the conductive material segments used for adjacent pixels and / or vias (e.g., electrically isolated from adjacent pixels, adjacent vias, and / or the conductive material therein, as illustrated in FIG. 5 in an exemplary manner), but may additionally or alternatively be electrically connected to the pixel coating and / or any other suitable element. The conductive material is preferably coated with one or more dielectric materials (e.g., hafnium oxide, tantalum oxide, barium strontium titanate, silicon nitride, LiF, NaF, Al2O3, SiO2, Si3N4, MgO, any suitable dielectric material, such as those described above with respect to dielectric coating 112, etc.) (partially or entirely), which can function to electrically isolate the conductive material from the manifold (e.g., prevent short circuits between the conductive material and the working metal); but may additionally or alternatively be coated, exposed, and / or otherwise configured by any other suitable material. Each via may include one or more driver elements (via driver element 120b) from the group of driver elements and / or associated with it (e.g., co-located with it, positioned adjacent to it, such as within the coverage area of ​​the same pixel, etc.; electrically connected to it; etc.), which function to control the positioning of working metal within the via (e.g., drawing working metal into the via). Each via preferably includes a single driver element from the group of driver elements (e.g., positioned along a pixel corner, edge, center, or other region, etc.), but may alternatively include two driver elements (e.g., positioned on opposite sides of the via, etc.), or any number of driver elements. The via driver element may be electrically isolated from the pixel driver element, but may alternatively be electrically connected in any other suitable manner.

[0070] However, cells can be configured in other ways.

[0071] Programmable circuit boards may include repositories that function to provide a source and / or sink for working metal. The repositories are preferably fluidly connected to the set of cells, but may additionally or alternatively be fluidly connected to an etchant source or other source or sink. The repositories may be connected to the set of cells via a set of manifolds (e.g., where working metal droplets are drawn through sequential cells, such as pixel by pixel, etc.), via a set of channels (e.g., through the body of the substrate, along the surface of the substrate, extending between cells, etc.), and / or otherwise connected to the cells; in some embodiments, where many (e.g., most) cells of the DPCB include one or more vias, cells connected to the repositories may optionally omit such vias (e.g., where the cells function to transfer working metal between the manifolds and the repositories), but may alternatively include one or more vias and / or any other suitable features. Programmable circuit boards may include one or more repositories. Different repositories may be connected to the same or different cell layers (e.g., each layer contains its own repositories; multiple layers share a single repositories; etc.), contain the same or different working metals (e.g., have different melting points, different connectivity, etc.), be located on the same or different sides of the system, and / or differ in other ways.

[0072] The reservoir may include one or more fluid control mechanisms positioned between the reservoir body and the set of cells, which control the flow of working metal into the base and may also control the droplet size and / or other parameters of the working metal. Examples of fluid control mechanisms that may be used include: valves (e.g., MEMS valves, solenoid valves, electrochemical actuators, etc.), actuators that apply voltage to control fluid flow, and / or any other suitable mechanism. However, the reservoir may include any other suitable components.

[0073] However, the memory can be configured in other ways.

[0074] The working metal serves to dynamically form conductive features in the PCB simulation. Examples of conductive features that can be formed include traces, vias, interconnect structures, and / or other conductive features. One or more working metals can be used in the DPCB. The working metal can be conductive. The conductivity and / or resistivity of the working metal is preferably similar to copper, but may additionally or alternatively be similar to gold, aluminum, and / or other PCB trace materials. The working metal preferably has a melting point above the test temperature, but may alternatively have a melting point at or below the test temperature. The test temperature is preferably the temperature (or the highest temperature) at which the PCB is tested (e.g., between -40°C and +80°C, between -55°C and +125°C, room temperature, 20°C, 200°C, solder reflow temperature, below a threshold of the solder reflow temperature, such as 0-100°C lower than the solder reflow temperature, etc.), but may be otherwise defined. The working metal preferably has a solidification point (e.g., curing temperature) above the test temperature, such that the working metal is solid during the test, but may alternatively have a solidification point below the test temperature. In several embodiments, the melting point and / or solidification point may be about -39°C (e.g., for mercury), about 30°C (e.g., for gallium), about 157°C (e.g., for indium), about 15°C (e.g., for eutectic gallium-indium mixtures), in the range of about 15-157°C (e.g., for gallium-indium mixtures), in the range of about 150-200°C, in the range of about 200-250°C, in the range of about 250-300°C, and / or any other suitable temperature. The working metal may include mercury, gallium, indium, other late transition metals, or alloys thereof, but may additionally or alternatively include any other suitable metal. Those skilled in the art will understand that liquid metals are not polar liquids, but are characterized by metallic bonding; therefore, the electrowetting (e.g., electrowetting on dielectric, EWOD) properties of the working metal may differ (e.g., significantly) from those observed in polar liquids (e.g., water).

[0075] In operation, the working metal is liquefied (e.g., in a reservoir), and droplets of liquefied working metal are moved through a base to a target cell using a set of actuators, wherein a holding mechanism (e.g., actuators) at the target cell holds the working metal droplet in position. Other working metal droplets can be positioned in their target cells by repeating the process. The positioned working metal droplets can optionally be solidified to form a testable PCB mockup (e.g., a DPCB); alternatively, the DPCB can be tested while the working metal is still liquefied. The working metal can be liquefied by melting (e.g., increasing the base temperature), vibration (e.g., applying focused ultrasound, microwaves, sound waves, etc.), applying electromagnetic heating, and / or otherwise liquefying the working metal. The working metal can be solidified by decreasing the base temperature, removing the applied vibration or electromagnetic field, and / or otherwise solidifying the working metal.

[0076] In several variations, the working metal may be used with one or more auxiliary materials (e.g., auxiliary fluids, such as auxiliary liquids; in some embodiments, counter-fluids) to prevent oxidation of the working metal, maintain or adjust the electromagnetic properties of the working metal, prevent the working metal from reacting with the substrate, control (and / or otherwise influence) the surface tension properties of the working metal droplets (e.g., to achieve a desired contact angle with the substrate, to achieve a contact angle with the substrate within a desired angle range, to increase the contact angle with the substrate to a value greater than a desired minimum angle, to decrease the contact angle with the substrate to a desired maximum angle, to control contact angle hysteresis with the substrate, such as by achieving a value less than a desired maximum hysteresis, etc.), and / or to perform other functions. In some embodiments, the dielectric constant of the auxiliary material may be selected to meet one or more design objectives, such as matching or substantially matching the desired overall dielectric constant of the device, helping to bring the average dielectric constant of the device to or towards a target value, and / or any other suitable design objective; in several specific embodiments, the dielectric constant of the auxiliary material may be approximately 4 (e.g., 4-4.4, 3.8-4.8, etc.), such as to match the dielectric constant of typical PCB materials (such as FR4); may be approximately 11.7 (e.g., 10-14, 11-13, 11.3-12.5, 11.5-12, etc.), such as to match the dielectric constant of silicon; may be less than 4 (e.g., 3-4, 2-3, 1-2, etc.), such as to reduce parasitic losses at high frequencies; may be greater than 4 (e.g., 4.5-5, 5-6, 6-8, 8-11, 11-14, greater than 14, etc.); and / or may have any other suitable value. Auxiliary materials may be polar, non-polar, and / or have any other suitable properties.

[0077] In some embodiments, one or more of the auxiliary materials preferably include (e.g., an etchant, which can act to remove oxide coatings on the working metal), but may additionally or alternatively include (e.g., a lubricant, such as an oil, polymer, etc.), and / or other auxiliary liquids. Examples of auxiliary materials that can be used include: silicon-based materials (e.g., polysiloxanes, siloxanes, etc.), acid-containing silicon-based materials (e.g., acid-containing polysiloxanes and / or siloxanes), and / or any other suitable substance. The auxiliary material is preferably coated onto the working metal (e.g., working metal droplets, etc.), but may alternatively be mixed into the working metal (e.g., as a suspension, etc.) or otherwise interfaced with the working metal. The auxiliary material can be disposed within a reservoir, injected onto the working metal droplets at the reservoir outlet, disposed within a manifold (e.g., a group of fluidly connected cell pixels), stored in a separate compartment within the reservoir and released as needed, continuously present at the reservoir outlet, and / or otherwise stored or released. In a first embodiment, the working metal is immersed (e.g., completely immersed) in an auxiliary fluid (e.g., an auxiliary liquid). In a second embodiment, a small amount (e.g., less than a threshold amount, such as less than 5%, 2%, 1%, 0.5%, 0.2%, 0.1%, 0.05%, and / or 0.02% V / V, wherein the volume fraction of the auxiliary material is expressed relative to the volume of the working metal; an amount between any two of the aforementioned volume fractions; etc.) of auxiliary material (e.g., silicon-based materials, such as polysiloxanes and / or siloxanes, with acidic vapors) is present at or near the working fluid (e.g., in contact with the working fluid) and / or in the vicinity of the working fluid (e.g., in the reservoir). In one specific embodiment, an auxiliary material (e.g., polysiloxane containing acidic vapor) of less than 0.1% V / V is present at and / or near the working fluid (e.g., in a reservoir).

[0078] Additionally or alternatively, one or more of the auxiliary materials may include (e.g., are) surface energy modification and / or control layers (e.g., low surface energy layers). For example, the system may include one or more surface energy modification layers on a substrate (e.g., a dielectric), such as a fluorinated layer (e.g., a self-assembled monolayer presenting a fluorinated surface), which can function to increase the working metal contact angle on the substrate (e.g., above a threshold, such as a minimum desired value; reaching a desired value; reaching a desired range; etc.), to reduce working metal contact angle hysteresis on the substrate by reducing and / or avoiding surface contamination (e.g., below the desired maximum contact angle hysteresis), and / or have any other suitable functionality. For electrowetting (e.g., EWOD) applications, a higher working metal contact angle (e.g., in the absence of an applied electrostatic field) can achieve electrowetting at lower applied field strengths (e.g., corresponding to lower actuation voltages), which may be advantageous in some variations of the system.

[0079] However, the system may additionally or alternatively contain any other suitable auxiliary materials with any suitable ingredients and / or functionality.

[0080] In several variations, the base may be used with one or more conductive layers that serve to electrically connect the cell to an external component (e.g., the embodiments shown in Figures 2 and 6).

[0081] In a first variant, the conductive layer may include a set of anisotropic electrical connections extending through the thickness of the conductive layer, wherein the anisotropic electrical connections may be electrically isolated from each other (e.g., by means of the body portion of the conductive layer material). The anisotropic electrical connections may be: conductive coils (e.g., helices having aligned or non-intersecting axes), wires, a row of conductive particles (e.g., wherein compression of the conductive layer electrically connects the particles), aligned arrays of conductors (e.g., wherein conductive nanostructures (such as carbon nanotubes and / or metal nanowires) are aligned with their long axes substantially perpendicular to the broad face of the layer), and / or formed in other ways. In several embodiments, the conductive layer may exhibit a conductivity anisotropy ratio greater than 100 (e.g., 10³-10⁴, 10⁴-10⁵, 10⁵-10⁶, greater than 10⁶, etc.), an in-plane resistivity greater than 10³ Ω·cm (e.g., 10³-10⁴, 10⁴-10⁵, 10⁵-10⁶, greater than 10⁶ Ω·cm, etc.), and / or a through-plane conductivity greater than 0.01 S / cm (e.g., 0.01-0.1, 0.1-1, 1-10, 10-100, or greater than 100 S / cm, etc.); however, the conductive layer may additionally or alternatively exhibit any suitable conductivity and / or its anisotropy ratio.

[0082] In a second variant, the conductive layer may comprise a set of patterned electrical connections, preferably extending perpendicularly or substantially perpendicular to a wide surface outside the outer substrate and / or extending through the thickness of the conductive layer, wherein the patterned electrical connections are preferably electrically isolated from each other (e.g., by means of discontinuities in the conductive layer defined between each such connection). For example, the set of patterned electrical connections may define an island array (e.g., a regular planar array) of conductive material (e.g., on a wide surface outside the outer substrate, such as deposited on a wide surface outside the outer substrate). The patterned electrical connections are preferably electrically connected to blind via caps of the substrate (e.g., where one of such electrical connections is deposited on the conductive cap of each blind via), but may additionally or alternatively have any other suitable connectivity. In several embodiments, the conductive layer may comprise: conductive paste and / or ink (e.g., metal paste and / or ink, such as silver paste or ink, aluminum paste or ink, copper paste or ink, etc.; carbon-based conductive ink, such as graphite, CNT and / or graphene-based ink; conductive nanoparticle ink; conductive polymer, such as PEDOT:PSS; etc.), deposited such as by screen printing, inkjet printing and / or the like; deposited metal (e.g., gold, aluminum, copper, silver, platinum, nickel, tin, titanium, etc.), deposited such as by physical vapor deposition (e.g., sputtering, thermal evaporation, electron beam evaporation, etc.), electroplating, electrochemical deposition, lithography (e.g., photolithography) patterning, and / or the like; anisotropic conductive material (e.g., as described above with respect to the first variant); and / or any other suitable conductive material.

[0083] However, the conductive layer may additionally or alternatively define any other suitable electrical connections, and / or be configured in other ways.

[0084] The conductive layer can be flexible, rigid, compressible, incompressible, and / or have any other suitable physical properties. For example, the conductive layer can be a gel, adhesive, and / or any other suitable material. The conductive layer can be permanently or removably attached to the substrate (e.g., attached to a wide surface outside the substrate).

[0085] However, the conductive layer can be configured in other ways.

[0086] Electronic components (e.g., discrete electronic components) may serve to model the rest of the PCB, but may alternatively serve to perform any other suitable task. The electronic components are preferably of the same type (e.g., brand, model, parameters, etc.) as the components used to manufacture the PCB (e.g., surface mount technology (SMT), through-hole technology (TMT), etc.), but may alternatively be different. Examples of electronic components that may be used include: chipsets, memory, interfaces (e.g., connectors), fuses, oscillators, resistors, capacitors, diodes, inductors, transistors, integrated circuits, and / or other components. Examples of interfaces that may be used include: communication interfaces (e.g., USB, Ethernet, CAN, serial interfaces (such as SPI or I2C), parallel interfaces, high-speed digital interfaces (such as MIPI DSI), etc.), memory interfaces (e.g., SDIO), display interfaces (e.g., eDP, LVDS, etc.), and / or any other suitable interface.

[0087] Electronic components can be picked up and placed on a programmable circuit board (PCB), glued to a DPCB, soldered to a DPCB (e.g., to a conductive layer), press-fitted (e.g., on an interposer 203 connected to a conductive layer; to an exposed via; etc.), and / or otherwise permanently or temporarily attached to the PCB. Electronic components can be attached to a conductive layer (e.g., where the conductive layer can be removed from the substrate) and / or attached to the substrate (e.g., via blind vias), or otherwise attached.

[0088] Electronic components may include surface mount components 202a, through-hole components 202b (e.g., attached using an interposer 203 connected to a conductive layer), and / or any other suitable component type. Through-hole connections can be modeled by adjacent stacks of working metal droplets disposed within voxels and vias (e.g., stacks of filled cells), aligned with the conductive layer connection regions of the interposer that electrically connect the through-hole components to intermediate traces (e.g., the embodiment shown in FIG. 2), but can be modeled in other ways. In this embodiment, filled cells can be separated from other cells by a threshold number of unfilled cells, such that the working metal within the filled cells is electrically isolated from the rest of the circuitry.

[0089] The programmable circuit board can be used with a set of controllers that function to: control the placement of working metal within the base, inject signals into the resulting PCB emulator, read signals from the PCB emulator, and / or perform other functionalities. In some variations, the set of controllers may include: a driver controller, a circuit board controller, and / or other controllers.

[0090] A driver controller functions to control the setup of a programmable circuit board (e.g., controlling the placement of working metal by controlling driver elements). The driver controller can be a display controller (e.g., an OLED display controller, AMOLED display controller, LED display controller, LCD driver, etc.), an ASIC, a microprocessor, and / or any other controller. The driver controller can be different from or integrated into other controllers. The driver controller can be electrically connected to and control the driver elements. For example, the driver controller can apply a voltage to the driver element of a cell, which can attract a working metal droplet to the cell. In another embodiment, the driver controller can remove or reverse the voltage applied to the driver element of the cell, which can remove the attractive force on the working metal droplet, remove the electromagnetic field on the working metal droplet, repel the working metal droplet, and / or otherwise manipulate the working metal droplet.

[0091] In several variations, the driver controller may optionally receive raw and / or low-order signals (e.g., current, resistance, voltage, etc.) from the cell and process the signals for higher-order interpretation.

[0092] A circuit board controller functions to control a programmable circuit board after a PCB emulator has been configured. This enables the PCB emulator to: be used as a circuit board (e.g., for computation); be tested (e.g., in place of a manufactured PCB prototype); and / or be used in other ways. The circuit board controller can provide signals to the PCB emulator, read signals from the PCB emulator, and / or perform any other suitable function. In a first variation, the circuit board controller can be directly connected to an interface (e.g., a communication interface) mounted to the PCB emulator. In a second variation, the circuit board controller can be connected to a driver controller and used to send inputs and / or receive outputs from the PCB emulator. However, the circuit board controller can be used in other ways.

[0093] A circuit board controller can be programmed or configured to execute test sequences, analyze results, adjust parameters based on feedback, and / or perform any other suitable tasks. For example, a circuit board controller can generate and control various electrical parameters of a PCB simulator (e.g., voltage level, frequency, timing, etc.). However, a circuit board controller can operate in any other manner.

[0094] However, a programmable circuit board can contain any other suitable group of components.

[0095] In several variations, the programmable circuit board can be used with a set of test equipment and / or test procedures to test the programmable circuit board layout, wherein the programmable circuit board can be dynamically reconfigured based on the test results. Examples of tests that can be used include: circuit testing, flying probe testing, functional testing, and / or other PCB layout testing. These tests can measure signal output at components mounted to conductive layers, at conductive layers, at the outer surface of the outer substrate (e.g., at the cover of blind vias), at cells (e.g., outer cells, inner cells, etc.), and / or at any other suitable point in the programmable circuit board. Test equipment that can be used includes: oscilloscopes, voltmeters, ohmmeters, ammeters, multimeters, LCR meters, power supplies, signal generators, digital pattern generators, pulse generators, frequency counters, test probes, logic analyzers, spectrum analyzers, protocol analyzers, vector signal analyzers, and / or any other suitable instrument, device, or component that functions to measure, analyze, or generate electrical signals.

[0096] 4. Methods.

[0097] In some variations, the method for dynamically programming a circuit board includes: receiving a circuit board design; pixelating traces in the circuit board design to identify target cell locations; positioning working metal droplets within each target cell location; assembling the remainder of the circuit board components; optionally testing the assembled PCB emulator; and / or optionally updating (e.g., dynamically updating) the physical PCB emulator configuration by repeating any or all of the previous steps.

[0098] The circuit board design is preferably received from a remote user, but can alternatively be generated programmatically and / or using one or more statistical models (e.g., using statistical models, such as neural network-like models trained on other PCB designs and associated characteristics and / or functionality; using physical models, such as circuit models, high-frequency electromagnetic models, thermal models, multi-physics models, etc.; using any other suitable model; etc.) to determine and / or notify the determination of the design, such as automatically generated and / or in response to user requests, and / or determined in other ways. In some variations, the circuit board design is stored only in volatile memory (e.g., RAM), which prevents design theft because the design will be lost when power to the programmable board is removed; in some such variations, traces defined by working metals are preferably also lost in response to the loss of system power, such as where the working metal has a melting temperature below ambient, and the system power is used to hold the working metal in place, such as by actively cooling the working metal to below ambient temperature, by electrowetting the working metal within the target cell, and / or in any other suitable manner. However, the circuit board design can be stored in persistent memory.

[0099] By rasterizing the circuit board design using a grid with a size equal to (or substantially equivalent to) the cell size, traces can be pixelated. Grid cells that overlap with traces in the circuit board design can be considered target cells. The location of vias in the circuit board design can also be identified. The location of discrete electronic components (e.g., SMT components, THT components, etc.) can also be identified, including additional target cells that connect the outer surface of the DPCB to the via connection endpoints.

[0100] Positioning the working metal droplet may include: optionally heating the DPCB and / or any suitable subset thereof, such as its working metal (e.g., to melt the working metal); generating the working metal droplet from the main working metal (e.g., using a valve, an electromagnetic field, etc.); moving the working metal droplet to a target cell (e.g., as shown in Figure 6); optionally holding the working metal droplet in the target cell (e.g., while positioning other working metal droplets); optionally testing the presence of working metal in the cell; and / or optionally cooling the DPCB and / or any suitable subset thereof, such as its working metal (e.g., to solidify the working metal), wherein cooling may include active cooling, passive cooling (e.g., allowing the working metal to cool to or towards ambient temperature), and / or cooling in any other suitable manner. The working metal droplet may be positioned in multiple columns of cells (e.g., in parallel); column-by-column in cells (e.g., in series); and / or otherwise. The working metal droplet is preferably positioned first in the cell row furthest from the reservoir, but may alternatively be positioned in any other order. The working metal droplets can be positioned relative to each other simultaneously, sequentially, and / or at any other suitable time. In some embodiments, the working metal may already be positioned in certain cells (e.g., corresponding to a previous circuit board design) before positioning. In some such embodiments, the working metal droplets can move directly from their previous positions to the target position, while in other such embodiments, all (or substantially all) of the working metal is returned to a reservoir (e.g., via a process similar to that used to guide the working metal droplets to the target cell) before the working metal droplets are positioned in the target cell.

[0101] In a first variation, the working metal droplet can be positioned by sequentially attracting it to adjacent cells until it reaches the target cell. For example, the driving element (e.g., transistor) in the next cell in the droplet path (e.g., between the reservoir and the target cell) can be selectively controlled (e.g., turned on) to attract the working metal droplet to the next cell, and / or the driving element in the cell currently occupied by the droplet can be selectively controlled (e.g., turned off) to stop attracting the working metal droplet and / or to repel it. In another embodiment, the driving element associated with a cell via can be turned on to draw the droplet into the via (e.g., to simulate a via within a circuit board design); and / or the driving element in the cell currently occupied by the droplet can be selectively controlled (e.g., turned off) to stop attracting the working metal droplet and / or to repel it. In a second variation, the working metal droplet can be positioned by applying an electromagnetic field to the droplet (e.g., using a permanent magnet, induction coil, etc.) and moving the electromagnetic field above the base to move the droplet to the target cell. In a third variation, the working metal droplet can be drawn to the target cell. For example, all target cells can be opened (e.g., the pixels and / or via transistors of each target cell can be opened); the working metal can flow through the base, and the working metal droplets attracted to the opened cells can collaboratively form traces. However, the working metal droplets can be moved to the target cells in other ways. The working metal droplets can be held in the target cells by: a driver element of the target cell (e.g., by applying voltage using a transistor); a holding mechanism of the target cell (e.g., the wall of the cell); cooling the DPCB; and / or holding in other ways.

[0102] The presence of working metal in a test cell can serve to determine whether the working metal has been correctly positioned, such as by confirming that the target cell contains working metal and / or confirming that other cells do not. In one embodiment, the test cell may include a capacitance measurement cell (e.g., independently measuring the capacitance of each cell or any suitable subset thereof, such as each target cell and / or each non-target cell adjacent to the target cell). Cells containing working metal droplets will typically have significantly larger capacitances (e.g., several orders of magnitude larger) than cells that do not contain (or contain minimal amounts of) working metal. Therefore, the measured capacitance values ​​can be used to determine the actual fill state of each cell with the measured capacitance, and these actual fill states can be compared with the expected fill state. If a mismatch between the actual and expected fill states is detected, the method preferably includes controlling a driver element to correct the detected mismatch (e.g., filling each currently unfilled target cell and / or clearing each currently filled non-target cell). This test is preferably performed when the working metal is liquid, but may additionally or alternatively be performed when the working metal is solid (e.g., where correcting any detected mismatch preferably involves melting the working metal before moving it) and / or at any other suitable time.

[0103] The remaining components of the circuit board can be assembled by attaching a conductive layer to the outside of the DPCB and mounting components to the conductive layer at locations corresponding to the circuit board design (e.g., using SMT, conductive adhesive, etc.).

[0104] The obtained PCB emulator (design under test; DUT) can be tested using conventional test equipment and methods. However, modified equipment and / or methods can be used. In several variations, signals from the PCB emulator can be corrected using corrections that take into account substrate misalignment (e.g., determined during initial substrate alignment).

[0105] In some embodiments, such as where the base includes one or more cells for routing connections of test equipment (e.g., power supplies, oscilloscopes, etc.) to target nodes of the DUT (e.g., layers containing one or more such cells), testing may involve reconfiguring the base to route (or reroute) some or all of these connections (e.g., similar to a test engineer repositioning test probes from one target node of the DUT to another), such as by controlling the base to reposition working metal to appropriate cells to achieve desired test equipment connectivity (e.g., holding working metal corresponding to a PCB dummy component in the desired position, such as by electrostatic control, by melting only the working metal within the layer to be reconfigured while keeping the layer corresponding to the DUT frozen, etc.). However, such cells may additionally or alternatively be controlled in any other suitable manner.

[0106] In several variations, test results (e.g., signals, summaries, etc.) may be sent to a remote user. Results may be sent immediately (or nearly immediately) or asynchronously. In several variations, the user device may include an application that: presents the capability of a PCB emulator; makes the PCB emulator's ports locally available on the user's device; simulates a local connection to the PCB emulator; simulates local PCB emulator test results on the user's device; and / or performs other functionalities. In one embodiment, local PCB emulator test results may be approximated or simulated by: forwarding data read from the PCB emulator's connectors (e.g., USB ports, Ethernet ports, etc.); allowing the user device to connect via SSH to a board controller connected to the PCB emulator; and / or otherwise providing test results to a remote user.

[0107] This method (and / or any suitable elements thereof) can be reused for new circuit board designs. In several variations, the new circuit board design can be generated by a user (e.g., based on test results) and / or other users, can be generated programmatically and / or by one or more statistical models (e.g., generating modifications to a previous design based on test results; generating a design based on one or more design criteria; etc.), and / or can be generated in any suitable manner and / or by any suitable entity. For example, a new set of target cells can be determined from the new circuit board design; the DPCB can be heated above the melting temperature of the working metal; working metal droplets can be moved back to the reservoir and / or to their new location (e.g., by controlling driver elements to achieve such movement); and the DPCB can be cooled to set up a new PCB emulator.

[0108] The method, in whole or in part, may be executed immediately (e.g., in response to a request), iteratively, simultaneously, asynchronously, periodically, and / or at any other suitable time. The method, in whole or in part, may be executed automatically, manually, semi-automatically, and / or otherwise.

[0109] 5. Specific implementation methods.

[0110] The following is a list of numbered embodiments of the technology described herein. Those skilled in the art will recognize that the scope of the technology is not limited to these specific embodiments and / or is not limited thereto.

[0111] 1. A programmable circuit board system, comprising: A substrate, which defines a first surface; An electrically controlled grid array is defined at the substrate; A dielectric material, the dielectric material being coated on at least some of the first surface; and One working metal; in: The system defines a pixel array, wherein each pixel in the pixel array comprises: One of the substrate portions of the substrate includes one of the corresponding surface portions of the first surface; One of the corresponding electrical control grids in the electrical control grid array, the corresponding electrical control grid being defined at the corresponding portion of the substrate; and One of the dielectric materials has a corresponding dielectric portion, which is coated on the corresponding surface portion; and The system can be operated as follows: Receive a positioning map indicating the selection of a plurality of conductor pixels from the pixel array; and The working metal is configured based on the positioning map, including controlling the electrical control grid array such that for each of the plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

[0112] 2. The system of specific embodiment 1, wherein the system is further operable to configure the working metal based on the positioning map, such that each of the plurality of conductor pixels contains a corresponding working metal portion contacting the corresponding dielectric portion, while for each of the plurality of conductor pixels: The conductive pixel is adjacent to each pixel in one group of corresponding adjacent conductive pixels in the plurality of conductive pixels, and is also adjacent to each pixel in one group of corresponding adjacent non-conductive pixels in the pixel array, wherein the intersection of the set of corresponding adjacent non-conductive pixels and the set of the plurality of conductive pixels is empty; For each adjacent conductor pixel in the group of corresponding adjacent conductor pixels, the corresponding working metal portion of the conductor pixel is in electrical contact with the corresponding working metal portion of the adjacent conductor pixel; and For each adjacent non-conducting pixel in the corresponding group of adjacent non-conducting pixels, the corresponding working metal portion of the conductor pixel does not make electrical contact with the adjacent non-conducting pixel.

[0113] 3. The system as described in specific embodiment 1 or 2, wherein the system is further operable to: Receive a second positioning map indicating the selection of a second plurality of conductor pixels from the pixel array, the second plurality of conductor pixels being different from the plurality of conductor pixels; and After configuring the working metal based on the positioning map, configuring the working metal based on the second positioning map includes controlling the electrical control grid array such that for each of the second plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

[0114] 4. The system as described in any of the foregoing specific embodiments, wherein: The substrate defines a second side that spans across the first side of the substrate; The substrate includes an electrical insulator; The system further includes a plurality of discrete electronic components; and Each of the plurality of discrete electronic components is electrically and mechanically connected to the second side.

[0115] 5. The system as described in Specific Embodiment 4, wherein: Each of the plurality of discrete electronic components is mechanically connected to the second side by solder; and The melting temperature of one of the working metals is lower than the melting temperature of one of the solders.

[0116] 6. The system of embodiment 4 or 5, wherein one of the working metals has a melting temperature higher than an ambient temperature surrounding the system.

[0117] 7. The system of any one of embodiments 4 to 6, further comprising an anisotropic conductive layer coated on the second surface, wherein: Each of the plurality of discrete electronic components is electrically connected to the anisotropic conductive layer; The anisotropic conductive layer exhibits a cross-surface conductivity perpendicular to the second surface; The anisotropic conductive layer exhibits in-plane conductivity parallel to the second surface; The conductivity across the surface is at least ten times greater than the conductivity within the surface. The substrate defines a plurality of blind vias passing through the first surface, wherein each of the plurality of blind vias is: Set within one of the different pixels in this array; A corresponding inlet hole is defined at the first surface, a corresponding terminal surface is defined within the substrate, and a corresponding sidewall extends between the inlet hole and the terminal surface; and This includes a corresponding conductive cap defining the surface of the corresponding terminal, the corresponding conductive cap electrically connecting the surface of the corresponding terminal to the anisotropic conductive layer; The plurality of blind holes includes a first blind hole, the first blind hole including a first conductive cap; The plurality of discrete electronic components includes a first component disposed across the anisotropic conductive layer from the first conductive cap, wherein a reference axis perpendicular to the second surface intersects the first conductive cap and one of the electrical conductors of the first component; and Based on the positioning diagram, the working metal is configured to further include controlling the electrical control grid array such that a first via portion of one of the working metals contacts the first conductive cap, thereby electrically connecting the first component to the first via portion of the working metal.

[0118] 8. The system as described in any of the foregoing specific embodiments, wherein: The electrically controlled lattice array includes a non-insulating material deposited on the first surface; and The dielectric is coated on the non-insulating material.

[0119] 9. The system of Specific Embodiment 8, wherein the working metal is electrically isolated from the non-insulating material by the dielectric, wherein the working metal, the non-insulating material and the dielectric collectively define a capacitor.

[0120] 10a. The system of any of the foregoing specific embodiments, wherein the electrical control grid array is a regular array.

[0121] 10b. The system of any of the foregoing specific embodiments, wherein the electrical control grid array is an irregular array.

[0122] 11. The system as described in any of the foregoing specific embodiments, wherein: The substrate defines an array of vias on the first surface; The system further includes a via electrical control grid array, wherein each via electrical control grid in the via electrical control grid array is disposed near the proximal end of a corresponding via in the via array; The dielectric is coated on at least some of each via in the array; The location map further indicates the plurality of conductor vias selected from the via array; and The working metal configuration based on the positioning map further includes controlling the electrical control grid array and the via electrical control grid array, such that for each of the plurality of conductor vias: a corresponding working metal portion of the working metal moves to the conductor via due to electrowetting force, such that the corresponding working metal portion substantially fills the conductor via.

[0123] 12a. The system of specific embodiment 11, further comprising: A second substrate is disposed substantially parallel to the first substrate, wherein the second surface is disposed between the second substrate and the first surface; A second electrically controlled grid array, defined at the second substrate; and A second dielectric material is coated on at least some of the second surface; in: The system further defines a second pixel array, wherein each pixel in the second pixel array includes: The corresponding substrate portion of one of the second substrates; One of the corresponding electrical control grids in the second electrical control grid array, the corresponding electrical control grid being defined at the corresponding portion of the second substrate; and One of the second dielectric materials has a corresponding dielectric portion, which is coated on the corresponding surface portion; The dielectric is fluidly coupled to the second dielectric via the via array; The positioning map further indicates a second plurality of conductor pixels selected from the second pixel array; and The configuration of the working metal based on the positioning map further includes controlling the second electrical control grid array such that for each of the second plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

[0124] 12b. The system of specific embodiment 12a, further comprising: A third substrate is disposed substantially parallel to the second substrate, wherein the second substrate is disposed between the third substrate and the first substrate; A third electrically controlled grid array, defined at the third substrate; and A third dielectric, the third dielectric being coated on at least some of the third surfaces; in: The substrate further defines a second via array through the second substrate; The system further includes a second via electrical control grid array, wherein each via electrical control grid in the second via electrical control grid array is disposed near the proximal end of a corresponding via in the second via array; The second dielectric is coated on at least some of each via in the second array; The system further defines a third pixel array, wherein each pixel in the third pixel array includes: The corresponding substrate portion of one of the third substrates; One of the corresponding electrical control grids in the third electrical control grid array, the corresponding electrical control grid being defined at the corresponding portion of the third substrate; and The corresponding dielectric portion of one of the third dielectrics is coated on the corresponding surface portion; The third dielectric is fluidly coupled to the second dielectric via the second via array; The positioning map further indicates a second plurality of conductor vias selected from the second via array and a third plurality of conductor pixels selected from the third pixel array; and Based on the positioning map, the working metal is configured to further include controlling the second electrically controlled grid array, the second via electrically controlled grid array, and the third electrically controlled grid array, such that: For each of the second plurality of conductor vias: a corresponding portion of the working metal moves to the conductor via due to electrowetting force, such that the corresponding portion of the working metal substantially fills the conductor via; and For each of the third plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

[0125] 13a. A system as described in any of specific embodiments 11, 12a, or 12b, wherein: The substrate comprises glass having a dielectric constant greater than 5; and An effective metamaterial dielectric constant defined by the substrate and the via array is between approximately 4 and approximately 4.4.

[0126] 13b. The system of any of the foregoing specific embodiments, wherein the substrate has a dielectric constant greater than 5.5.

[0127] 13c. The system of any of the foregoing specific embodiments, wherein the substrate has a dielectric constant of approximately 6.

[0128] 14. The system of any of the foregoing specific embodiments, wherein the system further defines a reservoir interior fluidly coupled to the first surface, the reservoir interior containing at least a portion of the working metal, wherein the system is operable to control the electrically controlled grid array such that a portion of the working metal moves between the reservoir interior and the pixel array.

[0129] 15. The system of specific embodiment 14, wherein the interior of the reservoir is fluidly isolated from an surrounding environment surrounding the system.

[0130] 16a. The system of specific embodiment 14 or 15, wherein the storage further contains an auxiliary material.

[0131] 16b. The system of specific embodiment 16a, wherein the auxiliary material comprises an acidic opposing fluid.

[0132] 16c. The system of specific embodiments 16a or 16b, wherein the auxiliary material comprises a silicon-based material.

[0133] 16d. The system of specific embodiment 16c, wherein the silicon-based material includes at least one of the following: polysiloxane or siloxane.

[0134] 16e. The system of any one of the specific embodiments 16a to 16d, wherein the auxiliary material comprises an acid.

[0135] 17a. A system as described in any of the foregoing specific embodiments, wherein the dielectric comprises a metal oxide comprising at least one of the following: hafnium, tantalum, barium, or strontium.

[0136] 17b. The system of specific embodiment 17a, wherein the metal oxide comprises hafnium oxide.

[0137] 17c. The system of specific embodiment 17a or 17b, wherein the metal oxide comprises tantalum oxide.

[0138] 17c. The system of any one of the specific embodiments 17a to 17c, wherein the metal oxide comprises barium strontium titanate.

[0139] 18a. The system of any of the foregoing specific embodiments, wherein the working metal comprises gallium.

[0140] 18b. The system of any of the foregoing specific embodiments, wherein the working metal comprises indium.

[0141] 18c. The system of specific embodiment 18b, wherein the working metal is primarily composed of indium.

[0142] 19. The system of any of the foregoing specific embodiments further includes a fluorinated layer coated on the dielectric.

[0143] 20. The system of any of the foregoing specific embodiments, wherein configuring the working metal based on the positioning map further includes melting at least some of the working metal.

[0144] 21a. A system as described in any of the foregoing specific embodiments, wherein each electrical control grid includes a corresponding transistor.

[0145] 21b. The system of specific embodiment 21a, wherein for each electrical control cell, the corresponding transistor is a thin-film transistor (TFT).

[0146] 22. The system of specific embodiment 21b, wherein for each pixel in the pixel array, the corresponding TFT is deposited on the corresponding surface portion.

[0147] 23. The system of any of the foregoing specific embodiments, wherein each electrical control cell includes a corresponding conductive pad.

[0148] 24. The system of specific embodiment 23, wherein the corresponding conductive pad of each electrical control cell includes a transparent conductive film.

[0149] 25. A method comprising: configuring the working metal based on the positioning map at a system as described in any of the foregoing specific embodiments, including controlling the electrically controlled grid array.

[0150] 26. The method of specific embodiment 25, wherein configuring the working metal based on the positioning map further includes melting at least a portion of the working metal.

[0151] 27. The method of specific embodiment 25 or 26, further comprising: after configuring the working metal based on the positioning map, allowing the working metal to cure while the working metal is configured based on the positioning map.

[0152] 28. The method of any one of embodiments 25 to 27, further comprising: soldering a plurality of discrete electronic components to the system before configuring the working metal based on the positioning map.

[0153] 29. A method comprising: Determine a trace location map indicating a plurality of target pixels in a pixel array; and Based on the routing location map, a working metal is configured, including, for each of the plurality of target pixels: via electrowetting, controlling a corresponding portion of the working metal to occupy the target pixel.

[0154] 30. The method of specific embodiment 29, wherein, for each of the plurality of target pixels, controlling the corresponding portion of the working metal to occupy the target pixel includes controlling the corresponding portion to move to the target pixel via the pixel array by sequentially applying electrowetting forces.

[0155] 31. The method of specific embodiment 29 or 30, further comprising: for each of the plurality of target pixels, melting the corresponding portion of the working metal before controlling the corresponding portion of the working metal to occupy the target pixel.

[0156] 32. The method of any one of embodiments 29 to 31, further comprising: for each of the plurality of target pixels, after controlling the corresponding portion of the working metal to occupy the target pixel, solidifying the corresponding portion of the working metal.

[0157] 33. The method of any one of embodiments 29 to 32, further comprising electrically connecting a plurality of discrete electronic components to the working metal.

[0158] 34. The method of any one of embodiments 29 to 33, further comprising receiving a circuit board specification indicating a plurality of traces, wherein determining the trace positioning pattern is performed based on the circuit board specification.

[0159] 35. The method of any one of specific embodiments 29 to 34, further comprising: Determine a second trace location map indicating a second plurality of target pixels in the pixel array; and The working metal is configured based on the routing location map. For each of the second plurality of target pixels, configuring the working metal based on the second routing location map includes controlling a corresponding portion of the working metal to occupy the target pixel via electrowetting.

[0160] 35. The method of any one of specific embodiments 29 to 34, further comprising: Connect a computer communication device to the working metal; The working metal receives electrical signals; and The computer provides information indicating the signal.

[0161] 36. The method of any of Specific Embodiments 29 to 35, which is performed using a system of any of Specific Embodiments 1 to 24.

[0162] All references cited in this article are incorporated herein in their entirety, unless the incorporated material is inconsistent with the explicit disclosure herein, in which case the disclosure herein shall prevail.

[0163] As used herein, "substantially" or other similar terms may be interpreted within a predetermined error threshold or tolerance of an indicator, component, or other reference, and / or otherwise.

[0164] Optional elements that may be included in some variations but not in others are indicated by dashed lines in the drawings. However, non-dashed lines in the drawings should not be interpreted as indicating that the depicted elements are indispensable or cannot be omitted from variations of the invention.

[0165] The different subsystems and / or modules discussed above can be operated and controlled by the same or different entities. In a variant of the latter, different subsystems can communicate via APIs (e.g., using API requests and responses, API keys, etc.), requests, and / or other communication channels. Communication between systems can be encrypted (e.g., using symmetric or asymmetric keys), signed, and / or otherwise authenticated or authorized.

[0166] Alternative implementations carry out the above methods and / or processing modules in a non-transitory computer-readable medium storing computer-readable instructions that, when executed by a processing system, cause the processing system to perform the methods discussed herein. The instructions may be executed by a computer-executable component integrated with the computer-readable medium and / or processing system. The computer-readable medium may comprise any suitable computer-readable medium, such as RAM, ROM, flash memory, EEPROM, optical devices (CD or DVD), hard disk drives, floppy disk drives, non-transitory computer-readable media, or any suitable device. The computer-executable component may comprise a computing system and / or processing system (e.g., comprising one or more collocated or distributed, remote or local processors) connected to the non-transitory computer-readable medium, such as a CPU, GPU, TPUS, microprocessor, or ASIC, but the instructions may alternatively or additionally be executed by any suitable dedicated hardware device.

[0167] The implementation of the system and / or method may include every combination and arrangement of various system components and various method flows, wherein one or more examples of the methods and / or flows described herein may be performed asynchronously (e.g., sequentially), concurrently (e.g., simultaneously, in parallel, etc.), or in any other suitable order by and / or using one or more examples of the systems, components, and / or entities described herein. The components and / or flows of the following systems and / or methods may be used, additionally used, alternatively used, or otherwise integrated with all or part of the systems and / or methods disclosed in the foregoing applications, each of which is incorporated herein by reference in its entirety.

[0168] The diagrams depict the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to preferred embodiments, configurations, and variations thereof. In this regard, each block in a flowchart or block diagram may represent a module, segment, step, or code portion containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may not appear in the order indicated in the diagrams. For example, depending on the functionality involved, two blocks shown sequentially may actually be executed substantially simultaneously, or such blocks may sometimes be executed in reverse order. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented by a special-purpose hardware system that performs the specified function or action, or by a combination of special-purpose hardware and computer instructions.

[0169] As will be apparent to those skilled in the art from the preceding detailed description and from the drawings and claims, modifications and alterations may be made to the preferred embodiments of the invention without departing from the scope of the invention as defined in the following claims.

[0170] 10: Programmable circuit board 90: Methods for Dynamic Programming of Circuit Boards 100: Base 101: Cell 102: Manifold 103: Via 103a: Through hole 103b: Blind hole 103b' : Capping 103b'' : Conductive cap 104 pixels 105: Gap 110: Substrate stacking 111: Conductive coating 112: Dielectric coating 120: Driver element 120a: Pixel driver element 120b: Through-hole driver element 130: Storage 140: Working metal 140' : Working metal droplet 201: Conductive layer 202: Electronic Components 202a: Surface Mount Components 202b: Through-hole insert component 203: Intermediary Layer 204: Drive circuit 210: Controller 300: Printed Circuit Board Simulation 301: Trace Simulation Component 302: Through-hole simulation part S910: Receiver Circuit Board Design S920: Determine the cell location chart S930: Positioning working metal S940: Remaining parts of the assembled circuit board components S950: Test assembled PCB emulator

Claims

1. A programmable circuit board system, comprising: A substrate that defines a first surface; An electrically controlled grid array is defined at the substrate; A dielectric material is coated on at least some of the first surface; The system also includes a working metal; wherein: the system defines a pixel array, wherein each pixel in the pixel array includes: a corresponding substrate portion of the substrate, which includes a corresponding surface portion of the first surface; a corresponding electrical control grid of the electrical control grid array, the corresponding electrical control grid being defined at the corresponding substrate portion; and a corresponding dielectric portion of the dielectric, the corresponding dielectric portion being coated on the corresponding surface portion; and the system is operable to: receive a positioning map indicating a plurality of conductor pixels selected from the pixel array; and configure the working metal based on the positioning map, including controlling the electrical control grid array such that for each conductor pixel in the plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to an electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

2. The system of claim 1, wherein the system is further operable to configure the working metal based on the positioning map such that each of the plurality of conductor pixels contains a corresponding working metal portion that contacts the corresponding dielectric portion, while for each of the plurality of conductor pixels: the conductor pixel is adjacent to each of a set of corresponding adjacent conductor pixels in the plurality of conductor pixels, and is adjacent to each of a set of corresponding adjacent non-conductor pixels in the pixel array, wherein the intersection of the set of corresponding adjacent non-conductor pixels and the set of the plurality of conductor pixels is empty; for each of the set of corresponding adjacent conductor pixels, the corresponding working metal portion of the conductor pixel is electrically in contact with the corresponding working metal portion of the adjacent conductor pixel; and for each of the set of corresponding adjacent non-conductor pixels, the corresponding working metal portion of the conductor pixel is not electrically in contact with the adjacent non-conductor pixel.

3. The system of claim 1, wherein the system is further operable to: receive a second positioning map indicating a second plurality of conductor pixels selected from the pixel array, the second plurality of conductor pixels being different from the plurality of conductor pixels; and after configuring the working metal based on the positioning map, configuring the working metal based on the second positioning map, including controlling the electrical control grid array such that for each of the second plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to an electrowetting force, such that the corresponding working metal portion contacts the corresponding dielectric portion.

4. As in the system of request item 1, where: The substrate defines a second surface across the substrate opposite to the first surface; the substrate includes an electrical insulator; the system further includes a plurality of discrete electronic components; and each of the plurality of discrete electronic components is electrically and mechanically connected to the second surface.

5. The system of claim 4, wherein one of the working metals has a melting temperature below 200 °C.

6. The system of claim 5, wherein the melting temperature of the working metal is higher than the ambient temperature of one of the environments surrounding the system.

7. The system of claim 4, further comprising an anisotropic conductive layer coated on the second surface, wherein: Each of the plurality of discrete electronic components is electrically connected to the anisotropic conductive layer; the anisotropic conductive layer exhibits an through-plane conductivity perpendicular to the second surface; the anisotropic conductive layer exhibits an in-plane conductivity parallel to the second surface; the through-plane conductivity is at least ten times greater than the in-plane conductivity; the substrate defines a plurality of blind vias through the first surface, wherein each of the plurality of blind vias: is disposed within a different pixel of one of the pixel arrays; defines a corresponding inlet hole at the first surface, a corresponding terminal surface within the substrate, and a corresponding sidewall extending between the corresponding inlet hole and the corresponding terminal surface; and includes a corresponding conductive cap defining the corresponding terminal surface, the corresponding conductive cap electrically connecting the corresponding terminal surface to the anisotropic conductive layer; the plurality of blind vias includes a first blind via, the first blind via including a first conductive cap; The plurality of discrete electronic components includes a first component disposed across the anisotropic conductive layer from the first conductive cap, wherein a reference axis perpendicular to the second surface intersects the first conductive cap and one of the electrical conductors of the first component; and the working metal configured based on the positioning diagram further includes controlling the electrical control grid array such that a first via portion of one of the working metals contacts the first conductive cap, thereby electrically connecting the first component to the first via portion of the working metal.

8. As in the system of request item 1, where: The electrically controlled grid array includes a non-insulating material deposited on the first surface; and the dielectric is coated on the non-insulating material.

9. The system of claim 8, wherein the working metal is electrically isolated from the non-insulating material by the dielectric, wherein the working metal, the non-insulating material and the dielectric cooperatively define a capacitor.

10. The system of request item 1, wherein the electrical control grid array is a regular array.

11. As in the system of request item 1, where: The substrate defines an array of vias on the first surface; the system further includes an array of via electrical control grids, wherein each via electrical control grid in the array is disposed near the proximal end of a corresponding via in the array; the dielectric is coated on at least some of each via in the array; the positioning map further indicates a plurality of conductor vias selected from the via array; and configuring the working metal based on the positioning map further includes controlling the electrical control grid array and the via electrical control grid array such that, for each of the plurality of conductor vias: a corresponding working metal portion of the working metal moves to the conductor via due to electrowetting force, such that the corresponding working metal portion substantially fills the conductor via.

12. The system as described in request item 11, further comprising: A second substrate, which is configured to be substantially parallel to the substrate, wherein a second surface of the second substrate faces the substrate; A second electrically controlled grid array defined at the second substrate; and a second dielectric coated on at least some of the second surfaces; wherein: the system further defines a second pixel array, wherein each pixel in the second pixel array includes: a corresponding second substrate portion of the second substrate, including a corresponding second surface portion of the second surface; a corresponding second electrically controlled grid of the second electrically controlled grid array defined at the corresponding second substrate portion; and a corresponding second dielectric portion of the second dielectric coated on the corresponding second surface portion; the dielectric is fluidly coupled to the second dielectric via the via array; the positioning map further indicates a second plurality of conductor pixels selected from the second pixel array; and configuring the working metal based on the positioning map further includes controlling the second electrically controlled grid array such that for each of the second plurality of conductor pixels: a corresponding working metal portion of the working metal moves to the conductor pixel due to electrowetting force, such that the corresponding working metal portion contacts the corresponding second dielectric portion.

13. As in request item 11, the system wherein: The substrate includes glass having a dielectric constant greater than 5; and an effective metamaterial dielectric constant defined by the substrate and the via array is between about 4 and about 4.

4.

14. The system of claim 1, wherein the system further defines a reservoir interior fluidly coupled to the first surface, the reservoir interior containing at least a portion of the working metal, wherein the system is operable to control the electrically controlled grid array such that a portion of the working metal moves between the reservoir interior and the pixel array.

15. The system of claim 14, wherein the interior of the storage device is fluidly isolated from an surrounding environment surrounding the system.

16. The system of claim 15, wherein the reservoir further contains an acidic opposing fluid.

17. The system of claim 1, wherein the dielectric comprises a metal oxide comprising at least one of the following: hafnium, tantalum, barium, or strontium.

18. The system of claim 1, wherein the working metal comprises at least one of the following: indium or gallium.

19. The system of claim 1, further comprising a fluorinated layer coated on the dielectric.

20. The system of claim 1, wherein configuring the working metal based on the positioning map further includes melting at least some of the working metal.

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